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- Analysis & Synthesis report for example_board
- Sat May 09 14:18:46 2026
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Partition Status Summary
- 7. Partition for Top-Level Resource Utilization by Entity
- 8. State Machine - |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state
- 9. State Machine - |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState
- 10. Registers Removed During Synthesis
- 11. Multiplexer Restructuring Statistics (Restructuring Performed)
- 12. Source assignments for Top-level Entity: |example_board
- 13. Source assignments for analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated
- 14. Parameter Settings for User Entity Instance: altpll:pll_inst
- 15. Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst
- 16. Parameter Settings for User Entity Instance: analog_ip:macro_inst
- 17. Parameter Settings for User Entity Instance: analog_ip:macro_inst|ahb2apb:ahb2apb_inst
- 18. Parameter Settings for User Entity Instance: analog_ip:macro_inst|cfg_reg:cfg_reg_inst
- 19. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst
- 20. Parameter Settings for User Entity Instance: analog_ip:macro_inst|baud_detect:u_baud_detect
- 21. Parameter Settings for User Entity Instance: analog_ip:macro_inst|altsyncram:u_dual_port_ram
- 22. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb2ram:u_apb2ram
- 23. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0
- 24. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2
- 25. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3
- 26. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1
- 27. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2
- 28. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1
- 29. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2
- 30. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1
- 31. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_out:mac_out2
- 32. Partition Dependent Files
- 33. Partition "macro_inst_apb_adc0_inst_adc_inst" Resource Utilization by Entity
- 34. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
- 35. Partition Dependent Files
- 36. Partition "macro_inst_apb_dac0_inst_dac_inst" Resource Utilization by Entity
- 37. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
- 38. Partition Dependent Files
- 39. Partition "rv32" Resource Utilization by Entity
- 40. Parameter Settings for User Entity Instance: alta_rv32:rv32
- 41. Partition Dependent Files
- 42. Port Connectivity Checks: "alta_rv32:rv32"
- 43. Port Connectivity Checks: "analog_ip:macro_inst|apb2ram:u_apb2ram"
- 44. Port Connectivity Checks: "analog_ip:macro_inst|baud_detect:u_baud_detect"
- 45. Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst"
- 46. Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst"
- 47. Port Connectivity Checks: "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"
- 48. Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst"
- 49. Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst"
- 50. Port Connectivity Checks: "analog_ip:macro_inst|ahb2apb:ahb2apb_inst"
- 51. Port Connectivity Checks: "alta_gclksw:gclksw_inst"
- 52. Elapsed Time Per Partition
- 53. Analysis & Synthesis Messages
- 54. Analysis & Synthesis Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +----------------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +------------------------------------+---------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Sat May 09 14:18:46 2026 ;
- ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
- ; Revision Name ; example_board ;
- ; Top-level Entity Name ; example_board ;
- ; Family ; Cyclone IV E ;
- ; Total logic elements ; N/A until Partition Merge ;
- ; Total combinational functions ; N/A until Partition Merge ;
- ; Dedicated logic registers ; N/A until Partition Merge ;
- ; Total registers ; N/A until Partition Merge ;
- ; Total pins ; N/A until Partition Merge ;
- ; Total virtual pins ; N/A until Partition Merge ;
- ; Total memory bits ; N/A until Partition Merge ;
- ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
- ; Total PLLs ; N/A until Partition Merge ;
- +------------------------------------+---------------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- ; Device ; EP4CE75F29C8 ; ;
- ; Top-level entity name ; example_board ; example_board ;
- ; Family name ; Cyclone IV E ; Cyclone IV GX ;
- ; Maximum processors allowed for parallel compilation ; All ; ;
- ; Maximum DSP Block Usage ; 0 ; -1 (Unlimited) ;
- ; Auto Open-Drain Pins ; Off ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
- ; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks ; 4 ; -1 (Unlimited) ;
- ; Use smart compilation ; Off ; Off ;
- ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
- ; Enable compact report table ; Off ; Off ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
- ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Infer RAMs from Raw Logic ; On ; On ;
- ; Parallel Synthesis ; On ; On ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique ; Balanced ; Balanced ;
- ; Carry Chain Length ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto DSP Block Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Strict RAM Replacement ; Off ; Off ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto RAM Block Balancing ; On ; On ;
- ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Timing-Driven Synthesis ; On ; On ;
- ; Report Parameter Settings ; On ; On ;
- ; Report Source Assignments ; On ; On ;
- ; Report Connectivity Checks ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Synchronization Register Chain Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Auto Gated Clock Conversion ; Off ; Off ;
- ; Block Design Naming ; Auto ; Auto ;
- ; SDC constraint protection ; Off ; Off ;
- ; Synthesis Effort ; Auto ; Auto ;
- ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
- ; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
- ; Analysis & Synthesis Message Level ; Medium ; Medium ;
- ; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
- ; Resource Aware Inference For Block RAM ; On ; On ;
- ; Synthesis Seed ; 1 ; 1 ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 8 ;
- ; Maximum allowed ; 4 ;
- ; ; ;
- ; Average used ; 3.73 ;
- ; Maximum used ; 4 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processors 2-4 ; 90.9% ;
- ; Processors 5-8 ; 0.0% ;
- +----------------------------+-------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
- +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
- ; trig_ctrl.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v ; ;
- ; cfg_reg.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v ; ;
- ; apb2ram.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v ; ;
- ; baud_detect.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v ; ;
- ; ahb2apb.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v ; ;
- ; example_board.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v ; ;
- ; analog_ip.v ; yes ; User Verilog HDL File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v ; ;
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; yes ; User Verilog HDL File ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; ;
- ; sine.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex ; ;
- ; altpll.tdf ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf ; ;
- ; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc ; ;
- ; stratix_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc ; ;
- ; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
- ; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
- ; db/altpll_6o32.tdf ; yes ; Auto-Generated Megafunction ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf ; ;
- ; altsyncram.tdf ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altsyncram.tdf ; ;
- ; stratix_ram_block.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
- ; lpm_mux.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_mux.inc ; ;
- ; lpm_decode.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_decode.inc ; ;
- ; a_rdenreg.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
- ; altrom.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altrom.inc ; ;
- ; altram.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altram.inc ; ;
- ; altdpram.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altdpram.inc ; ;
- ; db/altsyncram_sgu1.tdf ; yes ; Auto-Generated Megafunction ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altsyncram_sgu1.tdf ; ;
- +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
- +------------------------------------------------------------------------------+
- ; Partition Status Summary ;
- +-----------------------------------+-------------+----------------------------+
- ; Partition Name ; Synthesized ; Reason ;
- +-----------------------------------+-------------+----------------------------+
- ; Top ; yes ; netlist type = Source File ;
- ; macro_inst_apb_adc0_inst_adc_inst ; yes ; netlist type = Source File ;
- ; macro_inst_apb_dac0_inst_dac_inst ; yes ; netlist type = Source File ;
- ; rv32 ; yes ; netlist type = Source File ;
- +-----------------------------------+-------------+----------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition for Top-Level Resource Utilization by Entity ;
- +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- ; |example_board ; 1530 (46) ; 484 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board ; work ;
- ; |alta_gclksw:gclksw_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|alta_gclksw:gclksw_inst ; work ;
- ; |altpll:pll_inst| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|altpll:pll_inst ; work ;
- ; |altpll_6o32:auto_generated| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|altpll:pll_inst|altpll_6o32:auto_generated ; work ;
- ; |analog_ip:macro_inst| ; 1484 (30) ; 483 (4) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst ; work ;
- ; |ahb2apb:ahb2apb_inst| ; 25 (25) ; 74 (74) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst ; work ;
- ; |altsyncram:u_dual_port_ram| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|altsyncram:u_dual_port_ram ; work ;
- ; |altsyncram_sgu1:auto_generated| ; 0 (0) ; 0 (0) ; 16384 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated ; work ;
- ; |apb2ram:u_apb2ram| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb2ram:u_apb2ram ; work ;
- ; |apb_adc:apb_adc0_inst| ; 27 (27) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst ; work ;
- ; |apb_dac:apb_dac0_inst| ; 904 (488) ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst ; work ;
- ; |lpm_mult:Mult0| ; 149 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0 ; work ;
- ; |mult_oct:auto_generated| ; 149 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated ; work ;
- ; |alt_mac_mult:mac_mult1| ; 149 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ; work ;
- ; |mac_mult_iug1:auto_generated| ; 149 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated ; work ;
- ; |mult_aql:mult1| ; 149 (149) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated|mult_aql:mult1 ; work ;
- ; |lpm_mult:Mult2| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2 ; work ;
- ; |mult_pbt:auto_generated| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated ; work ;
- ; |alt_mac_mult:mac_mult1| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1 ; work ;
- ; |mac_mult_jtg1:auto_generated| ; 124 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1|mac_mult_jtg1:auto_generated ; work ;
- ; |mult_bpl:mult1| ; 124 (124) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1|mac_mult_jtg1:auto_generated|mult_bpl:mult1 ; work ;
- ; |lpm_mult:Mult3| ; 143 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3 ; work ;
- ; |mult_oct:auto_generated| ; 143 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated ; work ;
- ; |alt_mac_mult:mac_mult1| ; 143 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ; work ;
- ; |mac_mult_iug1:auto_generated| ; 143 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated ; work ;
- ; |mult_aql:mult1| ; 143 (143) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated|mult_aql:mult1 ; work ;
- ; |cfg_reg:cfg_reg_inst| ; 155 (155) ; 164 (164) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst ; work ;
- ; |trig_ctrl:trig_ctrl_inst| ; 341 (341) ; 149 (149) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst ; work ;
- +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- Encoding Type: One-Hot
- +-----------------------------------------------------------------------------------------------------------------------------+
- ; State Machine - |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state ;
- +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
- ; Name ; curr_state.POST_TRIG ; curr_state.SAMPLING ; curr_state.PRE_FILL ; curr_state.IDLE ; curr_state.DONE ;
- +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
- ; curr_state.IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; curr_state.PRE_FILL ; 0 ; 0 ; 1 ; 1 ; 0 ;
- ; curr_state.SAMPLING ; 0 ; 1 ; 0 ; 1 ; 0 ;
- ; curr_state.POST_TRIG ; 1 ; 0 ; 0 ; 1 ; 0 ;
- ; curr_state.DONE ; 0 ; 0 ; 0 ; 1 ; 1 ;
- +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
- Encoding Type: One-Hot
- +-----------------------------------------------------------------------------------+
- ; State Machine - |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState ;
- +--------------------+------------------+--------------------+----------------------+
- ; Name ; apbState.apbIdle ; apbState.apbAccess ; apbState.apbSetup ;
- +--------------------+------------------+--------------------+----------------------+
- ; apbState.apbIdle ; 0 ; 0 ; 0 ;
- ; apbState.apbSetup ; 1 ; 0 ; 1 ;
- ; apbState.apbAccess ; 1 ; 1 ; 0 ;
- +--------------------+------------------+--------------------+----------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Registers Removed During Synthesis ;
- +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
- ; Register name ; Reason for Removal ;
- +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|decim_factor[12,15] ; Stuck at GND due to stuck port data_in ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[10..31] ; Stuck at GND due to stuck port data_in ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[12..15] ; Stuck at GND due to stuck port data_in ;
- ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hresp ; Stuck at GND due to stuck port data_in ;
- ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_msb_r ; Merged with analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[9] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[8] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[7] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[6] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[5] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[4] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[3] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[2] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[1] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[0] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state~4 ; Lost fanout ;
- ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state~5 ; Lost fanout ;
- ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbAccess ; Lost fanout ;
- ; Total Number of Removed Registers = 42 ; ;
- +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
- ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
- ; 3:1 ; 17 bits ; 34 LEs ; 0 LEs ; 34 LEs ; Yes ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ;
- ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6] ;
- ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[7] ;
- ; 4:1 ; 12 bits ; 24 LEs ; 12 LEs ; 12 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[10] ;
- ; 4:1 ; 16 bits ; 32 LEs ; 32 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ;
- ; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14] ;
- ; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8] ;
- ; 5:1 ; 9 bits ; 27 LEs ; 9 LEs ; 18 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|post_trig_cnt[8] ;
- ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12] ;
- ; 5:1 ; 11 bits ; 33 LEs ; 11 LEs ; 22 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ;
- ; 6:1 ; 11 bits ; 44 LEs ; 11 LEs ; 33 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ;
- ; 5:1 ; 2 bits ; 6 LEs ; 4 LEs ; 2 LEs ; Yes ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[10] ;
- ; 18:1 ; 10 bits ; 120 LEs ; 20 LEs ; 100 LEs ; Yes ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ;
- ; 6:1 ; 10 bits ; 40 LEs ; 10 LEs ; 30 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[7] ;
- ; 9:1 ; 3 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[5] ;
- ; 10:1 ; 16 bits ; 96 LEs ; 16 LEs ; 80 LEs ; Yes ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[12] ;
- ; 10:1 ; 3 bits ; 18 LEs ; 18 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[4] ;
- ; 13:1 ; 2 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[1] ;
- ; 7:1 ; 10 bits ; 40 LEs ; 40 LEs ; 0 LEs ; No ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mux7 ;
- ; 13:1 ; 5 bits ; 40 LEs ; 30 LEs ; 10 LEs ; No ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|Selector0 ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
- +---------------------------------------------------------------------+
- ; Source assignments for Top-level Entity: |example_board ;
- +------------------------------+-------+------+-----------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------+------+-----------------------+
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_ENABLE ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_ENABLE ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_LOCK ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_LOCK ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_resetn ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_resetn ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_stop ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_stop ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio0_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio0_io_out_en[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_data[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_data[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_en[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_en[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[0] ;
- +------------------------------+-------+------+-----------------------+
- +-------------------------------------------------------------------------------------------------------+
- ; Source assignments for analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated ;
- +---------------------------------+--------------------+------+-----------------------------------------+
- ; Assignment ; Value ; From ; To ;
- +---------------------------------+--------------------+------+-----------------------------------------+
- ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
- +---------------------------------+--------------------+------+-----------------------------------------+
- +--------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: altpll:pll_inst ;
- +-------------------------------+-------------------+----------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+-------------------+----------------+
- ; OPERATION_MODE ; NORMAL ; Untyped ;
- ; PLL_TYPE ; AUTO ; Untyped ;
- ; LPM_HINT ; UNUSED ; Untyped ;
- ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
- ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
- ; SCAN_CHAIN ; LONG ; Untyped ;
- ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
- ; INCLK0_INPUT_FREQUENCY ; 125000 ; Signed Integer ;
- ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
- ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
- ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
- ; LOCK_HIGH ; 1 ; Untyped ;
- ; LOCK_LOW ; 1 ; Untyped ;
- ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
- ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
- ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
- ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
- ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
- ; SKIP_VCO ; OFF ; Untyped ;
- ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
- ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
- ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
- ; BANDWIDTH ; 0 ; Untyped ;
- ; BANDWIDTH_TYPE ; AUTO ; Untyped ;
- ; SPREAD_FREQUENCY ; 0 ; Untyped ;
- ; DOWN_SPREAD ; 0 ; Untyped ;
- ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
- ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
- ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
- ; CLK4_MULTIPLY_BY ; 104 ; Signed Integer ;
- ; CLK3_MULTIPLY_BY ; 104 ; Signed Integer ;
- ; CLK2_MULTIPLY_BY ; 104 ; Signed Integer ;
- ; CLK1_MULTIPLY_BY ; 104 ; Signed Integer ;
- ; CLK0_MULTIPLY_BY ; 104 ; Signed Integer ;
- ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
- ; CLK4_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK3_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK2_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK1_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK0_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_TIME_DELAY ; 0 ; Untyped ;
- ; CLK4_TIME_DELAY ; 0 ; Untyped ;
- ; CLK3_TIME_DELAY ; 0 ; Untyped ;
- ; CLK2_TIME_DELAY ; 0 ; Untyped ;
- ; CLK1_TIME_DELAY ; 0 ; Untyped ;
- ; CLK0_TIME_DELAY ; 0 ; Untyped ;
- ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK0_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
- ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
- ; DPA_MULTIPLY_BY ; 0 ; Untyped ;
- ; DPA_DIVIDE_BY ; 1 ; Untyped ;
- ; DPA_DIVIDER ; 0 ; Untyped ;
- ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
- ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
- ; VCO_DIVIDE_BY ; 0 ; Untyped ;
- ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
- ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
- ; VCO_MIN ; 0 ; Untyped ;
- ; VCO_MAX ; 0 ; Untyped ;
- ; VCO_CENTER ; 0 ; Untyped ;
- ; PFD_MIN ; 0 ; Untyped ;
- ; PFD_MAX ; 0 ; Untyped ;
- ; M_INITIAL ; 0 ; Untyped ;
- ; M ; 0 ; Untyped ;
- ; N ; 1 ; Untyped ;
- ; M2 ; 1 ; Untyped ;
- ; N2 ; 1 ; Untyped ;
- ; SS ; 1 ; Untyped ;
- ; C0_HIGH ; 0 ; Untyped ;
- ; C1_HIGH ; 0 ; Untyped ;
- ; C2_HIGH ; 0 ; Untyped ;
- ; C3_HIGH ; 0 ; Untyped ;
- ; C4_HIGH ; 0 ; Untyped ;
- ; C5_HIGH ; 0 ; Untyped ;
- ; C6_HIGH ; 0 ; Untyped ;
- ; C7_HIGH ; 0 ; Untyped ;
- ; C8_HIGH ; 0 ; Untyped ;
- ; C9_HIGH ; 0 ; Untyped ;
- ; C0_LOW ; 0 ; Untyped ;
- ; C1_LOW ; 0 ; Untyped ;
- ; C2_LOW ; 0 ; Untyped ;
- ; C3_LOW ; 0 ; Untyped ;
- ; C4_LOW ; 0 ; Untyped ;
- ; C5_LOW ; 0 ; Untyped ;
- ; C6_LOW ; 0 ; Untyped ;
- ; C7_LOW ; 0 ; Untyped ;
- ; C8_LOW ; 0 ; Untyped ;
- ; C9_LOW ; 0 ; Untyped ;
- ; C0_INITIAL ; 0 ; Untyped ;
- ; C1_INITIAL ; 0 ; Untyped ;
- ; C2_INITIAL ; 0 ; Untyped ;
- ; C3_INITIAL ; 0 ; Untyped ;
- ; C4_INITIAL ; 0 ; Untyped ;
- ; C5_INITIAL ; 0 ; Untyped ;
- ; C6_INITIAL ; 0 ; Untyped ;
- ; C7_INITIAL ; 0 ; Untyped ;
- ; C8_INITIAL ; 0 ; Untyped ;
- ; C9_INITIAL ; 0 ; Untyped ;
- ; C0_MODE ; BYPASS ; Untyped ;
- ; C1_MODE ; BYPASS ; Untyped ;
- ; C2_MODE ; BYPASS ; Untyped ;
- ; C3_MODE ; BYPASS ; Untyped ;
- ; C4_MODE ; BYPASS ; Untyped ;
- ; C5_MODE ; BYPASS ; Untyped ;
- ; C6_MODE ; BYPASS ; Untyped ;
- ; C7_MODE ; BYPASS ; Untyped ;
- ; C8_MODE ; BYPASS ; Untyped ;
- ; C9_MODE ; BYPASS ; Untyped ;
- ; C0_PH ; 0 ; Untyped ;
- ; C1_PH ; 0 ; Untyped ;
- ; C2_PH ; 0 ; Untyped ;
- ; C3_PH ; 0 ; Untyped ;
- ; C4_PH ; 0 ; Untyped ;
- ; C5_PH ; 0 ; Untyped ;
- ; C6_PH ; 0 ; Untyped ;
- ; C7_PH ; 0 ; Untyped ;
- ; C8_PH ; 0 ; Untyped ;
- ; C9_PH ; 0 ; Untyped ;
- ; L0_HIGH ; 1 ; Untyped ;
- ; L1_HIGH ; 1 ; Untyped ;
- ; G0_HIGH ; 1 ; Untyped ;
- ; G1_HIGH ; 1 ; Untyped ;
- ; G2_HIGH ; 1 ; Untyped ;
- ; G3_HIGH ; 1 ; Untyped ;
- ; E0_HIGH ; 1 ; Untyped ;
- ; E1_HIGH ; 1 ; Untyped ;
- ; E2_HIGH ; 1 ; Untyped ;
- ; E3_HIGH ; 1 ; Untyped ;
- ; L0_LOW ; 1 ; Untyped ;
- ; L1_LOW ; 1 ; Untyped ;
- ; G0_LOW ; 1 ; Untyped ;
- ; G1_LOW ; 1 ; Untyped ;
- ; G2_LOW ; 1 ; Untyped ;
- ; G3_LOW ; 1 ; Untyped ;
- ; E0_LOW ; 1 ; Untyped ;
- ; E1_LOW ; 1 ; Untyped ;
- ; E2_LOW ; 1 ; Untyped ;
- ; E3_LOW ; 1 ; Untyped ;
- ; L0_INITIAL ; 1 ; Untyped ;
- ; L1_INITIAL ; 1 ; Untyped ;
- ; G0_INITIAL ; 1 ; Untyped ;
- ; G1_INITIAL ; 1 ; Untyped ;
- ; G2_INITIAL ; 1 ; Untyped ;
- ; G3_INITIAL ; 1 ; Untyped ;
- ; E0_INITIAL ; 1 ; Untyped ;
- ; E1_INITIAL ; 1 ; Untyped ;
- ; E2_INITIAL ; 1 ; Untyped ;
- ; E3_INITIAL ; 1 ; Untyped ;
- ; L0_MODE ; BYPASS ; Untyped ;
- ; L1_MODE ; BYPASS ; Untyped ;
- ; G0_MODE ; BYPASS ; Untyped ;
- ; G1_MODE ; BYPASS ; Untyped ;
- ; G2_MODE ; BYPASS ; Untyped ;
- ; G3_MODE ; BYPASS ; Untyped ;
- ; E0_MODE ; BYPASS ; Untyped ;
- ; E1_MODE ; BYPASS ; Untyped ;
- ; E2_MODE ; BYPASS ; Untyped ;
- ; E3_MODE ; BYPASS ; Untyped ;
- ; L0_PH ; 0 ; Untyped ;
- ; L1_PH ; 0 ; Untyped ;
- ; G0_PH ; 0 ; Untyped ;
- ; G1_PH ; 0 ; Untyped ;
- ; G2_PH ; 0 ; Untyped ;
- ; G3_PH ; 0 ; Untyped ;
- ; E0_PH ; 0 ; Untyped ;
- ; E1_PH ; 0 ; Untyped ;
- ; E2_PH ; 0 ; Untyped ;
- ; E3_PH ; 0 ; Untyped ;
- ; M_PH ; 0 ; Untyped ;
- ; C1_USE_CASC_IN ; OFF ; Untyped ;
- ; C2_USE_CASC_IN ; OFF ; Untyped ;
- ; C3_USE_CASC_IN ; OFF ; Untyped ;
- ; C4_USE_CASC_IN ; OFF ; Untyped ;
- ; C5_USE_CASC_IN ; OFF ; Untyped ;
- ; C6_USE_CASC_IN ; OFF ; Untyped ;
- ; C7_USE_CASC_IN ; OFF ; Untyped ;
- ; C8_USE_CASC_IN ; OFF ; Untyped ;
- ; C9_USE_CASC_IN ; OFF ; Untyped ;
- ; CLK0_COUNTER ; G0 ; Untyped ;
- ; CLK1_COUNTER ; G0 ; Untyped ;
- ; CLK2_COUNTER ; G0 ; Untyped ;
- ; CLK3_COUNTER ; G0 ; Untyped ;
- ; CLK4_COUNTER ; G0 ; Untyped ;
- ; CLK5_COUNTER ; G0 ; Untyped ;
- ; CLK6_COUNTER ; E0 ; Untyped ;
- ; CLK7_COUNTER ; E1 ; Untyped ;
- ; CLK8_COUNTER ; E2 ; Untyped ;
- ; CLK9_COUNTER ; E3 ; Untyped ;
- ; L0_TIME_DELAY ; 0 ; Untyped ;
- ; L1_TIME_DELAY ; 0 ; Untyped ;
- ; G0_TIME_DELAY ; 0 ; Untyped ;
- ; G1_TIME_DELAY ; 0 ; Untyped ;
- ; G2_TIME_DELAY ; 0 ; Untyped ;
- ; G3_TIME_DELAY ; 0 ; Untyped ;
- ; E0_TIME_DELAY ; 0 ; Untyped ;
- ; E1_TIME_DELAY ; 0 ; Untyped ;
- ; E2_TIME_DELAY ; 0 ; Untyped ;
- ; E3_TIME_DELAY ; 0 ; Untyped ;
- ; M_TIME_DELAY ; 0 ; Untyped ;
- ; N_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_COUNTER ; E3 ; Untyped ;
- ; EXTCLK2_COUNTER ; E2 ; Untyped ;
- ; EXTCLK1_COUNTER ; E1 ; Untyped ;
- ; EXTCLK0_COUNTER ; E0 ; Untyped ;
- ; ENABLE0_COUNTER ; L0 ; Untyped ;
- ; ENABLE1_COUNTER ; L0 ; Untyped ;
- ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
- ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
- ; LOOP_FILTER_C ; 5 ; Untyped ;
- ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
- ; VCO_POST_SCALE ; 0 ; Untyped ;
- ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLK0 ; PORT_USED ; Untyped ;
- ; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK3 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_INCLK0 ; PORT_USED ; Untyped ;
- ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ARESET ; PORT_USED ; Untyped ;
- ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_LOCKED ; PORT_USED ; Untyped ;
- ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; M_TEST_SOURCE ; 5 ; Untyped ;
- ; C0_TEST_SOURCE ; 5 ; Untyped ;
- ; C1_TEST_SOURCE ; 5 ; Untyped ;
- ; C2_TEST_SOURCE ; 5 ; Untyped ;
- ; C3_TEST_SOURCE ; 5 ; Untyped ;
- ; C4_TEST_SOURCE ; 5 ; Untyped ;
- ; C5_TEST_SOURCE ; 5 ; Untyped ;
- ; C6_TEST_SOURCE ; 5 ; Untyped ;
- ; C7_TEST_SOURCE ; 5 ; Untyped ;
- ; C8_TEST_SOURCE ; 5 ; Untyped ;
- ; C9_TEST_SOURCE ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; altpll_6o32 ; Untyped ;
- ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
- ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
- ; WIDTH_CLOCK ; 5 ; Signed Integer ;
- ; WIDTH_PHASECOUNTERSELECT ; 3 ; Signed Integer ;
- ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
- ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- +-------------------------------+-------------------+----------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst ;
- +----------------+-------+---------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+---------------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- ; ENA_REG_MODE ; 0 ; Unsigned Binary ;
- +----------------+-------+---------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst ;
- +----------------+----------------------------------+-----------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+----------------------------------+-----------------+
- ; RAM_SIZE ; 2048 ; Signed Integer ;
- ; RAM_DEPTH ; 1024 ; Signed Integer ;
- ; RAM_WIDTH ; 16 ; Signed Integer ;
- ; ADDR_BITS ; 16 ; Signed Integer ;
- ; DATA_BITS ; 32 ; Signed Integer ;
- ; PER_BITS ; 12 ; Signed Integer ;
- ; PER_CNT ; 4 ; Signed Integer ;
- ; RAM_BASE_ADDR ; 00000000000000000110000000000000 ; Unsigned Binary ;
- +----------------+----------------------------------+-----------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|ahb2apb:ahb2apb_inst ;
- +----------------+-------+---------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+---------------------------------------------------------------+
- ; ADDR_BITS ; 16 ; Signed Integer ;
- ; DATA_BITS ; 32 ; Signed Integer ;
- +----------------+-------+---------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|cfg_reg:cfg_reg_inst ;
- +----------------+----------------------------------+------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+----------------------------------+------------------------------------+
- ; ADDR_CTRL ; 00000000000000000000000000000000 ; Unsigned Binary ;
- ; ADDR_CLK_DIV ; 00000000000000000000000000000100 ; Unsigned Binary ;
- ; ADDR_TRIG_TH ; 00000000000000000000000000001000 ; Unsigned Binary ;
- ; ADDR_TRIG_PW ; 00000000000000000000000000001100 ; Unsigned Binary ;
- ; ADDR_TRIG_CFG ; 00000000000000000000000000010000 ; Unsigned Binary ;
- ; ADDR_TRIG_TOUT ; 00000000000000000000000000010100 ; Unsigned Binary ;
- ; ADDR_RUN_CTRL ; 00000000000000000000000000011000 ; Unsigned Binary ;
- ; ADDR_DAC_CTRL ; 00000000000000000000000000011100 ; Unsigned Binary ;
- ; ADDR_DAC_WAVE ; 00000000000000000000000000100000 ; Unsigned Binary ;
- ; ADDR_DAC_AMP ; 00000000000000000000000000100100 ; Unsigned Binary ;
- ; ADDR_DAC_FREQ ; 00000000000000000000000000101000 ; Unsigned Binary ;
- ; ADDR_DAC_DUTY ; 00000000000000000000000000101100 ; Unsigned Binary ;
- +----------------+----------------------------------+------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst ;
- +----------------+-------+----------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+----------------------------------------------------------------+
- ; SCLK_BIT ; 16 ; Signed Integer ;
- +----------------+-------+----------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|baud_detect:u_baud_detect ;
- +----------------+-------+--------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+--------------------------------------------------------------------+
- ; NUM_EDGES ; 16 ; Signed Integer ;
- +----------------+-------+--------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|altsyncram:u_dual_port_ram ;
- +------------------------------------+----------------------+----------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------------+----------------------+----------------------------------+
- ; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- ; WIDTH_BYTEENA ; 1 ; Untyped ;
- ; OPERATION_MODE ; BIDIR_DUAL_PORT ; Untyped ;
- ; WIDTH_A ; 16 ; Signed Integer ;
- ; WIDTHAD_A ; 10 ; Signed Integer ;
- ; NUMWORDS_A ; 1024 ; Signed Integer ;
- ; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
- ; ADDRESS_ACLR_A ; NONE ; Untyped ;
- ; OUTDATA_ACLR_A ; NONE ; Untyped ;
- ; WRCONTROL_ACLR_A ; NONE ; Untyped ;
- ; INDATA_ACLR_A ; NONE ; Untyped ;
- ; BYTEENA_ACLR_A ; NONE ; Untyped ;
- ; WIDTH_B ; 16 ; Signed Integer ;
- ; WIDTHAD_B ; 10 ; Signed Integer ;
- ; NUMWORDS_B ; 1024 ; Signed Integer ;
- ; INDATA_REG_B ; CLOCK1 ; Untyped ;
- ; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
- ; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
- ; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
- ; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
- ; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
- ; INDATA_ACLR_B ; NONE ; Untyped ;
- ; WRCONTROL_ACLR_B ; NONE ; Untyped ;
- ; ADDRESS_ACLR_B ; NONE ; Untyped ;
- ; OUTDATA_ACLR_B ; NONE ; Untyped ;
- ; RDCONTROL_ACLR_B ; NONE ; Untyped ;
- ; BYTEENA_ACLR_B ; NONE ; Untyped ;
- ; WIDTH_BYTEENA_A ; 2 ; Signed Integer ;
- ; WIDTH_BYTEENA_B ; 2 ; Signed Integer ;
- ; RAM_BLOCK_TYPE ; M9K ; Untyped ;
- ; BYTE_SIZE ; 8 ; Signed Integer ;
- ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
- ; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
- ; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
- ; INIT_FILE ; UNUSED ; Untyped ;
- ; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
- ; MAXIMUM_DEPTH ; 0 ; Untyped ;
- ; CLOCK_ENABLE_INPUT_A ; BYPASS ; Untyped ;
- ; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
- ; CLOCK_ENABLE_OUTPUT_A ; BYPASS ; Untyped ;
- ; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
- ; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
- ; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
- ; ENABLE_ECC ; FALSE ; Untyped ;
- ; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
- ; WIDTH_ECCSTATUS ; 3 ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; CBXI_PARAMETER ; altsyncram_sgu1 ; Untyped ;
- +------------------------------------+----------------------+----------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb2ram:u_apb2ram ;
- +----------------+-------+------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+------------------------------------------------------------+
- ; ADDR_BITS ; 16 ; Signed Integer ;
- +----------------+-------+------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0 ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- ; LPM_WIDTHA ; 10 ; Untyped ;
- ; LPM_WIDTHB ; 10 ; Untyped ;
- ; LPM_WIDTHP ; 20 ; Untyped ;
- ; LPM_WIDTHR ; 20 ; Untyped ;
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_PIPELINE ; 0 ; Untyped ;
- ; LATENCY ; 0 ; Untyped ;
- ; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; USE_EAB ; OFF ; Untyped ;
- ; MAXIMIZE_SPEED ; 6 ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; CARRY_CHAIN ; MANUAL ; Untyped ;
- ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
- ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; CBXI_PARAMETER ; mult_oct ; Untyped ;
- ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
- +------------------------------------------------+--------------+--------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2 ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- ; LPM_WIDTHA ; 10 ; Untyped ;
- ; LPM_WIDTHB ; 9 ; Untyped ;
- ; LPM_WIDTHP ; 19 ; Untyped ;
- ; LPM_WIDTHR ; 19 ; Untyped ;
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_PIPELINE ; 0 ; Untyped ;
- ; LATENCY ; 0 ; Untyped ;
- ; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; USE_EAB ; OFF ; Untyped ;
- ; MAXIMIZE_SPEED ; 6 ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; CARRY_CHAIN ; MANUAL ; Untyped ;
- ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
- ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; CBXI_PARAMETER ; mult_pbt ; Untyped ;
- ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
- +------------------------------------------------+--------------+--------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3 ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------------------------+--------------+--------------------------------------------+
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- ; LPM_WIDTHA ; 10 ; Untyped ;
- ; LPM_WIDTHB ; 10 ; Untyped ;
- ; LPM_WIDTHP ; 20 ; Untyped ;
- ; LPM_WIDTHR ; 20 ; Untyped ;
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
- ; LPM_PIPELINE ; 0 ; Untyped ;
- ; LATENCY ; 0 ; Untyped ;
- ; INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; USE_EAB ; OFF ; Untyped ;
- ; MAXIMIZE_SPEED ; 6 ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; CARRY_CHAIN ; MANUAL ; Untyped ;
- ; APEX20K_TECHNOLOGY_MAPPER ; LUT ; TECH_MAPPER_APEX20K ;
- ; DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0 ; Untyped ;
- ; CBXI_PARAMETER ; mult_oct ; Untyped ;
- ; INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; USE_AHDL_IMPLEMENTATION ; OFF ; Untyped ;
- +------------------------------------------------+--------------+--------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; DATAA_WIDTH ; 10 ; Untyped ;
- ; DATAB_WIDTH ; 10 ; Untyped ;
- ; DATAA_CLOCK ; NONE ; Untyped ;
- ; DATAB_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; DATAA_CLEAR ; NONE ; Untyped ;
- ; DATAB_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ROUND_CLOCK ; none ; Untyped ;
- ; ROUND_CLEAR ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; BYPASS_MULTIPLIER ; NO ; Untyped ;
- ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; EXTRA_OUTPUT_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNA_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNB_CLOCK ; none ; Untyped ;
- ; EXTRA_OUTPUT_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNA_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNB_CLEAR ; none ; Untyped ;
- ; MULT_PIPELINE ; 0 ; Untyped ;
- ; MULT_CLOCK ; NONE ; Untyped ;
- ; MULT_CLEAR ; NONE ; Untyped ;
- ; MULT_REPRESENTATION_A ; UNSIGNED ; Untyped ;
- ; MULT_REPRESENTATION_B ; UNSIGNED ; Untyped ;
- ; MULT_INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_MAXIMIZE_SPEED ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; mac_mult_iug1 ; Untyped ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2 ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; OPERATION_MODE ; OUTPUT_ONLY ; Untyped ;
- ; DATAA_WIDTH ; 20 ; Untyped ;
- ; DATAB_WIDTH ; 0 ; Untyped ;
- ; DATAC_WIDTH ; 0 ; Untyped ;
- ; DATAD_WIDTH ; 0 ; Untyped ;
- ; ADDNSUB0_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_CLOCK ; NONE ; Untyped ;
- ; ROUND0_CLOCK ; none ; Untyped ;
- ; ROUND1_CLOCK ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_CLOCK ; none ; Untyped ;
- ; ZEROACC_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_CLEAR ; NONE ; Untyped ;
- ; ROUND0_CLEAR ; none ; Untyped ;
- ; ROUND1_CLEAR ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_CLEAR ; none ; Untyped ;
- ; ZEROACC_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLOCK ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLEAR ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; MODE0_CLOCK ; none ; Untyped ;
- ; MODE1_CLOCK ; none ; Untyped ;
- ; ZEROACC1_CLOCK ; none ; Untyped ;
- ; SATURATE1_CLOCK ; none ; Untyped ;
- ; OUTPUT1_CLOCK ; none ; Untyped ;
- ; OUTPUT2_CLOCK ; none ; Untyped ;
- ; OUTPUT3_CLOCK ; none ; Untyped ;
- ; OUTPUT4_CLOCK ; none ; Untyped ;
- ; OUTPUT5_CLOCK ; none ; Untyped ;
- ; OUTPUT6_CLOCK ; none ; Untyped ;
- ; OUTPUT7_CLOCK ; none ; Untyped ;
- ; MODE0_CLEAR ; none ; Untyped ;
- ; MODE1_CLEAR ; none ; Untyped ;
- ; ZEROACC1_CLEAR ; none ; Untyped ;
- ; SATURATE1_CLEAR ; none ; Untyped ;
- ; OUTPUT1_CLEAR ; none ; Untyped ;
- ; OUTPUT2_CLEAR ; none ; Untyped ;
- ; OUTPUT3_CLEAR ; none ; Untyped ;
- ; OUTPUT4_CLEAR ; none ; Untyped ;
- ; OUTPUT5_CLEAR ; none ; Untyped ;
- ; OUTPUT6_CLEAR ; none ; Untyped ;
- ; OUTPUT7_CLEAR ; none ; Untyped ;
- ; MODE0_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE0_PIPELINE_CLEAR ; none ; Untyped ;
- ; MODE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; FIRST_ADDER0_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER0_CLEAR ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLEAR ; NONE ; Untyped ;
- ; DATAA_FORCED_TO_ZERO ; NO ; Untyped ;
- ; DATAC_FORCED_TO_ZERO ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; USING_MULT_SATURATION ; NO ; Untyped ;
- ; USING_LOADABLE_ACCUM ; NO ; Untyped ;
- ; LOADABLE_ACCUM_SUPPORTED ; NO ; Untyped ;
- ; USING_CHAINOUT ; NO ; Untyped ;
- ; CHAININ_WIDTH ; 0 ; Untyped ;
- ; CHAINOUT_PIPELINE_CLOCK ; none ; Untyped ;
- ; CHAINOUT_PIPELINE_CLEAR ; none ; Untyped ;
- ; CBXI_PARAMETER ; mac_out_lr82 ; Untyped ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1 ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; DATAA_WIDTH ; 10 ; Untyped ;
- ; DATAB_WIDTH ; 9 ; Untyped ;
- ; DATAA_CLOCK ; NONE ; Untyped ;
- ; DATAB_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; DATAA_CLEAR ; NONE ; Untyped ;
- ; DATAB_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ROUND_CLOCK ; none ; Untyped ;
- ; ROUND_CLEAR ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; BYPASS_MULTIPLIER ; NO ; Untyped ;
- ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; EXTRA_OUTPUT_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNA_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNB_CLOCK ; none ; Untyped ;
- ; EXTRA_OUTPUT_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNA_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNB_CLEAR ; none ; Untyped ;
- ; MULT_PIPELINE ; 0 ; Untyped ;
- ; MULT_CLOCK ; NONE ; Untyped ;
- ; MULT_CLEAR ; NONE ; Untyped ;
- ; MULT_REPRESENTATION_A ; UNSIGNED ; Untyped ;
- ; MULT_REPRESENTATION_B ; UNSIGNED ; Untyped ;
- ; MULT_INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_MAXIMIZE_SPEED ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; mac_mult_jtg1 ; Untyped ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2 ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; OPERATION_MODE ; OUTPUT_ONLY ; Untyped ;
- ; DATAA_WIDTH ; 19 ; Untyped ;
- ; DATAB_WIDTH ; 0 ; Untyped ;
- ; DATAC_WIDTH ; 0 ; Untyped ;
- ; DATAD_WIDTH ; 0 ; Untyped ;
- ; ADDNSUB0_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_CLOCK ; NONE ; Untyped ;
- ; ROUND0_CLOCK ; none ; Untyped ;
- ; ROUND1_CLOCK ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_CLOCK ; none ; Untyped ;
- ; ZEROACC_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_CLEAR ; NONE ; Untyped ;
- ; ROUND0_CLEAR ; none ; Untyped ;
- ; ROUND1_CLEAR ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_CLEAR ; none ; Untyped ;
- ; ZEROACC_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLOCK ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLEAR ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; MODE0_CLOCK ; none ; Untyped ;
- ; MODE1_CLOCK ; none ; Untyped ;
- ; ZEROACC1_CLOCK ; none ; Untyped ;
- ; SATURATE1_CLOCK ; none ; Untyped ;
- ; OUTPUT1_CLOCK ; none ; Untyped ;
- ; OUTPUT2_CLOCK ; none ; Untyped ;
- ; OUTPUT3_CLOCK ; none ; Untyped ;
- ; OUTPUT4_CLOCK ; none ; Untyped ;
- ; OUTPUT5_CLOCK ; none ; Untyped ;
- ; OUTPUT6_CLOCK ; none ; Untyped ;
- ; OUTPUT7_CLOCK ; none ; Untyped ;
- ; MODE0_CLEAR ; none ; Untyped ;
- ; MODE1_CLEAR ; none ; Untyped ;
- ; ZEROACC1_CLEAR ; none ; Untyped ;
- ; SATURATE1_CLEAR ; none ; Untyped ;
- ; OUTPUT1_CLEAR ; none ; Untyped ;
- ; OUTPUT2_CLEAR ; none ; Untyped ;
- ; OUTPUT3_CLEAR ; none ; Untyped ;
- ; OUTPUT4_CLEAR ; none ; Untyped ;
- ; OUTPUT5_CLEAR ; none ; Untyped ;
- ; OUTPUT6_CLEAR ; none ; Untyped ;
- ; OUTPUT7_CLEAR ; none ; Untyped ;
- ; MODE0_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE0_PIPELINE_CLEAR ; none ; Untyped ;
- ; MODE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; FIRST_ADDER0_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER0_CLEAR ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLEAR ; NONE ; Untyped ;
- ; DATAA_FORCED_TO_ZERO ; NO ; Untyped ;
- ; DATAC_FORCED_TO_ZERO ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; USING_MULT_SATURATION ; NO ; Untyped ;
- ; USING_LOADABLE_ACCUM ; NO ; Untyped ;
- ; LOADABLE_ACCUM_SUPPORTED ; NO ; Untyped ;
- ; USING_CHAINOUT ; NO ; Untyped ;
- ; CHAININ_WIDTH ; 0 ; Untyped ;
- ; CHAINOUT_PIPELINE_CLOCK ; none ; Untyped ;
- ; CHAINOUT_PIPELINE_CLEAR ; none ; Untyped ;
- ; CBXI_PARAMETER ; mac_out_5s82 ; Untyped ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- ; LPM_WIDTHS ; 1 ; Untyped ;
- ; DATAA_WIDTH ; 10 ; Untyped ;
- ; DATAB_WIDTH ; 10 ; Untyped ;
- ; DATAA_CLOCK ; NONE ; Untyped ;
- ; DATAB_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; DATAA_CLEAR ; NONE ; Untyped ;
- ; DATAB_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ROUND_CLOCK ; none ; Untyped ;
- ; ROUND_CLEAR ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; BYPASS_MULTIPLIER ; NO ; Untyped ;
- ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; EXTRA_OUTPUT_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNA_CLOCK ; none ; Untyped ;
- ; EXTRA_SIGNB_CLOCK ; none ; Untyped ;
- ; EXTRA_OUTPUT_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNA_CLEAR ; none ; Untyped ;
- ; EXTRA_SIGNB_CLEAR ; none ; Untyped ;
- ; MULT_PIPELINE ; 0 ; Untyped ;
- ; MULT_CLOCK ; NONE ; Untyped ;
- ; MULT_CLEAR ; NONE ; Untyped ;
- ; MULT_REPRESENTATION_A ; UNSIGNED ; Untyped ;
- ; MULT_REPRESENTATION_B ; UNSIGNED ; Untyped ;
- ; MULT_INPUT_A_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_B_IS_CONSTANT ; NO ; Untyped ;
- ; MULT_INPUT_A_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_INPUT_B_FIXED_VALUE ; Bx ; Untyped ;
- ; MULT_MAXIMIZE_SPEED ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; mac_mult_iug1 ; Untyped ;
- +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_out:mac_out2 ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- ; OPERATION_MODE ; OUTPUT_ONLY ; Untyped ;
- ; DATAA_WIDTH ; 20 ; Untyped ;
- ; DATAB_WIDTH ; 0 ; Untyped ;
- ; DATAC_WIDTH ; 0 ; Untyped ;
- ; DATAD_WIDTH ; 0 ; Untyped ;
- ; ADDNSUB0_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_CLOCK ; NONE ; Untyped ;
- ; ROUND0_CLOCK ; none ; Untyped ;
- ; ROUND1_CLOCK ; none ; Untyped ;
- ; SATURATE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_CLOCK ; none ; Untyped ;
- ; ZEROACC_CLOCK ; NONE ; Untyped ;
- ; SIGNA_CLOCK ; NONE ; Untyped ;
- ; SIGNB_CLOCK ; NONE ; Untyped ;
- ; OUTPUT_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_CLEAR ; NONE ; Untyped ;
- ; ROUND0_CLEAR ; none ; Untyped ;
- ; ROUND1_CLEAR ; none ; Untyped ;
- ; SATURATE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_CLEAR ; none ; Untyped ;
- ; ZEROACC_CLEAR ; NONE ; Untyped ;
- ; SIGNA_CLEAR ; NONE ; Untyped ;
- ; SIGNB_CLEAR ; NONE ; Untyped ;
- ; OUTPUT_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLOCK ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLOCK ; NONE ; Untyped ;
- ; ADDNSUB0_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ADDNSUB1_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; ROUND0_PIPELINE_CLEAR ; none ; Untyped ;
- ; ROUND1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTABSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; MULTCDSATURATE_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNA_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; SIGNB_PIPELINE_CLEAR ; NONE ; Untyped ;
- ; MODE0_CLOCK ; none ; Untyped ;
- ; MODE1_CLOCK ; none ; Untyped ;
- ; ZEROACC1_CLOCK ; none ; Untyped ;
- ; SATURATE1_CLOCK ; none ; Untyped ;
- ; OUTPUT1_CLOCK ; none ; Untyped ;
- ; OUTPUT2_CLOCK ; none ; Untyped ;
- ; OUTPUT3_CLOCK ; none ; Untyped ;
- ; OUTPUT4_CLOCK ; none ; Untyped ;
- ; OUTPUT5_CLOCK ; none ; Untyped ;
- ; OUTPUT6_CLOCK ; none ; Untyped ;
- ; OUTPUT7_CLOCK ; none ; Untyped ;
- ; MODE0_CLEAR ; none ; Untyped ;
- ; MODE1_CLEAR ; none ; Untyped ;
- ; ZEROACC1_CLEAR ; none ; Untyped ;
- ; SATURATE1_CLEAR ; none ; Untyped ;
- ; OUTPUT1_CLEAR ; none ; Untyped ;
- ; OUTPUT2_CLEAR ; none ; Untyped ;
- ; OUTPUT3_CLEAR ; none ; Untyped ;
- ; OUTPUT4_CLEAR ; none ; Untyped ;
- ; OUTPUT5_CLEAR ; none ; Untyped ;
- ; OUTPUT6_CLEAR ; none ; Untyped ;
- ; OUTPUT7_CLEAR ; none ; Untyped ;
- ; MODE0_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLOCK ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLOCK ; none ; Untyped ;
- ; MODE0_PIPELINE_CLEAR ; none ; Untyped ;
- ; MODE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; ZEROACC1_PIPELINE_CLEAR ; none ; Untyped ;
- ; SATURATE1_PIPELINE_CLEAR ; none ; Untyped ;
- ; FIRST_ADDER0_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLOCK ; NONE ; Untyped ;
- ; FIRST_ADDER0_CLEAR ; NONE ; Untyped ;
- ; FIRST_ADDER1_CLEAR ; NONE ; Untyped ;
- ; DATAA_FORCED_TO_ZERO ; NO ; Untyped ;
- ; DATAC_FORCED_TO_ZERO ; NO ; Untyped ;
- ; USING_ROUNDING ; NO ; Untyped ;
- ; USING_SATURATION ; NO ; Untyped ;
- ; USING_MULT_SATURATION ; NO ; Untyped ;
- ; USING_LOADABLE_ACCUM ; NO ; Untyped ;
- ; LOADABLE_ACCUM_SUPPORTED ; NO ; Untyped ;
- ; USING_CHAINOUT ; NO ; Untyped ;
- ; CHAININ_WIDTH ; 0 ; Untyped ;
- ; CHAINOUT_PIPELINE_CLOCK ; none ; Untyped ;
- ; CHAINOUT_PIPELINE_CLEAR ; none ; Untyped ;
- ; CBXI_PARAMETER ; mac_out_lr82 ; Untyped ;
- +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +---------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition Dependent Files ;
- +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
- ; File ; Location ; Library ; Checksum ;
- +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
- ; libraries/megafunctions/a_rdenreg.inc ; Quartus II Install ; work ; 3fcdce7559590d5a8afbe64788d201fb ;
- ; libraries/megafunctions/aglobal130.inc ; Quartus II Install ; work ; 6fc5170a475a9c6f00c3fd7627b30d31 ;
- ; libraries/megafunctions/altdpram.inc ; Quartus II Install ; work ; 2f9e6727b678ffd76e72bc5a95a26300 ;
- ; libraries/megafunctions/altpll.tdf ; Quartus II Install ; work ; 2fbd40fef3231c521503c3b7162ebe3e ;
- ; libraries/megafunctions/altram.inc ; Quartus II Install ; work ; ad5518b39ffd3cf1df377e6360d1c9b6 ;
- ; libraries/megafunctions/altrom.inc ; Quartus II Install ; work ; 192b74eafa8debf2248ea73881e77f91 ;
- ; libraries/megafunctions/altsyncram.tdf ; Quartus II Install ; work ; 2d180e92194c1b32bb16b4887ae417e4 ;
- ; libraries/megafunctions/cycloneii_pll.inc ; Quartus II Install ; work ; c2ee779f089b03bc181df753ea85b3ef ;
- ; libraries/megafunctions/lpm_decode.inc ; Quartus II Install ; work ; 10da69a8bbd590d66779e7a142f73790 ;
- ; libraries/megafunctions/lpm_mux.inc ; Quartus II Install ; work ; dd87bed90959d6126db09970164b7ba6 ;
- ; libraries/megafunctions/stratix_pll.inc ; Quartus II Install ; work ; a9a94c5b0e18105f7ae8c218a67ec9f7 ;
- ; libraries/megafunctions/stratix_ram_block.inc ; Quartus II Install ; work ; e3a03868917f0b3dd57b6ed1dd195f22 ;
- ; libraries/megafunctions/stratixii_pll.inc ; Quartus II Install ; work ; 6797ab505ed700f1a221e4a213e106a6 ;
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ;
- ; ahb2apb.v ; Project Directory ; work ; c4d07e481d6d597cf56fdc254ec8bab8 ;
- ; analog_ip.v ; Project Directory ; work ; 9ce6f7736cc6ec764422aabb35957b2b ;
- ; apb2ram.v ; Project Directory ; work ; d2319d386e3f52f5093368b85cef65ef ;
- ; baud_detect.v ; Project Directory ; work ; edeaf273b63cd48e52285dd989701b7b ;
- ; cfg_reg.v ; Project Directory ; work ; 245eba41e85b4bf89560ef5b37a75d80 ;
- ; db/altpll_6o32.tdf ; Project Directory ; work ; 9c3386175185bf4e2c0ee36f607dfc7f ;
- ; db/altsyncram_sgu1.tdf ; Project Directory ; work ; 1c6c503332b5bdaf6aa11728cd197aa0 ;
- ; example_board.v ; Project Directory ; work ; 60f1dcec3c4b16342256f6ca0da2bbb3 ;
- ; sine.hex ; Project Directory ; work ; e7b4ee736c594f02a51ed06e6c1af8bd ;
- ; trig_ctrl.v ; Project Directory ; work ; 84250c2c4eb94fe0748883cbf26b4a05 ;
- +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition "macro_inst_apb_adc0_inst_adc_inst" Resource Utilization by Entity ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- ; |example_board ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board ; work ;
- ; |analog_ip:macro_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst ; work ;
- ; |apb_adc:apb_adc0_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst ; work ;
- ; |alta_adc:adc_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst ; work ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-----------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst ;
- +----------------+-------+----------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+----------------------------------------------------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- +----------------+-------+----------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition Dependent Files ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; File ; Location ; Library ; Checksum ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition "macro_inst_apb_dac0_inst_dac_inst" Resource Utilization by Entity ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- ; |example_board ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board ; work ;
- ; |analog_ip:macro_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst ; work ;
- ; |apb_dac:apb_dac0_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst ; work ;
- ; |alta_dac:dac_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst ; work ;
- +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-----------------------------------------------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst ;
- +----------------+-------+----------------------------------------------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+----------------------------------------------------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- +----------------+-------+----------------------------------------------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition Dependent Files ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; File ; Location ; Library ; Checksum ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition "rv32" Resource Utilization by Entity ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
- ; |example_board ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board ; work ;
- ; |alta_rv32:rv32| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |example_board|alta_rv32:rv32 ; work ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: alta_rv32:rv32 ;
- +----------------+-------+------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- +----------------+-------+------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition Dependent Files ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; File ; Location ; Library ; Checksum ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ;
- +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "alta_rv32:rv32" ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; ext_resetn ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; test_mode ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; usb0_xcvr_clk ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; usb0_id ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; sys_ctrl_hseEnable ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_hseBypass ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_sleep ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_standby ; Partition Output ; Info ; Explicitly unconnected ;
- ; dmactive ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGNSW ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGSTATE ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGIR ; Partition Output ; Info ; Explicitly unconnected ;
- ; ext_int ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio0_io_out_data[7..2] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio0_io_out_en[7..2] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio1_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio1_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio1_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio2_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio2_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio2_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio3_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio3_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio3_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_data[4..3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_data[0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_en[4..3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_en[0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio5_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio5_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio5_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio7_io_out_data[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_en[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio8_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio8_io_out_data[7..1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio8_io_out_en[7..1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio9_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio9_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio9_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|apb2ram:u_apb2ram" ;
- +-------------+--------+----------+-------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-------------+--------+----------+-------------------------------------------------------------------------------------+
- ; apb_pready ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
- ; apb_pslverr ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
- ; ram_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
- +-------------+--------+----------+-------------------------------------------------------------------------------------+
- +---------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|baud_detect:u_baud_detect" ;
- +-----------+--------+----------+-------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-----------+--------+----------+-------------------------------------------------------------------------------------+
- ; baud_rate ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
- +-----------+--------+----------+-------------------------------------------------------------------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst" ;
- +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; dout ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- +------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst" ;
- +---------+--------+----------+------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +---------+--------+----------+------------------------------------------+
- ; dma_req ; Output ; Info ; Explicitly unconnected ;
- ; dma_clr ; Input ; Info ; Stuck at GND ;
- +---------+--------+----------+------------------------------------------+
- +---------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst" ;
- +-------------+--------+----------+-----------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-------------+--------+----------+-----------------------------------------+
- ; trig_done ; Output ; Info ; Explicitly unconnected ;
- ; trigger_ptr ; Output ; Info ; Explicitly unconnected ;
- +-------------+--------+----------+-----------------------------------------+
- +----------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst" ;
- +----------+-----------------+----------+------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +----------+-----------------+----------+------------------------------------------------------------------------+
- ; insel[4] ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- +----------+-----------------+----------+------------------------------------------------------------------------+
- +------------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst" ;
- +---------+--------+----------+------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +---------+--------+----------+------------------------------------------+
- ; dma_req ; Output ; Info ; Explicitly unconnected ;
- ; dma_clr ; Input ; Info ; Stuck at GND ;
- +---------+--------+----------+------------------------------------------+
- +-----------------------------------------------------------------------+
- ; Port Connectivity Checks: "analog_ip:macro_inst|ahb2apb:ahb2apb_inst" ;
- +-----------------+-------+----------+----------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-----------------+-------+----------+----------------------------------+
- ; ahb_hmastlock ; Input ; Info ; Stuck at GND ;
- ; ahb_hsel ; Input ; Info ; Stuck at VCC ;
- ; ahb_hprot[1..0] ; Input ; Info ; Stuck at VCC ;
- ; ahb_hprot[3..2] ; Input ; Info ; Stuck at GND ;
- ; apb_pready ; Input ; Info ; Stuck at VCC ;
- ; apb_pslverr ; Input ; Info ; Stuck at GND ;
- +-----------------+-------+----------+----------------------------------+
- +-----------------------------------------------------+
- ; Port Connectivity Checks: "alta_gclksw:gclksw_inst" ;
- +--------+-------+----------+-------------------------+
- ; Port ; Type ; Severity ; Details ;
- +--------+-------+----------+-------------------------+
- ; ena ; Input ; Info ; Stuck at VCC ;
- ; clkin3 ; Input ; Info ; Explicitly unconnected ;
- +--------+-------+----------+-------------------------+
- +--------------------------------------------------+
- ; Elapsed Time Per Partition ;
- +-----------------------------------+--------------+
- ; Partition Name ; Elapsed Time ;
- +-----------------------------------+--------------+
- ; Top ; 00:00:09 ;
- ; rv32 ; 00:00:09 ;
- ; macro_inst_apb_adc0_inst_adc_inst ; 00:00:09 ;
- ; macro_inst_apb_dac0_inst_dac_inst ; 00:00:09 ;
- +-----------------------------------+--------------+
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 14:18:35 2026
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board
- Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
- Info (12021): Found 1 design units, including 1 entities, in source file trig_ctrl.v
- Info (12023): Found entity 1: trig_ctrl
- Info (12021): Found 1 design units, including 1 entities, in source file cfg_reg.v
- Info (12023): Found entity 1: cfg_reg
- Info (12021): Found 1 design units, including 1 entities, in source file apb2ram.v
- Info (12023): Found entity 1: apb2ram
- Info (12021): Found 1 design units, including 1 entities, in source file baud_detect.v
- Info (12023): Found entity 1: baud_detect
- Info (12021): Found 1 design units, including 1 entities, in source file ahb2apb.v
- Info (12023): Found entity 1: ahb2apb
- Info (12021): Found 1 design units, including 1 entities, in source file example_board.v
- Info (12023): Found entity 1: example_board
- Warning (10275): Verilog HDL Module Instantiation warning at analog_ip.v(314): ignored dangling comma in List of Port Connections
- Warning (10335): Unrecognized synthesis attribute "ram_style" at analog_ip.v(634)
- Info (12021): Found 3 design units, including 3 entities, in source file analog_ip.v
- Info (12023): Found entity 1: analog_ip
- Info (12023): Found entity 2: apb_adc
- Info (12023): Found entity 3: apb_dac
- Info (12021): Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v
- Info (12023): Found entity 1: alta_slice
- Info (12023): Found entity 2: alta_clkenctrl_rst
- Info (12023): Found entity 3: alta_clkenctrl
- Info (12023): Found entity 4: alta_asyncctrl
- Info (12023): Found entity 5: alta_syncctrl
- Info (12023): Found entity 6: alta_io_gclk
- Info (12023): Found entity 7: alta_gclksel
- Info (12023): Found entity 8: alta_gclkgen
- Info (12023): Found entity 9: alta_gclkgen0
- Info (12023): Found entity 10: alta_gclkgen2
- Info (12023): Found entity 11: alta_io
- Info (12023): Found entity 12: alta_rio
- Info (12023): Found entity 13: alta_srff
- Info (12023): Found entity 14: alta_dff
- Info (12023): Found entity 15: alta_ufm_gddd
- Info (12023): Found entity 16: alta_dff_stall
- Info (12023): Found entity 17: alta_srlat
- Info (12023): Found entity 18: alta_dio
- Info (12023): Found entity 19: alta_indel
- Info (12023): Found entity 20: alta_dpclkdel
- Info (12023): Found entity 21: alta_ufms
- Info (12023): Found entity 22: alta_ufms_sim
- Info (12023): Found entity 23: alta_pll
- Info (12023): Found entity 24: alta_pllx
- Info (12023): Found entity 25: pll_clk_trim
- Info (12023): Found entity 26: alta_pllv
- Info (12023): Found entity 27: alta_pllve
- Info (12023): Found entity 28: alta_sram
- Info (12023): Found entity 29: alta_dpram16x4
- Info (12023): Found entity 30: alta_spram16x4
- Info (12023): Found entity 31: alta_wram
- Info (12023): Found entity 32: alta_bram_pulse_generator
- Info (12023): Found entity 33: alta_bram
- Info (12023): Found entity 34: alta_boot
- Info (12023): Found entity 35: alta_osc
- Info (12023): Found entity 36: alta_ufml
- Info (12023): Found entity 37: alta_jtag
- Info (12023): Found entity 38: alta_mult
- Info (12023): Found entity 39: alta_dff_en
- Info (12023): Found entity 40: alta_multm_add
- Info (12023): Found entity 41: alta_multm
- Info (12023): Found entity 42: alta_i2c
- Info (12023): Found entity 43: alta_spi
- Info (12023): Found entity 44: alta_irda
- Info (12023): Found entity 45: alta_bram9k
- Info (12023): Found entity 46: alta_mcu
- Info (12023): Found entity 47: alta_mcu_m3
- Info (12023): Found entity 48: alta_remote
- Info (12023): Found entity 49: alta_saradc
- Info (12023): Found entity 50: alta_gclksw
- Info (12023): Found entity 51: alta_rv32
- Info (12023): Found entity 52: alta_mipi_clk
- Info (12023): Found entity 53: alta_adc
- Info (12023): Found entity 54: alta_dac
- Info (12023): Found entity 55: alta_cmp
- Info (12023): Found entity 56: alta_ram4k
- Info (12023): Found entity 57: alta_ram9k
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(39): created implicit net for "PIN_10_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(55): created implicit net for "PIN_21_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(58): created implicit net for "PIN_29_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(69): created implicit net for "PIN_31_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(75): created implicit net for "PIN_HSE_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(78): created implicit net for "PIN_HSI_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(81): created implicit net for "PIN_OSC_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(204): created implicit net for "usb0_xcvr_clk"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(205): created implicit net for "bus_clk"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(216): created implicit net for "sys_clk"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(269): created implicit net for "csn_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(270): created implicit net for "csn_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(271): created implicit net for "rxd1_ip_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(272): created implicit net for "sck_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(273): created implicit net for "sck_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(274): created implicit net for "so_io1_in"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(275): created implicit net for "so_io1_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(276): created implicit net for "so_io1_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(277): created implicit net for "txd1_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at example_board.v(278): created implicit net for "txd1_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for "ena_reg"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for "ena_int"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for "ena_reg"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for "outreg_h"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for "outreg_l"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for "oe_reg_h"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for "oe_reg_l"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for "dffOut"
- Warning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
- Info (12127): Elaborating entity "example_board" for the top level hierarchy
- Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll_inst"
- Info (12130): Elaborated megafunction instantiation "altpll:pll_inst"
- Info (12133): Instantiated megafunction "altpll:pll_inst" with the following parameter:
- Info (12134): Parameter "bandwidth_type" = "AUTO"
- Info (12134): Parameter "clk0_divide_by" = "8"
- Info (12134): Parameter "clk0_multiply_by" = "104"
- Info (12134): Parameter "clk0_phase_shift" = "0"
- Info (12134): Parameter "clk1_divide_by" = "8"
- Info (12134): Parameter "clk1_multiply_by" = "104"
- Info (12134): Parameter "clk1_phase_shift" = "0"
- Info (12134): Parameter "clk2_divide_by" = "8"
- Info (12134): Parameter "clk2_multiply_by" = "104"
- Info (12134): Parameter "clk2_phase_shift" = "0"
- Info (12134): Parameter "clk3_divide_by" = "8"
- Info (12134): Parameter "clk3_multiply_by" = "104"
- Info (12134): Parameter "clk3_phase_shift" = "0"
- Info (12134): Parameter "clk4_divide_by" = "8"
- Info (12134): Parameter "clk4_multiply_by" = "104"
- Info (12134): Parameter "clk4_phase_shift" = "0"
- Info (12134): Parameter "compensate_clock" = "CLK0"
- Info (12134): Parameter "inclk0_input_frequency" = "125000"
- Info (12134): Parameter "lpm_type" = "altpll"
- Info (12134): Parameter "operation_mode" = "NORMAL"
- Info (12134): Parameter "pll_type" = "AUTO"
- Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
- Info (12134): Parameter "port_areset" = "PORT_USED"
- Info (12134): Parameter "port_inclk0" = "PORT_USED"
- Info (12134): Parameter "port_locked" = "PORT_USED"
- Info (12134): Parameter "port_clk0" = "PORT_USED"
- Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
- Info (12134): Parameter "width_clock" = "5"
- Info (12134): Parameter "width_phasecounterselect" = "3"
- Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_6o32.tdf
- Info (12023): Found entity 1: altpll_6o32
- Info (12128): Elaborating entity "altpll_6o32" for hierarchy "altpll:pll_inst|altpll_6o32:auto_generated"
- Info (12128): Elaborating entity "alta_gclksw" for hierarchy "alta_gclksw:gclksw_inst"
- Info (12128): Elaborating entity "analog_ip" for hierarchy "analog_ip:macro_inst"
- Warning (10230): Verilog HDL assignment warning at analog_ip.v(136): truncated value with size 32 to match size of target (4)
- Info (10264): Verilog HDL Case Statement information at analog_ip.v(475): all case item expressions in this case statement are onehot
- Info (12128): Elaborating entity "ahb2apb" for hierarchy "analog_ip:macro_inst|ahb2apb:ahb2apb_inst"
- Warning (10764): Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned
- Warning (10230): Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4)
- Info (12128): Elaborating entity "cfg_reg" for hierarchy "analog_ip:macro_inst|cfg_reg:cfg_reg_inst"
- Info (12128): Elaborating entity "apb_adc" for hierarchy "analog_ip:macro_inst|apb_adc:apb_adc0_inst"
- Info (12128): Elaborating entity "alta_adc" for hierarchy "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst"
- Info (12128): Elaborating entity "trig_ctrl" for hierarchy "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"
- Warning (10230): Verilog HDL assignment warning at trig_ctrl.v(163): truncated value with size 32 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at trig_ctrl.v(359): truncated value with size 32 to match size of target (10)
- Info (10264): Verilog HDL Case Statement information at trig_ctrl.v(345): all case item expressions in this case statement are onehot
- Info (12128): Elaborating entity "apb_dac" for hierarchy "analog_ip:macro_inst|apb_dac:apb_dac0_inst"
- Warning (10230): Verilog HDL assignment warning at sine.hex(1): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(2): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(3): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(4): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(5): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(6): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(7): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(8): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(9): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(10): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(11): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(12): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(13): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(14): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(15): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(16): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(17): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(18): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(19): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(20): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(21): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(22): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(23): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(24): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(25): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(26): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(27): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(28): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(29): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(30): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(31): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(32): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(33): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(34): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(35): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(36): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(37): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(38): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(39): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(40): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(41): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(42): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(43): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(44): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(45): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(46): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(47): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(48): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(49): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(50): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(51): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(52): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(53): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(54): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(55): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(56): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(57): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(58): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(59): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(60): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(61): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(62): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(63): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(64): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(65): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(66): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(67): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(68): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(69): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(70): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(71): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(72): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(73): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(74): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(75): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(76): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(77): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(78): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(79): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(80): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(81): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(82): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(83): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(84): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(85): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(86): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(87): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(88): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(89): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(90): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(91): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(92): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(93): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(94): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(95): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(96): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(97): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(98): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(99): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(100): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(101): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(102): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(103): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(104): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(105): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(106): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(107): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(108): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(109): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(110): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(111): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(112): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(113): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(114): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(115): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(116): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(117): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(118): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(119): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(120): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(121): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(122): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(123): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(124): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(125): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(126): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(127): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(128): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(129): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(130): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(131): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(132): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(133): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(134): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(135): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(136): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(137): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(138): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(139): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(140): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(141): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(142): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(143): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(144): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(145): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(146): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(147): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(148): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(149): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(150): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(151): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(152): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(153): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(154): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(155): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(156): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(157): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(158): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(159): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(160): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(161): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(162): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(163): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(164): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(165): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(166): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(167): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(168): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(169): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(170): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(171): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(172): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(173): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(174): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(175): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(176): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(177): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(178): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(179): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(180): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(181): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(182): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(183): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(184): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(185): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(186): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(187): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(188): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(189): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(190): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(191): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(192): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(193): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(194): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(195): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(196): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(197): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(198): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(199): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(200): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(201): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(202): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(203): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(204): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(205): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(206): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(207): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(208): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(209): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(210): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(211): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(212): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(213): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(214): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(215): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(216): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(217): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(218): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(219): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(220): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(221): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(222): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(223): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(224): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(225): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(226): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(227): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(228): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(229): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(230): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(231): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(232): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(233): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(234): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(235): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(236): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(237): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(238): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(239): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(240): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(241): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(242): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(243): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(244): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(245): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(246): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(247): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(248): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(249): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(250): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(251): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(252): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(253): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(254): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(255): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(256): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(257): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(258): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(259): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(260): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(261): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(262): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(263): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(264): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(265): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(266): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(267): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(268): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(269): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(270): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(271): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(272): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(273): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(274): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(275): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(276): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(277): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(278): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(279): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(280): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(281): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(282): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(283): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(284): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(285): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(286): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(287): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(288): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(289): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(290): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(291): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(292): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(293): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(294): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(295): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(296): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(297): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(298): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(299): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(300): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(301): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(302): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(303): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(304): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(305): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(306): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(307): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(308): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(309): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(310): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(311): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(312): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(313): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(314): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(315): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(316): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(317): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(318): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(319): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(320): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(321): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(322): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(323): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(324): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(325): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(326): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(327): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(328): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(329): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(330): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(331): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(332): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(333): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(334): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(335): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(336): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(337): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(338): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(339): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(340): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(341): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(342): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(343): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(344): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(345): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(346): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(347): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(348): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(349): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(350): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(351): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(352): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(353): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(354): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(355): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(356): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(357): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(358): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(359): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(360): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(361): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(362): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(363): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(364): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(365): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(366): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(367): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(368): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(369): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(370): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(371): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(372): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(373): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(374): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(375): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(376): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(377): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(378): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(379): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(380): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(381): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(382): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(383): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(384): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(385): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(386): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(387): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(388): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(389): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(390): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(391): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(392): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(393): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(394): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(395): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(396): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(397): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(398): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(399): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(400): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(401): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(402): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(403): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(404): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(405): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(406): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(407): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(408): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(409): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(410): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(411): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(412): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(413): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(414): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(415): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(416): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(417): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(418): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(419): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(420): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(421): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(422): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(423): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(424): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(425): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(426): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(427): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(428): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(429): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(430): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(431): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(432): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(433): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(434): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(435): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(436): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(437): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(438): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(439): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(440): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(441): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(442): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(443): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(444): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(445): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(446): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(447): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(448): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(449): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(450): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(451): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(452): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(453): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(454): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(455): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(456): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(457): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(458): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(459): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(460): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(461): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(462): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(463): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(464): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(465): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(466): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(467): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(468): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(469): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(470): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(471): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(472): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(473): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(474): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(475): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(476): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(477): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(478): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(479): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(480): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(481): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(482): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(483): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(484): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(485): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(486): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(487): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(488): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(489): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(490): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(491): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(492): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(493): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(494): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(495): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(496): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(497): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(498): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(499): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(500): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(501): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(502): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(503): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(504): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(505): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(506): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(507): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(508): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(509): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(510): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(511): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(512): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(513): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(514): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(515): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(516): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(517): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(518): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(519): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(520): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(521): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(522): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(523): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(524): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(525): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(526): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(527): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(528): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(529): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(530): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(531): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(532): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(533): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(534): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(535): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(536): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(537): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(538): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(539): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(540): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(541): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(542): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(543): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(544): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(545): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(546): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(547): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(548): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(549): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(550): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(551): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(552): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(553): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(554): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(555): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(556): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(557): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(558): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(559): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(560): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(561): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(562): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(563): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(564): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(565): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(566): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(567): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(568): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(569): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(570): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(571): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(572): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(573): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(574): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(575): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(576): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(577): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(578): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(579): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(580): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(581): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(582): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(583): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(584): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(585): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(586): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(587): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(588): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(589): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(590): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(591): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(592): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(593): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(594): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(595): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(596): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(597): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(598): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(599): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(600): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(601): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(602): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(603): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(604): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(605): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(606): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(607): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(608): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(609): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(610): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(611): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(612): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(613): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(614): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(615): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(616): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(617): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(618): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(619): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(620): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(621): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(622): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(623): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(624): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(625): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(626): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(627): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(628): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(629): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(630): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(631): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(632): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(633): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(634): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(635): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(636): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(637): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(638): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(639): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(640): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(641): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(642): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(643): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(644): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(645): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(646): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(647): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(648): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(649): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(650): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(651): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(652): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(653): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(654): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(655): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(656): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(657): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(658): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(659): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(660): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(661): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(662): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(663): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(664): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(665): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(666): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(667): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(668): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(669): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(670): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(671): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(672): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(673): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(674): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(675): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(676): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(677): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(678): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(679): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(680): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(681): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(682): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(683): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(684): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(685): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(686): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(687): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(688): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(689): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(690): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(691): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(692): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(693): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(694): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(695): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(696): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(697): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(698): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(699): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(700): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(701): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(702): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(703): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(704): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(705): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(706): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(707): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(708): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(709): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(710): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(711): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(712): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(713): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(714): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(715): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(716): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(717): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(718): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(719): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(720): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(721): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(722): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(723): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(724): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(725): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(726): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(727): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(728): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(729): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(730): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(731): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(732): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(733): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(734): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(735): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(736): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(737): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(738): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(739): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(740): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(741): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(742): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(743): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(744): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(745): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(746): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(747): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(748): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(749): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(750): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(751): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(752): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(753): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(754): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(755): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(756): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(757): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(758): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(759): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(760): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(761): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(762): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(763): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(764): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(765): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(766): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(767): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(768): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(769): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(770): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(771): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(772): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(773): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(774): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(775): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(776): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(777): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(778): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(779): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(780): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(781): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(782): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(783): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(784): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(785): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(786): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(787): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(788): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(789): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(790): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(791): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(792): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(793): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(794): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(795): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(796): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(797): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(798): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(799): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(800): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(801): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(802): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(803): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(804): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(805): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(806): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(807): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(808): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(809): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(810): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(811): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(812): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(813): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(814): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(815): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(816): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(817): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(818): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(819): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(820): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(821): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(822): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(823): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(824): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(825): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(826): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(827): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(828): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(829): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(830): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(831): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(832): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(833): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(834): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(835): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(836): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(837): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(838): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(839): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(840): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(841): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(842): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(843): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(844): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(845): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(846): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(847): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(848): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(849): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(850): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(851): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(852): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(853): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(854): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(855): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(856): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(857): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(858): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(859): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(860): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(861): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(862): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(863): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(864): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(865): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(866): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(867): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(868): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(869): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(870): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(871): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(872): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(873): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(874): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(875): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(876): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(877): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(878): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(879): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(880): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(881): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(882): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(883): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(884): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(885): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(886): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(887): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(888): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(889): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(890): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(891): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(892): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(893): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(894): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(895): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(896): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(897): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(898): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(899): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(900): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(901): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(902): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(903): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(904): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(905): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(906): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(907): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(908): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(909): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(910): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(911): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(912): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(913): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(914): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(915): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(916): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(917): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(918): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(919): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(920): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(921): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(922): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(923): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(924): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(925): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(926): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(927): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(928): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(929): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(930): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(931): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(932): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(933): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(934): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(935): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(936): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(937): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(938): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(939): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(940): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(941): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(942): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(943): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(944): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(945): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(946): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(947): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(948): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(949): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(950): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(951): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(952): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(953): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(954): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(955): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(956): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(957): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(958): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(959): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(960): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(961): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(962): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(963): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(964): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(965): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(966): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(967): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(968): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(969): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(970): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(971): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(972): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(973): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(974): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(975): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(976): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(977): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(978): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(979): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(980): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(981): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(982): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(983): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(984): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(985): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(986): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(987): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(988): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(989): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(990): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(991): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(992): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(993): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(994): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(995): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(996): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(997): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(998): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(999): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1000): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1001): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1002): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1003): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1004): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1005): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1006): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1007): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1008): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1009): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1010): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1011): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1012): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1013): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1014): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1015): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1016): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1017): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1018): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1019): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1020): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1021): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1022): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1023): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at sine.hex(1024): truncated value with size 12 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at analog_ip.v(678): truncated value with size 20 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at analog_ip.v(686): truncated value with size 20 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at analog_ip.v(691): truncated value with size 20 to match size of target (10)
- Warning (10230): Verilog HDL assignment warning at analog_ip.v(699): truncated value with size 20 to match size of target (10)
- Warning (10240): Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable "mult", which holds its previous value in one or more paths through the always construct
- Warning (10240): Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable "step", which holds its previous value in one or more paths through the always construct
- Warning (10030): Net "sine_rom.data_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
- Warning (10030): Net "sine_rom.waddr_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
- Warning (10030): Net "sine_rom.we_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
- Info (12128): Elaborating entity "alta_dac" for hierarchy "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst"
- Info (12128): Elaborating entity "baud_detect" for hierarchy "analog_ip:macro_inst|baud_detect:u_baud_detect"
- Warning (10230): Verilog HDL assignment warning at baud_detect.v(33): truncated value with size 32 to match size of target (24)
- Warning (10230): Verilog HDL assignment warning at baud_detect.v(35): truncated value with size 32 to match size of target (24)
- Warning (10230): Verilog HDL assignment warning at baud_detect.v(40): truncated value with size 32 to match size of target (4)
- Warning (10240): Verilog HDL Always Construct warning at baud_detect.v(28): inferring latch(es) for variable "min_time", which holds its previous value in one or more paths through the always construct
- Warning (10230): Verilog HDL assignment warning at baud_detect.v(50): truncated value with size 32 to match size of target (24)
- Info (12128): Elaborating entity "altsyncram" for hierarchy "analog_ip:macro_inst|altsyncram:u_dual_port_ram"
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|altsyncram:u_dual_port_ram"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|altsyncram:u_dual_port_ram" with the following parameter:
- Info (12134): Parameter "byte_size" = "8"
- Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
- Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
- Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
- Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
- Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
- Info (12134): Parameter "numwords_a" = "1024"
- Info (12134): Parameter "widthad_a" = "10"
- Info (12134): Parameter "width_a" = "16"
- Info (12134): Parameter "width_byteena_a" = "2"
- Info (12134): Parameter "outdata_aclr_a" = "NONE"
- Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
- Info (12134): Parameter "numwords_b" = "1024"
- Info (12134): Parameter "widthad_b" = "10"
- Info (12134): Parameter "width_b" = "16"
- Info (12134): Parameter "width_byteena_b" = "2"
- Info (12134): Parameter "outdata_aclr_b" = "NONE"
- Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
- Info (12134): Parameter "ram_block_type" = "M9K"
- Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
- Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sgu1.tdf
- Info (12023): Found entity 1: altsyncram_sgu1
- Info (12128): Elaborating entity "altsyncram_sgu1" for hierarchy "analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated"
- Info (12128): Elaborating entity "apb2ram" for hierarchy "analog_ip:macro_inst|apb2ram:u_apb2ram"
- Warning (10230): Verilog HDL assignment warning at apb2ram.v(26): truncated value with size 15 to match size of target (10)
- Info (12128): Elaborating entity "alta_rv32" for hierarchy "alta_rv32:rv32"
- Warning (10034): Output port "gpio0_io_out_data" at alta_sim.v(3739) has no driver
- Warning (10034): Output port "gpio0_io_out_en" at alta_sim.v(3740) has no driver
- Warning (10034): Output port "gpio1_io_out_data" at alta_sim.v(3742) has no driver
- Warning (10034): Output port "gpio1_io_out_en" at alta_sim.v(3743) has no driver
- Warning (10034): Output port "gpio2_io_out_data" at alta_sim.v(3753) has no driver
- Warning (10034): Output port "gpio2_io_out_en" at alta_sim.v(3754) has no driver
- Warning (10034): Output port "gpio3_io_out_data" at alta_sim.v(3756) has no driver
- Warning (10034): Output port "gpio3_io_out_en" at alta_sim.v(3757) has no driver
- Warning (10034): Output port "gpio4_io_out_data" at alta_sim.v(3759) has no driver
- Warning (10034): Output port "gpio4_io_out_en" at alta_sim.v(3760) has no driver
- Warning (10034): Output port "gpio5_io_out_data" at alta_sim.v(3762) has no driver
- Warning (10034): Output port "gpio5_io_out_en" at alta_sim.v(3763) has no driver
- Warning (10034): Output port "gpio6_io_out_data" at alta_sim.v(3765) has no driver
- Warning (10034): Output port "gpio6_io_out_en" at alta_sim.v(3766) has no driver
- Warning (10034): Output port "gpio7_io_out_data" at alta_sim.v(3768) has no driver
- Warning (10034): Output port "gpio7_io_out_en" at alta_sim.v(3769) has no driver
- Warning (10034): Output port "gpio8_io_out_data" at alta_sim.v(3771) has no driver
- Warning (10034): Output port "gpio8_io_out_en" at alta_sim.v(3772) has no driver
- Warning (10034): Output port "gpio9_io_out_data" at alta_sim.v(3774) has no driver
- Warning (10034): Output port "gpio9_io_out_en" at alta_sim.v(3775) has no driver
- Warning (10034): Output port "swj_JTAGSTATE" at alta_sim.v(3780) has no driver
- Warning (10034): Output port "swj_JTAGIR" at alta_sim.v(3781) has no driver
- Warning (10034): Output port "dmactive" at alta_sim.v(3778) has no driver
- Warning (10034): Output port "swj_JTAGNSW" at alta_sim.v(3779) has no driver
- Info (12206): 4 design partitions require synthesis
- Info (12210): Partition "Top" requires synthesis because its netlist type is Source File
- Info (12210): Partition "macro_inst_apb_adc0_inst_adc_inst" requires synthesis because its netlist type is Source File
- Info (12210): Partition "macro_inst_apb_dac0_inst_dac_inst" requires synthesis because its netlist type is Source File
- Info (12210): Partition "rv32" requires synthesis because its netlist type is Source File
- Info (12209): No design partitions will skip synthesis in the current incremental compilation
- Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
- Info (281037): Using 4 processors to synthesize 4 partitions in parallel
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 14:18:37 2026
- Info: Command: quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board
- Info (278001): Inferred 3 megafunctions from design logic
- Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult0"
- Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult2"
- Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult3"
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0" with the following parameter:
- Info (12134): Parameter "LPM_WIDTHA" = "10"
- Info (12134): Parameter "LPM_WIDTHB" = "10"
- Info (12134): Parameter "LPM_WIDTHP" = "20"
- Info (12134): Parameter "LPM_WIDTHR" = "20"
- Info (12134): Parameter "LPM_WIDTHS" = "1"
- Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
- Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
- Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
- Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mult_oct.tdf
- Info (12023): Found entity 1: mult_oct
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2" with the following parameter:
- Info (12134): Parameter "LPM_WIDTHA" = "10"
- Info (12134): Parameter "LPM_WIDTHB" = "9"
- Info (12134): Parameter "LPM_WIDTHP" = "19"
- Info (12134): Parameter "LPM_WIDTHR" = "19"
- Info (12134): Parameter "LPM_WIDTHS" = "1"
- Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
- Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
- Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
- Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mult_pbt.tdf
- Info (12023): Found entity 1: mult_pbt
- Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top
- Info (270001): Converted 3 DSP block slices
- Info (270002): Used 3 DSP blocks before DSP block balancing
- Info (270003): Used 3 DSP block slices in "Simple Multiplier (18-bit)" mode implemented in approximately 3 DSP blocks
- Info (270013): Converted the following 3 DSP block slices to logic elements
- Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_out2"
- Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_out2"
- Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_mult1"
- Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_out2"
- Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_out2"
- Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_mult1"
- Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_out2"
- Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_out2"
- Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_mult1"
- Info (270002): Used 0 DSP blocks after DSP block balancing
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1" with the following parameter:
- Info (12134): Parameter "MULT_REPRESENTATION_A" = "UNSIGNED"
- Info (12134): Parameter "MULT_REPRESENTATION_B" = "UNSIGNED"
- Info (12134): Parameter "MULT_PIPELINE" = "0"
- Info (12134): Parameter "MULT_CLOCK" = "NONE"
- Info (12134): Parameter "MULT_CLEAR" = "NONE"
- Info (12134): Parameter "MULT_INPUT_A_IS_CONSTANT" = "NO"
- Info (12134): Parameter "MULT_INPUT_B_IS_CONSTANT" = "NO"
- Info (12134): Parameter "dataa_width" = "10"
- Info (12134): Parameter "datab_width" = "10"
- Info (12134): Parameter "output_width" = "20"
- Info (12134): Parameter "dataa_clock" = "NONE"
- Info (12134): Parameter "datab_clock" = "NONE"
- Info (12134): Parameter "signa_clock" = "NONE"
- Info (12134): Parameter "signb_clock" = "NONE"
- Info (12134): Parameter "output_clock" = "NONE"
- Info (12134): Parameter "dataa_clear" = "NONE"
- Info (12134): Parameter "datab_clear" = "NONE"
- Info (12134): Parameter "signa_clear" = "NONE"
- Info (12134): Parameter "signb_clear" = "NONE"
- Info (12134): Parameter "output_clear" = "NONE"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mac_mult_iug1.tdf
- Info (12023): Found entity 1: mac_mult_iug1
- Info (12021): Found 1 design units, including 1 entities, in source file db/mult_aql.tdf
- Info (12023): Found entity 1: mult_aql
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2" with the following parameter:
- Info (12134): Parameter "OPERATION_MODE" = "OUTPUT_ONLY"
- Info (12134): Parameter "dataa_width" = "20"
- Info (12134): Parameter "datab_width" = "0"
- Info (12134): Parameter "datac_width" = "0"
- Info (12134): Parameter "datad_width" = "0"
- Info (12134): Parameter "output_width" = "20"
- Info (12134): Parameter "signa_clock" = "NONE"
- Info (12134): Parameter "signb_clock" = "NONE"
- Info (12134): Parameter "addnsub0_clock" = "NONE"
- Info (12134): Parameter "addnsub1_clock" = "NONE"
- Info (12134): Parameter "zeroacc_clock" = "NONE"
- Info (12134): Parameter "first_adder0_clock" = "NONE"
- Info (12134): Parameter "first_adder1_clock" = "NONE"
- Info (12134): Parameter "output_clock" = "NONE"
- Info (12134): Parameter "signa_clear" = "NONE"
- Info (12134): Parameter "signb_clear" = "NONE"
- Info (12134): Parameter "addnsub0_clear" = "NONE"
- Info (12134): Parameter "addnsub1_clear" = "NONE"
- Info (12134): Parameter "zeroacc_clear" = "NONE"
- Info (12134): Parameter "first_adder0_clear" = "NONE"
- Info (12134): Parameter "first_adder1_clear" = "NONE"
- Info (12134): Parameter "output_clear" = "NONE"
- Info (12134): Parameter "signa_pipeline_clock" = "NONE"
- Info (12134): Parameter "signb_pipeline_clock" = "NONE"
- Info (12134): Parameter "addnsub0_pipeline_clock" = "NONE"
- Info (12134): Parameter "addnsub1_pipeline_clock" = "NONE"
- Info (12134): Parameter "zeroacc_pipeline_clock" = "NONE"
- Info (12134): Parameter "signa_pipeline_clear" = "NONE"
- Info (12134): Parameter "signb_pipeline_clear" = "NONE"
- Info (12134): Parameter "addnsub0_pipeline_clear" = "NONE"
- Info (12134): Parameter "addnsub1_pipeline_clear" = "NONE"
- Info (12134): Parameter "zeroacc_pipeline_clear" = "NONE"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mac_out_lr82.tdf
- Info (12023): Found entity 1: mac_out_lr82
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1" with the following parameter:
- Info (12134): Parameter "MULT_REPRESENTATION_A" = "UNSIGNED"
- Info (12134): Parameter "MULT_REPRESENTATION_B" = "UNSIGNED"
- Info (12134): Parameter "MULT_PIPELINE" = "0"
- Info (12134): Parameter "MULT_CLOCK" = "NONE"
- Info (12134): Parameter "MULT_CLEAR" = "NONE"
- Info (12134): Parameter "MULT_INPUT_A_IS_CONSTANT" = "NO"
- Info (12134): Parameter "MULT_INPUT_B_IS_CONSTANT" = "NO"
- Info (12134): Parameter "dataa_width" = "10"
- Info (12134): Parameter "datab_width" = "9"
- Info (12134): Parameter "output_width" = "19"
- Info (12134): Parameter "dataa_clock" = "NONE"
- Info (12134): Parameter "datab_clock" = "NONE"
- Info (12134): Parameter "signa_clock" = "NONE"
- Info (12134): Parameter "signb_clock" = "NONE"
- Info (12134): Parameter "output_clock" = "NONE"
- Info (12134): Parameter "dataa_clear" = "NONE"
- Info (12134): Parameter "datab_clear" = "NONE"
- Info (12134): Parameter "signa_clear" = "NONE"
- Info (12134): Parameter "signb_clear" = "NONE"
- Info (12134): Parameter "output_clear" = "NONE"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mac_mult_jtg1.tdf
- Info (12023): Found entity 1: mac_mult_jtg1
- Info (12021): Found 1 design units, including 1 entities, in source file db/mult_bpl.tdf
- Info (12023): Found entity 1: mult_bpl
- Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2"
- Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2" with the following parameter:
- Info (12134): Parameter "OPERATION_MODE" = "OUTPUT_ONLY"
- Info (12134): Parameter "dataa_width" = "19"
- Info (12134): Parameter "datab_width" = "0"
- Info (12134): Parameter "datac_width" = "0"
- Info (12134): Parameter "datad_width" = "0"
- Info (12134): Parameter "output_width" = "19"
- Info (12134): Parameter "signa_clock" = "NONE"
- Info (12134): Parameter "signb_clock" = "NONE"
- Info (12134): Parameter "addnsub0_clock" = "NONE"
- Info (12134): Parameter "addnsub1_clock" = "NONE"
- Info (12134): Parameter "zeroacc_clock" = "NONE"
- Info (12134): Parameter "first_adder0_clock" = "NONE"
- Info (12134): Parameter "first_adder1_clock" = "NONE"
- Info (12134): Parameter "output_clock" = "NONE"
- Info (12134): Parameter "signa_clear" = "NONE"
- Info (12134): Parameter "signb_clear" = "NONE"
- Info (12134): Parameter "addnsub0_clear" = "NONE"
- Info (12134): Parameter "addnsub1_clear" = "NONE"
- Info (12134): Parameter "zeroacc_clear" = "NONE"
- Info (12134): Parameter "first_adder0_clear" = "NONE"
- Info (12134): Parameter "first_adder1_clear" = "NONE"
- Info (12134): Parameter "output_clear" = "NONE"
- Info (12134): Parameter "signa_pipeline_clock" = "NONE"
- Info (12134): Parameter "signb_pipeline_clock" = "NONE"
- Info (12134): Parameter "addnsub0_pipeline_clock" = "NONE"
- Info (12134): Parameter "addnsub1_pipeline_clock" = "NONE"
- Info (12134): Parameter "zeroacc_pipeline_clock" = "NONE"
- Info (12134): Parameter "signa_pipeline_clear" = "NONE"
- Info (12134): Parameter "signb_pipeline_clear" = "NONE"
- Info (12134): Parameter "addnsub0_pipeline_clear" = "NONE"
- Info (12134): Parameter "addnsub1_pipeline_clear" = "NONE"
- Info (12134): Parameter "zeroacc_pipeline_clear" = "NONE"
- Info (12021): Found 1 design units, including 1 entities, in source file db/mac_out_5s82.tdf
- Info (12023): Found entity 1: mac_out_5s82
- Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition
- Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
- Info (13014): Ignored 585 buffer(s)
- Info (13016): Ignored 30 CARRY_SUM buffer(s)
- Info (13019): Ignored 555 SOFT buffer(s)
- Warning (13039): The following bidir pins have no drivers
- Warning (13040): Bidir "BAUD_RATE" has no driver
- Warning (13040): Bidir "TEST_SINGLE" has no driver
- Warning (13040): Bidir "UART1_RX" has no driver
- Warning (13040): Bidir "so_io1" has no driver
- Info (13000): Registers with preset signals will power-up high
- Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
- Warning (13008): TRI or OPNDRN buffers permanently disabled
- Warning (13010): Node "BAUD_RATE~synth"
- Warning (13010): Node "TEST_SINGLE~synth"
- Warning (13010): Node "UART1_RX~synth"
- Warning (13010): Node "so_io1~synth"
- Info (286031): Timing-Driven Synthesis is running on partition "Top"
- Info (17049): 3 registers lost all their fanouts during netlist optimizations.
- Info (17016): Found the following redundant logic cells in design
- Info (17048): Logic cell "sys_ctrl_stop"
- Info (17048): Logic cell "gpio0_io_in[0]"
- Info (17048): Logic cell "gpio4_io_in[1]"
- Info (17048): Logic cell "gpio4_io_in[2]"
- Info (17048): Logic cell "gpio6_io_in[1]"
- Info (17048): Logic cell "gpio6_io_in[3]"
- Info (17048): Logic cell "gpio4_io_out_data[6]"
- Info (17048): Logic cell "gpio4_io_out_en[6]"
- Info (17048): Logic cell "gpio4_io_out_data[5]"
- Info (17048): Logic cell "gpio4_io_out_en[5]"
- Info (17048): Logic cell "gpio7_io_out_data[6]"
- Info (17048): Logic cell "gpio7_io_out_en[6]"
- Info (17048): Logic cell "sys_resetn"
- Info (17048): Logic cell "sys_ctrl_clkSource[0]"
- Info (17048): Logic cell "sys_ctrl_clkSource[1]"
- Info (17048): Logic cell "gpio4_io_out_data[1]"
- Info (17048): Logic cell "gpio4_io_out_en[1]"
- Info (17048): Logic cell "gpio4_io_out_data[2]"
- Info (17048): Logic cell "gpio4_io_out_en[2]"
- Info (17048): Logic cell "gpio0_io_out_data[0]"
- Info (17048): Logic cell "gpio0_io_out_en[0]"
- Info (17048): Logic cell "gpio8_io_out_data[0]"
- Info (17048): Logic cell "gpio8_io_out_en[0]"
- Info (17048): Logic cell "PLL_ENABLE"
- Warning (15899): PLL "altpll:pll_inst|altpll_6o32:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
- Info (128000): Starting physical synthesis optimizations for speed
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 4 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 125.000 PIN_HSE
- Info (332111): 100.000 PIN_HSI
- Info (332111): 125.000 PLL_CLKIN
- Info (332111): 9.615 pll_inst|auto_generated|pll1|clk[0]
- Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
- Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
- Info (21057): Implemented 1764 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 4 input pins
- Info (21059): Implemented 3 output pins
- Info (21060): Implemented 8 bidirectional pins
- Info (21061): Implemented 1728 logic cells
- Info (21064): Implemented 16 RAM segments
- Info (21065): Implemented 1 PLLs
- Info (21071): Implemented 3 partitions
- Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 11 warnings
- Info: Peak virtual memory: 4703 megabytes
- Info: Processing ended: Sat May 09 14:18:46 2026
- Info: Elapsed time: 00:00:09
- Info: Total CPU time (on all processors): 00:00:15
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 14:18:37 2026
- Info: Command: quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board
- Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
- Info (281019): Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_adc0_inst_adc_inst
- Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
- Info (128000): Starting physical synthesis optimizations for speed
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 3 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 100.000 PIN_HSI
- Info (332111): 125.000 PLL_CLKIN
- Info (332111): 9.615 pll_inst|auto_generated|pll1|clk[0]
- Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
- Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
- Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 8 input pins
- Info (21059): Implemented 13 output pins
- Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4684 megabytes
- Info: Processing ended: Sat May 09 14:18:39 2026
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:08
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 14:18:37 2026
- Info: Command: quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board
- Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
- Info (281019): Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_dac0_inst_dac_inst
- Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
- Info (128000): Starting physical synthesis optimizations for speed
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 3 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 100.000 PIN_HSI
- Info (332111): 125.000 PLL_CLKIN
- Info (332111): 9.615 pll_inst|auto_generated|pll1|clk[0]
- Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
- Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
- Info (21057): Implemented 14 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 13 input pins
- Info (21059): Implemented 1 output pins
- Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4684 megabytes
- Info: Processing ended: Sat May 09 14:18:39 2026
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:08
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 14:18:37 2026
- Info: Command: quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board
- Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
- Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
- Info (281019): Starting Logic Optimization and Technology Mapping for Partition rv32
- Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
- Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[4]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[5]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[6]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[7]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|dmactive" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGNSW" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[3]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[0]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[1]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[2]" is stuck at GND
- Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[3]" is stuck at GND
- Info (128000): Starting physical synthesis optimizations for speed
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 3 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 100.000 PIN_HSI
- Info (332111): 125.000 PLL_CLKIN
- Info (332111): 9.615 pll_inst|auto_generated|pll1|clk[0]
- Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
- Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
- Info (21057): Implemented 520 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 224 input pins
- Info (21059): Implemented 295 output pins
- Info (21061): Implemented 1 logic cells
- Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings
- Info: Peak virtual memory: 4684 megabytes
- Info: Processing ended: Sat May 09 14:18:39 2026
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:09
- Info (281038): Finished parallel synthesis of all partitions
- Info (144001): Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg
- Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1282 warnings
- Info: Peak virtual memory: 4640 megabytes
- Info: Processing ended: Sat May 09 14:18:46 2026
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:18
- +------------------------------------------+
- ; Analysis & Synthesis Suppressed Messages ;
- +------------------------------------------+
- The suppressed messages can be found in D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg.
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