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example_board.map.rpt

example_board.map.rpt 385 KB
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
  1. Analysis & Synthesis report for example_board
    2. 

  2. Sat May 09 14:18:46 2026
    3. 

  3. Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    4. 

  4. 

  5. 

  6. ---------------------
    7. 

  7. ; Table of Contents ;
    8. 

  8. ---------------------
    9. 

  9.   1. Legal Notice
    10. 

  10.   2. Analysis & Synthesis Summary
    11. 

  11.   3. Analysis & Synthesis Settings
    12. 

  12.   4. Parallel Compilation
    13. 

  13.   5. Analysis & Synthesis Source Files Read
    14. 

  14.   6. Partition Status Summary
    15. 

  15.   7. Partition for Top-Level Resource Utilization by Entity
    16. 

  16.   8. State Machine - |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state
    17. 

  17.   9. State Machine - |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState
    18. 

  18.  10. Registers Removed During Synthesis
    19. 

  19.  11. Multiplexer Restructuring Statistics (Restructuring Performed)
    20. 

  20.  12. Source assignments for Top-level Entity: |example_board
    21. 

  21.  13. Source assignments for analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated
    22. 

  22.  14. Parameter Settings for User Entity Instance: altpll:pll_inst
    23. 

  23.  15. Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst
    24. 

  24.  16. Parameter Settings for User Entity Instance: analog_ip:macro_inst
    25. 

  25.  17. Parameter Settings for User Entity Instance: analog_ip:macro_inst|ahb2apb:ahb2apb_inst
    26. 

  26.  18. Parameter Settings for User Entity Instance: analog_ip:macro_inst|cfg_reg:cfg_reg_inst
    27. 

  27.  19. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst
    28. 

  28.  20. Parameter Settings for User Entity Instance: analog_ip:macro_inst|baud_detect:u_baud_detect
    29. 

  29.  21. Parameter Settings for User Entity Instance: analog_ip:macro_inst|altsyncram:u_dual_port_ram
    30. 

  30.  22. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb2ram:u_apb2ram
    31. 

  31.  23. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0
    32. 

  32.  24. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2
    33. 

  33.  25. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3
    34. 

  34.  26. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1
    35. 

  35.  27. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2
    36. 

  36.  28. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1
    37. 

  37.  29. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2
    38. 

  38.  30. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1
    39. 

  39.  31. Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_out:mac_out2
    40. 

  40.  32. Partition Dependent Files
    41. 

  41.  33. Partition "macro_inst_apb_adc0_inst_adc_inst" Resource Utilization by Entity
    42. 

  42.  34. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
    43. 

  43.  35. Partition Dependent Files
    44. 

  44.  36. Partition "macro_inst_apb_dac0_inst_dac_inst" Resource Utilization by Entity
    45. 

  45.  37. Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
    46. 

  46.  38. Partition Dependent Files
    47. 

  47.  39. Partition "rv32" Resource Utilization by Entity
    48. 

  48.  40. Parameter Settings for User Entity Instance: alta_rv32:rv32
    49. 

  49.  41. Partition Dependent Files
    50. 

  50.  42. Port Connectivity Checks: "alta_rv32:rv32"
    51. 

  51.  43. Port Connectivity Checks: "analog_ip:macro_inst|apb2ram:u_apb2ram"
    52. 

  52.  44. Port Connectivity Checks: "analog_ip:macro_inst|baud_detect:u_baud_detect"
    53. 

  53.  45. Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst"
    54. 

  54.  46. Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst"
    55. 

  55.  47. Port Connectivity Checks: "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"
    56. 

  56.  48. Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst"
    57. 

  57.  49. Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst"
    58. 

  58.  50. Port Connectivity Checks: "analog_ip:macro_inst|ahb2apb:ahb2apb_inst"
    59. 

  59.  51. Port Connectivity Checks: "alta_gclksw:gclksw_inst"
    60. 

  60.  52. Elapsed Time Per Partition
    61. 

  61.  53. Analysis & Synthesis Messages
    62. 

  62.  54. Analysis & Synthesis Suppressed Messages
    63. 

  63. 

  64. 

  65. 

  66. ----------------
    67. 

  67. ; Legal Notice ;
    68. 

  68. ----------------
    69. 

  69. Copyright (C) 1991-2013 Altera Corporation
    70. 

  70. Your use of Altera Corporation's design tools, logic functions 
    71. 

  71. and other software and tools, and its AMPP partner logic 
    72. 

  72. functions, and any output files from any of the foregoing 
    73. 

  73. (including device programming or simulation files), and any 
    74. 

  74. associated documentation or information are expressly subject 
    75. 

  75. to the terms and conditions of the Altera Program License 
    76. 

  76. Subscription Agreement, Altera MegaCore Function License 
    77. 

  77. Agreement, or other applicable license agreement, including, 
    78. 

  78. without limitation, that your use is for the sole purpose of 
    79. 

  79. programming logic devices manufactured by Altera and sold by 
    80. 

  80. Altera or its authorized distributors.  Please refer to the 
    81. 

  81. applicable agreement for further details.
    82. 

  82. 

  83. 

  84. 

  85. +----------------------------------------------------------------------------------+
    86. 

  86. ; Analysis & Synthesis Summary                                                     ;
    87. 

  87. +------------------------------------+---------------------------------------------+
    88. 

  88. ; Analysis & Synthesis Status        ; Successful - Sat May 09 14:18:46 2026       ;
    89. 

  89. ; Quartus II 64-Bit Version          ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
    90. 

  90. ; Revision Name                      ; example_board                               ;
    91. 

  91. ; Top-level Entity Name              ; example_board                               ;
    92. 

  92. ; Family                             ; Cyclone IV E                                ;
    93. 

  93. ; Total logic elements               ; N/A until Partition Merge                   ;
    94. 

  94. ;     Total combinational functions  ; N/A until Partition Merge                   ;
    95. 

  95. ;     Dedicated logic registers      ; N/A until Partition Merge                   ;
    96. 

  96. ; Total registers                    ; N/A until Partition Merge                   ;
    97. 

  97. ; Total pins                         ; N/A until Partition Merge                   ;
    98. 

  98. ; Total virtual pins                 ; N/A until Partition Merge                   ;
    99. 

  99. ; Total memory bits                  ; N/A until Partition Merge                   ;
    100. 

  100. ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                   ;
    101. 

  101. ; Total PLLs                         ; N/A until Partition Merge                   ;
    102. 

  102. +------------------------------------+---------------------------------------------+
    103. 

  103. 

  104. 

  105. +----------------------------------------------------------------------------------------------------------------------+
    106. 

  106. ; Analysis & Synthesis Settings                                                                                        ;
    107. 

  107. +----------------------------------------------------------------------------+--------------------+--------------------+
    108. 

  108. ; Option                                                                     ; Setting            ; Default Value      ;
    109. 

  109. +----------------------------------------------------------------------------+--------------------+--------------------+
    110. 

  110. ; Device                                                                     ; EP4CE75F29C8       ;                    ;
    111. 

  111. ; Top-level entity name                                                      ; example_board      ; example_board      ;
    112. 

  112. ; Family name                                                                ; Cyclone IV E       ; Cyclone IV GX      ;
    113. 

  113. ; Maximum processors allowed for parallel compilation                        ; All                ;                    ;
    114. 

  114. ; Maximum DSP Block Usage                                                    ; 0                  ; -1 (Unlimited)     ;
    115. 

  115. ; Auto Open-Drain Pins                                                       ; Off                ; On                 ;
    116. 

  116. ; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
    117. 

  117. ; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks                          ; 4                  ; -1 (Unlimited)     ;
    118. 

  118. ; Use smart compilation                                                      ; Off                ; Off                ;
    119. 

  119. ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
    120. 

  120. ; Enable compact report table                                                ; Off                ; Off                ;
    121. 

  121. ; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
    122. 

  122. ; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
    123. 

  123. ; Preserve fewer node names                                                  ; On                 ; On                 ;
    124. 

  124. ; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
    125. 

  125. ; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
    126. 

  126. ; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
    127. 

  127. ; State Machine Processing                                                   ; Auto               ; Auto               ;
    128. 

  128. ; Safe State Machine                                                         ; Off                ; Off                ;
    129. 

  129. ; Extract Verilog State Machines                                             ; On                 ; On                 ;
    130. 

  130. ; Extract VHDL State Machines                                                ; On                 ; On                 ;
    131. 

  131. ; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
    132. 

  132. ; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
    133. 

  133. ; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
    134. 

  134. ; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
    135. 

  135. ; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
    136. 

  136. ; Parallel Synthesis                                                         ; On                 ; On                 ;
    137. 

  137. ; DSP Block Balancing                                                        ; Auto               ; Auto               ;
    138. 

  138. ; NOT Gate Push-Back                                                         ; On                 ; On                 ;
    139. 

  139. ; Power-Up Don't Care                                                        ; On                 ; On                 ;
    140. 

  140. ; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
    141. 

  141. ; Remove Duplicate Registers                                                 ; On                 ; On                 ;
    142. 

  142. ; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
    143. 

  143. ; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
    144. 

  144. ; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
    145. 

  145. ; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
    146. 

  146. ; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
    147. 

  147. ; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
    148. 

  148. ; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
    149. 

  149. ; Optimization Technique                                                     ; Balanced           ; Balanced           ;
    150. 

  150. ; Carry Chain Length                                                         ; 70                 ; 70                 ;
    151. 

  151. ; Auto Carry Chains                                                          ; On                 ; On                 ;
    152. 

  152. ; Auto ROM Replacement                                                       ; On                 ; On                 ;
    153. 

  153. ; Auto RAM Replacement                                                       ; On                 ; On                 ;
    154. 

  154. ; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
    155. 

  155. ; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
    156. 

  156. ; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
    157. 

  157. ; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
    158. 

  158. ; Strict RAM Replacement                                                     ; Off                ; Off                ;
    159. 

  159. ; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
    160. 

  160. ; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
    161. 

  161. ; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
    162. 

  162. ; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
    163. 

  163. ; Auto Resource Sharing                                                      ; Off                ; Off                ;
    164. 

  164. ; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
    165. 

  165. ; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
    166. 

  166. ; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
    167. 

  167. ; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
    168. 

  168. ; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
    169. 

  169. ; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
    170. 

  170. ; Report Parameter Settings                                                  ; On                 ; On                 ;
    171. 

  171. ; Report Source Assignments                                                  ; On                 ; On                 ;
    172. 

  172. ; Report Connectivity Checks                                                 ; On                 ; On                 ;
    173. 

  173. ; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
    174. 

  174. ; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
    175. 

  175. ; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
    176. 

  176. ; HDL message level                                                          ; Level2             ; Level2             ;
    177. 

  177. ; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
    178. 

  178. ; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
    179. 

  179. ; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
    180. 

  180. ; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
    181. 

  181. ; Clock MUX Protection                                                       ; On                 ; On                 ;
    182. 

  182. ; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
    183. 

  183. ; Block Design Naming                                                        ; Auto               ; Auto               ;
    184. 

  184. ; SDC constraint protection                                                  ; Off                ; Off                ;
    185. 

  185. ; Synthesis Effort                                                           ; Auto               ; Auto               ;
    186. 

  186. ; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
    187. 

  187. ; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
    188. 

  188. ; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
    189. 

  189. ; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
    190. 

  190. ; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
    191. 

  191. ; Synthesis Seed                                                             ; 1                  ; 1                  ;
    192. 

  192. +----------------------------------------------------------------------------+--------------------+--------------------+
    193. 

  193. 

  194. 

  195. +------------------------------------------+
    196. 

  196. ; Parallel Compilation                     ;
    197. 

  197. +----------------------------+-------------+
    198. 

  198. ; Processors                 ; Number      ;
    199. 

  199. +----------------------------+-------------+
    200. 

  200. ; Number detected on machine ; 8           ;
    201. 

  201. ; Maximum allowed            ; 4           ;
    202. 

  202. ;                            ;             ;
    203. 

  203. ; Average used               ; 3.73        ;
    204. 

  204. ; Maximum used               ; 4           ;
    205. 

  205. ;                            ;             ;
    206. 

  206. ; Usage by Processor         ; % Time Used ;
    207. 

  207. ;     Processor 1            ; 100.0%      ;
    208. 

  208. ;     Processors 2-4         ;  90.9%      ;
    209. 

  209. ;     Processors 5-8         ;   0.0%      ;
    210. 

  210. +----------------------------+-------------+
    211. 

  211. 

  212. 

  213. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    214. 

  214. ; Analysis & Synthesis Source Files Read                                                                                                                                                                                                      ;
    215. 

  215. +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
    216. 

  216. ; File Name with User-Entered Path                                                ; Used in Netlist ; File Type                                   ; File Name with Absolute Path                                                    ; Library ;
    217. 

  217. +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
    218. 

  218. ; trig_ctrl.v                                                                     ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v                     ;         ;
    219. 

  219. ; cfg_reg.v                                                                       ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v                       ;         ;
    220. 

  220. ; apb2ram.v                                                                       ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v                       ;         ;
    221. 

  221. ; baud_detect.v                                                                   ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v                   ;         ;
    222. 

  222. ; ahb2apb.v                                                                       ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v                       ;         ;
    223. 

  223. ; example_board.v                                                                 ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v                 ;         ;
    224. 

  224. ; analog_ip.v                                                                     ; yes             ; User Verilog HDL File                       ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v                     ;         ;
    225. 

  225. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; yes             ; User Verilog HDL File                       ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ;         ;
    226. 

  226. ; sine.hex                                                                        ; yes             ; Auto-Found Hexadecimal (Intel-Format) File  ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex                        ;         ;
    227. 

  227. ; altpll.tdf                                                                      ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf                       ;         ;
    228. 

  228. ; aglobal130.inc                                                                  ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc                   ;         ;
    229. 

  229. ; stratix_pll.inc                                                                 ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc                  ;         ;
    230. 

  230. ; stratixii_pll.inc                                                               ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc                ;         ;
    231. 

  231. ; cycloneii_pll.inc                                                               ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc                ;         ;
    232. 

  232. ; db/altpll_6o32.tdf                                                              ; yes             ; Auto-Generated Megafunction                 ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf              ;         ;
    233. 

  233. ; altsyncram.tdf                                                                  ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/altsyncram.tdf                   ;         ;
    234. 

  234. ; stratix_ram_block.inc                                                           ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_ram_block.inc            ;         ;
    235. 

  235. ; lpm_mux.inc                                                                     ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_mux.inc                      ;         ;
    236. 

  236. ; lpm_decode.inc                                                                  ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/lpm_decode.inc                   ;         ;
    237. 

  237. ; a_rdenreg.inc                                                                   ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/a_rdenreg.inc                    ;         ;
    238. 

  238. ; altrom.inc                                                                      ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/altrom.inc                       ;         ;
    239. 

  239. ; altram.inc                                                                      ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/altram.inc                       ;         ;
    240. 

  240. ; altdpram.inc                                                                    ; yes             ; Megafunction                                ; c:/altera/13.0/quartus/libraries/megafunctions/altdpram.inc                     ;         ;
    241. 

  241. ; db/altsyncram_sgu1.tdf                                                          ; yes             ; Auto-Generated Megafunction                 ; D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altsyncram_sgu1.tdf          ;         ;
    242. 

  242. +---------------------------------------------------------------------------------+-----------------+---------------------------------------------+---------------------------------------------------------------------------------+---------+
    243. 

  243. 

  244. 

  245. +------------------------------------------------------------------------------+
    246. 

  246. ; Partition Status Summary                                                     ;
    247. 

  247. +-----------------------------------+-------------+----------------------------+
    248. 

  248. ; Partition Name                    ; Synthesized ; Reason                     ;
    249. 

  249. +-----------------------------------+-------------+----------------------------+
    250. 

  250. ; Top                               ; yes         ; netlist type = Source File ;
    251. 

  251. ; macro_inst_apb_adc0_inst_adc_inst ; yes         ; netlist type = Source File ;
    252. 

  252. ; macro_inst_apb_dac0_inst_dac_inst ; yes         ; netlist type = Source File ;
    253. 

  253. ; rv32                              ; yes         ; netlist type = Source File ;
    254. 

  254. +-----------------------------------+-------------+----------------------------+
    255. 

  255. 

  256. 

  257. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    258. 

  258. ; Partition for Top-Level Resource Utilization by Entity                                                                                                                                                                                                                                                                                            ;
    259. 

  259. +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
    260. 

  260. ; Compilation Hierarchy Node                       ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                                 ; Library Name ;
    261. 

  261. +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
    262. 

  262. ; |example_board                                   ; 1530 (46)         ; 484 (0)      ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board                                                                                                                                                      ; work         ;
    263. 

  263. ;    |alta_gclksw:gclksw_inst|                     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|alta_gclksw:gclksw_inst                                                                                                                              ; work         ;
    264. 

  264. ;    |altpll:pll_inst|                             ; 0 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|altpll:pll_inst                                                                                                                                      ; work         ;
    265. 

  265. ;       |altpll_6o32:auto_generated|               ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|altpll:pll_inst|altpll_6o32:auto_generated                                                                                                           ; work         ;
    266. 

  266. ;    |analog_ip:macro_inst|                        ; 1484 (30)         ; 483 (4)      ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst                                                                                                                                 ; work         ;
    267. 

  267. ;       |ahb2apb:ahb2apb_inst|                     ; 25 (25)           ; 74 (74)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst                                                                                                            ; work         ;
    268. 

  268. ;       |altsyncram:u_dual_port_ram|               ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|altsyncram:u_dual_port_ram                                                                                                      ; work         ;
    269. 

  269. ;          |altsyncram_sgu1:auto_generated|        ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated                                                                       ; work         ;
    270. 

  270. ;       |apb2ram:u_apb2ram|                        ; 2 (2)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb2ram:u_apb2ram                                                                                                               ; work         ;
    271. 

  271. ;       |apb_adc:apb_adc0_inst|                    ; 27 (27)           ; 30 (30)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst                                                                                                           ; work         ;
    272. 

  272. ;       |apb_dac:apb_dac0_inst|                    ; 904 (488)         ; 62 (62)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst                                                                                                           ; work         ;
    273. 

  273. ;          |lpm_mult:Mult0|                        ; 149 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0                                                                                            ; work         ;
    274. 

  274. ;             |mult_oct:auto_generated|            ; 149 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated                                                                    ; work         ;
    275. 

  275. ;                |alt_mac_mult:mac_mult1|          ; 149 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1                                             ; work         ;
    276. 

  276. ;                   |mac_mult_iug1:auto_generated| ; 149 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated                ; work         ;
    277. 

  277. ;                      |mult_aql:mult1|            ; 149 (149)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated|mult_aql:mult1 ; work         ;
    278. 

  278. ;          |lpm_mult:Mult2|                        ; 124 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2                                                                                            ; work         ;
    279. 

  279. ;             |mult_pbt:auto_generated|            ; 124 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated                                                                    ; work         ;
    280. 

  280. ;                |alt_mac_mult:mac_mult1|          ; 124 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1                                             ; work         ;
    281. 

  281. ;                   |mac_mult_jtg1:auto_generated| ; 124 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1|mac_mult_jtg1:auto_generated                ; work         ;
    282. 

  282. ;                      |mult_bpl:mult1|            ; 124 (124)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1|mac_mult_jtg1:auto_generated|mult_bpl:mult1 ; work         ;
    283. 

  283. ;          |lpm_mult:Mult3|                        ; 143 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3                                                                                            ; work         ;
    284. 

  284. ;             |mult_oct:auto_generated|            ; 143 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated                                                                    ; work         ;
    285. 

  285. ;                |alt_mac_mult:mac_mult1|          ; 143 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1                                             ; work         ;
    286. 

  286. ;                   |mac_mult_iug1:auto_generated| ; 143 (0)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated                ; work         ;
    287. 

  287. ;                      |mult_aql:mult1|            ; 143 (143)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1|mac_mult_iug1:auto_generated|mult_aql:mult1 ; work         ;
    288. 

  288. ;       |cfg_reg:cfg_reg_inst|                     ; 155 (155)         ; 164 (164)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst                                                                                                            ; work         ;
    289. 

  289. ;       |trig_ctrl:trig_ctrl_inst|                 ; 341 (341)         ; 149 (149)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst                                                                                                        ; work         ;
    290. 

  290. +--------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
    291. 

  291. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    292. 

  292. 

  293. 

  294. Encoding Type:  One-Hot
    295. 

  295. +-----------------------------------------------------------------------------------------------------------------------------+
    296. 

  296. ; State Machine - |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state                                     ;
    297. 

  297. +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
    298. 

  298. ; Name                 ; curr_state.POST_TRIG ; curr_state.SAMPLING ; curr_state.PRE_FILL ; curr_state.IDLE ; curr_state.DONE ;
    299. 

  299. +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
    300. 

  300. ; curr_state.IDLE      ; 0                    ; 0                   ; 0                   ; 0               ; 0               ;
    301. 

  301. ; curr_state.PRE_FILL  ; 0                    ; 0                   ; 1                   ; 1               ; 0               ;
    302. 

  302. ; curr_state.SAMPLING  ; 0                    ; 1                   ; 0                   ; 1               ; 0               ;
    303. 

  303. ; curr_state.POST_TRIG ; 1                    ; 0                   ; 0                   ; 1               ; 0               ;
    304. 

  304. ; curr_state.DONE      ; 0                    ; 0                   ; 0                   ; 1               ; 1               ;
    305. 

  305. +----------------------+----------------------+---------------------+---------------------+-----------------+-----------------+
    306. 

  306. 

  307. 

  308. Encoding Type:  One-Hot
    309. 

  309. +-----------------------------------------------------------------------------------+
    310. 

  310. ; State Machine - |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState ;
    311. 

  311. +--------------------+------------------+--------------------+----------------------+
    312. 

  312. ; Name               ; apbState.apbIdle ; apbState.apbAccess ; apbState.apbSetup    ;
    313. 

  313. +--------------------+------------------+--------------------+----------------------+
    314. 

  314. ; apbState.apbIdle   ; 0                ; 0                  ; 0                    ;
    315. 

  315. ; apbState.apbSetup  ; 1                ; 0                  ; 1                    ;
    316. 

  316. ; apbState.apbAccess ; 1                ; 1                  ; 0                    ;
    317. 

  317. +--------------------+------------------+--------------------+----------------------+
    318. 

  318. 

  319. 

  320. +-----------------------------------------------------------------------------------------------------------------------------------------------------+
    321. 

  321. ; Registers Removed During Synthesis                                                                                                                  ;
    322. 

  322. +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
    323. 

  323. ; Register name                                                            ; Reason for Removal                                                       ;
    324. 

  324. +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
    325. 

  325. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|decim_factor[12,15]        ; Stuck at GND due to stuck port data_in                                   ;
    326. 

  326. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[10..31]             ; Stuck at GND due to stuck port data_in                                   ;
    327. 

  327. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[12..15]      ; Stuck at GND due to stuck port data_in                                   ;
    328. 

  328. ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hresp                          ; Stuck at GND due to stuck port data_in                                   ;
    329. 

  329. ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_msb_r                   ; Merged with analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[9]        ;
    330. 

  330. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[8] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ;
    331. 

  331. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[7] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ;
    332. 

  332. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[6] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ;
    333. 

  333. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[5] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ;
    334. 

  334. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[4] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ;
    335. 

  335. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[3] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ;
    336. 

  336. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[2] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ;
    337. 

  337. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[1] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ;
    338. 

  338. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[0] ; Merged with analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ;
    339. 

  339. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state~4               ; Lost fanout                                                              ;
    340. 

  340. ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state~5               ; Lost fanout                                                              ;
    341. 

  341. ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbAccess             ; Lost fanout                                                              ;
    342. 

  342. ; Total Number of Removed Registers = 42                                   ;                                                                          ;
    343. 

  343. +--------------------------------------------------------------------------+--------------------------------------------------------------------------+
    344. 

  344. 

  345. 

  346. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    347. 

  347. ; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                               ;
    348. 

  348. +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
    349. 

  349. ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                     ;
    350. 

  350. +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
    351. 

  351. ; 3:1                ; 17 bits   ; 34 LEs        ; 0 LEs                ; 34 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7]              ;
    352. 

  352. ; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6]    ;
    353. 

  353. ; 3:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[7]      ;
    354. 

  354. ; 4:1                ; 12 bits   ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[10] ;
    355. 

  355. ; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29]            ;
    356. 

  356. ; 4:1                ; 6 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14]            ;
    357. 

  357. ; 4:1                ; 16 bits   ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8]        ;
    358. 

  358. ; 5:1                ; 9 bits    ; 27 LEs        ; 9 LEs                ; 18 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|post_trig_cnt[8]  ;
    359. 

  359. ; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12]            ;
    360. 

  360. ; 5:1                ; 11 bits   ; 33 LEs        ; 11 LEs               ; 22 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2]    ;
    361. 

  361. ; 6:1                ; 11 bits   ; 44 LEs        ; 11 LEs               ; 33 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2]   ;
    362. 

  362. ; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[10]            ;
    363. 

  363. ; 18:1               ; 10 bits   ; 120 LEs       ; 20 LEs               ; 100 LEs                ; Yes        ; |example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9]             ;
    364. 

  364. ; 6:1                ; 10 bits   ; 40 LEs        ; 10 LEs               ; 30 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[7]  ;
    365. 

  365. ; 9:1                ; 3 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[5]             ;
    366. 

  366. ; 10:1               ; 16 bits   ; 96 LEs        ; 16 LEs               ; 80 LEs                 ; Yes        ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[12]     ;
    367. 

  367. ; 10:1               ; 3 bits    ; 18 LEs        ; 18 LEs               ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[4]             ;
    368. 

  368. ; 13:1               ; 2 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; Yes        ; |example_board|analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[1]             ;
    369. 

  369. ; 7:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; No         ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mux7                 ;
    370. 

  370. ; 13:1               ; 5 bits    ; 40 LEs        ; 30 LEs               ; 10 LEs                 ; No         ; |example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|Selector0         ;
    371. 

  371. +--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------+
    372. 

  372. 

  373. 

  374. +---------------------------------------------------------------------+
    375. 

  375. ; Source assignments for Top-level Entity: |example_board             ;
    376. 

  376. +------------------------------+-------+------+-----------------------+
    377. 

  377. ; Assignment                   ; Value ; From ; To                    ;
    378. 

  378. +------------------------------+-------+------+-----------------------+
    379. 

  379. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[7]        ;
    380. 

  380. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[7]        ;
    381. 

  381. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[6]        ;
    382. 

  382. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[6]        ;
    383. 

  383. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[5]        ;
    384. 

  384. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[5]        ;
    385. 

  385. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[4]        ;
    386. 

  386. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[4]        ;
    387. 

  387. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[3]        ;
    388. 

  388. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[3]        ;
    389. 

  389. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[2]        ;
    390. 

  390. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[2]        ;
    391. 

  391. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[1]        ;
    392. 

  392. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[1]        ;
    393. 

  393. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_in[0]        ;
    394. 

  394. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_in[0]        ;
    395. 

  395. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[7]        ;
    396. 

  396. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[7]        ;
    397. 

  397. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[6]        ;
    398. 

  398. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[6]        ;
    399. 

  399. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[5]        ;
    400. 

  400. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[5]        ;
    401. 

  401. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[4]        ;
    402. 

  402. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[4]        ;
    403. 

  403. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[3]        ;
    404. 

  404. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[3]        ;
    405. 

  405. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[2]        ;
    406. 

  406. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[2]        ;
    407. 

  407. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[1]        ;
    408. 

  408. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[1]        ;
    409. 

  409. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[0]        ;
    410. 

  410. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[0]        ;
    411. 

  411. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[7]        ;
    412. 

  412. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[7]        ;
    413. 

  413. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[6]        ;
    414. 

  414. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[6]        ;
    415. 

  415. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[5]        ;
    416. 

  416. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[5]        ;
    417. 

  417. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[4]        ;
    418. 

  418. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[4]        ;
    419. 

  419. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[3]        ;
    420. 

  420. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[3]        ;
    421. 

  421. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[2]        ;
    422. 

  422. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[2]        ;
    423. 

  423. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[1]        ;
    424. 

  424. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[1]        ;
    425. 

  425. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[0]        ;
    426. 

  426. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[0]        ;
    427. 

  427. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; PLL_ENABLE            ;
    428. 

  428. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; PLL_ENABLE            ;
    429. 

  429. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; PLL_LOCK              ;
    430. 

  430. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; PLL_LOCK              ;
    431. 

  431. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_resetn            ;
    432. 

  432. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_resetn            ;
    433. 

  433. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_stop         ;
    434. 

  434. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_stop         ;
    435. 

  435. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_clkSource[1] ;
    436. 

  436. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_clkSource[1] ;
    437. 

  437. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_clkSource[0] ;
    438. 

  438. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_clkSource[0] ;
    439. 

  439. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_out_data[1]  ;
    440. 

  440. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_out_data[1]  ;
    441. 

  441. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_out_data[0]  ;
    442. 

  442. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_out_data[0]  ;
    443. 

  443. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_out_en[1]    ;
    444. 

  444. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_out_en[1]    ;
    445. 

  445. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio0_io_out_en[0]    ;
    446. 

  446. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio0_io_out_en[0]    ;
    447. 

  447. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_data[6]  ;
    448. 

  448. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_data[6]  ;
    449. 

  449. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_data[5]  ;
    450. 

  450. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_data[5]  ;
    451. 

  451. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_data[2]  ;
    452. 

  452. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_data[2]  ;
    453. 

  453. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_data[1]  ;
    454. 

  454. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_data[1]  ;
    455. 

  455. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_en[6]    ;
    456. 

  456. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_en[6]    ;
    457. 

  457. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_en[5]    ;
    458. 

  458. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_en[5]    ;
    459. 

  459. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_en[2]    ;
    460. 

  460. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_en[2]    ;
    461. 

  461. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_out_en[1]    ;
    462. 

  462. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_out_en[1]    ;
    463. 

  463. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_out_data[6]  ;
    464. 

  464. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_out_data[6]  ;
    465. 

  465. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_out_en[6]    ;
    466. 

  466. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_out_en[6]    ;
    467. 

  467. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[0]  ;
    468. 

  468. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[0]  ;
    469. 

  469. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[0]    ;
    470. 

  470. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[0]    ;
    471. 

  471. +------------------------------+-------+------+-----------------------+
    472. 

  472. 

  473. 

  474. +-------------------------------------------------------------------------------------------------------+
    475. 

  475. ; Source assignments for analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated ;
    476. 

  476. +---------------------------------+--------------------+------+-----------------------------------------+
    477. 

  477. ; Assignment                      ; Value              ; From ; To                                      ;
    478. 

  478. +---------------------------------+--------------------+------+-----------------------------------------+
    479. 

  479. ; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                       ;
    480. 

  480. +---------------------------------+--------------------+------+-----------------------------------------+
    481. 

  481. 

  482. 

  483. +--------------------------------------------------------------------+
    484. 

  484. ; Parameter Settings for User Entity Instance: altpll:pll_inst       ;
    485. 

  485. +-------------------------------+-------------------+----------------+
    486. 

  486. ; Parameter Name                ; Value             ; Type           ;
    487. 

  487. +-------------------------------+-------------------+----------------+
    488. 

  488. ; OPERATION_MODE                ; NORMAL            ; Untyped        ;
    489. 

  489. ; PLL_TYPE                      ; AUTO              ; Untyped        ;
    490. 

  490. ; LPM_HINT                      ; UNUSED            ; Untyped        ;
    491. 

  491. ; QUALIFY_CONF_DONE             ; OFF               ; Untyped        ;
    492. 

  492. ; COMPENSATE_CLOCK              ; CLK0              ; Untyped        ;
    493. 

  493. ; SCAN_CHAIN                    ; LONG              ; Untyped        ;
    494. 

  494. ; PRIMARY_CLOCK                 ; INCLK0            ; Untyped        ;
    495. 

  495. ; INCLK0_INPUT_FREQUENCY        ; 125000            ; Signed Integer ;
    496. 

  496. ; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped        ;
    497. 

  497. ; GATE_LOCK_SIGNAL              ; NO                ; Untyped        ;
    498. 

  498. ; GATE_LOCK_COUNTER             ; 0                 ; Untyped        ;
    499. 

  499. ; LOCK_HIGH                     ; 1                 ; Untyped        ;
    500. 

  500. ; LOCK_LOW                      ; 1                 ; Untyped        ;
    501. 

  501. ; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped        ;
    502. 

  502. ; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped        ;
    503. 

  503. ; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped        ;
    504. 

  504. ; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped        ;
    505. 

  505. ; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped        ;
    506. 

  506. ; SKIP_VCO                      ; OFF               ; Untyped        ;
    507. 

  507. ; SWITCH_OVER_COUNTER           ; 0                 ; Untyped        ;
    508. 

  508. ; SWITCH_OVER_TYPE              ; AUTO              ; Untyped        ;
    509. 

  509. ; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped        ;
    510. 

  510. ; BANDWIDTH                     ; 0                 ; Untyped        ;
    511. 

  511. ; BANDWIDTH_TYPE                ; AUTO              ; Untyped        ;
    512. 

  512. ; SPREAD_FREQUENCY              ; 0                 ; Untyped        ;
    513. 

  513. ; DOWN_SPREAD                   ; 0                 ; Untyped        ;
    514. 

  514. ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped        ;
    515. 

  515. ; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped        ;
    516. 

  516. ; CLK9_MULTIPLY_BY              ; 0                 ; Untyped        ;
    517. 

  517. ; CLK8_MULTIPLY_BY              ; 0                 ; Untyped        ;
    518. 

  518. ; CLK7_MULTIPLY_BY              ; 0                 ; Untyped        ;
    519. 

  519. ; CLK6_MULTIPLY_BY              ; 0                 ; Untyped        ;
    520. 

  520. ; CLK5_MULTIPLY_BY              ; 1                 ; Untyped        ;
    521. 

  521. ; CLK4_MULTIPLY_BY              ; 104               ; Signed Integer ;
    522. 

  522. ; CLK3_MULTIPLY_BY              ; 104               ; Signed Integer ;
    523. 

  523. ; CLK2_MULTIPLY_BY              ; 104               ; Signed Integer ;
    524. 

  524. ; CLK1_MULTIPLY_BY              ; 104               ; Signed Integer ;
    525. 

  525. ; CLK0_MULTIPLY_BY              ; 104               ; Signed Integer ;
    526. 

  526. ; CLK9_DIVIDE_BY                ; 0                 ; Untyped        ;
    527. 

  527. ; CLK8_DIVIDE_BY                ; 0                 ; Untyped        ;
    528. 

  528. ; CLK7_DIVIDE_BY                ; 0                 ; Untyped        ;
    529. 

  529. ; CLK6_DIVIDE_BY                ; 0                 ; Untyped        ;
    530. 

  530. ; CLK5_DIVIDE_BY                ; 1                 ; Untyped        ;
    531. 

  531. ; CLK4_DIVIDE_BY                ; 8                 ; Signed Integer ;
    532. 

  532. ; CLK3_DIVIDE_BY                ; 8                 ; Signed Integer ;
    533. 

  533. ; CLK2_DIVIDE_BY                ; 8                 ; Signed Integer ;
    534. 

  534. ; CLK1_DIVIDE_BY                ; 8                 ; Signed Integer ;
    535. 

  535. ; CLK0_DIVIDE_BY                ; 8                 ; Signed Integer ;
    536. 

  536. ; CLK9_PHASE_SHIFT              ; 0                 ; Untyped        ;
    537. 

  537. ; CLK8_PHASE_SHIFT              ; 0                 ; Untyped        ;
    538. 

  538. ; CLK7_PHASE_SHIFT              ; 0                 ; Untyped        ;
    539. 

  539. ; CLK6_PHASE_SHIFT              ; 0                 ; Untyped        ;
    540. 

  540. ; CLK5_PHASE_SHIFT              ; 0                 ; Untyped        ;
    541. 

  541. ; CLK4_PHASE_SHIFT              ; 0                 ; Untyped        ;
    542. 

  542. ; CLK3_PHASE_SHIFT              ; 0                 ; Untyped        ;
    543. 

  543. ; CLK2_PHASE_SHIFT              ; 0                 ; Untyped        ;
    544. 

  544. ; CLK1_PHASE_SHIFT              ; 0                 ; Untyped        ;
    545. 

  545. ; CLK0_PHASE_SHIFT              ; 0                 ; Untyped        ;
    546. 

  546. ; CLK5_TIME_DELAY               ; 0                 ; Untyped        ;
    547. 

  547. ; CLK4_TIME_DELAY               ; 0                 ; Untyped        ;
    548. 

  548. ; CLK3_TIME_DELAY               ; 0                 ; Untyped        ;
    549. 

  549. ; CLK2_TIME_DELAY               ; 0                 ; Untyped        ;
    550. 

  550. ; CLK1_TIME_DELAY               ; 0                 ; Untyped        ;
    551. 

  551. ; CLK0_TIME_DELAY               ; 0                 ; Untyped        ;
    552. 

  552. ; CLK9_DUTY_CYCLE               ; 50                ; Untyped        ;
    553. 

  553. ; CLK8_DUTY_CYCLE               ; 50                ; Untyped        ;
    554. 

  554. ; CLK7_DUTY_CYCLE               ; 50                ; Untyped        ;
    555. 

  555. ; CLK6_DUTY_CYCLE               ; 50                ; Untyped        ;
    556. 

  556. ; CLK5_DUTY_CYCLE               ; 50                ; Untyped        ;
    557. 

  557. ; CLK4_DUTY_CYCLE               ; 50                ; Untyped        ;
    558. 

  558. ; CLK3_DUTY_CYCLE               ; 50                ; Untyped        ;
    559. 

  559. ; CLK2_DUTY_CYCLE               ; 50                ; Untyped        ;
    560. 

  560. ; CLK1_DUTY_CYCLE               ; 50                ; Untyped        ;
    561. 

  561. ; CLK0_DUTY_CYCLE               ; 50                ; Untyped        ;
    562. 

  562. ; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    563. 

  563. ; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    564. 

  564. ; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    565. 

  565. ; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    566. 

  566. ; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    567. 

  567. ; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    568. 

  568. ; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    569. 

  569. ; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    570. 

  570. ; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    571. 

  571. ; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    572. 

  572. ; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    573. 

  573. ; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    574. 

  574. ; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    575. 

  575. ; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    576. 

  576. ; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    577. 

  577. ; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    578. 

  578. ; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    579. 

  579. ; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    580. 

  580. ; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    581. 

  581. ; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    582. 

  582. ; LOCK_WINDOW_UI                ;  0.05             ; Untyped        ;
    583. 

  583. ; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped        ;
    584. 

  584. ; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped        ;
    585. 

  585. ; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped        ;
    586. 

  586. ; DPA_MULTIPLY_BY               ; 0                 ; Untyped        ;
    587. 

  587. ; DPA_DIVIDE_BY                 ; 1                 ; Untyped        ;
    588. 

  588. ; DPA_DIVIDER                   ; 0                 ; Untyped        ;
    589. 

  589. ; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped        ;
    590. 

  590. ; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped        ;
    591. 

  591. ; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped        ;
    592. 

  592. ; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped        ;
    593. 

  593. ; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped        ;
    594. 

  594. ; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped        ;
    595. 

  595. ; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped        ;
    596. 

  596. ; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped        ;
    597. 

  597. ; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped        ;
    598. 

  598. ; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped        ;
    599. 

  599. ; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped        ;
    600. 

  600. ; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped        ;
    601. 

  601. ; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped        ;
    602. 

  602. ; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped        ;
    603. 

  603. ; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped        ;
    604. 

  604. ; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped        ;
    605. 

  605. ; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped        ;
    606. 

  606. ; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped        ;
    607. 

  607. ; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped        ;
    608. 

  608. ; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped        ;
    609. 

  609. ; VCO_MULTIPLY_BY               ; 0                 ; Untyped        ;
    610. 

  610. ; VCO_DIVIDE_BY                 ; 0                 ; Untyped        ;
    611. 

  611. ; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped        ;
    612. 

  612. ; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped        ;
    613. 

  613. ; VCO_MIN                       ; 0                 ; Untyped        ;
    614. 

  614. ; VCO_MAX                       ; 0                 ; Untyped        ;
    615. 

  615. ; VCO_CENTER                    ; 0                 ; Untyped        ;
    616. 

  616. ; PFD_MIN                       ; 0                 ; Untyped        ;
    617. 

  617. ; PFD_MAX                       ; 0                 ; Untyped        ;
    618. 

  618. ; M_INITIAL                     ; 0                 ; Untyped        ;
    619. 

  619. ; M                             ; 0                 ; Untyped        ;
    620. 

  620. ; N                             ; 1                 ; Untyped        ;
    621. 

  621. ; M2                            ; 1                 ; Untyped        ;
    622. 

  622. ; N2                            ; 1                 ; Untyped        ;
    623. 

  623. ; SS                            ; 1                 ; Untyped        ;
    624. 

  624. ; C0_HIGH                       ; 0                 ; Untyped        ;
    625. 

  625. ; C1_HIGH                       ; 0                 ; Untyped        ;
    626. 

  626. ; C2_HIGH                       ; 0                 ; Untyped        ;
    627. 

  627. ; C3_HIGH                       ; 0                 ; Untyped        ;
    628. 

  628. ; C4_HIGH                       ; 0                 ; Untyped        ;
    629. 

  629. ; C5_HIGH                       ; 0                 ; Untyped        ;
    630. 

  630. ; C6_HIGH                       ; 0                 ; Untyped        ;
    631. 

  631. ; C7_HIGH                       ; 0                 ; Untyped        ;
    632. 

  632. ; C8_HIGH                       ; 0                 ; Untyped        ;
    633. 

  633. ; C9_HIGH                       ; 0                 ; Untyped        ;
    634. 

  634. ; C0_LOW                        ; 0                 ; Untyped        ;
    635. 

  635. ; C1_LOW                        ; 0                 ; Untyped        ;
    636. 

  636. ; C2_LOW                        ; 0                 ; Untyped        ;
    637. 

  637. ; C3_LOW                        ; 0                 ; Untyped        ;
    638. 

  638. ; C4_LOW                        ; 0                 ; Untyped        ;
    639. 

  639. ; C5_LOW                        ; 0                 ; Untyped        ;
    640. 

  640. ; C6_LOW                        ; 0                 ; Untyped        ;
    641. 

  641. ; C7_LOW                        ; 0                 ; Untyped        ;
    642. 

  642. ; C8_LOW                        ; 0                 ; Untyped        ;
    643. 

  643. ; C9_LOW                        ; 0                 ; Untyped        ;
    644. 

  644. ; C0_INITIAL                    ; 0                 ; Untyped        ;
    645. 

  645. ; C1_INITIAL                    ; 0                 ; Untyped        ;
    646. 

  646. ; C2_INITIAL                    ; 0                 ; Untyped        ;
    647. 

  647. ; C3_INITIAL                    ; 0                 ; Untyped        ;
    648. 

  648. ; C4_INITIAL                    ; 0                 ; Untyped        ;
    649. 

  649. ; C5_INITIAL                    ; 0                 ; Untyped        ;
    650. 

  650. ; C6_INITIAL                    ; 0                 ; Untyped        ;
    651. 

  651. ; C7_INITIAL                    ; 0                 ; Untyped        ;
    652. 

  652. ; C8_INITIAL                    ; 0                 ; Untyped        ;
    653. 

  653. ; C9_INITIAL                    ; 0                 ; Untyped        ;
    654. 

  654. ; C0_MODE                       ; BYPASS            ; Untyped        ;
    655. 

  655. ; C1_MODE                       ; BYPASS            ; Untyped        ;
    656. 

  656. ; C2_MODE                       ; BYPASS            ; Untyped        ;
    657. 

  657. ; C3_MODE                       ; BYPASS            ; Untyped        ;
    658. 

  658. ; C4_MODE                       ; BYPASS            ; Untyped        ;
    659. 

  659. ; C5_MODE                       ; BYPASS            ; Untyped        ;
    660. 

  660. ; C6_MODE                       ; BYPASS            ; Untyped        ;
    661. 

  661. ; C7_MODE                       ; BYPASS            ; Untyped        ;
    662. 

  662. ; C8_MODE                       ; BYPASS            ; Untyped        ;
    663. 

  663. ; C9_MODE                       ; BYPASS            ; Untyped        ;
    664. 

  664. ; C0_PH                         ; 0                 ; Untyped        ;
    665. 

  665. ; C1_PH                         ; 0                 ; Untyped        ;
    666. 

  666. ; C2_PH                         ; 0                 ; Untyped        ;
    667. 

  667. ; C3_PH                         ; 0                 ; Untyped        ;
    668. 

  668. ; C4_PH                         ; 0                 ; Untyped        ;
    669. 

  669. ; C5_PH                         ; 0                 ; Untyped        ;
    670. 

  670. ; C6_PH                         ; 0                 ; Untyped        ;
    671. 

  671. ; C7_PH                         ; 0                 ; Untyped        ;
    672. 

  672. ; C8_PH                         ; 0                 ; Untyped        ;
    673. 

  673. ; C9_PH                         ; 0                 ; Untyped        ;
    674. 

  674. ; L0_HIGH                       ; 1                 ; Untyped        ;
    675. 

  675. ; L1_HIGH                       ; 1                 ; Untyped        ;
    676. 

  676. ; G0_HIGH                       ; 1                 ; Untyped        ;
    677. 

  677. ; G1_HIGH                       ; 1                 ; Untyped        ;
    678. 

  678. ; G2_HIGH                       ; 1                 ; Untyped        ;
    679. 

  679. ; G3_HIGH                       ; 1                 ; Untyped        ;
    680. 

  680. ; E0_HIGH                       ; 1                 ; Untyped        ;
    681. 

  681. ; E1_HIGH                       ; 1                 ; Untyped        ;
    682. 

  682. ; E2_HIGH                       ; 1                 ; Untyped        ;
    683. 

  683. ; E3_HIGH                       ; 1                 ; Untyped        ;
    684. 

  684. ; L0_LOW                        ; 1                 ; Untyped        ;
    685. 

  685. ; L1_LOW                        ; 1                 ; Untyped        ;
    686. 

  686. ; G0_LOW                        ; 1                 ; Untyped        ;
    687. 

  687. ; G1_LOW                        ; 1                 ; Untyped        ;
    688. 

  688. ; G2_LOW                        ; 1                 ; Untyped        ;
    689. 

  689. ; G3_LOW                        ; 1                 ; Untyped        ;
    690. 

  690. ; E0_LOW                        ; 1                 ; Untyped        ;
    691. 

  691. ; E1_LOW                        ; 1                 ; Untyped        ;
    692. 

  692. ; E2_LOW                        ; 1                 ; Untyped        ;
    693. 

  693. ; E3_LOW                        ; 1                 ; Untyped        ;
    694. 

  694. ; L0_INITIAL                    ; 1                 ; Untyped        ;
    695. 

  695. ; L1_INITIAL                    ; 1                 ; Untyped        ;
    696. 

  696. ; G0_INITIAL                    ; 1                 ; Untyped        ;
    697. 

  697. ; G1_INITIAL                    ; 1                 ; Untyped        ;
    698. 

  698. ; G2_INITIAL                    ; 1                 ; Untyped        ;
    699. 

  699. ; G3_INITIAL                    ; 1                 ; Untyped        ;
    700. 

  700. ; E0_INITIAL                    ; 1                 ; Untyped        ;
    701. 

  701. ; E1_INITIAL                    ; 1                 ; Untyped        ;
    702. 

  702. ; E2_INITIAL                    ; 1                 ; Untyped        ;
    703. 

  703. ; E3_INITIAL                    ; 1                 ; Untyped        ;
    704. 

  704. ; L0_MODE                       ; BYPASS            ; Untyped        ;
    705. 

  705. ; L1_MODE                       ; BYPASS            ; Untyped        ;
    706. 

  706. ; G0_MODE                       ; BYPASS            ; Untyped        ;
    707. 

  707. ; G1_MODE                       ; BYPASS            ; Untyped        ;
    708. 

  708. ; G2_MODE                       ; BYPASS            ; Untyped        ;
    709. 

  709. ; G3_MODE                       ; BYPASS            ; Untyped        ;
    710. 

  710. ; E0_MODE                       ; BYPASS            ; Untyped        ;
    711. 

  711. ; E1_MODE                       ; BYPASS            ; Untyped        ;
    712. 

  712. ; E2_MODE                       ; BYPASS            ; Untyped        ;
    713. 

  713. ; E3_MODE                       ; BYPASS            ; Untyped        ;
    714. 

  714. ; L0_PH                         ; 0                 ; Untyped        ;
    715. 

  715. ; L1_PH                         ; 0                 ; Untyped        ;
    716. 

  716. ; G0_PH                         ; 0                 ; Untyped        ;
    717. 

  717. ; G1_PH                         ; 0                 ; Untyped        ;
    718. 

  718. ; G2_PH                         ; 0                 ; Untyped        ;
    719. 

  719. ; G3_PH                         ; 0                 ; Untyped        ;
    720. 

  720. ; E0_PH                         ; 0                 ; Untyped        ;
    721. 

  721. ; E1_PH                         ; 0                 ; Untyped        ;
    722. 

  722. ; E2_PH                         ; 0                 ; Untyped        ;
    723. 

  723. ; E3_PH                         ; 0                 ; Untyped        ;
    724. 

  724. ; M_PH                          ; 0                 ; Untyped        ;
    725. 

  725. ; C1_USE_CASC_IN                ; OFF               ; Untyped        ;
    726. 

  726. ; C2_USE_CASC_IN                ; OFF               ; Untyped        ;
    727. 

  727. ; C3_USE_CASC_IN                ; OFF               ; Untyped        ;
    728. 

  728. ; C4_USE_CASC_IN                ; OFF               ; Untyped        ;
    729. 

  729. ; C5_USE_CASC_IN                ; OFF               ; Untyped        ;
    730. 

  730. ; C6_USE_CASC_IN                ; OFF               ; Untyped        ;
    731. 

  731. ; C7_USE_CASC_IN                ; OFF               ; Untyped        ;
    732. 

  732. ; C8_USE_CASC_IN                ; OFF               ; Untyped        ;
    733. 

  733. ; C9_USE_CASC_IN                ; OFF               ; Untyped        ;
    734. 

  734. ; CLK0_COUNTER                  ; G0                ; Untyped        ;
    735. 

  735. ; CLK1_COUNTER                  ; G0                ; Untyped        ;
    736. 

  736. ; CLK2_COUNTER                  ; G0                ; Untyped        ;
    737. 

  737. ; CLK3_COUNTER                  ; G0                ; Untyped        ;
    738. 

  738. ; CLK4_COUNTER                  ; G0                ; Untyped        ;
    739. 

  739. ; CLK5_COUNTER                  ; G0                ; Untyped        ;
    740. 

  740. ; CLK6_COUNTER                  ; E0                ; Untyped        ;
    741. 

  741. ; CLK7_COUNTER                  ; E1                ; Untyped        ;
    742. 

  742. ; CLK8_COUNTER                  ; E2                ; Untyped        ;
    743. 

  743. ; CLK9_COUNTER                  ; E3                ; Untyped        ;
    744. 

  744. ; L0_TIME_DELAY                 ; 0                 ; Untyped        ;
    745. 

  745. ; L1_TIME_DELAY                 ; 0                 ; Untyped        ;
    746. 

  746. ; G0_TIME_DELAY                 ; 0                 ; Untyped        ;
    747. 

  747. ; G1_TIME_DELAY                 ; 0                 ; Untyped        ;
    748. 

  748. ; G2_TIME_DELAY                 ; 0                 ; Untyped        ;
    749. 

  749. ; G3_TIME_DELAY                 ; 0                 ; Untyped        ;
    750. 

  750. ; E0_TIME_DELAY                 ; 0                 ; Untyped        ;
    751. 

  751. ; E1_TIME_DELAY                 ; 0                 ; Untyped        ;
    752. 

  752. ; E2_TIME_DELAY                 ; 0                 ; Untyped        ;
    753. 

  753. ; E3_TIME_DELAY                 ; 0                 ; Untyped        ;
    754. 

  754. ; M_TIME_DELAY                  ; 0                 ; Untyped        ;
    755. 

  755. ; N_TIME_DELAY                  ; 0                 ; Untyped        ;
    756. 

  756. ; EXTCLK3_COUNTER               ; E3                ; Untyped        ;
    757. 

  757. ; EXTCLK2_COUNTER               ; E2                ; Untyped        ;
    758. 

  758. ; EXTCLK1_COUNTER               ; E1                ; Untyped        ;
    759. 

  759. ; EXTCLK0_COUNTER               ; E0                ; Untyped        ;
    760. 

  760. ; ENABLE0_COUNTER               ; L0                ; Untyped        ;
    761. 

  761. ; ENABLE1_COUNTER               ; L0                ; Untyped        ;
    762. 

  762. ; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped        ;
    763. 

  763. ; LOOP_FILTER_R                 ;  1.000000         ; Untyped        ;
    764. 

  764. ; LOOP_FILTER_C                 ; 5                 ; Untyped        ;
    765. 

  765. ; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped        ;
    766. 

  766. ; LOOP_FILTER_R_BITS            ; 9999              ; Untyped        ;
    767. 

  767. ; LOOP_FILTER_C_BITS            ; 9999              ; Untyped        ;
    768. 

  768. ; VCO_POST_SCALE                ; 0                 ; Untyped        ;
    769. 

  769. ; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    770. 

  770. ; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    771. 

  771. ; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    772. 

  772. ; INTENDED_DEVICE_FAMILY        ; Cyclone IV E      ; Untyped        ;
    773. 

  773. ; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped        ;
    774. 

  774. ; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped        ;
    775. 

  775. ; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped        ;
    776. 

  776. ; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped        ;
    777. 

  777. ; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped        ;
    778. 

  778. ; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped        ;
    779. 

  779. ; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped        ;
    780. 

  780. ; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped        ;
    781. 

  781. ; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped        ;
    782. 

  782. ; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped        ;
    783. 

  783. ; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped        ;
    784. 

  784. ; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped        ;
    785. 

  785. ; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped        ;
    786. 

  786. ; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped        ;
    787. 

  787. ; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped        ;
    788. 

  788. ; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped        ;
    789. 

  789. ; PORT_CLK0                     ; PORT_USED         ; Untyped        ;
    790. 

  790. ; PORT_CLK1                     ; PORT_UNUSED       ; Untyped        ;
    791. 

  791. ; PORT_CLK2                     ; PORT_UNUSED       ; Untyped        ;
    792. 

  792. ; PORT_CLK3                     ; PORT_UNUSED       ; Untyped        ;
    793. 

  793. ; PORT_CLK4                     ; PORT_UNUSED       ; Untyped        ;
    794. 

  794. ; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped        ;
    795. 

  795. ; PORT_CLK6                     ; PORT_UNUSED       ; Untyped        ;
    796. 

  796. ; PORT_CLK7                     ; PORT_UNUSED       ; Untyped        ;
    797. 

  797. ; PORT_CLK8                     ; PORT_UNUSED       ; Untyped        ;
    798. 

  798. ; PORT_CLK9                     ; PORT_UNUSED       ; Untyped        ;
    799. 

  799. ; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped        ;
    800. 

  800. ; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped        ;
    801. 

  801. ; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped        ;
    802. 

  802. ; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped        ;
    803. 

  803. ; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped        ;
    804. 

  804. ; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped        ;
    805. 

  805. ; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped        ;
    806. 

  806. ; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped        ;
    807. 

  807. ; PORT_INCLK0                   ; PORT_USED         ; Untyped        ;
    808. 

  808. ; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped        ;
    809. 

  809. ; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped        ;
    810. 

  810. ; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped        ;
    811. 

  811. ; PORT_ARESET                   ; PORT_USED         ; Untyped        ;
    812. 

  812. ; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped        ;
    813. 

  813. ; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped        ;
    814. 

  814. ; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped        ;
    815. 

  815. ; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped        ;
    816. 

  816. ; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped        ;
    817. 

  817. ; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped        ;
    818. 

  818. ; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped        ;
    819. 

  819. ; PORT_LOCKED                   ; PORT_USED         ; Untyped        ;
    820. 

  820. ; PORT_CONFIGUPDATE             ; PORT_CONNECTIVITY ; Untyped        ;
    821. 

  821. ; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped        ;
    822. 

  822. ; PORT_PHASEDONE                ; PORT_CONNECTIVITY ; Untyped        ;
    823. 

  823. ; PORT_PHASESTEP                ; PORT_CONNECTIVITY ; Untyped        ;
    824. 

  824. ; PORT_PHASEUPDOWN              ; PORT_CONNECTIVITY ; Untyped        ;
    825. 

  825. ; PORT_SCANCLKENA               ; PORT_CONNECTIVITY ; Untyped        ;
    826. 

  826. ; PORT_PHASECOUNTERSELECT       ; PORT_CONNECTIVITY ; Untyped        ;
    827. 

  827. ; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped        ;
    828. 

  828. ; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped        ;
    829. 

  829. ; M_TEST_SOURCE                 ; 5                 ; Untyped        ;
    830. 

  830. ; C0_TEST_SOURCE                ; 5                 ; Untyped        ;
    831. 

  831. ; C1_TEST_SOURCE                ; 5                 ; Untyped        ;
    832. 

  832. ; C2_TEST_SOURCE                ; 5                 ; Untyped        ;
    833. 

  833. ; C3_TEST_SOURCE                ; 5                 ; Untyped        ;
    834. 

  834. ; C4_TEST_SOURCE                ; 5                 ; Untyped        ;
    835. 

  835. ; C5_TEST_SOURCE                ; 5                 ; Untyped        ;
    836. 

  836. ; C6_TEST_SOURCE                ; 5                 ; Untyped        ;
    837. 

  837. ; C7_TEST_SOURCE                ; 5                 ; Untyped        ;
    838. 

  838. ; C8_TEST_SOURCE                ; 5                 ; Untyped        ;
    839. 

  839. ; C9_TEST_SOURCE                ; 5                 ; Untyped        ;
    840. 

  840. ; CBXI_PARAMETER                ; altpll_6o32       ; Untyped        ;
    841. 

  841. ; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped        ;
    842. 

  842. ; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped        ;
    843. 

  843. ; WIDTH_CLOCK                   ; 5                 ; Signed Integer ;
    844. 

  844. ; WIDTH_PHASECOUNTERSELECT      ; 3                 ; Signed Integer ;
    845. 

  845. ; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped        ;
    846. 

  846. ; DEVICE_FAMILY                 ; Cyclone IV E      ; Untyped        ;
    847. 

  847. ; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped        ;
    848. 

  848. ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped        ;
    849. 

  849. ; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY     ;
    850. 

  850. ; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY   ;
    851. 

  851. ; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE   ;
    852. 

  852. ; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE ;
    853. 

  853. +-------------------------------+-------------------+----------------+
    854. 

  854. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    855. 

  855. 

  856. 

  857. +----------------------------------------------------------------------+
    858. 

  858. ; Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst ;
    859. 

  859. +----------------+-------+---------------------------------------------+
    860. 

  860. ; Parameter Name ; Value ; Type                                        ;
    861. 

  861. +----------------+-------+---------------------------------------------+
    862. 

  862. ; coord_x        ; 0     ; Signed Integer                              ;
    863. 

  863. ; coord_y        ; 0     ; Signed Integer                              ;
    864. 

  864. ; coord_z        ; 0     ; Signed Integer                              ;
    865. 

  865. ; ENA_REG_MODE   ; 0     ; Unsigned Binary                             ;
    866. 

  866. +----------------+-------+---------------------------------------------+
    867. 

  867. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    868. 

  868. 

  869. 

  870. +---------------------------------------------------------------------+
    871. 

  871. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst   ;
    872. 

  872. +----------------+----------------------------------+-----------------+
    873. 

  873. ; Parameter Name ; Value                            ; Type            ;
    874. 

  874. +----------------+----------------------------------+-----------------+
    875. 

  875. ; RAM_SIZE       ; 2048                             ; Signed Integer  ;
    876. 

  876. ; RAM_DEPTH      ; 1024                             ; Signed Integer  ;
    877. 

  877. ; RAM_WIDTH      ; 16                               ; Signed Integer  ;
    878. 

  878. ; ADDR_BITS      ; 16                               ; Signed Integer  ;
    879. 

  879. ; DATA_BITS      ; 32                               ; Signed Integer  ;
    880. 

  880. ; PER_BITS       ; 12                               ; Signed Integer  ;
    881. 

  881. ; PER_CNT        ; 4                                ; Signed Integer  ;
    882. 

  882. ; RAM_BASE_ADDR  ; 00000000000000000110000000000000 ; Unsigned Binary ;
    883. 

  883. +----------------+----------------------------------+-----------------+
    884. 

  884. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    885. 

  885. 

  886. 

  887. +----------------------------------------------------------------------------------------+
    888. 

  888. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|ahb2apb:ahb2apb_inst ;
    889. 

  889. +----------------+-------+---------------------------------------------------------------+
    890. 

  890. ; Parameter Name ; Value ; Type                                                          ;
    891. 

  891. +----------------+-------+---------------------------------------------------------------+
    892. 

  892. ; ADDR_BITS      ; 16    ; Signed Integer                                                ;
    893. 

  893. ; DATA_BITS      ; 32    ; Signed Integer                                                ;
    894. 

  894. +----------------+-------+---------------------------------------------------------------+
    895. 

  895. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    896. 

  896. 

  897. 

  898. +----------------------------------------------------------------------------------------+
    899. 

  899. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|cfg_reg:cfg_reg_inst ;
    900. 

  900. +----------------+----------------------------------+------------------------------------+
    901. 

  901. ; Parameter Name ; Value                            ; Type                               ;
    902. 

  902. +----------------+----------------------------------+------------------------------------+
    903. 

  903. ; ADDR_CTRL      ; 00000000000000000000000000000000 ; Unsigned Binary                    ;
    904. 

  904. ; ADDR_CLK_DIV   ; 00000000000000000000000000000100 ; Unsigned Binary                    ;
    905. 

  905. ; ADDR_TRIG_TH   ; 00000000000000000000000000001000 ; Unsigned Binary                    ;
    906. 

  906. ; ADDR_TRIG_PW   ; 00000000000000000000000000001100 ; Unsigned Binary                    ;
    907. 

  907. ; ADDR_TRIG_CFG  ; 00000000000000000000000000010000 ; Unsigned Binary                    ;
    908. 

  908. ; ADDR_TRIG_TOUT ; 00000000000000000000000000010100 ; Unsigned Binary                    ;
    909. 

  909. ; ADDR_RUN_CTRL  ; 00000000000000000000000000011000 ; Unsigned Binary                    ;
    910. 

  910. ; ADDR_DAC_CTRL  ; 00000000000000000000000000011100 ; Unsigned Binary                    ;
    911. 

  911. ; ADDR_DAC_WAVE  ; 00000000000000000000000000100000 ; Unsigned Binary                    ;
    912. 

  912. ; ADDR_DAC_AMP   ; 00000000000000000000000000100100 ; Unsigned Binary                    ;
    913. 

  913. ; ADDR_DAC_FREQ  ; 00000000000000000000000000101000 ; Unsigned Binary                    ;
    914. 

  914. ; ADDR_DAC_DUTY  ; 00000000000000000000000000101100 ; Unsigned Binary                    ;
    915. 

  915. +----------------+----------------------------------+------------------------------------+
    916. 

  916. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    917. 

  917. 

  918. 

  919. +-----------------------------------------------------------------------------------------+
    920. 

  920. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst ;
    921. 

  921. +----------------+-------+----------------------------------------------------------------+
    922. 

  922. ; Parameter Name ; Value ; Type                                                           ;
    923. 

  923. +----------------+-------+----------------------------------------------------------------+
    924. 

  924. ; SCLK_BIT       ; 16    ; Signed Integer                                                 ;
    925. 

  925. +----------------+-------+----------------------------------------------------------------+
    926. 

  926. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    927. 

  927. 

  928. 

  929. +---------------------------------------------------------------------------------------------+
    930. 

  930. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|baud_detect:u_baud_detect ;
    931. 

  931. +----------------+-------+--------------------------------------------------------------------+
    932. 

  932. ; Parameter Name ; Value ; Type                                                               ;
    933. 

  933. +----------------+-------+--------------------------------------------------------------------+
    934. 

  934. ; NUM_EDGES      ; 16    ; Signed Integer                                                     ;
    935. 

  935. +----------------+-------+--------------------------------------------------------------------+
    936. 

  936. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    937. 

  937. 

  938. 

  939. +----------------------------------------------------------------------------------------------+
    940. 

  940. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|altsyncram:u_dual_port_ram ;
    941. 

  941. +------------------------------------+----------------------+----------------------------------+
    942. 

  942. ; Parameter Name                     ; Value                ; Type                             ;
    943. 

  943. +------------------------------------+----------------------+----------------------------------+
    944. 

  944. ; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                          ;
    945. 

  945. ; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                       ;
    946. 

  946. ; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                     ;
    947. 

  947. ; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                     ;
    948. 

  948. ; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                   ;
    949. 

  949. ; WIDTH_BYTEENA                      ; 1                    ; Untyped                          ;
    950. 

  950. ; OPERATION_MODE                     ; BIDIR_DUAL_PORT      ; Untyped                          ;
    951. 

  951. ; WIDTH_A                            ; 16                   ; Signed Integer                   ;
    952. 

  952. ; WIDTHAD_A                          ; 10                   ; Signed Integer                   ;
    953. 

  953. ; NUMWORDS_A                         ; 1024                 ; Signed Integer                   ;
    954. 

  954. ; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                          ;
    955. 

  955. ; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                          ;
    956. 

  956. ; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                          ;
    957. 

  957. ; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                          ;
    958. 

  958. ; INDATA_ACLR_A                      ; NONE                 ; Untyped                          ;
    959. 

  959. ; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                          ;
    960. 

  960. ; WIDTH_B                            ; 16                   ; Signed Integer                   ;
    961. 

  961. ; WIDTHAD_B                          ; 10                   ; Signed Integer                   ;
    962. 

  962. ; NUMWORDS_B                         ; 1024                 ; Signed Integer                   ;
    963. 

  963. ; INDATA_REG_B                       ; CLOCK1               ; Untyped                          ;
    964. 

  964. ; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                          ;
    965. 

  965. ; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                          ;
    966. 

  966. ; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                          ;
    967. 

  967. ; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                          ;
    968. 

  968. ; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                          ;
    969. 

  969. ; INDATA_ACLR_B                      ; NONE                 ; Untyped                          ;
    970. 

  970. ; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
    971. 

  971. ; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                          ;
    972. 

  972. ; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                          ;
    973. 

  973. ; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                          ;
    974. 

  974. ; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                          ;
    975. 

  975. ; WIDTH_BYTEENA_A                    ; 2                    ; Signed Integer                   ;
    976. 

  976. ; WIDTH_BYTEENA_B                    ; 2                    ; Signed Integer                   ;
    977. 

  977. ; RAM_BLOCK_TYPE                     ; M9K                  ; Untyped                          ;
    978. 

  978. ; BYTE_SIZE                          ; 8                    ; Signed Integer                   ;
    979. 

  979. ; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                          ;
    980. 

  980. ; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
    981. 

  981. ; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                          ;
    982. 

  982. ; INIT_FILE                          ; UNUSED               ; Untyped                          ;
    983. 

  983. ; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                          ;
    984. 

  984. ; MAXIMUM_DEPTH                      ; 0                    ; Untyped                          ;
    985. 

  985. ; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                          ;
    986. 

  986. ; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                          ;
    987. 

  987. ; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                          ;
    988. 

  988. ; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                          ;
    989. 

  989. ; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                          ;
    990. 

  990. ; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                          ;
    991. 

  991. ; ENABLE_ECC                         ; FALSE                ; Untyped                          ;
    992. 

  992. ; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                          ;
    993. 

  993. ; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                          ;
    994. 

  994. ; DEVICE_FAMILY                      ; Cyclone IV E         ; Untyped                          ;
    995. 

  995. ; CBXI_PARAMETER                     ; altsyncram_sgu1      ; Untyped                          ;
    996. 

  996. +------------------------------------+----------------------+----------------------------------+
    997. 

  997. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    998. 

  998. 

  999. 

  1000. +-------------------------------------------------------------------------------------+
    1001. 

  1001. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb2ram:u_apb2ram ;
    1002. 

  1002. +----------------+-------+------------------------------------------------------------+
    1003. 

  1003. ; Parameter Name ; Value ; Type                                                       ;
    1004. 

  1004. +----------------+-------+------------------------------------------------------------+
    1005. 

  1005. ; ADDR_BITS      ; 16    ; Signed Integer                                             ;
    1006. 

  1006. +----------------+-------+------------------------------------------------------------+
    1007. 

  1007. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1008. 

  1008. 

  1009. 

  1010. +------------------------------------------------------------------------------------------------------------+
    1011. 

  1011. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0 ;
    1012. 

  1012. +------------------------------------------------+--------------+--------------------------------------------+
    1013. 

  1013. ; Parameter Name                                 ; Value        ; Type                                       ;
    1014. 

  1014. +------------------------------------------------+--------------+--------------------------------------------+
    1015. 

  1015. ; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY                                 ;
    1016. 

  1016. ; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY                               ;
    1017. 

  1017. ; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE                               ;
    1018. 

  1018. ; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE                             ;
    1019. 

  1019. ; LPM_WIDTHA                                     ; 10           ; Untyped                                    ;
    1020. 

  1020. ; LPM_WIDTHB                                     ; 10           ; Untyped                                    ;
    1021. 

  1021. ; LPM_WIDTHP                                     ; 20           ; Untyped                                    ;
    1022. 

  1022. ; LPM_WIDTHR                                     ; 20           ; Untyped                                    ;
    1023. 

  1023. ; LPM_WIDTHS                                     ; 1            ; Untyped                                    ;
    1024. 

  1024. ; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped                                    ;
    1025. 

  1025. ; LPM_PIPELINE                                   ; 0            ; Untyped                                    ;
    1026. 

  1026. ; LATENCY                                        ; 0            ; Untyped                                    ;
    1027. 

  1027. ; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1028. 

  1028. ; INPUT_B_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1029. 

  1029. ; USE_EAB                                        ; OFF          ; Untyped                                    ;
    1030. 

  1030. ; MAXIMIZE_SPEED                                 ; 6            ; Untyped                                    ;
    1031. 

  1031. ; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped                                    ;
    1032. 

  1032. ; CARRY_CHAIN                                    ; MANUAL       ; Untyped                                    ;
    1033. 

  1033. ; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K                        ;
    1034. 

  1034. ; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped                                    ;
    1035. 

  1035. ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped                                    ;
    1036. 

  1036. ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped                                    ;
    1037. 

  1037. ; CBXI_PARAMETER                                 ; mult_oct     ; Untyped                                    ;
    1038. 

  1038. ; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1039. 

  1039. ; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1040. 

  1040. ; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped                                    ;
    1041. 

  1041. +------------------------------------------------+--------------+--------------------------------------------+
    1042. 

  1042. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1043. 

  1043. 

  1044. 

  1045. +------------------------------------------------------------------------------------------------------------+
    1046. 

  1046. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2 ;
    1047. 

  1047. +------------------------------------------------+--------------+--------------------------------------------+
    1048. 

  1048. ; Parameter Name                                 ; Value        ; Type                                       ;
    1049. 

  1049. +------------------------------------------------+--------------+--------------------------------------------+
    1050. 

  1050. ; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY                                 ;
    1051. 

  1051. ; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY                               ;
    1052. 

  1052. ; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE                               ;
    1053. 

  1053. ; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE                             ;
    1054. 

  1054. ; LPM_WIDTHA                                     ; 10           ; Untyped                                    ;
    1055. 

  1055. ; LPM_WIDTHB                                     ; 9            ; Untyped                                    ;
    1056. 

  1056. ; LPM_WIDTHP                                     ; 19           ; Untyped                                    ;
    1057. 

  1057. ; LPM_WIDTHR                                     ; 19           ; Untyped                                    ;
    1058. 

  1058. ; LPM_WIDTHS                                     ; 1            ; Untyped                                    ;
    1059. 

  1059. ; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped                                    ;
    1060. 

  1060. ; LPM_PIPELINE                                   ; 0            ; Untyped                                    ;
    1061. 

  1061. ; LATENCY                                        ; 0            ; Untyped                                    ;
    1062. 

  1062. ; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1063. 

  1063. ; INPUT_B_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1064. 

  1064. ; USE_EAB                                        ; OFF          ; Untyped                                    ;
    1065. 

  1065. ; MAXIMIZE_SPEED                                 ; 6            ; Untyped                                    ;
    1066. 

  1066. ; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped                                    ;
    1067. 

  1067. ; CARRY_CHAIN                                    ; MANUAL       ; Untyped                                    ;
    1068. 

  1068. ; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K                        ;
    1069. 

  1069. ; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped                                    ;
    1070. 

  1070. ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped                                    ;
    1071. 

  1071. ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped                                    ;
    1072. 

  1072. ; CBXI_PARAMETER                                 ; mult_pbt     ; Untyped                                    ;
    1073. 

  1073. ; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1074. 

  1074. ; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1075. 

  1075. ; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped                                    ;
    1076. 

  1076. +------------------------------------------------+--------------+--------------------------------------------+
    1077. 

  1077. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1078. 

  1078. 

  1079. 

  1080. +------------------------------------------------------------------------------------------------------------+
    1081. 

  1081. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3 ;
    1082. 

  1082. +------------------------------------------------+--------------+--------------------------------------------+
    1083. 

  1083. ; Parameter Name                                 ; Value        ; Type                                       ;
    1084. 

  1084. +------------------------------------------------+--------------+--------------------------------------------+
    1085. 

  1085. ; AUTO_CARRY_CHAINS                              ; ON           ; AUTO_CARRY                                 ;
    1086. 

  1086. ; IGNORE_CARRY_BUFFERS                           ; OFF          ; IGNORE_CARRY                               ;
    1087. 

  1087. ; AUTO_CASCADE_CHAINS                            ; ON           ; AUTO_CASCADE                               ;
    1088. 

  1088. ; IGNORE_CASCADE_BUFFERS                         ; OFF          ; IGNORE_CASCADE                             ;
    1089. 

  1089. ; LPM_WIDTHA                                     ; 10           ; Untyped                                    ;
    1090. 

  1090. ; LPM_WIDTHB                                     ; 10           ; Untyped                                    ;
    1091. 

  1091. ; LPM_WIDTHP                                     ; 20           ; Untyped                                    ;
    1092. 

  1092. ; LPM_WIDTHR                                     ; 20           ; Untyped                                    ;
    1093. 

  1093. ; LPM_WIDTHS                                     ; 1            ; Untyped                                    ;
    1094. 

  1094. ; LPM_REPRESENTATION                             ; UNSIGNED     ; Untyped                                    ;
    1095. 

  1095. ; LPM_PIPELINE                                   ; 0            ; Untyped                                    ;
    1096. 

  1096. ; LATENCY                                        ; 0            ; Untyped                                    ;
    1097. 

  1097. ; INPUT_A_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1098. 

  1098. ; INPUT_B_IS_CONSTANT                            ; NO           ; Untyped                                    ;
    1099. 

  1099. ; USE_EAB                                        ; OFF          ; Untyped                                    ;
    1100. 

  1100. ; MAXIMIZE_SPEED                                 ; 6            ; Untyped                                    ;
    1101. 

  1101. ; DEVICE_FAMILY                                  ; Cyclone IV E ; Untyped                                    ;
    1102. 

  1102. ; CARRY_CHAIN                                    ; MANUAL       ; Untyped                                    ;
    1103. 

  1103. ; APEX20K_TECHNOLOGY_MAPPER                      ; LUT          ; TECH_MAPPER_APEX20K                        ;
    1104. 

  1104. ; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO         ; Untyped                                    ;
    1105. 

  1105. ; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0            ; Untyped                                    ;
    1106. 

  1106. ; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0            ; Untyped                                    ;
    1107. 

  1107. ; CBXI_PARAMETER                                 ; mult_oct     ; Untyped                                    ;
    1108. 

  1108. ; INPUT_A_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1109. 

  1109. ; INPUT_B_FIXED_VALUE                            ; Bx           ; Untyped                                    ;
    1110. 

  1110. ; USE_AHDL_IMPLEMENTATION                        ; OFF          ; Untyped                                    ;
    1111. 

  1111. +------------------------------------------------+--------------+--------------------------------------------+
    1112. 

  1112. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1113. 

  1113. 

  1114. 

  1115. +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
    1116. 

  1116. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ;
    1117. 

  1117. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1118. 

  1118. ; Parameter Name               ; Value         ; Type                                                                                                       ;
    1119. 

  1119. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1120. 

  1120. ; LPM_WIDTHS                   ; 1             ; Untyped                                                                                                    ;
    1121. 

  1121. ; DATAA_WIDTH                  ; 10            ; Untyped                                                                                                    ;
    1122. 

  1122. ; DATAB_WIDTH                  ; 10            ; Untyped                                                                                                    ;
    1123. 

  1123. ; DATAA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1124. 

  1124. ; DATAB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1125. 

  1125. ; SIGNA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1126. 

  1126. ; SIGNB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1127. 

  1127. ; OUTPUT_CLOCK                 ; NONE          ; Untyped                                                                                                    ;
    1128. 

  1128. ; DATAA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1129. 

  1129. ; DATAB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1130. 

  1130. ; SIGNA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1131. 

  1131. ; SIGNB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1132. 

  1132. ; OUTPUT_CLEAR                 ; NONE          ; Untyped                                                                                                    ;
    1133. 

  1133. ; ROUND_CLOCK                  ; none          ; Untyped                                                                                                    ;
    1134. 

  1134. ; ROUND_CLEAR                  ; none          ; Untyped                                                                                                    ;
    1135. 

  1135. ; SATURATE_CLOCK               ; none          ; Untyped                                                                                                    ;
    1136. 

  1136. ; SATURATE_CLEAR               ; none          ; Untyped                                                                                                    ;
    1137. 

  1137. ; BYPASS_MULTIPLIER            ; NO            ; Untyped                                                                                                    ;
    1138. 

  1138. ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO            ; Untyped                                                                                                    ;
    1139. 

  1139. ; USING_ROUNDING               ; NO            ; Untyped                                                                                                    ;
    1140. 

  1140. ; USING_SATURATION             ; NO            ; Untyped                                                                                                    ;
    1141. 

  1141. ; EXTRA_OUTPUT_CLOCK           ; none          ; Untyped                                                                                                    ;
    1142. 

  1142. ; EXTRA_SIGNA_CLOCK            ; none          ; Untyped                                                                                                    ;
    1143. 

  1143. ; EXTRA_SIGNB_CLOCK            ; none          ; Untyped                                                                                                    ;
    1144. 

  1144. ; EXTRA_OUTPUT_CLEAR           ; none          ; Untyped                                                                                                    ;
    1145. 

  1145. ; EXTRA_SIGNA_CLEAR            ; none          ; Untyped                                                                                                    ;
    1146. 

  1146. ; EXTRA_SIGNB_CLEAR            ; none          ; Untyped                                                                                                    ;
    1147. 

  1147. ; MULT_PIPELINE                ; 0             ; Untyped                                                                                                    ;
    1148. 

  1148. ; MULT_CLOCK                   ; NONE          ; Untyped                                                                                                    ;
    1149. 

  1149. ; MULT_CLEAR                   ; NONE          ; Untyped                                                                                                    ;
    1150. 

  1150. ; MULT_REPRESENTATION_A        ; UNSIGNED      ; Untyped                                                                                                    ;
    1151. 

  1151. ; MULT_REPRESENTATION_B        ; UNSIGNED      ; Untyped                                                                                                    ;
    1152. 

  1152. ; MULT_INPUT_A_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1153. 

  1153. ; MULT_INPUT_B_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1154. 

  1154. ; MULT_INPUT_A_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1155. 

  1155. ; MULT_INPUT_B_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1156. 

  1156. ; MULT_MAXIMIZE_SPEED          ; 5             ; Untyped                                                                                                    ;
    1157. 

  1157. ; CBXI_PARAMETER               ; mac_mult_iug1 ; Untyped                                                                                                    ;
    1158. 

  1158. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1159. 

  1159. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1160. 

  1160. 

  1161. 

  1162. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
    1163. 

  1163. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2 ;
    1164. 

  1164. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1165. 

  1165. ; Parameter Name                ; Value        ; Type                                                                                                     ;
    1166. 

  1166. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1167. 

  1167. ; OPERATION_MODE                ; OUTPUT_ONLY  ; Untyped                                                                                                  ;
    1168. 

  1168. ; DATAA_WIDTH                   ; 20           ; Untyped                                                                                                  ;
    1169. 

  1169. ; DATAB_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1170. 

  1170. ; DATAC_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1171. 

  1171. ; DATAD_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1172. 

  1172. ; ADDNSUB0_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1173. 

  1173. ; ADDNSUB1_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1174. 

  1174. ; ROUND0_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1175. 

  1175. ; ROUND1_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1176. 

  1176. ; SATURATE_CLOCK                ; none         ; Untyped                                                                                                  ;
    1177. 

  1177. ; MULTABSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1178. 

  1178. ; MULTCDSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1179. 

  1179. ; ZEROACC_CLOCK                 ; NONE         ; Untyped                                                                                                  ;
    1180. 

  1180. ; SIGNA_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1181. 

  1181. ; SIGNB_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1182. 

  1182. ; OUTPUT_CLOCK                  ; NONE         ; Untyped                                                                                                  ;
    1183. 

  1183. ; ADDNSUB0_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1184. 

  1184. ; ADDNSUB1_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1185. 

  1185. ; ROUND0_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1186. 

  1186. ; ROUND1_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1187. 

  1187. ; SATURATE_CLEAR                ; none         ; Untyped                                                                                                  ;
    1188. 

  1188. ; MULTABSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1189. 

  1189. ; MULTCDSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1190. 

  1190. ; ZEROACC_CLEAR                 ; NONE         ; Untyped                                                                                                  ;
    1191. 

  1191. ; SIGNA_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1192. 

  1192. ; SIGNB_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1193. 

  1193. ; OUTPUT_CLEAR                  ; NONE         ; Untyped                                                                                                  ;
    1194. 

  1194. ; ADDNSUB0_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1195. 

  1195. ; ADDNSUB1_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1196. 

  1196. ; ROUND0_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1197. 

  1197. ; ROUND1_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1198. 

  1198. ; SATURATE_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1199. 

  1199. ; MULTABSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1200. 

  1200. ; MULTCDSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1201. 

  1201. ; ZEROACC_PIPELINE_CLOCK        ; NONE         ; Untyped                                                                                                  ;
    1202. 

  1202. ; SIGNA_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1203. 

  1203. ; SIGNB_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1204. 

  1204. ; ADDNSUB0_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1205. 

  1205. ; ADDNSUB1_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1206. 

  1206. ; ROUND0_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1207. 

  1207. ; ROUND1_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1208. 

  1208. ; SATURATE_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1209. 

  1209. ; MULTABSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1210. 

  1210. ; MULTCDSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1211. 

  1211. ; ZEROACC_PIPELINE_CLEAR        ; NONE         ; Untyped                                                                                                  ;
    1212. 

  1212. ; SIGNA_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1213. 

  1213. ; SIGNB_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1214. 

  1214. ; MODE0_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1215. 

  1215. ; MODE1_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1216. 

  1216. ; ZEROACC1_CLOCK                ; none         ; Untyped                                                                                                  ;
    1217. 

  1217. ; SATURATE1_CLOCK               ; none         ; Untyped                                                                                                  ;
    1218. 

  1218. ; OUTPUT1_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1219. 

  1219. ; OUTPUT2_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1220. 

  1220. ; OUTPUT3_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1221. 

  1221. ; OUTPUT4_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1222. 

  1222. ; OUTPUT5_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1223. 

  1223. ; OUTPUT6_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1224. 

  1224. ; OUTPUT7_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1225. 

  1225. ; MODE0_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1226. 

  1226. ; MODE1_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1227. 

  1227. ; ZEROACC1_CLEAR                ; none         ; Untyped                                                                                                  ;
    1228. 

  1228. ; SATURATE1_CLEAR               ; none         ; Untyped                                                                                                  ;
    1229. 

  1229. ; OUTPUT1_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1230. 

  1230. ; OUTPUT2_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1231. 

  1231. ; OUTPUT3_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1232. 

  1232. ; OUTPUT4_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1233. 

  1233. ; OUTPUT5_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1234. 

  1234. ; OUTPUT6_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1235. 

  1235. ; OUTPUT7_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1236. 

  1236. ; MODE0_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1237. 

  1237. ; MODE1_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1238. 

  1238. ; ZEROACC1_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1239. 

  1239. ; SATURATE1_PIPELINE_CLOCK      ; none         ; Untyped                                                                                                  ;
    1240. 

  1240. ; MODE0_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1241. 

  1241. ; MODE1_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1242. 

  1242. ; ZEROACC1_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1243. 

  1243. ; SATURATE1_PIPELINE_CLEAR      ; none         ; Untyped                                                                                                  ;
    1244. 

  1244. ; FIRST_ADDER0_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1245. 

  1245. ; FIRST_ADDER1_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1246. 

  1246. ; FIRST_ADDER0_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1247. 

  1247. ; FIRST_ADDER1_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1248. 

  1248. ; DATAA_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1249. 

  1249. ; DATAC_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1250. 

  1250. ; USING_ROUNDING                ; NO           ; Untyped                                                                                                  ;
    1251. 

  1251. ; USING_SATURATION              ; NO           ; Untyped                                                                                                  ;
    1252. 

  1252. ; USING_MULT_SATURATION         ; NO           ; Untyped                                                                                                  ;
    1253. 

  1253. ; USING_LOADABLE_ACCUM          ; NO           ; Untyped                                                                                                  ;
    1254. 

  1254. ; LOADABLE_ACCUM_SUPPORTED      ; NO           ; Untyped                                                                                                  ;
    1255. 

  1255. ; USING_CHAINOUT                ; NO           ; Untyped                                                                                                  ;
    1256. 

  1256. ; CHAININ_WIDTH                 ; 0            ; Untyped                                                                                                  ;
    1257. 

  1257. ; CHAINOUT_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1258. 

  1258. ; CHAINOUT_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1259. 

  1259. ; CBXI_PARAMETER                ; mac_out_lr82 ; Untyped                                                                                                  ;
    1260. 

  1260. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1261. 

  1261. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1262. 

  1262. 

  1263. 

  1264. +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
    1265. 

  1265. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1 ;
    1266. 

  1266. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1267. 

  1267. ; Parameter Name               ; Value         ; Type                                                                                                       ;
    1268. 

  1268. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1269. 

  1269. ; LPM_WIDTHS                   ; 1             ; Untyped                                                                                                    ;
    1270. 

  1270. ; DATAA_WIDTH                  ; 10            ; Untyped                                                                                                    ;
    1271. 

  1271. ; DATAB_WIDTH                  ; 9             ; Untyped                                                                                                    ;
    1272. 

  1272. ; DATAA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1273. 

  1273. ; DATAB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1274. 

  1274. ; SIGNA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1275. 

  1275. ; SIGNB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1276. 

  1276. ; OUTPUT_CLOCK                 ; NONE          ; Untyped                                                                                                    ;
    1277. 

  1277. ; DATAA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1278. 

  1278. ; DATAB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1279. 

  1279. ; SIGNA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1280. 

  1280. ; SIGNB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1281. 

  1281. ; OUTPUT_CLEAR                 ; NONE          ; Untyped                                                                                                    ;
    1282. 

  1282. ; ROUND_CLOCK                  ; none          ; Untyped                                                                                                    ;
    1283. 

  1283. ; ROUND_CLEAR                  ; none          ; Untyped                                                                                                    ;
    1284. 

  1284. ; SATURATE_CLOCK               ; none          ; Untyped                                                                                                    ;
    1285. 

  1285. ; SATURATE_CLEAR               ; none          ; Untyped                                                                                                    ;
    1286. 

  1286. ; BYPASS_MULTIPLIER            ; NO            ; Untyped                                                                                                    ;
    1287. 

  1287. ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO            ; Untyped                                                                                                    ;
    1288. 

  1288. ; USING_ROUNDING               ; NO            ; Untyped                                                                                                    ;
    1289. 

  1289. ; USING_SATURATION             ; NO            ; Untyped                                                                                                    ;
    1290. 

  1290. ; EXTRA_OUTPUT_CLOCK           ; none          ; Untyped                                                                                                    ;
    1291. 

  1291. ; EXTRA_SIGNA_CLOCK            ; none          ; Untyped                                                                                                    ;
    1292. 

  1292. ; EXTRA_SIGNB_CLOCK            ; none          ; Untyped                                                                                                    ;
    1293. 

  1293. ; EXTRA_OUTPUT_CLEAR           ; none          ; Untyped                                                                                                    ;
    1294. 

  1294. ; EXTRA_SIGNA_CLEAR            ; none          ; Untyped                                                                                                    ;
    1295. 

  1295. ; EXTRA_SIGNB_CLEAR            ; none          ; Untyped                                                                                                    ;
    1296. 

  1296. ; MULT_PIPELINE                ; 0             ; Untyped                                                                                                    ;
    1297. 

  1297. ; MULT_CLOCK                   ; NONE          ; Untyped                                                                                                    ;
    1298. 

  1298. ; MULT_CLEAR                   ; NONE          ; Untyped                                                                                                    ;
    1299. 

  1299. ; MULT_REPRESENTATION_A        ; UNSIGNED      ; Untyped                                                                                                    ;
    1300. 

  1300. ; MULT_REPRESENTATION_B        ; UNSIGNED      ; Untyped                                                                                                    ;
    1301. 

  1301. ; MULT_INPUT_A_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1302. 

  1302. ; MULT_INPUT_B_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1303. 

  1303. ; MULT_INPUT_A_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1304. 

  1304. ; MULT_INPUT_B_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1305. 

  1305. ; MULT_MAXIMIZE_SPEED          ; 5             ; Untyped                                                                                                    ;
    1306. 

  1306. ; CBXI_PARAMETER               ; mac_mult_jtg1 ; Untyped                                                                                                    ;
    1307. 

  1307. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1308. 

  1308. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1309. 

  1309. 

  1310. 

  1311. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
    1312. 

  1312. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2 ;
    1313. 

  1313. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1314. 

  1314. ; Parameter Name                ; Value        ; Type                                                                                                     ;
    1315. 

  1315. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1316. 

  1316. ; OPERATION_MODE                ; OUTPUT_ONLY  ; Untyped                                                                                                  ;
    1317. 

  1317. ; DATAA_WIDTH                   ; 19           ; Untyped                                                                                                  ;
    1318. 

  1318. ; DATAB_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1319. 

  1319. ; DATAC_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1320. 

  1320. ; DATAD_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1321. 

  1321. ; ADDNSUB0_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1322. 

  1322. ; ADDNSUB1_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1323. 

  1323. ; ROUND0_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1324. 

  1324. ; ROUND1_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1325. 

  1325. ; SATURATE_CLOCK                ; none         ; Untyped                                                                                                  ;
    1326. 

  1326. ; MULTABSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1327. 

  1327. ; MULTCDSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1328. 

  1328. ; ZEROACC_CLOCK                 ; NONE         ; Untyped                                                                                                  ;
    1329. 

  1329. ; SIGNA_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1330. 

  1330. ; SIGNB_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1331. 

  1331. ; OUTPUT_CLOCK                  ; NONE         ; Untyped                                                                                                  ;
    1332. 

  1332. ; ADDNSUB0_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1333. 

  1333. ; ADDNSUB1_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1334. 

  1334. ; ROUND0_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1335. 

  1335. ; ROUND1_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1336. 

  1336. ; SATURATE_CLEAR                ; none         ; Untyped                                                                                                  ;
    1337. 

  1337. ; MULTABSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1338. 

  1338. ; MULTCDSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1339. 

  1339. ; ZEROACC_CLEAR                 ; NONE         ; Untyped                                                                                                  ;
    1340. 

  1340. ; SIGNA_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1341. 

  1341. ; SIGNB_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1342. 

  1342. ; OUTPUT_CLEAR                  ; NONE         ; Untyped                                                                                                  ;
    1343. 

  1343. ; ADDNSUB0_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1344. 

  1344. ; ADDNSUB1_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1345. 

  1345. ; ROUND0_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1346. 

  1346. ; ROUND1_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1347. 

  1347. ; SATURATE_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1348. 

  1348. ; MULTABSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1349. 

  1349. ; MULTCDSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1350. 

  1350. ; ZEROACC_PIPELINE_CLOCK        ; NONE         ; Untyped                                                                                                  ;
    1351. 

  1351. ; SIGNA_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1352. 

  1352. ; SIGNB_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1353. 

  1353. ; ADDNSUB0_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1354. 

  1354. ; ADDNSUB1_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1355. 

  1355. ; ROUND0_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1356. 

  1356. ; ROUND1_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1357. 

  1357. ; SATURATE_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1358. 

  1358. ; MULTABSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1359. 

  1359. ; MULTCDSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1360. 

  1360. ; ZEROACC_PIPELINE_CLEAR        ; NONE         ; Untyped                                                                                                  ;
    1361. 

  1361. ; SIGNA_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1362. 

  1362. ; SIGNB_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1363. 

  1363. ; MODE0_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1364. 

  1364. ; MODE1_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1365. 

  1365. ; ZEROACC1_CLOCK                ; none         ; Untyped                                                                                                  ;
    1366. 

  1366. ; SATURATE1_CLOCK               ; none         ; Untyped                                                                                                  ;
    1367. 

  1367. ; OUTPUT1_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1368. 

  1368. ; OUTPUT2_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1369. 

  1369. ; OUTPUT3_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1370. 

  1370. ; OUTPUT4_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1371. 

  1371. ; OUTPUT5_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1372. 

  1372. ; OUTPUT6_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1373. 

  1373. ; OUTPUT7_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1374. 

  1374. ; MODE0_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1375. 

  1375. ; MODE1_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1376. 

  1376. ; ZEROACC1_CLEAR                ; none         ; Untyped                                                                                                  ;
    1377. 

  1377. ; SATURATE1_CLEAR               ; none         ; Untyped                                                                                                  ;
    1378. 

  1378. ; OUTPUT1_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1379. 

  1379. ; OUTPUT2_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1380. 

  1380. ; OUTPUT3_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1381. 

  1381. ; OUTPUT4_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1382. 

  1382. ; OUTPUT5_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1383. 

  1383. ; OUTPUT6_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1384. 

  1384. ; OUTPUT7_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1385. 

  1385. ; MODE0_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1386. 

  1386. ; MODE1_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1387. 

  1387. ; ZEROACC1_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1388. 

  1388. ; SATURATE1_PIPELINE_CLOCK      ; none         ; Untyped                                                                                                  ;
    1389. 

  1389. ; MODE0_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1390. 

  1390. ; MODE1_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1391. 

  1391. ; ZEROACC1_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1392. 

  1392. ; SATURATE1_PIPELINE_CLEAR      ; none         ; Untyped                                                                                                  ;
    1393. 

  1393. ; FIRST_ADDER0_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1394. 

  1394. ; FIRST_ADDER1_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1395. 

  1395. ; FIRST_ADDER0_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1396. 

  1396. ; FIRST_ADDER1_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1397. 

  1397. ; DATAA_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1398. 

  1398. ; DATAC_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1399. 

  1399. ; USING_ROUNDING                ; NO           ; Untyped                                                                                                  ;
    1400. 

  1400. ; USING_SATURATION              ; NO           ; Untyped                                                                                                  ;
    1401. 

  1401. ; USING_MULT_SATURATION         ; NO           ; Untyped                                                                                                  ;
    1402. 

  1402. ; USING_LOADABLE_ACCUM          ; NO           ; Untyped                                                                                                  ;
    1403. 

  1403. ; LOADABLE_ACCUM_SUPPORTED      ; NO           ; Untyped                                                                                                  ;
    1404. 

  1404. ; USING_CHAINOUT                ; NO           ; Untyped                                                                                                  ;
    1405. 

  1405. ; CHAININ_WIDTH                 ; 0            ; Untyped                                                                                                  ;
    1406. 

  1406. ; CHAINOUT_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1407. 

  1407. ; CHAINOUT_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1408. 

  1408. ; CBXI_PARAMETER                ; mac_out_5s82 ; Untyped                                                                                                  ;
    1409. 

  1409. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1410. 

  1410. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1411. 

  1411. 

  1412. 

  1413. +-----------------------------------------------------------------------------------------------------------------------------------------------------------+
    1414. 

  1414. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_mult:mac_mult1 ;
    1415. 

  1415. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1416. 

  1416. ; Parameter Name               ; Value         ; Type                                                                                                       ;
    1417. 

  1417. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1418. 

  1418. ; LPM_WIDTHS                   ; 1             ; Untyped                                                                                                    ;
    1419. 

  1419. ; DATAA_WIDTH                  ; 10            ; Untyped                                                                                                    ;
    1420. 

  1420. ; DATAB_WIDTH                  ; 10            ; Untyped                                                                                                    ;
    1421. 

  1421. ; DATAA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1422. 

  1422. ; DATAB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1423. 

  1423. ; SIGNA_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1424. 

  1424. ; SIGNB_CLOCK                  ; NONE          ; Untyped                                                                                                    ;
    1425. 

  1425. ; OUTPUT_CLOCK                 ; NONE          ; Untyped                                                                                                    ;
    1426. 

  1426. ; DATAA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1427. 

  1427. ; DATAB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1428. 

  1428. ; SIGNA_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1429. 

  1429. ; SIGNB_CLEAR                  ; NONE          ; Untyped                                                                                                    ;
    1430. 

  1430. ; OUTPUT_CLEAR                 ; NONE          ; Untyped                                                                                                    ;
    1431. 

  1431. ; ROUND_CLOCK                  ; none          ; Untyped                                                                                                    ;
    1432. 

  1432. ; ROUND_CLEAR                  ; none          ; Untyped                                                                                                    ;
    1433. 

  1433. ; SATURATE_CLOCK               ; none          ; Untyped                                                                                                    ;
    1434. 

  1434. ; SATURATE_CLEAR               ; none          ; Untyped                                                                                                    ;
    1435. 

  1435. ; BYPASS_MULTIPLIER            ; NO            ; Untyped                                                                                                    ;
    1436. 

  1436. ; DYNAMIC_SCAN_CHAIN_SUPPORTED ; NO            ; Untyped                                                                                                    ;
    1437. 

  1437. ; USING_ROUNDING               ; NO            ; Untyped                                                                                                    ;
    1438. 

  1438. ; USING_SATURATION             ; NO            ; Untyped                                                                                                    ;
    1439. 

  1439. ; EXTRA_OUTPUT_CLOCK           ; none          ; Untyped                                                                                                    ;
    1440. 

  1440. ; EXTRA_SIGNA_CLOCK            ; none          ; Untyped                                                                                                    ;
    1441. 

  1441. ; EXTRA_SIGNB_CLOCK            ; none          ; Untyped                                                                                                    ;
    1442. 

  1442. ; EXTRA_OUTPUT_CLEAR           ; none          ; Untyped                                                                                                    ;
    1443. 

  1443. ; EXTRA_SIGNA_CLEAR            ; none          ; Untyped                                                                                                    ;
    1444. 

  1444. ; EXTRA_SIGNB_CLEAR            ; none          ; Untyped                                                                                                    ;
    1445. 

  1445. ; MULT_PIPELINE                ; 0             ; Untyped                                                                                                    ;
    1446. 

  1446. ; MULT_CLOCK                   ; NONE          ; Untyped                                                                                                    ;
    1447. 

  1447. ; MULT_CLEAR                   ; NONE          ; Untyped                                                                                                    ;
    1448. 

  1448. ; MULT_REPRESENTATION_A        ; UNSIGNED      ; Untyped                                                                                                    ;
    1449. 

  1449. ; MULT_REPRESENTATION_B        ; UNSIGNED      ; Untyped                                                                                                    ;
    1450. 

  1450. ; MULT_INPUT_A_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1451. 

  1451. ; MULT_INPUT_B_IS_CONSTANT     ; NO            ; Untyped                                                                                                    ;
    1452. 

  1452. ; MULT_INPUT_A_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1453. 

  1453. ; MULT_INPUT_B_FIXED_VALUE     ; Bx            ; Untyped                                                                                                    ;
    1454. 

  1454. ; MULT_MAXIMIZE_SPEED          ; 5             ; Untyped                                                                                                    ;
    1455. 

  1455. ; CBXI_PARAMETER               ; mac_mult_iug1 ; Untyped                                                                                                    ;
    1456. 

  1456. +------------------------------+---------------+------------------------------------------------------------------------------------------------------------+
    1457. 

  1457. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1458. 

  1458. 

  1459. 

  1460. +---------------------------------------------------------------------------------------------------------------------------------------------------------+
    1461. 

  1461. ; Parameter Settings for Inferred Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|alt_mac_out:mac_out2 ;
    1462. 

  1462. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1463. 

  1463. ; Parameter Name                ; Value        ; Type                                                                                                     ;
    1464. 

  1464. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1465. 

  1465. ; OPERATION_MODE                ; OUTPUT_ONLY  ; Untyped                                                                                                  ;
    1466. 

  1466. ; DATAA_WIDTH                   ; 20           ; Untyped                                                                                                  ;
    1467. 

  1467. ; DATAB_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1468. 

  1468. ; DATAC_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1469. 

  1469. ; DATAD_WIDTH                   ; 0            ; Untyped                                                                                                  ;
    1470. 

  1470. ; ADDNSUB0_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1471. 

  1471. ; ADDNSUB1_CLOCK                ; NONE         ; Untyped                                                                                                  ;
    1472. 

  1472. ; ROUND0_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1473. 

  1473. ; ROUND1_CLOCK                  ; none         ; Untyped                                                                                                  ;
    1474. 

  1474. ; SATURATE_CLOCK                ; none         ; Untyped                                                                                                  ;
    1475. 

  1475. ; MULTABSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1476. 

  1476. ; MULTCDSATURATE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1477. 

  1477. ; ZEROACC_CLOCK                 ; NONE         ; Untyped                                                                                                  ;
    1478. 

  1478. ; SIGNA_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1479. 

  1479. ; SIGNB_CLOCK                   ; NONE         ; Untyped                                                                                                  ;
    1480. 

  1480. ; OUTPUT_CLOCK                  ; NONE         ; Untyped                                                                                                  ;
    1481. 

  1481. ; ADDNSUB0_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1482. 

  1482. ; ADDNSUB1_CLEAR                ; NONE         ; Untyped                                                                                                  ;
    1483. 

  1483. ; ROUND0_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1484. 

  1484. ; ROUND1_CLEAR                  ; none         ; Untyped                                                                                                  ;
    1485. 

  1485. ; SATURATE_CLEAR                ; none         ; Untyped                                                                                                  ;
    1486. 

  1486. ; MULTABSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1487. 

  1487. ; MULTCDSATURATE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1488. 

  1488. ; ZEROACC_CLEAR                 ; NONE         ; Untyped                                                                                                  ;
    1489. 

  1489. ; SIGNA_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1490. 

  1490. ; SIGNB_CLEAR                   ; NONE         ; Untyped                                                                                                  ;
    1491. 

  1491. ; OUTPUT_CLEAR                  ; NONE         ; Untyped                                                                                                  ;
    1492. 

  1492. ; ADDNSUB0_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1493. 

  1493. ; ADDNSUB1_PIPELINE_CLOCK       ; NONE         ; Untyped                                                                                                  ;
    1494. 

  1494. ; ROUND0_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1495. 

  1495. ; ROUND1_PIPELINE_CLOCK         ; none         ; Untyped                                                                                                  ;
    1496. 

  1496. ; SATURATE_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1497. 

  1497. ; MULTABSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1498. 

  1498. ; MULTCDSATURATE_PIPELINE_CLOCK ; none         ; Untyped                                                                                                  ;
    1499. 

  1499. ; ZEROACC_PIPELINE_CLOCK        ; NONE         ; Untyped                                                                                                  ;
    1500. 

  1500. ; SIGNA_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1501. 

  1501. ; SIGNB_PIPELINE_CLOCK          ; NONE         ; Untyped                                                                                                  ;
    1502. 

  1502. ; ADDNSUB0_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1503. 

  1503. ; ADDNSUB1_PIPELINE_CLEAR       ; NONE         ; Untyped                                                                                                  ;
    1504. 

  1504. ; ROUND0_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1505. 

  1505. ; ROUND1_PIPELINE_CLEAR         ; none         ; Untyped                                                                                                  ;
    1506. 

  1506. ; SATURATE_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1507. 

  1507. ; MULTABSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1508. 

  1508. ; MULTCDSATURATE_PIPELINE_CLEAR ; none         ; Untyped                                                                                                  ;
    1509. 

  1509. ; ZEROACC_PIPELINE_CLEAR        ; NONE         ; Untyped                                                                                                  ;
    1510. 

  1510. ; SIGNA_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1511. 

  1511. ; SIGNB_PIPELINE_CLEAR          ; NONE         ; Untyped                                                                                                  ;
    1512. 

  1512. ; MODE0_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1513. 

  1513. ; MODE1_CLOCK                   ; none         ; Untyped                                                                                                  ;
    1514. 

  1514. ; ZEROACC1_CLOCK                ; none         ; Untyped                                                                                                  ;
    1515. 

  1515. ; SATURATE1_CLOCK               ; none         ; Untyped                                                                                                  ;
    1516. 

  1516. ; OUTPUT1_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1517. 

  1517. ; OUTPUT2_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1518. 

  1518. ; OUTPUT3_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1519. 

  1519. ; OUTPUT4_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1520. 

  1520. ; OUTPUT5_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1521. 

  1521. ; OUTPUT6_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1522. 

  1522. ; OUTPUT7_CLOCK                 ; none         ; Untyped                                                                                                  ;
    1523. 

  1523. ; MODE0_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1524. 

  1524. ; MODE1_CLEAR                   ; none         ; Untyped                                                                                                  ;
    1525. 

  1525. ; ZEROACC1_CLEAR                ; none         ; Untyped                                                                                                  ;
    1526. 

  1526. ; SATURATE1_CLEAR               ; none         ; Untyped                                                                                                  ;
    1527. 

  1527. ; OUTPUT1_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1528. 

  1528. ; OUTPUT2_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1529. 

  1529. ; OUTPUT3_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1530. 

  1530. ; OUTPUT4_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1531. 

  1531. ; OUTPUT5_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1532. 

  1532. ; OUTPUT6_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1533. 

  1533. ; OUTPUT7_CLEAR                 ; none         ; Untyped                                                                                                  ;
    1534. 

  1534. ; MODE0_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1535. 

  1535. ; MODE1_PIPELINE_CLOCK          ; none         ; Untyped                                                                                                  ;
    1536. 

  1536. ; ZEROACC1_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1537. 

  1537. ; SATURATE1_PIPELINE_CLOCK      ; none         ; Untyped                                                                                                  ;
    1538. 

  1538. ; MODE0_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1539. 

  1539. ; MODE1_PIPELINE_CLEAR          ; none         ; Untyped                                                                                                  ;
    1540. 

  1540. ; ZEROACC1_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1541. 

  1541. ; SATURATE1_PIPELINE_CLEAR      ; none         ; Untyped                                                                                                  ;
    1542. 

  1542. ; FIRST_ADDER0_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1543. 

  1543. ; FIRST_ADDER1_CLOCK            ; NONE         ; Untyped                                                                                                  ;
    1544. 

  1544. ; FIRST_ADDER0_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1545. 

  1545. ; FIRST_ADDER1_CLEAR            ; NONE         ; Untyped                                                                                                  ;
    1546. 

  1546. ; DATAA_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1547. 

  1547. ; DATAC_FORCED_TO_ZERO          ; NO           ; Untyped                                                                                                  ;
    1548. 

  1548. ; USING_ROUNDING                ; NO           ; Untyped                                                                                                  ;
    1549. 

  1549. ; USING_SATURATION              ; NO           ; Untyped                                                                                                  ;
    1550. 

  1550. ; USING_MULT_SATURATION         ; NO           ; Untyped                                                                                                  ;
    1551. 

  1551. ; USING_LOADABLE_ACCUM          ; NO           ; Untyped                                                                                                  ;
    1552. 

  1552. ; LOADABLE_ACCUM_SUPPORTED      ; NO           ; Untyped                                                                                                  ;
    1553. 

  1553. ; USING_CHAINOUT                ; NO           ; Untyped                                                                                                  ;
    1554. 

  1554. ; CHAININ_WIDTH                 ; 0            ; Untyped                                                                                                  ;
    1555. 

  1555. ; CHAINOUT_PIPELINE_CLOCK       ; none         ; Untyped                                                                                                  ;
    1556. 

  1556. ; CHAINOUT_PIPELINE_CLEAR       ; none         ; Untyped                                                                                                  ;
    1557. 

  1557. ; CBXI_PARAMETER                ; mac_out_lr82 ; Untyped                                                                                                  ;
    1558. 

  1558. +-------------------------------+--------------+----------------------------------------------------------------------------------------------------------+
    1559. 

  1559. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1560. 

  1560. 

  1561. 

  1562. +---------------------------------------------------------------------------------------------------------------------------------------------------+
    1563. 

  1563. ; Partition Dependent Files                                                                                                                         ;
    1564. 

  1564. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    1565. 

  1565. ; File                                                                            ; Location           ; Library ; Checksum                         ;
    1566. 

  1566. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    1567. 

  1567. ; libraries/megafunctions/a_rdenreg.inc                                           ; Quartus II Install ; work    ; 3fcdce7559590d5a8afbe64788d201fb ;
    1568. 

  1568. ; libraries/megafunctions/aglobal130.inc                                          ; Quartus II Install ; work    ; 6fc5170a475a9c6f00c3fd7627b30d31 ;
    1569. 

  1569. ; libraries/megafunctions/altdpram.inc                                            ; Quartus II Install ; work    ; 2f9e6727b678ffd76e72bc5a95a26300 ;
    1570. 

  1570. ; libraries/megafunctions/altpll.tdf                                              ; Quartus II Install ; work    ; 2fbd40fef3231c521503c3b7162ebe3e ;
    1571. 

  1571. ; libraries/megafunctions/altram.inc                                              ; Quartus II Install ; work    ; ad5518b39ffd3cf1df377e6360d1c9b6 ;
    1572. 

  1572. ; libraries/megafunctions/altrom.inc                                              ; Quartus II Install ; work    ; 192b74eafa8debf2248ea73881e77f91 ;
    1573. 

  1573. ; libraries/megafunctions/altsyncram.tdf                                          ; Quartus II Install ; work    ; 2d180e92194c1b32bb16b4887ae417e4 ;
    1574. 

  1574. ; libraries/megafunctions/cycloneii_pll.inc                                       ; Quartus II Install ; work    ; c2ee779f089b03bc181df753ea85b3ef ;
    1575. 

  1575. ; libraries/megafunctions/lpm_decode.inc                                          ; Quartus II Install ; work    ; 10da69a8bbd590d66779e7a142f73790 ;
    1576. 

  1576. ; libraries/megafunctions/lpm_mux.inc                                             ; Quartus II Install ; work    ; dd87bed90959d6126db09970164b7ba6 ;
    1577. 

  1577. ; libraries/megafunctions/stratix_pll.inc                                         ; Quartus II Install ; work    ; a9a94c5b0e18105f7ae8c218a67ec9f7 ;
    1578. 

  1578. ; libraries/megafunctions/stratix_ram_block.inc                                   ; Quartus II Install ; work    ; e3a03868917f0b3dd57b6ed1dd195f22 ;
    1579. 

  1579. ; libraries/megafunctions/stratixii_pll.inc                                       ; Quartus II Install ; work    ; 6797ab505ed700f1a221e4a213e106a6 ;
    1580. 

  1580. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute           ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    1581. 

  1581. ; ahb2apb.v                                                                       ; Project Directory  ; work    ; c4d07e481d6d597cf56fdc254ec8bab8 ;
    1582. 

  1582. ; analog_ip.v                                                                     ; Project Directory  ; work    ; 9ce6f7736cc6ec764422aabb35957b2b ;
    1583. 

  1583. ; apb2ram.v                                                                       ; Project Directory  ; work    ; d2319d386e3f52f5093368b85cef65ef ;
    1584. 

  1584. ; baud_detect.v                                                                   ; Project Directory  ; work    ; edeaf273b63cd48e52285dd989701b7b ;
    1585. 

  1585. ; cfg_reg.v                                                                       ; Project Directory  ; work    ; 245eba41e85b4bf89560ef5b37a75d80 ;
    1586. 

  1586. ; db/altpll_6o32.tdf                                                              ; Project Directory  ; work    ; 9c3386175185bf4e2c0ee36f607dfc7f ;
    1587. 

  1587. ; db/altsyncram_sgu1.tdf                                                          ; Project Directory  ; work    ; 1c6c503332b5bdaf6aa11728cd197aa0 ;
    1588. 

  1588. ; example_board.v                                                                 ; Project Directory  ; work    ; 60f1dcec3c4b16342256f6ca0da2bbb3 ;
    1589. 

  1589. ; sine.hex                                                                        ; Project Directory  ; work    ; e7b4ee736c594f02a51ed06e6c1af8bd ;
    1590. 

  1590. ; trig_ctrl.v                                                                     ; Project Directory  ; work    ; 84250c2c4eb94fe0748883cbf26b4a05 ;
    1591. 

  1591. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    1592. 

  1592. 

  1593. 

  1594. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    1595. 

  1595. ; Partition "macro_inst_apb_adc0_inst_adc_inst" Resource Utilization by Entity                                                                                                                                                           ;
    1596. 

  1596. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1597. 

  1597. ; Compilation Hierarchy Node    ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                         ; Library Name ;
    1598. 

  1598. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1599. 

  1599. ; |example_board                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board                                                              ; work         ;
    1600. 

  1600. ;    |analog_ip:macro_inst|     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst                                         ; work         ;
    1601. 

  1601. ;       |apb_adc:apb_adc0_inst| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst                   ; work         ;
    1602. 

  1602. ;          |alta_adc:adc_inst|  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst ; work         ;
    1603. 

  1603. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1604. 

  1604. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    1605. 

  1605. 

  1606. 

  1607. +-----------------------------------------------------------------------------------------------------------+
    1608. 

  1608. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst ;
    1609. 

  1609. +----------------+-------+----------------------------------------------------------------------------------+
    1610. 

  1610. ; Parameter Name ; Value ; Type                                                                             ;
    1611. 

  1611. +----------------+-------+----------------------------------------------------------------------------------+
    1612. 

  1612. ; coord_x        ; 0     ; Signed Integer                                                                   ;
    1613. 

  1613. ; coord_y        ; 0     ; Signed Integer                                                                   ;
    1614. 

  1614. ; coord_z        ; 0     ; Signed Integer                                                                   ;
    1615. 

  1615. +----------------+-------+----------------------------------------------------------------------------------+
    1616. 

  1616. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1617. 

  1617. 

  1618. 

  1619. +-----------------------------------------------------------------------------------------------------------------------------------------+
    1620. 

  1620. ; Partition Dependent Files                                                                                                               ;
    1621. 

  1621. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1622. 

  1622. ; File                                                                            ; Location ; Library ; Checksum                         ;
    1623. 

  1623. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1624. 

  1624. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    1625. 

  1625. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1626. 

  1626. 

  1627. 

  1628. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    1629. 

  1629. ; Partition "macro_inst_apb_dac0_inst_dac_inst" Resource Utilization by Entity                                                                                                                                                           ;
    1630. 

  1630. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1631. 

  1631. ; Compilation Hierarchy Node    ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                         ; Library Name ;
    1632. 

  1632. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1633. 

  1633. ; |example_board                ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board                                                              ; work         ;
    1634. 

  1634. ;    |analog_ip:macro_inst|     ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst                                         ; work         ;
    1635. 

  1635. ;       |apb_dac:apb_dac0_inst| ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst                   ; work         ;
    1636. 

  1636. ;          |alta_dac:dac_inst|  ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst ; work         ;
    1637. 

  1637. +-------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------+--------------+
    1638. 

  1638. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    1639. 

  1639. 

  1640. 

  1641. +-----------------------------------------------------------------------------------------------------------+
    1642. 

  1642. ; Parameter Settings for User Entity Instance: analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst ;
    1643. 

  1643. +----------------+-------+----------------------------------------------------------------------------------+
    1644. 

  1644. ; Parameter Name ; Value ; Type                                                                             ;
    1645. 

  1645. +----------------+-------+----------------------------------------------------------------------------------+
    1646. 

  1646. ; coord_x        ; 0     ; Signed Integer                                                                   ;
    1647. 

  1647. ; coord_y        ; 0     ; Signed Integer                                                                   ;
    1648. 

  1648. ; coord_z        ; 0     ; Signed Integer                                                                   ;
    1649. 

  1649. +----------------+-------+----------------------------------------------------------------------------------+
    1650. 

  1650. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1651. 

  1651. 

  1652. 

  1653. +-----------------------------------------------------------------------------------------------------------------------------------------+
    1654. 

  1654. ; Partition Dependent Files                                                                                                               ;
    1655. 

  1655. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1656. 

  1656. ; File                                                                            ; Location ; Library ; Checksum                         ;
    1657. 

  1657. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1658. 

  1658. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    1659. 

  1659. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1660. 

  1660. 

  1661. 

  1662. +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    1663. 

  1663. ; Partition "rv32" Resource Utilization by Entity                                                                                                                                       ;
    1664. 

  1664. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
    1665. 

  1665. ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name           ; Library Name ;
    1666. 

  1666. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
    1667. 

  1667. ; |example_board             ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board                ; work         ;
    1668. 

  1668. ;    |alta_rv32:rv32|        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |example_board|alta_rv32:rv32 ; work         ;
    1669. 

  1669. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------+--------------+
    1670. 

  1670. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    1671. 

  1671. 

  1672. 

  1673. +-------------------------------------------------------------+
    1674. 

  1674. ; Parameter Settings for User Entity Instance: alta_rv32:rv32 ;
    1675. 

  1675. +----------------+-------+------------------------------------+
    1676. 

  1676. ; Parameter Name ; Value ; Type                               ;
    1677. 

  1677. +----------------+-------+------------------------------------+
    1678. 

  1678. ; coord_x        ; 0     ; Signed Integer                     ;
    1679. 

  1679. ; coord_y        ; 0     ; Signed Integer                     ;
    1680. 

  1680. ; coord_z        ; 0     ; Signed Integer                     ;
    1681. 

  1681. +----------------+-------+------------------------------------+
    1682. 

  1682. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1683. 

  1683. 

  1684. 

  1685. +-----------------------------------------------------------------------------------------------------------------------------------------+
    1686. 

  1686. ; Partition Dependent Files                                                                                                               ;
    1687. 

  1687. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1688. 

  1688. ; File                                                                            ; Location ; Library ; Checksum                         ;
    1689. 

  1689. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1690. 

  1690. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    1691. 

  1691. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    1692. 

  1692. 

  1693. 

  1694. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    1695. 

  1695. ; Port Connectivity Checks: "alta_rv32:rv32"                                                                                                                               ;
    1696. 

  1696. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1697. 

  1697. ; Port                    ; Type             ; Severity ; Details                                                                                                          ;
    1698. 

  1698. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1699. 

  1699. ; ext_resetn              ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    1700. 

  1700. ; test_mode               ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1701. 

  1701. ; usb0_xcvr_clk           ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    1702. 

  1702. ; usb0_id                 ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    1703. 

  1703. ; sys_ctrl_hseEnable      ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1704. 

  1704. ; sys_ctrl_hseBypass      ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1705. 

  1705. ; sys_ctrl_sleep          ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1706. 

  1706. ; sys_ctrl_standby        ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1707. 

  1707. ; dmactive                ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1708. 

  1708. ; swj_JTAGNSW             ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1709. 

  1709. ; swj_JTAGSTATE           ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1710. 

  1710. ; swj_JTAGIR              ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    1711. 

  1711. ; ext_int                 ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1712. 

  1712. ; gpio0_io_out_data[7..2] ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1713. 

  1713. ; gpio0_io_out_en[7..2]   ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1714. 

  1714. ; gpio1_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1715. 

  1715. ; gpio1_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1716. 

  1716. ; gpio1_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1717. 

  1717. ; gpio2_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1718. 

  1718. ; gpio2_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1719. 

  1719. ; gpio2_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1720. 

  1720. ; gpio3_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1721. 

  1721. ; gpio3_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1722. 

  1722. ; gpio3_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1723. 

  1723. ; gpio4_io_out_data[4..3] ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1724. 

  1724. ; gpio4_io_out_data[7]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1725. 

  1725. ; gpio4_io_out_data[0]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1726. 

  1726. ; gpio4_io_out_en[4..3]   ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1727. 

  1727. ; gpio4_io_out_en[7]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1728. 

  1728. ; gpio4_io_out_en[0]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1729. 

  1729. ; gpio5_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1730. 

  1730. ; gpio5_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1731. 

  1731. ; gpio5_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1732. 

  1732. ; gpio6_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1733. 

  1733. ; gpio6_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1734. 

  1734. ; gpio7_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1735. 

  1735. ; gpio7_io_out_data[5..0] ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1736. 

  1736. ; gpio7_io_out_data[7]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1737. 

  1737. ; gpio7_io_out_en[5..0]   ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1738. 

  1738. ; gpio7_io_out_en[7]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1739. 

  1739. ; gpio8_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1740. 

  1740. ; gpio8_io_out_data[7..1] ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1741. 

  1741. ; gpio8_io_out_en[7..1]   ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1742. 

  1742. ; gpio9_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    1743. 

  1743. ; gpio9_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1744. 

  1744. ; gpio9_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1745. 

  1745. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1746. 

  1746. 

  1747. 

  1748. +-----------------------------------------------------------------------------------------------------------------------+
    1749. 

  1749. ; Port Connectivity Checks: "analog_ip:macro_inst|apb2ram:u_apb2ram"                                                    ;
    1750. 

  1750. +-------------+--------+----------+-------------------------------------------------------------------------------------+
    1751. 

  1751. ; Port        ; Type   ; Severity ; Details                                                                             ;
    1752. 

  1752. +-------------+--------+----------+-------------------------------------------------------------------------------------+
    1753. 

  1753. ; apb_pready  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    1754. 

  1754. ; apb_pslverr ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    1755. 

  1755. ; ram_data    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    1756. 

  1756. +-------------+--------+----------+-------------------------------------------------------------------------------------+
    1757. 

  1757. 

  1758. 

  1759. +---------------------------------------------------------------------------------------------------------------------+
    1760. 

  1760. ; Port Connectivity Checks: "analog_ip:macro_inst|baud_detect:u_baud_detect"                                          ;
    1761. 

  1761. +-----------+--------+----------+-------------------------------------------------------------------------------------+
    1762. 

  1762. ; Port      ; Type   ; Severity ; Details                                                                             ;
    1763. 

  1763. +-----------+--------+----------+-------------------------------------------------------------------------------------+
    1764. 

  1764. ; baud_rate ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    1765. 

  1765. +-----------+--------+----------+-------------------------------------------------------------------------------------+
    1766. 

  1766. 

  1767. 

  1768. +-------------------------------------------------------------------------------------------------------------------------------------------------------+
    1769. 

  1769. ; Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst"                                                              ;
    1770. 

  1770. +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1771. 

  1771. ; Port ; Type             ; Severity ; Details                                                                                                          ;
    1772. 

  1772. +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1773. 

  1773. ; dout ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    1774. 

  1774. +------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    1775. 

  1775. 

  1776. 

  1777. +------------------------------------------------------------------------+
    1778. 

  1778. ; Port Connectivity Checks: "analog_ip:macro_inst|apb_dac:apb_dac0_inst" ;
    1779. 

  1779. +---------+--------+----------+------------------------------------------+
    1780. 

  1780. ; Port    ; Type   ; Severity ; Details                                  ;
    1781. 

  1781. +---------+--------+----------+------------------------------------------+
    1782. 

  1782. ; dma_req ; Output ; Info     ; Explicitly unconnected                   ;
    1783. 

  1783. ; dma_clr ; Input  ; Info     ; Stuck at GND                             ;
    1784. 

  1784. +---------+--------+----------+------------------------------------------+
    1785. 

  1785. 

  1786. 

  1787. +---------------------------------------------------------------------------+
    1788. 

  1788. ; Port Connectivity Checks: "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst" ;
    1789. 

  1789. +-------------+--------+----------+-----------------------------------------+
    1790. 

  1790. ; Port        ; Type   ; Severity ; Details                                 ;
    1791. 

  1791. +-------------+--------+----------+-----------------------------------------+
    1792. 

  1792. ; trig_done   ; Output ; Info     ; Explicitly unconnected                  ;
    1793. 

  1793. ; trigger_ptr ; Output ; Info     ; Explicitly unconnected                  ;
    1794. 

  1794. +-------------+--------+----------+-----------------------------------------+
    1795. 

  1795. 

  1796. 

  1797. +----------------------------------------------------------------------------------------------------------------+
    1798. 

  1798. ; Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst"                       ;
    1799. 

  1799. +----------+-----------------+----------+------------------------------------------------------------------------+
    1800. 

  1800. ; Port     ; Type            ; Severity ; Details                                                                ;
    1801. 

  1801. +----------+-----------------+----------+------------------------------------------------------------------------+
    1802. 

  1802. ; insel[4] ; Partition Input ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries ;
    1803. 

  1803. +----------+-----------------+----------+------------------------------------------------------------------------+
    1804. 

  1804. 

  1805. 

  1806. +------------------------------------------------------------------------+
    1807. 

  1807. ; Port Connectivity Checks: "analog_ip:macro_inst|apb_adc:apb_adc0_inst" ;
    1808. 

  1808. +---------+--------+----------+------------------------------------------+
    1809. 

  1809. ; Port    ; Type   ; Severity ; Details                                  ;
    1810. 

  1810. +---------+--------+----------+------------------------------------------+
    1811. 

  1811. ; dma_req ; Output ; Info     ; Explicitly unconnected                   ;
    1812. 

  1812. ; dma_clr ; Input  ; Info     ; Stuck at GND                             ;
    1813. 

  1813. +---------+--------+----------+------------------------------------------+
    1814. 

  1814. 

  1815. 

  1816. +-----------------------------------------------------------------------+
    1817. 

  1817. ; Port Connectivity Checks: "analog_ip:macro_inst|ahb2apb:ahb2apb_inst" ;
    1818. 

  1818. +-----------------+-------+----------+----------------------------------+
    1819. 

  1819. ; Port            ; Type  ; Severity ; Details                          ;
    1820. 

  1820. +-----------------+-------+----------+----------------------------------+
    1821. 

  1821. ; ahb_hmastlock   ; Input ; Info     ; Stuck at GND                     ;
    1822. 

  1822. ; ahb_hsel        ; Input ; Info     ; Stuck at VCC                     ;
    1823. 

  1823. ; ahb_hprot[1..0] ; Input ; Info     ; Stuck at VCC                     ;
    1824. 

  1824. ; ahb_hprot[3..2] ; Input ; Info     ; Stuck at GND                     ;
    1825. 

  1825. ; apb_pready      ; Input ; Info     ; Stuck at VCC                     ;
    1826. 

  1826. ; apb_pslverr     ; Input ; Info     ; Stuck at GND                     ;
    1827. 

  1827. +-----------------+-------+----------+----------------------------------+
    1828. 

  1828. 

  1829. 

  1830. +-----------------------------------------------------+
    1831. 

  1831. ; Port Connectivity Checks: "alta_gclksw:gclksw_inst" ;
    1832. 

  1832. +--------+-------+----------+-------------------------+
    1833. 

  1833. ; Port   ; Type  ; Severity ; Details                 ;
    1834. 

  1834. +--------+-------+----------+-------------------------+
    1835. 

  1835. ; ena    ; Input ; Info     ; Stuck at VCC            ;
    1836. 

  1836. ; clkin3 ; Input ; Info     ; Explicitly unconnected  ;
    1837. 

  1837. +--------+-------+----------+-------------------------+
    1838. 

  1838. 

  1839. 

  1840. +--------------------------------------------------+
    1841. 

  1841. ; Elapsed Time Per Partition                       ;
    1842. 

  1842. +-----------------------------------+--------------+
    1843. 

  1843. ; Partition Name                    ; Elapsed Time ;
    1844. 

  1844. +-----------------------------------+--------------+
    1845. 

  1845. ; Top                               ; 00:00:09     ;
    1846. 

  1846. ; rv32                              ; 00:00:09     ;
    1847. 

  1847. ; macro_inst_apb_adc0_inst_adc_inst ; 00:00:09     ;
    1848. 

  1848. ; macro_inst_apb_dac0_inst_dac_inst ; 00:00:09     ;
    1849. 

  1849. +-----------------------------------+--------------+
    1850. 

  1850. 

  1851. 

  1852. +-------------------------------+
    1853. 

  1853. ; Analysis & Synthesis Messages ;
    1854. 

  1854. +-------------------------------+
    1855. 

  1855. Info: *******************************************************************
    1856. 

  1856. Info: Running Quartus II 64-Bit Analysis & Synthesis
    1857. 

  1857.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    1858. 

  1858.     Info: Processing started: Sat May 09 14:18:35 2026
    1859. 

  1859. Info: Command: quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board
    1860. 

  1860. Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
    1861. 

  1861. Info (12021): Found 1 design units, including 1 entities, in source file trig_ctrl.v
    1862. 

  1862.     Info (12023): Found entity 1: trig_ctrl
    1863. 

  1863. Info (12021): Found 1 design units, including 1 entities, in source file cfg_reg.v
    1864. 

  1864.     Info (12023): Found entity 1: cfg_reg
    1865. 

  1865. Info (12021): Found 1 design units, including 1 entities, in source file apb2ram.v
    1866. 

  1866.     Info (12023): Found entity 1: apb2ram
    1867. 

  1867. Info (12021): Found 1 design units, including 1 entities, in source file baud_detect.v
    1868. 

  1868.     Info (12023): Found entity 1: baud_detect
    1869. 

  1869. Info (12021): Found 1 design units, including 1 entities, in source file ahb2apb.v
    1870. 

  1870.     Info (12023): Found entity 1: ahb2apb
    1871. 

  1871. Info (12021): Found 1 design units, including 1 entities, in source file example_board.v
    1872. 

  1872.     Info (12023): Found entity 1: example_board
    1873. 

  1873. Warning (10275): Verilog HDL Module Instantiation warning at analog_ip.v(314): ignored dangling comma in List of Port Connections
    1874. 

  1874. Warning (10335): Unrecognized synthesis attribute "ram_style" at analog_ip.v(634)
    1875. 

  1875. Info (12021): Found 3 design units, including 3 entities, in source file analog_ip.v
    1876. 

  1876.     Info (12023): Found entity 1: analog_ip
    1877. 

  1877.     Info (12023): Found entity 2: apb_adc
    1878. 

  1878.     Info (12023): Found entity 3: apb_dac
    1879. 

  1879. Info (12021): Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v
    1880. 

  1880.     Info (12023): Found entity 1: alta_slice
    1881. 

  1881.     Info (12023): Found entity 2: alta_clkenctrl_rst
    1882. 

  1882.     Info (12023): Found entity 3: alta_clkenctrl
    1883. 

  1883.     Info (12023): Found entity 4: alta_asyncctrl
    1884. 

  1884.     Info (12023): Found entity 5: alta_syncctrl
    1885. 

  1885.     Info (12023): Found entity 6: alta_io_gclk
    1886. 

  1886.     Info (12023): Found entity 7: alta_gclksel
    1887. 

  1887.     Info (12023): Found entity 8: alta_gclkgen
    1888. 

  1888.     Info (12023): Found entity 9: alta_gclkgen0
    1889. 

  1889.     Info (12023): Found entity 10: alta_gclkgen2
    1890. 

  1890.     Info (12023): Found entity 11: alta_io
    1891. 

  1891.     Info (12023): Found entity 12: alta_rio
    1892. 

  1892.     Info (12023): Found entity 13: alta_srff
    1893. 

  1893.     Info (12023): Found entity 14: alta_dff
    1894. 

  1894.     Info (12023): Found entity 15: alta_ufm_gddd
    1895. 

  1895.     Info (12023): Found entity 16: alta_dff_stall
    1896. 

  1896.     Info (12023): Found entity 17: alta_srlat
    1897. 

  1897.     Info (12023): Found entity 18: alta_dio
    1898. 

  1898.     Info (12023): Found entity 19: alta_indel
    1899. 

  1899.     Info (12023): Found entity 20: alta_dpclkdel
    1900. 

  1900.     Info (12023): Found entity 21: alta_ufms
    1901. 

  1901.     Info (12023): Found entity 22: alta_ufms_sim
    1902. 

  1902.     Info (12023): Found entity 23: alta_pll
    1903. 

  1903.     Info (12023): Found entity 24: alta_pllx
    1904. 

  1904.     Info (12023): Found entity 25: pll_clk_trim
    1905. 

  1905.     Info (12023): Found entity 26: alta_pllv
    1906. 

  1906.     Info (12023): Found entity 27: alta_pllve
    1907. 

  1907.     Info (12023): Found entity 28: alta_sram
    1908. 

  1908.     Info (12023): Found entity 29: alta_dpram16x4
    1909. 

  1909.     Info (12023): Found entity 30: alta_spram16x4
    1910. 

  1910.     Info (12023): Found entity 31: alta_wram
    1911. 

  1911.     Info (12023): Found entity 32: alta_bram_pulse_generator
    1912. 

  1912.     Info (12023): Found entity 33: alta_bram
    1913. 

  1913.     Info (12023): Found entity 34: alta_boot
    1914. 

  1914.     Info (12023): Found entity 35: alta_osc
    1915. 

  1915.     Info (12023): Found entity 36: alta_ufml
    1916. 

  1916.     Info (12023): Found entity 37: alta_jtag
    1917. 

  1917.     Info (12023): Found entity 38: alta_mult
    1918. 

  1918.     Info (12023): Found entity 39: alta_dff_en
    1919. 

  1919.     Info (12023): Found entity 40: alta_multm_add
    1920. 

  1920.     Info (12023): Found entity 41: alta_multm
    1921. 

  1921.     Info (12023): Found entity 42: alta_i2c
    1922. 

  1922.     Info (12023): Found entity 43: alta_spi
    1923. 

  1923.     Info (12023): Found entity 44: alta_irda
    1924. 

  1924.     Info (12023): Found entity 45: alta_bram9k
    1925. 

  1925.     Info (12023): Found entity 46: alta_mcu
    1926. 

  1926.     Info (12023): Found entity 47: alta_mcu_m3
    1927. 

  1927.     Info (12023): Found entity 48: alta_remote
    1928. 

  1928.     Info (12023): Found entity 49: alta_saradc
    1929. 

  1929.     Info (12023): Found entity 50: alta_gclksw
    1930. 

  1930.     Info (12023): Found entity 51: alta_rv32
    1931. 

  1931.     Info (12023): Found entity 52: alta_mipi_clk
    1932. 

  1932.     Info (12023): Found entity 53: alta_adc
    1933. 

  1933.     Info (12023): Found entity 54: alta_dac
    1934. 

  1934.     Info (12023): Found entity 55: alta_cmp
    1935. 

  1935.     Info (12023): Found entity 56: alta_ram4k
    1936. 

  1936.     Info (12023): Found entity 57: alta_ram9k
    1937. 

  1937. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(39): created implicit net for "PIN_10_in"
    1938. 

  1938. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(55): created implicit net for "PIN_21_in"
    1939. 

  1939. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(58): created implicit net for "PIN_29_in"
    1940. 

  1940. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(69): created implicit net for "PIN_31_in"
    1941. 

  1941. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(75): created implicit net for "PIN_HSE_in"
    1942. 

  1942. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(78): created implicit net for "PIN_HSI_in"
    1943. 

  1943. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(81): created implicit net for "PIN_OSC_in"
    1944. 

  1944. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(204): created implicit net for "usb0_xcvr_clk"
    1945. 

  1945. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(205): created implicit net for "bus_clk"
    1946. 

  1946. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(216): created implicit net for "sys_clk"
    1947. 

  1947. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(269): created implicit net for "csn_out_data"
    1948. 

  1948. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(270): created implicit net for "csn_out_en"
    1949. 

  1949. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(271): created implicit net for "rxd1_ip_in"
    1950. 

  1950. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(272): created implicit net for "sck_out_data"
    1951. 

  1951. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(273): created implicit net for "sck_out_en"
    1952. 

  1952. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(274): created implicit net for "so_io1_in"
    1953. 

  1953. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(275): created implicit net for "so_io1_out_data"
    1954. 

  1954. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(276): created implicit net for "so_io1_out_en"
    1955. 

  1955. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(277): created implicit net for "txd1_ip_out_data"
    1956. 

  1956. Warning (10236): Verilog HDL Implicit Net warning at example_board.v(278): created implicit net for "txd1_ip_out_en"
    1957. 

  1957. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for "ena_reg"
    1958. 

  1958. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for "ena_int"
    1959. 

  1959. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for "ena_reg"
    1960. 

  1960. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for "outreg_h"
    1961. 

  1961. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for "outreg_l"
    1962. 

  1962. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for "oe_reg_h"
    1963. 

  1963. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for "oe_reg_l"
    1964. 

  1964. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for "dffOut"
    1965. 

  1965. Warning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    1966. 

  1966. Info (12127): Elaborating entity "example_board" for the top level hierarchy
    1967. 

  1967. Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll_inst"
    1968. 

  1968. Info (12130): Elaborated megafunction instantiation "altpll:pll_inst"
    1969. 

  1969. Info (12133): Instantiated megafunction "altpll:pll_inst" with the following parameter:
    1970. 

  1970.     Info (12134): Parameter "bandwidth_type" = "AUTO"
    1971. 

  1971.     Info (12134): Parameter "clk0_divide_by" = "8"
    1972. 

  1972.     Info (12134): Parameter "clk0_multiply_by" = "104"
    1973. 

  1973.     Info (12134): Parameter "clk0_phase_shift" = "0"
    1974. 

  1974.     Info (12134): Parameter "clk1_divide_by" = "8"
    1975. 

  1975.     Info (12134): Parameter "clk1_multiply_by" = "104"
    1976. 

  1976.     Info (12134): Parameter "clk1_phase_shift" = "0"
    1977. 

  1977.     Info (12134): Parameter "clk2_divide_by" = "8"
    1978. 

  1978.     Info (12134): Parameter "clk2_multiply_by" = "104"
    1979. 

  1979.     Info (12134): Parameter "clk2_phase_shift" = "0"
    1980. 

  1980.     Info (12134): Parameter "clk3_divide_by" = "8"
    1981. 

  1981.     Info (12134): Parameter "clk3_multiply_by" = "104"
    1982. 

  1982.     Info (12134): Parameter "clk3_phase_shift" = "0"
    1983. 

  1983.     Info (12134): Parameter "clk4_divide_by" = "8"
    1984. 

  1984.     Info (12134): Parameter "clk4_multiply_by" = "104"
    1985. 

  1985.     Info (12134): Parameter "clk4_phase_shift" = "0"
    1986. 

  1986.     Info (12134): Parameter "compensate_clock" = "CLK0"
    1987. 

  1987.     Info (12134): Parameter "inclk0_input_frequency" = "125000"
    1988. 

  1988.     Info (12134): Parameter "lpm_type" = "altpll"
    1989. 

  1989.     Info (12134): Parameter "operation_mode" = "NORMAL"
    1990. 

  1990.     Info (12134): Parameter "pll_type" = "AUTO"
    1991. 

  1991.     Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    1992. 

  1992.     Info (12134): Parameter "port_areset" = "PORT_USED"
    1993. 

  1993.     Info (12134): Parameter "port_inclk0" = "PORT_USED"
    1994. 

  1994.     Info (12134): Parameter "port_locked" = "PORT_USED"
    1995. 

  1995.     Info (12134): Parameter "port_clk0" = "PORT_USED"
    1996. 

  1996.     Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    1997. 

  1997.     Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    1998. 

  1998.     Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
    1999. 

  1999.     Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    2000. 

  2000.     Info (12134): Parameter "width_clock" = "5"
    2001. 

  2001.     Info (12134): Parameter "width_phasecounterselect" = "3"
    2002. 

  2002. Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_6o32.tdf
    2003. 

  2003.     Info (12023): Found entity 1: altpll_6o32
    2004. 

  2004. Info (12128): Elaborating entity "altpll_6o32" for hierarchy "altpll:pll_inst|altpll_6o32:auto_generated"
    2005. 

  2005. Info (12128): Elaborating entity "alta_gclksw" for hierarchy "alta_gclksw:gclksw_inst"
    2006. 

  2006. Info (12128): Elaborating entity "analog_ip" for hierarchy "analog_ip:macro_inst"
    2007. 

  2007. Warning (10230): Verilog HDL assignment warning at analog_ip.v(136): truncated value with size 32 to match size of target (4)
    2008. 

  2008. Info (10264): Verilog HDL Case Statement information at analog_ip.v(475): all case item expressions in this case statement are onehot
    2009. 

  2009. Info (12128): Elaborating entity "ahb2apb" for hierarchy "analog_ip:macro_inst|ahb2apb:ahb2apb_inst"
    2010. 

  2010. Warning (10764): Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned
    2011. 

  2011. Warning (10230): Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4)
    2012. 

  2012. Info (12128): Elaborating entity "cfg_reg" for hierarchy "analog_ip:macro_inst|cfg_reg:cfg_reg_inst"
    2013. 

  2013. Info (12128): Elaborating entity "apb_adc" for hierarchy "analog_ip:macro_inst|apb_adc:apb_adc0_inst"
    2014. 

  2014. Info (12128): Elaborating entity "alta_adc" for hierarchy "analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst"
    2015. 

  2015. Info (12128): Elaborating entity "trig_ctrl" for hierarchy "analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"
    2016. 

  2016. Warning (10230): Verilog HDL assignment warning at trig_ctrl.v(163): truncated value with size 32 to match size of target (10)
    2017. 

  2017. Warning (10230): Verilog HDL assignment warning at trig_ctrl.v(359): truncated value with size 32 to match size of target (10)
    2018. 

  2018. Info (10264): Verilog HDL Case Statement information at trig_ctrl.v(345): all case item expressions in this case statement are onehot
    2019. 

  2019. Info (12128): Elaborating entity "apb_dac" for hierarchy "analog_ip:macro_inst|apb_dac:apb_dac0_inst"
    2020. 

  2020. Warning (10230): Verilog HDL assignment warning at sine.hex(1): truncated value with size 12 to match size of target (10)
    2021. 

  2021. Warning (10230): Verilog HDL assignment warning at sine.hex(2): truncated value with size 12 to match size of target (10)
    2022. 

  2022. Warning (10230): Verilog HDL assignment warning at sine.hex(3): truncated value with size 12 to match size of target (10)
    2023. 

  2023. Warning (10230): Verilog HDL assignment warning at sine.hex(4): truncated value with size 12 to match size of target (10)
    2024. 

  2024. Warning (10230): Verilog HDL assignment warning at sine.hex(5): truncated value with size 12 to match size of target (10)
    2025. 

  2025. Warning (10230): Verilog HDL assignment warning at sine.hex(6): truncated value with size 12 to match size of target (10)
    2026. 

  2026. Warning (10230): Verilog HDL assignment warning at sine.hex(7): truncated value with size 12 to match size of target (10)
    2027. 

  2027. Warning (10230): Verilog HDL assignment warning at sine.hex(8): truncated value with size 12 to match size of target (10)
    2028. 

  2028. Warning (10230): Verilog HDL assignment warning at sine.hex(9): truncated value with size 12 to match size of target (10)
    2029. 

  2029. Warning (10230): Verilog HDL assignment warning at sine.hex(10): truncated value with size 12 to match size of target (10)
    2030. 

  2030. Warning (10230): Verilog HDL assignment warning at sine.hex(11): truncated value with size 12 to match size of target (10)
    2031. 

  2031. Warning (10230): Verilog HDL assignment warning at sine.hex(12): truncated value with size 12 to match size of target (10)
    2032. 

  2032. Warning (10230): Verilog HDL assignment warning at sine.hex(13): truncated value with size 12 to match size of target (10)
    2033. 

  2033. Warning (10230): Verilog HDL assignment warning at sine.hex(14): truncated value with size 12 to match size of target (10)
    2034. 

  2034. Warning (10230): Verilog HDL assignment warning at sine.hex(15): truncated value with size 12 to match size of target (10)
    2035. 

  2035. Warning (10230): Verilog HDL assignment warning at sine.hex(16): truncated value with size 12 to match size of target (10)
    2036. 

  2036. Warning (10230): Verilog HDL assignment warning at sine.hex(17): truncated value with size 12 to match size of target (10)
    2037. 

  2037. Warning (10230): Verilog HDL assignment warning at sine.hex(18): truncated value with size 12 to match size of target (10)
    2038. 

  2038. Warning (10230): Verilog HDL assignment warning at sine.hex(19): truncated value with size 12 to match size of target (10)
    2039. 

  2039. Warning (10230): Verilog HDL assignment warning at sine.hex(20): truncated value with size 12 to match size of target (10)
    2040. 

  2040. Warning (10230): Verilog HDL assignment warning at sine.hex(21): truncated value with size 12 to match size of target (10)
    2041. 

  2041. Warning (10230): Verilog HDL assignment warning at sine.hex(22): truncated value with size 12 to match size of target (10)
    2042. 

  2042. Warning (10230): Verilog HDL assignment warning at sine.hex(23): truncated value with size 12 to match size of target (10)
    2043. 

  2043. Warning (10230): Verilog HDL assignment warning at sine.hex(24): truncated value with size 12 to match size of target (10)
    2044. 

  2044. Warning (10230): Verilog HDL assignment warning at sine.hex(25): truncated value with size 12 to match size of target (10)
    2045. 

  2045. Warning (10230): Verilog HDL assignment warning at sine.hex(26): truncated value with size 12 to match size of target (10)
    2046. 

  2046. Warning (10230): Verilog HDL assignment warning at sine.hex(27): truncated value with size 12 to match size of target (10)
    2047. 

  2047. Warning (10230): Verilog HDL assignment warning at sine.hex(28): truncated value with size 12 to match size of target (10)
    2048. 

  2048. Warning (10230): Verilog HDL assignment warning at sine.hex(29): truncated value with size 12 to match size of target (10)
    2049. 

  2049. Warning (10230): Verilog HDL assignment warning at sine.hex(30): truncated value with size 12 to match size of target (10)
    2050. 

  2050. Warning (10230): Verilog HDL assignment warning at sine.hex(31): truncated value with size 12 to match size of target (10)
    2051. 

  2051. Warning (10230): Verilog HDL assignment warning at sine.hex(32): truncated value with size 12 to match size of target (10)
    2052. 

  2052. Warning (10230): Verilog HDL assignment warning at sine.hex(33): truncated value with size 12 to match size of target (10)
    2053. 

  2053. Warning (10230): Verilog HDL assignment warning at sine.hex(34): truncated value with size 12 to match size of target (10)
    2054. 

  2054. Warning (10230): Verilog HDL assignment warning at sine.hex(35): truncated value with size 12 to match size of target (10)
    2055. 

  2055. Warning (10230): Verilog HDL assignment warning at sine.hex(36): truncated value with size 12 to match size of target (10)
    2056. 

  2056. Warning (10230): Verilog HDL assignment warning at sine.hex(37): truncated value with size 12 to match size of target (10)
    2057. 

  2057. Warning (10230): Verilog HDL assignment warning at sine.hex(38): truncated value with size 12 to match size of target (10)
    2058. 

  2058. Warning (10230): Verilog HDL assignment warning at sine.hex(39): truncated value with size 12 to match size of target (10)
    2059. 

  2059. Warning (10230): Verilog HDL assignment warning at sine.hex(40): truncated value with size 12 to match size of target (10)
    2060. 

  2060. Warning (10230): Verilog HDL assignment warning at sine.hex(41): truncated value with size 12 to match size of target (10)
    2061. 

  2061. Warning (10230): Verilog HDL assignment warning at sine.hex(42): truncated value with size 12 to match size of target (10)
    2062. 

  2062. Warning (10230): Verilog HDL assignment warning at sine.hex(43): truncated value with size 12 to match size of target (10)
    2063. 

  2063. Warning (10230): Verilog HDL assignment warning at sine.hex(44): truncated value with size 12 to match size of target (10)
    2064. 

  2064. Warning (10230): Verilog HDL assignment warning at sine.hex(45): truncated value with size 12 to match size of target (10)
    2065. 

  2065. Warning (10230): Verilog HDL assignment warning at sine.hex(46): truncated value with size 12 to match size of target (10)
    2066. 

  2066. Warning (10230): Verilog HDL assignment warning at sine.hex(47): truncated value with size 12 to match size of target (10)
    2067. 

  2067. Warning (10230): Verilog HDL assignment warning at sine.hex(48): truncated value with size 12 to match size of target (10)
    2068. 

  2068. Warning (10230): Verilog HDL assignment warning at sine.hex(49): truncated value with size 12 to match size of target (10)
    2069. 

  2069. Warning (10230): Verilog HDL assignment warning at sine.hex(50): truncated value with size 12 to match size of target (10)
    2070. 

  2070. Warning (10230): Verilog HDL assignment warning at sine.hex(51): truncated value with size 12 to match size of target (10)
    2071. 

  2071. Warning (10230): Verilog HDL assignment warning at sine.hex(52): truncated value with size 12 to match size of target (10)
    2072. 

  2072. Warning (10230): Verilog HDL assignment warning at sine.hex(53): truncated value with size 12 to match size of target (10)
    2073. 

  2073. Warning (10230): Verilog HDL assignment warning at sine.hex(54): truncated value with size 12 to match size of target (10)
    2074. 

  2074. Warning (10230): Verilog HDL assignment warning at sine.hex(55): truncated value with size 12 to match size of target (10)
    2075. 

  2075. Warning (10230): Verilog HDL assignment warning at sine.hex(56): truncated value with size 12 to match size of target (10)
    2076. 

  2076. Warning (10230): Verilog HDL assignment warning at sine.hex(57): truncated value with size 12 to match size of target (10)
    2077. 

  2077. Warning (10230): Verilog HDL assignment warning at sine.hex(58): truncated value with size 12 to match size of target (10)
    2078. 

  2078. Warning (10230): Verilog HDL assignment warning at sine.hex(59): truncated value with size 12 to match size of target (10)
    2079. 

  2079. Warning (10230): Verilog HDL assignment warning at sine.hex(60): truncated value with size 12 to match size of target (10)
    2080. 

  2080. Warning (10230): Verilog HDL assignment warning at sine.hex(61): truncated value with size 12 to match size of target (10)
    2081. 

  2081. Warning (10230): Verilog HDL assignment warning at sine.hex(62): truncated value with size 12 to match size of target (10)
    2082. 

  2082. Warning (10230): Verilog HDL assignment warning at sine.hex(63): truncated value with size 12 to match size of target (10)
    2083. 

  2083. Warning (10230): Verilog HDL assignment warning at sine.hex(64): truncated value with size 12 to match size of target (10)
    2084. 

  2084. Warning (10230): Verilog HDL assignment warning at sine.hex(65): truncated value with size 12 to match size of target (10)
    2085. 

  2085. Warning (10230): Verilog HDL assignment warning at sine.hex(66): truncated value with size 12 to match size of target (10)
    2086. 

  2086. Warning (10230): Verilog HDL assignment warning at sine.hex(67): truncated value with size 12 to match size of target (10)
    2087. 

  2087. Warning (10230): Verilog HDL assignment warning at sine.hex(68): truncated value with size 12 to match size of target (10)
    2088. 

  2088. Warning (10230): Verilog HDL assignment warning at sine.hex(69): truncated value with size 12 to match size of target (10)
    2089. 

  2089. Warning (10230): Verilog HDL assignment warning at sine.hex(70): truncated value with size 12 to match size of target (10)
    2090. 

  2090. Warning (10230): Verilog HDL assignment warning at sine.hex(71): truncated value with size 12 to match size of target (10)
    2091. 

  2091. Warning (10230): Verilog HDL assignment warning at sine.hex(72): truncated value with size 12 to match size of target (10)
    2092. 

  2092. Warning (10230): Verilog HDL assignment warning at sine.hex(73): truncated value with size 12 to match size of target (10)
    2093. 

  2093. Warning (10230): Verilog HDL assignment warning at sine.hex(74): truncated value with size 12 to match size of target (10)
    2094. 

  2094. Warning (10230): Verilog HDL assignment warning at sine.hex(75): truncated value with size 12 to match size of target (10)
    2095. 

  2095. Warning (10230): Verilog HDL assignment warning at sine.hex(76): truncated value with size 12 to match size of target (10)
    2096. 

  2096. Warning (10230): Verilog HDL assignment warning at sine.hex(77): truncated value with size 12 to match size of target (10)
    2097. 

  2097. Warning (10230): Verilog HDL assignment warning at sine.hex(78): truncated value with size 12 to match size of target (10)
    2098. 

  2098. Warning (10230): Verilog HDL assignment warning at sine.hex(79): truncated value with size 12 to match size of target (10)
    2099. 

  2099. Warning (10230): Verilog HDL assignment warning at sine.hex(80): truncated value with size 12 to match size of target (10)
    2100. 

  2100. Warning (10230): Verilog HDL assignment warning at sine.hex(81): truncated value with size 12 to match size of target (10)
    2101. 

  2101. Warning (10230): Verilog HDL assignment warning at sine.hex(82): truncated value with size 12 to match size of target (10)
    2102. 

  2102. Warning (10230): Verilog HDL assignment warning at sine.hex(83): truncated value with size 12 to match size of target (10)
    2103. 

  2103. Warning (10230): Verilog HDL assignment warning at sine.hex(84): truncated value with size 12 to match size of target (10)
    2104. 

  2104. Warning (10230): Verilog HDL assignment warning at sine.hex(85): truncated value with size 12 to match size of target (10)
    2105. 

  2105. Warning (10230): Verilog HDL assignment warning at sine.hex(86): truncated value with size 12 to match size of target (10)
    2106. 

  2106. Warning (10230): Verilog HDL assignment warning at sine.hex(87): truncated value with size 12 to match size of target (10)
    2107. 

  2107. Warning (10230): Verilog HDL assignment warning at sine.hex(88): truncated value with size 12 to match size of target (10)
    2108. 

  2108. Warning (10230): Verilog HDL assignment warning at sine.hex(89): truncated value with size 12 to match size of target (10)
    2109. 

  2109. Warning (10230): Verilog HDL assignment warning at sine.hex(90): truncated value with size 12 to match size of target (10)
    2110. 

  2110. Warning (10230): Verilog HDL assignment warning at sine.hex(91): truncated value with size 12 to match size of target (10)
    2111. 

  2111. Warning (10230): Verilog HDL assignment warning at sine.hex(92): truncated value with size 12 to match size of target (10)
    2112. 

  2112. Warning (10230): Verilog HDL assignment warning at sine.hex(93): truncated value with size 12 to match size of target (10)
    2113. 

  2113. Warning (10230): Verilog HDL assignment warning at sine.hex(94): truncated value with size 12 to match size of target (10)
    2114. 

  2114. Warning (10230): Verilog HDL assignment warning at sine.hex(95): truncated value with size 12 to match size of target (10)
    2115. 

  2115. Warning (10230): Verilog HDL assignment warning at sine.hex(96): truncated value with size 12 to match size of target (10)
    2116. 

  2116. Warning (10230): Verilog HDL assignment warning at sine.hex(97): truncated value with size 12 to match size of target (10)
    2117. 

  2117. Warning (10230): Verilog HDL assignment warning at sine.hex(98): truncated value with size 12 to match size of target (10)
    2118. 

  2118. Warning (10230): Verilog HDL assignment warning at sine.hex(99): truncated value with size 12 to match size of target (10)
    2119. 

  2119. Warning (10230): Verilog HDL assignment warning at sine.hex(100): truncated value with size 12 to match size of target (10)
    2120. 

  2120. Warning (10230): Verilog HDL assignment warning at sine.hex(101): truncated value with size 12 to match size of target (10)
    2121. 

  2121. Warning (10230): Verilog HDL assignment warning at sine.hex(102): truncated value with size 12 to match size of target (10)
    2122. 

  2122. Warning (10230): Verilog HDL assignment warning at sine.hex(103): truncated value with size 12 to match size of target (10)
    2123. 

  2123. Warning (10230): Verilog HDL assignment warning at sine.hex(104): truncated value with size 12 to match size of target (10)
    2124. 

  2124. Warning (10230): Verilog HDL assignment warning at sine.hex(105): truncated value with size 12 to match size of target (10)
    2125. 

  2125. Warning (10230): Verilog HDL assignment warning at sine.hex(106): truncated value with size 12 to match size of target (10)
    2126. 

  2126. Warning (10230): Verilog HDL assignment warning at sine.hex(107): truncated value with size 12 to match size of target (10)
    2127. 

  2127. Warning (10230): Verilog HDL assignment warning at sine.hex(108): truncated value with size 12 to match size of target (10)
    2128. 

  2128. Warning (10230): Verilog HDL assignment warning at sine.hex(109): truncated value with size 12 to match size of target (10)
    2129. 

  2129. Warning (10230): Verilog HDL assignment warning at sine.hex(110): truncated value with size 12 to match size of target (10)
    2130. 

  2130. Warning (10230): Verilog HDL assignment warning at sine.hex(111): truncated value with size 12 to match size of target (10)
    2131. 

  2131. Warning (10230): Verilog HDL assignment warning at sine.hex(112): truncated value with size 12 to match size of target (10)
    2132. 

  2132. Warning (10230): Verilog HDL assignment warning at sine.hex(113): truncated value with size 12 to match size of target (10)
    2133. 

  2133. Warning (10230): Verilog HDL assignment warning at sine.hex(114): truncated value with size 12 to match size of target (10)
    2134. 

  2134. Warning (10230): Verilog HDL assignment warning at sine.hex(115): truncated value with size 12 to match size of target (10)
    2135. 

  2135. Warning (10230): Verilog HDL assignment warning at sine.hex(116): truncated value with size 12 to match size of target (10)
    2136. 

  2136. Warning (10230): Verilog HDL assignment warning at sine.hex(117): truncated value with size 12 to match size of target (10)
    2137. 

  2137. Warning (10230): Verilog HDL assignment warning at sine.hex(118): truncated value with size 12 to match size of target (10)
    2138. 

  2138. Warning (10230): Verilog HDL assignment warning at sine.hex(119): truncated value with size 12 to match size of target (10)
    2139. 

  2139. Warning (10230): Verilog HDL assignment warning at sine.hex(120): truncated value with size 12 to match size of target (10)
    2140. 

  2140. Warning (10230): Verilog HDL assignment warning at sine.hex(121): truncated value with size 12 to match size of target (10)
    2141. 

  2141. Warning (10230): Verilog HDL assignment warning at sine.hex(122): truncated value with size 12 to match size of target (10)
    2142. 

  2142. Warning (10230): Verilog HDL assignment warning at sine.hex(123): truncated value with size 12 to match size of target (10)
    2143. 

  2143. Warning (10230): Verilog HDL assignment warning at sine.hex(124): truncated value with size 12 to match size of target (10)
    2144. 

  2144. Warning (10230): Verilog HDL assignment warning at sine.hex(125): truncated value with size 12 to match size of target (10)
    2145. 

  2145. Warning (10230): Verilog HDL assignment warning at sine.hex(126): truncated value with size 12 to match size of target (10)
    2146. 

  2146. Warning (10230): Verilog HDL assignment warning at sine.hex(127): truncated value with size 12 to match size of target (10)
    2147. 

  2147. Warning (10230): Verilog HDL assignment warning at sine.hex(128): truncated value with size 12 to match size of target (10)
    2148. 

  2148. Warning (10230): Verilog HDL assignment warning at sine.hex(129): truncated value with size 12 to match size of target (10)
    2149. 

  2149. Warning (10230): Verilog HDL assignment warning at sine.hex(130): truncated value with size 12 to match size of target (10)
    2150. 

  2150. Warning (10230): Verilog HDL assignment warning at sine.hex(131): truncated value with size 12 to match size of target (10)
    2151. 

  2151. Warning (10230): Verilog HDL assignment warning at sine.hex(132): truncated value with size 12 to match size of target (10)
    2152. 

  2152. Warning (10230): Verilog HDL assignment warning at sine.hex(133): truncated value with size 12 to match size of target (10)
    2153. 

  2153. Warning (10230): Verilog HDL assignment warning at sine.hex(134): truncated value with size 12 to match size of target (10)
    2154. 

  2154. Warning (10230): Verilog HDL assignment warning at sine.hex(135): truncated value with size 12 to match size of target (10)
    2155. 

  2155. Warning (10230): Verilog HDL assignment warning at sine.hex(136): truncated value with size 12 to match size of target (10)
    2156. 

  2156. Warning (10230): Verilog HDL assignment warning at sine.hex(137): truncated value with size 12 to match size of target (10)
    2157. 

  2157. Warning (10230): Verilog HDL assignment warning at sine.hex(138): truncated value with size 12 to match size of target (10)
    2158. 

  2158. Warning (10230): Verilog HDL assignment warning at sine.hex(139): truncated value with size 12 to match size of target (10)
    2159. 

  2159. Warning (10230): Verilog HDL assignment warning at sine.hex(140): truncated value with size 12 to match size of target (10)
    2160. 

  2160. Warning (10230): Verilog HDL assignment warning at sine.hex(141): truncated value with size 12 to match size of target (10)
    2161. 

  2161. Warning (10230): Verilog HDL assignment warning at sine.hex(142): truncated value with size 12 to match size of target (10)
    2162. 

  2162. Warning (10230): Verilog HDL assignment warning at sine.hex(143): truncated value with size 12 to match size of target (10)
    2163. 

  2163. Warning (10230): Verilog HDL assignment warning at sine.hex(144): truncated value with size 12 to match size of target (10)
    2164. 

  2164. Warning (10230): Verilog HDL assignment warning at sine.hex(145): truncated value with size 12 to match size of target (10)
    2165. 

  2165. Warning (10230): Verilog HDL assignment warning at sine.hex(146): truncated value with size 12 to match size of target (10)
    2166. 

  2166. Warning (10230): Verilog HDL assignment warning at sine.hex(147): truncated value with size 12 to match size of target (10)
    2167. 

  2167. Warning (10230): Verilog HDL assignment warning at sine.hex(148): truncated value with size 12 to match size of target (10)
    2168. 

  2168. Warning (10230): Verilog HDL assignment warning at sine.hex(149): truncated value with size 12 to match size of target (10)
    2169. 

  2169. Warning (10230): Verilog HDL assignment warning at sine.hex(150): truncated value with size 12 to match size of target (10)
    2170. 

  2170. Warning (10230): Verilog HDL assignment warning at sine.hex(151): truncated value with size 12 to match size of target (10)
    2171. 

  2171. Warning (10230): Verilog HDL assignment warning at sine.hex(152): truncated value with size 12 to match size of target (10)
    2172. 

  2172. Warning (10230): Verilog HDL assignment warning at sine.hex(153): truncated value with size 12 to match size of target (10)
    2173. 

  2173. Warning (10230): Verilog HDL assignment warning at sine.hex(154): truncated value with size 12 to match size of target (10)
    2174. 

  2174. Warning (10230): Verilog HDL assignment warning at sine.hex(155): truncated value with size 12 to match size of target (10)
    2175. 

  2175. Warning (10230): Verilog HDL assignment warning at sine.hex(156): truncated value with size 12 to match size of target (10)
    2176. 

  2176. Warning (10230): Verilog HDL assignment warning at sine.hex(157): truncated value with size 12 to match size of target (10)
    2177. 

  2177. Warning (10230): Verilog HDL assignment warning at sine.hex(158): truncated value with size 12 to match size of target (10)
    2178. 

  2178. Warning (10230): Verilog HDL assignment warning at sine.hex(159): truncated value with size 12 to match size of target (10)
    2179. 

  2179. Warning (10230): Verilog HDL assignment warning at sine.hex(160): truncated value with size 12 to match size of target (10)
    2180. 

  2180. Warning (10230): Verilog HDL assignment warning at sine.hex(161): truncated value with size 12 to match size of target (10)
    2181. 

  2181. Warning (10230): Verilog HDL assignment warning at sine.hex(162): truncated value with size 12 to match size of target (10)
    2182. 

  2182. Warning (10230): Verilog HDL assignment warning at sine.hex(163): truncated value with size 12 to match size of target (10)
    2183. 

  2183. Warning (10230): Verilog HDL assignment warning at sine.hex(164): truncated value with size 12 to match size of target (10)
    2184. 

  2184. Warning (10230): Verilog HDL assignment warning at sine.hex(165): truncated value with size 12 to match size of target (10)
    2185. 

  2185. Warning (10230): Verilog HDL assignment warning at sine.hex(166): truncated value with size 12 to match size of target (10)
    2186. 

  2186. Warning (10230): Verilog HDL assignment warning at sine.hex(167): truncated value with size 12 to match size of target (10)
    2187. 

  2187. Warning (10230): Verilog HDL assignment warning at sine.hex(168): truncated value with size 12 to match size of target (10)
    2188. 

  2188. Warning (10230): Verilog HDL assignment warning at sine.hex(169): truncated value with size 12 to match size of target (10)
    2189. 

  2189. Warning (10230): Verilog HDL assignment warning at sine.hex(170): truncated value with size 12 to match size of target (10)
    2190. 

  2190. Warning (10230): Verilog HDL assignment warning at sine.hex(171): truncated value with size 12 to match size of target (10)
    2191. 

  2191. Warning (10230): Verilog HDL assignment warning at sine.hex(172): truncated value with size 12 to match size of target (10)
    2192. 

  2192. Warning (10230): Verilog HDL assignment warning at sine.hex(173): truncated value with size 12 to match size of target (10)
    2193. 

  2193. Warning (10230): Verilog HDL assignment warning at sine.hex(174): truncated value with size 12 to match size of target (10)
    2194. 

  2194. Warning (10230): Verilog HDL assignment warning at sine.hex(175): truncated value with size 12 to match size of target (10)
    2195. 

  2195. Warning (10230): Verilog HDL assignment warning at sine.hex(176): truncated value with size 12 to match size of target (10)
    2196. 

  2196. Warning (10230): Verilog HDL assignment warning at sine.hex(177): truncated value with size 12 to match size of target (10)
    2197. 

  2197. Warning (10230): Verilog HDL assignment warning at sine.hex(178): truncated value with size 12 to match size of target (10)
    2198. 

  2198. Warning (10230): Verilog HDL assignment warning at sine.hex(179): truncated value with size 12 to match size of target (10)
    2199. 

  2199. Warning (10230): Verilog HDL assignment warning at sine.hex(180): truncated value with size 12 to match size of target (10)
    2200. 

  2200. Warning (10230): Verilog HDL assignment warning at sine.hex(181): truncated value with size 12 to match size of target (10)
    2201. 

  2201. Warning (10230): Verilog HDL assignment warning at sine.hex(182): truncated value with size 12 to match size of target (10)
    2202. 

  2202. Warning (10230): Verilog HDL assignment warning at sine.hex(183): truncated value with size 12 to match size of target (10)
    2203. 

  2203. Warning (10230): Verilog HDL assignment warning at sine.hex(184): truncated value with size 12 to match size of target (10)
    2204. 

  2204. Warning (10230): Verilog HDL assignment warning at sine.hex(185): truncated value with size 12 to match size of target (10)
    2205. 

  2205. Warning (10230): Verilog HDL assignment warning at sine.hex(186): truncated value with size 12 to match size of target (10)
    2206. 

  2206. Warning (10230): Verilog HDL assignment warning at sine.hex(187): truncated value with size 12 to match size of target (10)
    2207. 

  2207. Warning (10230): Verilog HDL assignment warning at sine.hex(188): truncated value with size 12 to match size of target (10)
    2208. 

  2208. Warning (10230): Verilog HDL assignment warning at sine.hex(189): truncated value with size 12 to match size of target (10)
    2209. 

  2209. Warning (10230): Verilog HDL assignment warning at sine.hex(190): truncated value with size 12 to match size of target (10)
    2210. 

  2210. Warning (10230): Verilog HDL assignment warning at sine.hex(191): truncated value with size 12 to match size of target (10)
    2211. 

  2211. Warning (10230): Verilog HDL assignment warning at sine.hex(192): truncated value with size 12 to match size of target (10)
    2212. 

  2212. Warning (10230): Verilog HDL assignment warning at sine.hex(193): truncated value with size 12 to match size of target (10)
    2213. 

  2213. Warning (10230): Verilog HDL assignment warning at sine.hex(194): truncated value with size 12 to match size of target (10)
    2214. 

  2214. Warning (10230): Verilog HDL assignment warning at sine.hex(195): truncated value with size 12 to match size of target (10)
    2215. 

  2215. Warning (10230): Verilog HDL assignment warning at sine.hex(196): truncated value with size 12 to match size of target (10)
    2216. 

  2216. Warning (10230): Verilog HDL assignment warning at sine.hex(197): truncated value with size 12 to match size of target (10)
    2217. 

  2217. Warning (10230): Verilog HDL assignment warning at sine.hex(198): truncated value with size 12 to match size of target (10)
    2218. 

  2218. Warning (10230): Verilog HDL assignment warning at sine.hex(199): truncated value with size 12 to match size of target (10)
    2219. 

  2219. Warning (10230): Verilog HDL assignment warning at sine.hex(200): truncated value with size 12 to match size of target (10)
    2220. 

  2220. Warning (10230): Verilog HDL assignment warning at sine.hex(201): truncated value with size 12 to match size of target (10)
    2221. 

  2221. Warning (10230): Verilog HDL assignment warning at sine.hex(202): truncated value with size 12 to match size of target (10)
    2222. 

  2222. Warning (10230): Verilog HDL assignment warning at sine.hex(203): truncated value with size 12 to match size of target (10)
    2223. 

  2223. Warning (10230): Verilog HDL assignment warning at sine.hex(204): truncated value with size 12 to match size of target (10)
    2224. 

  2224. Warning (10230): Verilog HDL assignment warning at sine.hex(205): truncated value with size 12 to match size of target (10)
    2225. 

  2225. Warning (10230): Verilog HDL assignment warning at sine.hex(206): truncated value with size 12 to match size of target (10)
    2226. 

  2226. Warning (10230): Verilog HDL assignment warning at sine.hex(207): truncated value with size 12 to match size of target (10)
    2227. 

  2227. Warning (10230): Verilog HDL assignment warning at sine.hex(208): truncated value with size 12 to match size of target (10)
    2228. 

  2228. Warning (10230): Verilog HDL assignment warning at sine.hex(209): truncated value with size 12 to match size of target (10)
    2229. 

  2229. Warning (10230): Verilog HDL assignment warning at sine.hex(210): truncated value with size 12 to match size of target (10)
    2230. 

  2230. Warning (10230): Verilog HDL assignment warning at sine.hex(211): truncated value with size 12 to match size of target (10)
    2231. 

  2231. Warning (10230): Verilog HDL assignment warning at sine.hex(212): truncated value with size 12 to match size of target (10)
    2232. 

  2232. Warning (10230): Verilog HDL assignment warning at sine.hex(213): truncated value with size 12 to match size of target (10)
    2233. 

  2233. Warning (10230): Verilog HDL assignment warning at sine.hex(214): truncated value with size 12 to match size of target (10)
    2234. 

  2234. Warning (10230): Verilog HDL assignment warning at sine.hex(215): truncated value with size 12 to match size of target (10)
    2235. 

  2235. Warning (10230): Verilog HDL assignment warning at sine.hex(216): truncated value with size 12 to match size of target (10)
    2236. 

  2236. Warning (10230): Verilog HDL assignment warning at sine.hex(217): truncated value with size 12 to match size of target (10)
    2237. 

  2237. Warning (10230): Verilog HDL assignment warning at sine.hex(218): truncated value with size 12 to match size of target (10)
    2238. 

  2238. Warning (10230): Verilog HDL assignment warning at sine.hex(219): truncated value with size 12 to match size of target (10)
    2239. 

  2239. Warning (10230): Verilog HDL assignment warning at sine.hex(220): truncated value with size 12 to match size of target (10)
    2240. 

  2240. Warning (10230): Verilog HDL assignment warning at sine.hex(221): truncated value with size 12 to match size of target (10)
    2241. 

  2241. Warning (10230): Verilog HDL assignment warning at sine.hex(222): truncated value with size 12 to match size of target (10)
    2242. 

  2242. Warning (10230): Verilog HDL assignment warning at sine.hex(223): truncated value with size 12 to match size of target (10)
    2243. 

  2243. Warning (10230): Verilog HDL assignment warning at sine.hex(224): truncated value with size 12 to match size of target (10)
    2244. 

  2244. Warning (10230): Verilog HDL assignment warning at sine.hex(225): truncated value with size 12 to match size of target (10)
    2245. 

  2245. Warning (10230): Verilog HDL assignment warning at sine.hex(226): truncated value with size 12 to match size of target (10)
    2246. 

  2246. Warning (10230): Verilog HDL assignment warning at sine.hex(227): truncated value with size 12 to match size of target (10)
    2247. 

  2247. Warning (10230): Verilog HDL assignment warning at sine.hex(228): truncated value with size 12 to match size of target (10)
    2248. 

  2248. Warning (10230): Verilog HDL assignment warning at sine.hex(229): truncated value with size 12 to match size of target (10)
    2249. 

  2249. Warning (10230): Verilog HDL assignment warning at sine.hex(230): truncated value with size 12 to match size of target (10)
    2250. 

  2250. Warning (10230): Verilog HDL assignment warning at sine.hex(231): truncated value with size 12 to match size of target (10)
    2251. 

  2251. Warning (10230): Verilog HDL assignment warning at sine.hex(232): truncated value with size 12 to match size of target (10)
    2252. 

  2252. Warning (10230): Verilog HDL assignment warning at sine.hex(233): truncated value with size 12 to match size of target (10)
    2253. 

  2253. Warning (10230): Verilog HDL assignment warning at sine.hex(234): truncated value with size 12 to match size of target (10)
    2254. 

  2254. Warning (10230): Verilog HDL assignment warning at sine.hex(235): truncated value with size 12 to match size of target (10)
    2255. 

  2255. Warning (10230): Verilog HDL assignment warning at sine.hex(236): truncated value with size 12 to match size of target (10)
    2256. 

  2256. Warning (10230): Verilog HDL assignment warning at sine.hex(237): truncated value with size 12 to match size of target (10)
    2257. 

  2257. Warning (10230): Verilog HDL assignment warning at sine.hex(238): truncated value with size 12 to match size of target (10)
    2258. 

  2258. Warning (10230): Verilog HDL assignment warning at sine.hex(239): truncated value with size 12 to match size of target (10)
    2259. 

  2259. Warning (10230): Verilog HDL assignment warning at sine.hex(240): truncated value with size 12 to match size of target (10)
    2260. 

  2260. Warning (10230): Verilog HDL assignment warning at sine.hex(241): truncated value with size 12 to match size of target (10)
    2261. 

  2261. Warning (10230): Verilog HDL assignment warning at sine.hex(242): truncated value with size 12 to match size of target (10)
    2262. 

  2262. Warning (10230): Verilog HDL assignment warning at sine.hex(243): truncated value with size 12 to match size of target (10)
    2263. 

  2263. Warning (10230): Verilog HDL assignment warning at sine.hex(244): truncated value with size 12 to match size of target (10)
    2264. 

  2264. Warning (10230): Verilog HDL assignment warning at sine.hex(245): truncated value with size 12 to match size of target (10)
    2265. 

  2265. Warning (10230): Verilog HDL assignment warning at sine.hex(246): truncated value with size 12 to match size of target (10)
    2266. 

  2266. Warning (10230): Verilog HDL assignment warning at sine.hex(247): truncated value with size 12 to match size of target (10)
    2267. 

  2267. Warning (10230): Verilog HDL assignment warning at sine.hex(248): truncated value with size 12 to match size of target (10)
    2268. 

  2268. Warning (10230): Verilog HDL assignment warning at sine.hex(249): truncated value with size 12 to match size of target (10)
    2269. 

  2269. Warning (10230): Verilog HDL assignment warning at sine.hex(250): truncated value with size 12 to match size of target (10)
    2270. 

  2270. Warning (10230): Verilog HDL assignment warning at sine.hex(251): truncated value with size 12 to match size of target (10)
    2271. 

  2271. Warning (10230): Verilog HDL assignment warning at sine.hex(252): truncated value with size 12 to match size of target (10)
    2272. 

  2272. Warning (10230): Verilog HDL assignment warning at sine.hex(253): truncated value with size 12 to match size of target (10)
    2273. 

  2273. Warning (10230): Verilog HDL assignment warning at sine.hex(254): truncated value with size 12 to match size of target (10)
    2274. 

  2274. Warning (10230): Verilog HDL assignment warning at sine.hex(255): truncated value with size 12 to match size of target (10)
    2275. 

  2275. Warning (10230): Verilog HDL assignment warning at sine.hex(256): truncated value with size 12 to match size of target (10)
    2276. 

  2276. Warning (10230): Verilog HDL assignment warning at sine.hex(257): truncated value with size 12 to match size of target (10)
    2277. 

  2277. Warning (10230): Verilog HDL assignment warning at sine.hex(258): truncated value with size 12 to match size of target (10)
    2278. 

  2278. Warning (10230): Verilog HDL assignment warning at sine.hex(259): truncated value with size 12 to match size of target (10)
    2279. 

  2279. Warning (10230): Verilog HDL assignment warning at sine.hex(260): truncated value with size 12 to match size of target (10)
    2280. 

  2280. Warning (10230): Verilog HDL assignment warning at sine.hex(261): truncated value with size 12 to match size of target (10)
    2281. 

  2281. Warning (10230): Verilog HDL assignment warning at sine.hex(262): truncated value with size 12 to match size of target (10)
    2282. 

  2282. Warning (10230): Verilog HDL assignment warning at sine.hex(263): truncated value with size 12 to match size of target (10)
    2283. 

  2283. Warning (10230): Verilog HDL assignment warning at sine.hex(264): truncated value with size 12 to match size of target (10)
    2284. 

  2284. Warning (10230): Verilog HDL assignment warning at sine.hex(265): truncated value with size 12 to match size of target (10)
    2285. 

  2285. Warning (10230): Verilog HDL assignment warning at sine.hex(266): truncated value with size 12 to match size of target (10)
    2286. 

  2286. Warning (10230): Verilog HDL assignment warning at sine.hex(267): truncated value with size 12 to match size of target (10)
    2287. 

  2287. Warning (10230): Verilog HDL assignment warning at sine.hex(268): truncated value with size 12 to match size of target (10)
    2288. 

  2288. Warning (10230): Verilog HDL assignment warning at sine.hex(269): truncated value with size 12 to match size of target (10)
    2289. 

  2289. Warning (10230): Verilog HDL assignment warning at sine.hex(270): truncated value with size 12 to match size of target (10)
    2290. 

  2290. Warning (10230): Verilog HDL assignment warning at sine.hex(271): truncated value with size 12 to match size of target (10)
    2291. 

  2291. Warning (10230): Verilog HDL assignment warning at sine.hex(272): truncated value with size 12 to match size of target (10)
    2292. 

  2292. Warning (10230): Verilog HDL assignment warning at sine.hex(273): truncated value with size 12 to match size of target (10)
    2293. 

  2293. Warning (10230): Verilog HDL assignment warning at sine.hex(274): truncated value with size 12 to match size of target (10)
    2294. 

  2294. Warning (10230): Verilog HDL assignment warning at sine.hex(275): truncated value with size 12 to match size of target (10)
    2295. 

  2295. Warning (10230): Verilog HDL assignment warning at sine.hex(276): truncated value with size 12 to match size of target (10)
    2296. 

  2296. Warning (10230): Verilog HDL assignment warning at sine.hex(277): truncated value with size 12 to match size of target (10)
    2297. 

  2297. Warning (10230): Verilog HDL assignment warning at sine.hex(278): truncated value with size 12 to match size of target (10)
    2298. 

  2298. Warning (10230): Verilog HDL assignment warning at sine.hex(279): truncated value with size 12 to match size of target (10)
    2299. 

  2299. Warning (10230): Verilog HDL assignment warning at sine.hex(280): truncated value with size 12 to match size of target (10)
    2300. 

  2300. Warning (10230): Verilog HDL assignment warning at sine.hex(281): truncated value with size 12 to match size of target (10)
    2301. 

  2301. Warning (10230): Verilog HDL assignment warning at sine.hex(282): truncated value with size 12 to match size of target (10)
    2302. 

  2302. Warning (10230): Verilog HDL assignment warning at sine.hex(283): truncated value with size 12 to match size of target (10)
    2303. 

  2303. Warning (10230): Verilog HDL assignment warning at sine.hex(284): truncated value with size 12 to match size of target (10)
    2304. 

  2304. Warning (10230): Verilog HDL assignment warning at sine.hex(285): truncated value with size 12 to match size of target (10)
    2305. 

  2305. Warning (10230): Verilog HDL assignment warning at sine.hex(286): truncated value with size 12 to match size of target (10)
    2306. 

  2306. Warning (10230): Verilog HDL assignment warning at sine.hex(287): truncated value with size 12 to match size of target (10)
    2307. 

  2307. Warning (10230): Verilog HDL assignment warning at sine.hex(288): truncated value with size 12 to match size of target (10)
    2308. 

  2308. Warning (10230): Verilog HDL assignment warning at sine.hex(289): truncated value with size 12 to match size of target (10)
    2309. 

  2309. Warning (10230): Verilog HDL assignment warning at sine.hex(290): truncated value with size 12 to match size of target (10)
    2310. 

  2310. Warning (10230): Verilog HDL assignment warning at sine.hex(291): truncated value with size 12 to match size of target (10)
    2311. 

  2311. Warning (10230): Verilog HDL assignment warning at sine.hex(292): truncated value with size 12 to match size of target (10)
    2312. 

  2312. Warning (10230): Verilog HDL assignment warning at sine.hex(293): truncated value with size 12 to match size of target (10)
    2313. 

  2313. Warning (10230): Verilog HDL assignment warning at sine.hex(294): truncated value with size 12 to match size of target (10)
    2314. 

  2314. Warning (10230): Verilog HDL assignment warning at sine.hex(295): truncated value with size 12 to match size of target (10)
    2315. 

  2315. Warning (10230): Verilog HDL assignment warning at sine.hex(296): truncated value with size 12 to match size of target (10)
    2316. 

  2316. Warning (10230): Verilog HDL assignment warning at sine.hex(297): truncated value with size 12 to match size of target (10)
    2317. 

  2317. Warning (10230): Verilog HDL assignment warning at sine.hex(298): truncated value with size 12 to match size of target (10)
    2318. 

  2318. Warning (10230): Verilog HDL assignment warning at sine.hex(299): truncated value with size 12 to match size of target (10)
    2319. 

  2319. Warning (10230): Verilog HDL assignment warning at sine.hex(300): truncated value with size 12 to match size of target (10)
    2320. 

  2320. Warning (10230): Verilog HDL assignment warning at sine.hex(301): truncated value with size 12 to match size of target (10)
    2321. 

  2321. Warning (10230): Verilog HDL assignment warning at sine.hex(302): truncated value with size 12 to match size of target (10)
    2322. 

  2322. Warning (10230): Verilog HDL assignment warning at sine.hex(303): truncated value with size 12 to match size of target (10)
    2323. 

  2323. Warning (10230): Verilog HDL assignment warning at sine.hex(304): truncated value with size 12 to match size of target (10)
    2324. 

  2324. Warning (10230): Verilog HDL assignment warning at sine.hex(305): truncated value with size 12 to match size of target (10)
    2325. 

  2325. Warning (10230): Verilog HDL assignment warning at sine.hex(306): truncated value with size 12 to match size of target (10)
    2326. 

  2326. Warning (10230): Verilog HDL assignment warning at sine.hex(307): truncated value with size 12 to match size of target (10)
    2327. 

  2327. Warning (10230): Verilog HDL assignment warning at sine.hex(308): truncated value with size 12 to match size of target (10)
    2328. 

  2328. Warning (10230): Verilog HDL assignment warning at sine.hex(309): truncated value with size 12 to match size of target (10)
    2329. 

  2329. Warning (10230): Verilog HDL assignment warning at sine.hex(310): truncated value with size 12 to match size of target (10)
    2330. 

  2330. Warning (10230): Verilog HDL assignment warning at sine.hex(311): truncated value with size 12 to match size of target (10)
    2331. 

  2331. Warning (10230): Verilog HDL assignment warning at sine.hex(312): truncated value with size 12 to match size of target (10)
    2332. 

  2332. Warning (10230): Verilog HDL assignment warning at sine.hex(313): truncated value with size 12 to match size of target (10)
    2333. 

  2333. Warning (10230): Verilog HDL assignment warning at sine.hex(314): truncated value with size 12 to match size of target (10)
    2334. 

  2334. Warning (10230): Verilog HDL assignment warning at sine.hex(315): truncated value with size 12 to match size of target (10)
    2335. 

  2335. Warning (10230): Verilog HDL assignment warning at sine.hex(316): truncated value with size 12 to match size of target (10)
    2336. 

  2336. Warning (10230): Verilog HDL assignment warning at sine.hex(317): truncated value with size 12 to match size of target (10)
    2337. 

  2337. Warning (10230): Verilog HDL assignment warning at sine.hex(318): truncated value with size 12 to match size of target (10)
    2338. 

  2338. Warning (10230): Verilog HDL assignment warning at sine.hex(319): truncated value with size 12 to match size of target (10)
    2339. 

  2339. Warning (10230): Verilog HDL assignment warning at sine.hex(320): truncated value with size 12 to match size of target (10)
    2340. 

  2340. Warning (10230): Verilog HDL assignment warning at sine.hex(321): truncated value with size 12 to match size of target (10)
    2341. 

  2341. Warning (10230): Verilog HDL assignment warning at sine.hex(322): truncated value with size 12 to match size of target (10)
    2342. 

  2342. Warning (10230): Verilog HDL assignment warning at sine.hex(323): truncated value with size 12 to match size of target (10)
    2343. 

  2343. Warning (10230): Verilog HDL assignment warning at sine.hex(324): truncated value with size 12 to match size of target (10)
    2344. 

  2344. Warning (10230): Verilog HDL assignment warning at sine.hex(325): truncated value with size 12 to match size of target (10)
    2345. 

  2345. Warning (10230): Verilog HDL assignment warning at sine.hex(326): truncated value with size 12 to match size of target (10)
    2346. 

  2346. Warning (10230): Verilog HDL assignment warning at sine.hex(327): truncated value with size 12 to match size of target (10)
    2347. 

  2347. Warning (10230): Verilog HDL assignment warning at sine.hex(328): truncated value with size 12 to match size of target (10)
    2348. 

  2348. Warning (10230): Verilog HDL assignment warning at sine.hex(329): truncated value with size 12 to match size of target (10)
    2349. 

  2349. Warning (10230): Verilog HDL assignment warning at sine.hex(330): truncated value with size 12 to match size of target (10)
    2350. 

  2350. Warning (10230): Verilog HDL assignment warning at sine.hex(331): truncated value with size 12 to match size of target (10)
    2351. 

  2351. Warning (10230): Verilog HDL assignment warning at sine.hex(332): truncated value with size 12 to match size of target (10)
    2352. 

  2352. Warning (10230): Verilog HDL assignment warning at sine.hex(333): truncated value with size 12 to match size of target (10)
    2353. 

  2353. Warning (10230): Verilog HDL assignment warning at sine.hex(334): truncated value with size 12 to match size of target (10)
    2354. 

  2354. Warning (10230): Verilog HDL assignment warning at sine.hex(335): truncated value with size 12 to match size of target (10)
    2355. 

  2355. Warning (10230): Verilog HDL assignment warning at sine.hex(336): truncated value with size 12 to match size of target (10)
    2356. 

  2356. Warning (10230): Verilog HDL assignment warning at sine.hex(337): truncated value with size 12 to match size of target (10)
    2357. 

  2357. Warning (10230): Verilog HDL assignment warning at sine.hex(338): truncated value with size 12 to match size of target (10)
    2358. 

  2358. Warning (10230): Verilog HDL assignment warning at sine.hex(339): truncated value with size 12 to match size of target (10)
    2359. 

  2359. Warning (10230): Verilog HDL assignment warning at sine.hex(340): truncated value with size 12 to match size of target (10)
    2360. 

  2360. Warning (10230): Verilog HDL assignment warning at sine.hex(341): truncated value with size 12 to match size of target (10)
    2361. 

  2361. Warning (10230): Verilog HDL assignment warning at sine.hex(342): truncated value with size 12 to match size of target (10)
    2362. 

  2362. Warning (10230): Verilog HDL assignment warning at sine.hex(343): truncated value with size 12 to match size of target (10)
    2363. 

  2363. Warning (10230): Verilog HDL assignment warning at sine.hex(344): truncated value with size 12 to match size of target (10)
    2364. 

  2364. Warning (10230): Verilog HDL assignment warning at sine.hex(345): truncated value with size 12 to match size of target (10)
    2365. 

  2365. Warning (10230): Verilog HDL assignment warning at sine.hex(346): truncated value with size 12 to match size of target (10)
    2366. 

  2366. Warning (10230): Verilog HDL assignment warning at sine.hex(347): truncated value with size 12 to match size of target (10)
    2367. 

  2367. Warning (10230): Verilog HDL assignment warning at sine.hex(348): truncated value with size 12 to match size of target (10)
    2368. 

  2368. Warning (10230): Verilog HDL assignment warning at sine.hex(349): truncated value with size 12 to match size of target (10)
    2369. 

  2369. Warning (10230): Verilog HDL assignment warning at sine.hex(350): truncated value with size 12 to match size of target (10)
    2370. 

  2370. Warning (10230): Verilog HDL assignment warning at sine.hex(351): truncated value with size 12 to match size of target (10)
    2371. 

  2371. Warning (10230): Verilog HDL assignment warning at sine.hex(352): truncated value with size 12 to match size of target (10)
    2372. 

  2372. Warning (10230): Verilog HDL assignment warning at sine.hex(353): truncated value with size 12 to match size of target (10)
    2373. 

  2373. Warning (10230): Verilog HDL assignment warning at sine.hex(354): truncated value with size 12 to match size of target (10)
    2374. 

  2374. Warning (10230): Verilog HDL assignment warning at sine.hex(355): truncated value with size 12 to match size of target (10)
    2375. 

  2375. Warning (10230): Verilog HDL assignment warning at sine.hex(356): truncated value with size 12 to match size of target (10)
    2376. 

  2376. Warning (10230): Verilog HDL assignment warning at sine.hex(357): truncated value with size 12 to match size of target (10)
    2377. 

  2377. Warning (10230): Verilog HDL assignment warning at sine.hex(358): truncated value with size 12 to match size of target (10)
    2378. 

  2378. Warning (10230): Verilog HDL assignment warning at sine.hex(359): truncated value with size 12 to match size of target (10)
    2379. 

  2379. Warning (10230): Verilog HDL assignment warning at sine.hex(360): truncated value with size 12 to match size of target (10)
    2380. 

  2380. Warning (10230): Verilog HDL assignment warning at sine.hex(361): truncated value with size 12 to match size of target (10)
    2381. 

  2381. Warning (10230): Verilog HDL assignment warning at sine.hex(362): truncated value with size 12 to match size of target (10)
    2382. 

  2382. Warning (10230): Verilog HDL assignment warning at sine.hex(363): truncated value with size 12 to match size of target (10)
    2383. 

  2383. Warning (10230): Verilog HDL assignment warning at sine.hex(364): truncated value with size 12 to match size of target (10)
    2384. 

  2384. Warning (10230): Verilog HDL assignment warning at sine.hex(365): truncated value with size 12 to match size of target (10)
    2385. 

  2385. Warning (10230): Verilog HDL assignment warning at sine.hex(366): truncated value with size 12 to match size of target (10)
    2386. 

  2386. Warning (10230): Verilog HDL assignment warning at sine.hex(367): truncated value with size 12 to match size of target (10)
    2387. 

  2387. Warning (10230): Verilog HDL assignment warning at sine.hex(368): truncated value with size 12 to match size of target (10)
    2388. 

  2388. Warning (10230): Verilog HDL assignment warning at sine.hex(369): truncated value with size 12 to match size of target (10)
    2389. 

  2389. Warning (10230): Verilog HDL assignment warning at sine.hex(370): truncated value with size 12 to match size of target (10)
    2390. 

  2390. Warning (10230): Verilog HDL assignment warning at sine.hex(371): truncated value with size 12 to match size of target (10)
    2391. 

  2391. Warning (10230): Verilog HDL assignment warning at sine.hex(372): truncated value with size 12 to match size of target (10)
    2392. 

  2392. Warning (10230): Verilog HDL assignment warning at sine.hex(373): truncated value with size 12 to match size of target (10)
    2393. 

  2393. Warning (10230): Verilog HDL assignment warning at sine.hex(374): truncated value with size 12 to match size of target (10)
    2394. 

  2394. Warning (10230): Verilog HDL assignment warning at sine.hex(375): truncated value with size 12 to match size of target (10)
    2395. 

  2395. Warning (10230): Verilog HDL assignment warning at sine.hex(376): truncated value with size 12 to match size of target (10)
    2396. 

  2396. Warning (10230): Verilog HDL assignment warning at sine.hex(377): truncated value with size 12 to match size of target (10)
    2397. 

  2397. Warning (10230): Verilog HDL assignment warning at sine.hex(378): truncated value with size 12 to match size of target (10)
    2398. 

  2398. Warning (10230): Verilog HDL assignment warning at sine.hex(379): truncated value with size 12 to match size of target (10)
    2399. 

  2399. Warning (10230): Verilog HDL assignment warning at sine.hex(380): truncated value with size 12 to match size of target (10)
    2400. 

  2400. Warning (10230): Verilog HDL assignment warning at sine.hex(381): truncated value with size 12 to match size of target (10)
    2401. 

  2401. Warning (10230): Verilog HDL assignment warning at sine.hex(382): truncated value with size 12 to match size of target (10)
    2402. 

  2402. Warning (10230): Verilog HDL assignment warning at sine.hex(383): truncated value with size 12 to match size of target (10)
    2403. 

  2403. Warning (10230): Verilog HDL assignment warning at sine.hex(384): truncated value with size 12 to match size of target (10)
    2404. 

  2404. Warning (10230): Verilog HDL assignment warning at sine.hex(385): truncated value with size 12 to match size of target (10)
    2405. 

  2405. Warning (10230): Verilog HDL assignment warning at sine.hex(386): truncated value with size 12 to match size of target (10)
    2406. 

  2406. Warning (10230): Verilog HDL assignment warning at sine.hex(387): truncated value with size 12 to match size of target (10)
    2407. 

  2407. Warning (10230): Verilog HDL assignment warning at sine.hex(388): truncated value with size 12 to match size of target (10)
    2408. 

  2408. Warning (10230): Verilog HDL assignment warning at sine.hex(389): truncated value with size 12 to match size of target (10)
    2409. 

  2409. Warning (10230): Verilog HDL assignment warning at sine.hex(390): truncated value with size 12 to match size of target (10)
    2410. 

  2410. Warning (10230): Verilog HDL assignment warning at sine.hex(391): truncated value with size 12 to match size of target (10)
    2411. 

  2411. Warning (10230): Verilog HDL assignment warning at sine.hex(392): truncated value with size 12 to match size of target (10)
    2412. 

  2412. Warning (10230): Verilog HDL assignment warning at sine.hex(393): truncated value with size 12 to match size of target (10)
    2413. 

  2413. Warning (10230): Verilog HDL assignment warning at sine.hex(394): truncated value with size 12 to match size of target (10)
    2414. 

  2414. Warning (10230): Verilog HDL assignment warning at sine.hex(395): truncated value with size 12 to match size of target (10)
    2415. 

  2415. Warning (10230): Verilog HDL assignment warning at sine.hex(396): truncated value with size 12 to match size of target (10)
    2416. 

  2416. Warning (10230): Verilog HDL assignment warning at sine.hex(397): truncated value with size 12 to match size of target (10)
    2417. 

  2417. Warning (10230): Verilog HDL assignment warning at sine.hex(398): truncated value with size 12 to match size of target (10)
    2418. 

  2418. Warning (10230): Verilog HDL assignment warning at sine.hex(399): truncated value with size 12 to match size of target (10)
    2419. 

  2419. Warning (10230): Verilog HDL assignment warning at sine.hex(400): truncated value with size 12 to match size of target (10)
    2420. 

  2420. Warning (10230): Verilog HDL assignment warning at sine.hex(401): truncated value with size 12 to match size of target (10)
    2421. 

  2421. Warning (10230): Verilog HDL assignment warning at sine.hex(402): truncated value with size 12 to match size of target (10)
    2422. 

  2422. Warning (10230): Verilog HDL assignment warning at sine.hex(403): truncated value with size 12 to match size of target (10)
    2423. 

  2423. Warning (10230): Verilog HDL assignment warning at sine.hex(404): truncated value with size 12 to match size of target (10)
    2424. 

  2424. Warning (10230): Verilog HDL assignment warning at sine.hex(405): truncated value with size 12 to match size of target (10)
    2425. 

  2425. Warning (10230): Verilog HDL assignment warning at sine.hex(406): truncated value with size 12 to match size of target (10)
    2426. 

  2426. Warning (10230): Verilog HDL assignment warning at sine.hex(407): truncated value with size 12 to match size of target (10)
    2427. 

  2427. Warning (10230): Verilog HDL assignment warning at sine.hex(408): truncated value with size 12 to match size of target (10)
    2428. 

  2428. Warning (10230): Verilog HDL assignment warning at sine.hex(409): truncated value with size 12 to match size of target (10)
    2429. 

  2429. Warning (10230): Verilog HDL assignment warning at sine.hex(410): truncated value with size 12 to match size of target (10)
    2430. 

  2430. Warning (10230): Verilog HDL assignment warning at sine.hex(411): truncated value with size 12 to match size of target (10)
    2431. 

  2431. Warning (10230): Verilog HDL assignment warning at sine.hex(412): truncated value with size 12 to match size of target (10)
    2432. 

  2432. Warning (10230): Verilog HDL assignment warning at sine.hex(413): truncated value with size 12 to match size of target (10)
    2433. 

  2433. Warning (10230): Verilog HDL assignment warning at sine.hex(414): truncated value with size 12 to match size of target (10)
    2434. 

  2434. Warning (10230): Verilog HDL assignment warning at sine.hex(415): truncated value with size 12 to match size of target (10)
    2435. 

  2435. Warning (10230): Verilog HDL assignment warning at sine.hex(416): truncated value with size 12 to match size of target (10)
    2436. 

  2436. Warning (10230): Verilog HDL assignment warning at sine.hex(417): truncated value with size 12 to match size of target (10)
    2437. 

  2437. Warning (10230): Verilog HDL assignment warning at sine.hex(418): truncated value with size 12 to match size of target (10)
    2438. 

  2438. Warning (10230): Verilog HDL assignment warning at sine.hex(419): truncated value with size 12 to match size of target (10)
    2439. 

  2439. Warning (10230): Verilog HDL assignment warning at sine.hex(420): truncated value with size 12 to match size of target (10)
    2440. 

  2440. Warning (10230): Verilog HDL assignment warning at sine.hex(421): truncated value with size 12 to match size of target (10)
    2441. 

  2441. Warning (10230): Verilog HDL assignment warning at sine.hex(422): truncated value with size 12 to match size of target (10)
    2442. 

  2442. Warning (10230): Verilog HDL assignment warning at sine.hex(423): truncated value with size 12 to match size of target (10)
    2443. 

  2443. Warning (10230): Verilog HDL assignment warning at sine.hex(424): truncated value with size 12 to match size of target (10)
    2444. 

  2444. Warning (10230): Verilog HDL assignment warning at sine.hex(425): truncated value with size 12 to match size of target (10)
    2445. 

  2445. Warning (10230): Verilog HDL assignment warning at sine.hex(426): truncated value with size 12 to match size of target (10)
    2446. 

  2446. Warning (10230): Verilog HDL assignment warning at sine.hex(427): truncated value with size 12 to match size of target (10)
    2447. 

  2447. Warning (10230): Verilog HDL assignment warning at sine.hex(428): truncated value with size 12 to match size of target (10)
    2448. 

  2448. Warning (10230): Verilog HDL assignment warning at sine.hex(429): truncated value with size 12 to match size of target (10)
    2449. 

  2449. Warning (10230): Verilog HDL assignment warning at sine.hex(430): truncated value with size 12 to match size of target (10)
    2450. 

  2450. Warning (10230): Verilog HDL assignment warning at sine.hex(431): truncated value with size 12 to match size of target (10)
    2451. 

  2451. Warning (10230): Verilog HDL assignment warning at sine.hex(432): truncated value with size 12 to match size of target (10)
    2452. 

  2452. Warning (10230): Verilog HDL assignment warning at sine.hex(433): truncated value with size 12 to match size of target (10)
    2453. 

  2453. Warning (10230): Verilog HDL assignment warning at sine.hex(434): truncated value with size 12 to match size of target (10)
    2454. 

  2454. Warning (10230): Verilog HDL assignment warning at sine.hex(435): truncated value with size 12 to match size of target (10)
    2455. 

  2455. Warning (10230): Verilog HDL assignment warning at sine.hex(436): truncated value with size 12 to match size of target (10)
    2456. 

  2456. Warning (10230): Verilog HDL assignment warning at sine.hex(437): truncated value with size 12 to match size of target (10)
    2457. 

  2457. Warning (10230): Verilog HDL assignment warning at sine.hex(438): truncated value with size 12 to match size of target (10)
    2458. 

  2458. Warning (10230): Verilog HDL assignment warning at sine.hex(439): truncated value with size 12 to match size of target (10)
    2459. 

  2459. Warning (10230): Verilog HDL assignment warning at sine.hex(440): truncated value with size 12 to match size of target (10)
    2460. 

  2460. Warning (10230): Verilog HDL assignment warning at sine.hex(441): truncated value with size 12 to match size of target (10)
    2461. 

  2461. Warning (10230): Verilog HDL assignment warning at sine.hex(442): truncated value with size 12 to match size of target (10)
    2462. 

  2462. Warning (10230): Verilog HDL assignment warning at sine.hex(443): truncated value with size 12 to match size of target (10)
    2463. 

  2463. Warning (10230): Verilog HDL assignment warning at sine.hex(444): truncated value with size 12 to match size of target (10)
    2464. 

  2464. Warning (10230): Verilog HDL assignment warning at sine.hex(445): truncated value with size 12 to match size of target (10)
    2465. 

  2465. Warning (10230): Verilog HDL assignment warning at sine.hex(446): truncated value with size 12 to match size of target (10)
    2466. 

  2466. Warning (10230): Verilog HDL assignment warning at sine.hex(447): truncated value with size 12 to match size of target (10)
    2467. 

  2467. Warning (10230): Verilog HDL assignment warning at sine.hex(448): truncated value with size 12 to match size of target (10)
    2468. 

  2468. Warning (10230): Verilog HDL assignment warning at sine.hex(449): truncated value with size 12 to match size of target (10)
    2469. 

  2469. Warning (10230): Verilog HDL assignment warning at sine.hex(450): truncated value with size 12 to match size of target (10)
    2470. 

  2470. Warning (10230): Verilog HDL assignment warning at sine.hex(451): truncated value with size 12 to match size of target (10)
    2471. 

  2471. Warning (10230): Verilog HDL assignment warning at sine.hex(452): truncated value with size 12 to match size of target (10)
    2472. 

  2472. Warning (10230): Verilog HDL assignment warning at sine.hex(453): truncated value with size 12 to match size of target (10)
    2473. 

  2473. Warning (10230): Verilog HDL assignment warning at sine.hex(454): truncated value with size 12 to match size of target (10)
    2474. 

  2474. Warning (10230): Verilog HDL assignment warning at sine.hex(455): truncated value with size 12 to match size of target (10)
    2475. 

  2475. Warning (10230): Verilog HDL assignment warning at sine.hex(456): truncated value with size 12 to match size of target (10)
    2476. 

  2476. Warning (10230): Verilog HDL assignment warning at sine.hex(457): truncated value with size 12 to match size of target (10)
    2477. 

  2477. Warning (10230): Verilog HDL assignment warning at sine.hex(458): truncated value with size 12 to match size of target (10)
    2478. 

  2478. Warning (10230): Verilog HDL assignment warning at sine.hex(459): truncated value with size 12 to match size of target (10)
    2479. 

  2479. Warning (10230): Verilog HDL assignment warning at sine.hex(460): truncated value with size 12 to match size of target (10)
    2480. 

  2480. Warning (10230): Verilog HDL assignment warning at sine.hex(461): truncated value with size 12 to match size of target (10)
    2481. 

  2481. Warning (10230): Verilog HDL assignment warning at sine.hex(462): truncated value with size 12 to match size of target (10)
    2482. 

  2482. Warning (10230): Verilog HDL assignment warning at sine.hex(463): truncated value with size 12 to match size of target (10)
    2483. 

  2483. Warning (10230): Verilog HDL assignment warning at sine.hex(464): truncated value with size 12 to match size of target (10)
    2484. 

  2484. Warning (10230): Verilog HDL assignment warning at sine.hex(465): truncated value with size 12 to match size of target (10)
    2485. 

  2485. Warning (10230): Verilog HDL assignment warning at sine.hex(466): truncated value with size 12 to match size of target (10)
    2486. 

  2486. Warning (10230): Verilog HDL assignment warning at sine.hex(467): truncated value with size 12 to match size of target (10)
    2487. 

  2487. Warning (10230): Verilog HDL assignment warning at sine.hex(468): truncated value with size 12 to match size of target (10)
    2488. 

  2488. Warning (10230): Verilog HDL assignment warning at sine.hex(469): truncated value with size 12 to match size of target (10)
    2489. 

  2489. Warning (10230): Verilog HDL assignment warning at sine.hex(470): truncated value with size 12 to match size of target (10)
    2490. 

  2490. Warning (10230): Verilog HDL assignment warning at sine.hex(471): truncated value with size 12 to match size of target (10)
    2491. 

  2491. Warning (10230): Verilog HDL assignment warning at sine.hex(472): truncated value with size 12 to match size of target (10)
    2492. 

  2492. Warning (10230): Verilog HDL assignment warning at sine.hex(473): truncated value with size 12 to match size of target (10)
    2493. 

  2493. Warning (10230): Verilog HDL assignment warning at sine.hex(474): truncated value with size 12 to match size of target (10)
    2494. 

  2494. Warning (10230): Verilog HDL assignment warning at sine.hex(475): truncated value with size 12 to match size of target (10)
    2495. 

  2495. Warning (10230): Verilog HDL assignment warning at sine.hex(476): truncated value with size 12 to match size of target (10)
    2496. 

  2496. Warning (10230): Verilog HDL assignment warning at sine.hex(477): truncated value with size 12 to match size of target (10)
    2497. 

  2497. Warning (10230): Verilog HDL assignment warning at sine.hex(478): truncated value with size 12 to match size of target (10)
    2498. 

  2498. Warning (10230): Verilog HDL assignment warning at sine.hex(479): truncated value with size 12 to match size of target (10)
    2499. 

  2499. Warning (10230): Verilog HDL assignment warning at sine.hex(480): truncated value with size 12 to match size of target (10)
    2500. 

  2500. Warning (10230): Verilog HDL assignment warning at sine.hex(481): truncated value with size 12 to match size of target (10)
    2501. 

  2501. Warning (10230): Verilog HDL assignment warning at sine.hex(482): truncated value with size 12 to match size of target (10)
    2502. 

  2502. Warning (10230): Verilog HDL assignment warning at sine.hex(483): truncated value with size 12 to match size of target (10)
    2503. 

  2503. Warning (10230): Verilog HDL assignment warning at sine.hex(484): truncated value with size 12 to match size of target (10)
    2504. 

  2504. Warning (10230): Verilog HDL assignment warning at sine.hex(485): truncated value with size 12 to match size of target (10)
    2505. 

  2505. Warning (10230): Verilog HDL assignment warning at sine.hex(486): truncated value with size 12 to match size of target (10)
    2506. 

  2506. Warning (10230): Verilog HDL assignment warning at sine.hex(487): truncated value with size 12 to match size of target (10)
    2507. 

  2507. Warning (10230): Verilog HDL assignment warning at sine.hex(488): truncated value with size 12 to match size of target (10)
    2508. 

  2508. Warning (10230): Verilog HDL assignment warning at sine.hex(489): truncated value with size 12 to match size of target (10)
    2509. 

  2509. Warning (10230): Verilog HDL assignment warning at sine.hex(490): truncated value with size 12 to match size of target (10)
    2510. 

  2510. Warning (10230): Verilog HDL assignment warning at sine.hex(491): truncated value with size 12 to match size of target (10)
    2511. 

  2511. Warning (10230): Verilog HDL assignment warning at sine.hex(492): truncated value with size 12 to match size of target (10)
    2512. 

  2512. Warning (10230): Verilog HDL assignment warning at sine.hex(493): truncated value with size 12 to match size of target (10)
    2513. 

  2513. Warning (10230): Verilog HDL assignment warning at sine.hex(494): truncated value with size 12 to match size of target (10)
    2514. 

  2514. Warning (10230): Verilog HDL assignment warning at sine.hex(495): truncated value with size 12 to match size of target (10)
    2515. 

  2515. Warning (10230): Verilog HDL assignment warning at sine.hex(496): truncated value with size 12 to match size of target (10)
    2516. 

  2516. Warning (10230): Verilog HDL assignment warning at sine.hex(497): truncated value with size 12 to match size of target (10)
    2517. 

  2517. Warning (10230): Verilog HDL assignment warning at sine.hex(498): truncated value with size 12 to match size of target (10)
    2518. 

  2518. Warning (10230): Verilog HDL assignment warning at sine.hex(499): truncated value with size 12 to match size of target (10)
    2519. 

  2519. Warning (10230): Verilog HDL assignment warning at sine.hex(500): truncated value with size 12 to match size of target (10)
    2520. 

  2520. Warning (10230): Verilog HDL assignment warning at sine.hex(501): truncated value with size 12 to match size of target (10)
    2521. 

  2521. Warning (10230): Verilog HDL assignment warning at sine.hex(502): truncated value with size 12 to match size of target (10)
    2522. 

  2522. Warning (10230): Verilog HDL assignment warning at sine.hex(503): truncated value with size 12 to match size of target (10)
    2523. 

  2523. Warning (10230): Verilog HDL assignment warning at sine.hex(504): truncated value with size 12 to match size of target (10)
    2524. 

  2524. Warning (10230): Verilog HDL assignment warning at sine.hex(505): truncated value with size 12 to match size of target (10)
    2525. 

  2525. Warning (10230): Verilog HDL assignment warning at sine.hex(506): truncated value with size 12 to match size of target (10)
    2526. 

  2526. Warning (10230): Verilog HDL assignment warning at sine.hex(507): truncated value with size 12 to match size of target (10)
    2527. 

  2527. Warning (10230): Verilog HDL assignment warning at sine.hex(508): truncated value with size 12 to match size of target (10)
    2528. 

  2528. Warning (10230): Verilog HDL assignment warning at sine.hex(509): truncated value with size 12 to match size of target (10)
    2529. 

  2529. Warning (10230): Verilog HDL assignment warning at sine.hex(510): truncated value with size 12 to match size of target (10)
    2530. 

  2530. Warning (10230): Verilog HDL assignment warning at sine.hex(511): truncated value with size 12 to match size of target (10)
    2531. 

  2531. Warning (10230): Verilog HDL assignment warning at sine.hex(512): truncated value with size 12 to match size of target (10)
    2532. 

  2532. Warning (10230): Verilog HDL assignment warning at sine.hex(513): truncated value with size 12 to match size of target (10)
    2533. 

  2533. Warning (10230): Verilog HDL assignment warning at sine.hex(514): truncated value with size 12 to match size of target (10)
    2534. 

  2534. Warning (10230): Verilog HDL assignment warning at sine.hex(515): truncated value with size 12 to match size of target (10)
    2535. 

  2535. Warning (10230): Verilog HDL assignment warning at sine.hex(516): truncated value with size 12 to match size of target (10)
    2536. 

  2536. Warning (10230): Verilog HDL assignment warning at sine.hex(517): truncated value with size 12 to match size of target (10)
    2537. 

  2537. Warning (10230): Verilog HDL assignment warning at sine.hex(518): truncated value with size 12 to match size of target (10)
    2538. 

  2538. Warning (10230): Verilog HDL assignment warning at sine.hex(519): truncated value with size 12 to match size of target (10)
    2539. 

  2539. Warning (10230): Verilog HDL assignment warning at sine.hex(520): truncated value with size 12 to match size of target (10)
    2540. 

  2540. Warning (10230): Verilog HDL assignment warning at sine.hex(521): truncated value with size 12 to match size of target (10)
    2541. 

  2541. Warning (10230): Verilog HDL assignment warning at sine.hex(522): truncated value with size 12 to match size of target (10)
    2542. 

  2542. Warning (10230): Verilog HDL assignment warning at sine.hex(523): truncated value with size 12 to match size of target (10)
    2543. 

  2543. Warning (10230): Verilog HDL assignment warning at sine.hex(524): truncated value with size 12 to match size of target (10)
    2544. 

  2544. Warning (10230): Verilog HDL assignment warning at sine.hex(525): truncated value with size 12 to match size of target (10)
    2545. 

  2545. Warning (10230): Verilog HDL assignment warning at sine.hex(526): truncated value with size 12 to match size of target (10)
    2546. 

  2546. Warning (10230): Verilog HDL assignment warning at sine.hex(527): truncated value with size 12 to match size of target (10)
    2547. 

  2547. Warning (10230): Verilog HDL assignment warning at sine.hex(528): truncated value with size 12 to match size of target (10)
    2548. 

  2548. Warning (10230): Verilog HDL assignment warning at sine.hex(529): truncated value with size 12 to match size of target (10)
    2549. 

  2549. Warning (10230): Verilog HDL assignment warning at sine.hex(530): truncated value with size 12 to match size of target (10)
    2550. 

  2550. Warning (10230): Verilog HDL assignment warning at sine.hex(531): truncated value with size 12 to match size of target (10)
    2551. 

  2551. Warning (10230): Verilog HDL assignment warning at sine.hex(532): truncated value with size 12 to match size of target (10)
    2552. 

  2552. Warning (10230): Verilog HDL assignment warning at sine.hex(533): truncated value with size 12 to match size of target (10)
    2553. 

  2553. Warning (10230): Verilog HDL assignment warning at sine.hex(534): truncated value with size 12 to match size of target (10)
    2554. 

  2554. Warning (10230): Verilog HDL assignment warning at sine.hex(535): truncated value with size 12 to match size of target (10)
    2555. 

  2555. Warning (10230): Verilog HDL assignment warning at sine.hex(536): truncated value with size 12 to match size of target (10)
    2556. 

  2556. Warning (10230): Verilog HDL assignment warning at sine.hex(537): truncated value with size 12 to match size of target (10)
    2557. 

  2557. Warning (10230): Verilog HDL assignment warning at sine.hex(538): truncated value with size 12 to match size of target (10)
    2558. 

  2558. Warning (10230): Verilog HDL assignment warning at sine.hex(539): truncated value with size 12 to match size of target (10)
    2559. 

  2559. Warning (10230): Verilog HDL assignment warning at sine.hex(540): truncated value with size 12 to match size of target (10)
    2560. 

  2560. Warning (10230): Verilog HDL assignment warning at sine.hex(541): truncated value with size 12 to match size of target (10)
    2561. 

  2561. Warning (10230): Verilog HDL assignment warning at sine.hex(542): truncated value with size 12 to match size of target (10)
    2562. 

  2562. Warning (10230): Verilog HDL assignment warning at sine.hex(543): truncated value with size 12 to match size of target (10)
    2563. 

  2563. Warning (10230): Verilog HDL assignment warning at sine.hex(544): truncated value with size 12 to match size of target (10)
    2564. 

  2564. Warning (10230): Verilog HDL assignment warning at sine.hex(545): truncated value with size 12 to match size of target (10)
    2565. 

  2565. Warning (10230): Verilog HDL assignment warning at sine.hex(546): truncated value with size 12 to match size of target (10)
    2566. 

  2566. Warning (10230): Verilog HDL assignment warning at sine.hex(547): truncated value with size 12 to match size of target (10)
    2567. 

  2567. Warning (10230): Verilog HDL assignment warning at sine.hex(548): truncated value with size 12 to match size of target (10)
    2568. 

  2568. Warning (10230): Verilog HDL assignment warning at sine.hex(549): truncated value with size 12 to match size of target (10)
    2569. 

  2569. Warning (10230): Verilog HDL assignment warning at sine.hex(550): truncated value with size 12 to match size of target (10)
    2570. 

  2570. Warning (10230): Verilog HDL assignment warning at sine.hex(551): truncated value with size 12 to match size of target (10)
    2571. 

  2571. Warning (10230): Verilog HDL assignment warning at sine.hex(552): truncated value with size 12 to match size of target (10)
    2572. 

  2572. Warning (10230): Verilog HDL assignment warning at sine.hex(553): truncated value with size 12 to match size of target (10)
    2573. 

  2573. Warning (10230): Verilog HDL assignment warning at sine.hex(554): truncated value with size 12 to match size of target (10)
    2574. 

  2574. Warning (10230): Verilog HDL assignment warning at sine.hex(555): truncated value with size 12 to match size of target (10)
    2575. 

  2575. Warning (10230): Verilog HDL assignment warning at sine.hex(556): truncated value with size 12 to match size of target (10)
    2576. 

  2576. Warning (10230): Verilog HDL assignment warning at sine.hex(557): truncated value with size 12 to match size of target (10)
    2577. 

  2577. Warning (10230): Verilog HDL assignment warning at sine.hex(558): truncated value with size 12 to match size of target (10)
    2578. 

  2578. Warning (10230): Verilog HDL assignment warning at sine.hex(559): truncated value with size 12 to match size of target (10)
    2579. 

  2579. Warning (10230): Verilog HDL assignment warning at sine.hex(560): truncated value with size 12 to match size of target (10)
    2580. 

  2580. Warning (10230): Verilog HDL assignment warning at sine.hex(561): truncated value with size 12 to match size of target (10)
    2581. 

  2581. Warning (10230): Verilog HDL assignment warning at sine.hex(562): truncated value with size 12 to match size of target (10)
    2582. 

  2582. Warning (10230): Verilog HDL assignment warning at sine.hex(563): truncated value with size 12 to match size of target (10)
    2583. 

  2583. Warning (10230): Verilog HDL assignment warning at sine.hex(564): truncated value with size 12 to match size of target (10)
    2584. 

  2584. Warning (10230): Verilog HDL assignment warning at sine.hex(565): truncated value with size 12 to match size of target (10)
    2585. 

  2585. Warning (10230): Verilog HDL assignment warning at sine.hex(566): truncated value with size 12 to match size of target (10)
    2586. 

  2586. Warning (10230): Verilog HDL assignment warning at sine.hex(567): truncated value with size 12 to match size of target (10)
    2587. 

  2587. Warning (10230): Verilog HDL assignment warning at sine.hex(568): truncated value with size 12 to match size of target (10)
    2588. 

  2588. Warning (10230): Verilog HDL assignment warning at sine.hex(569): truncated value with size 12 to match size of target (10)
    2589. 

  2589. Warning (10230): Verilog HDL assignment warning at sine.hex(570): truncated value with size 12 to match size of target (10)
    2590. 

  2590. Warning (10230): Verilog HDL assignment warning at sine.hex(571): truncated value with size 12 to match size of target (10)
    2591. 

  2591. Warning (10230): Verilog HDL assignment warning at sine.hex(572): truncated value with size 12 to match size of target (10)
    2592. 

  2592. Warning (10230): Verilog HDL assignment warning at sine.hex(573): truncated value with size 12 to match size of target (10)
    2593. 

  2593. Warning (10230): Verilog HDL assignment warning at sine.hex(574): truncated value with size 12 to match size of target (10)
    2594. 

  2594. Warning (10230): Verilog HDL assignment warning at sine.hex(575): truncated value with size 12 to match size of target (10)
    2595. 

  2595. Warning (10230): Verilog HDL assignment warning at sine.hex(576): truncated value with size 12 to match size of target (10)
    2596. 

  2596. Warning (10230): Verilog HDL assignment warning at sine.hex(577): truncated value with size 12 to match size of target (10)
    2597. 

  2597. Warning (10230): Verilog HDL assignment warning at sine.hex(578): truncated value with size 12 to match size of target (10)
    2598. 

  2598. Warning (10230): Verilog HDL assignment warning at sine.hex(579): truncated value with size 12 to match size of target (10)
    2599. 

  2599. Warning (10230): Verilog HDL assignment warning at sine.hex(580): truncated value with size 12 to match size of target (10)
    2600. 

  2600. Warning (10230): Verilog HDL assignment warning at sine.hex(581): truncated value with size 12 to match size of target (10)
    2601. 

  2601. Warning (10230): Verilog HDL assignment warning at sine.hex(582): truncated value with size 12 to match size of target (10)
    2602. 

  2602. Warning (10230): Verilog HDL assignment warning at sine.hex(583): truncated value with size 12 to match size of target (10)
    2603. 

  2603. Warning (10230): Verilog HDL assignment warning at sine.hex(584): truncated value with size 12 to match size of target (10)
    2604. 

  2604. Warning (10230): Verilog HDL assignment warning at sine.hex(585): truncated value with size 12 to match size of target (10)
    2605. 

  2605. Warning (10230): Verilog HDL assignment warning at sine.hex(586): truncated value with size 12 to match size of target (10)
    2606. 

  2606. Warning (10230): Verilog HDL assignment warning at sine.hex(587): truncated value with size 12 to match size of target (10)
    2607. 

  2607. Warning (10230): Verilog HDL assignment warning at sine.hex(588): truncated value with size 12 to match size of target (10)
    2608. 

  2608. Warning (10230): Verilog HDL assignment warning at sine.hex(589): truncated value with size 12 to match size of target (10)
    2609. 

  2609. Warning (10230): Verilog HDL assignment warning at sine.hex(590): truncated value with size 12 to match size of target (10)
    2610. 

  2610. Warning (10230): Verilog HDL assignment warning at sine.hex(591): truncated value with size 12 to match size of target (10)
    2611. 

  2611. Warning (10230): Verilog HDL assignment warning at sine.hex(592): truncated value with size 12 to match size of target (10)
    2612. 

  2612. Warning (10230): Verilog HDL assignment warning at sine.hex(593): truncated value with size 12 to match size of target (10)
    2613. 

  2613. Warning (10230): Verilog HDL assignment warning at sine.hex(594): truncated value with size 12 to match size of target (10)
    2614. 

  2614. Warning (10230): Verilog HDL assignment warning at sine.hex(595): truncated value with size 12 to match size of target (10)
    2615. 

  2615. Warning (10230): Verilog HDL assignment warning at sine.hex(596): truncated value with size 12 to match size of target (10)
    2616. 

  2616. Warning (10230): Verilog HDL assignment warning at sine.hex(597): truncated value with size 12 to match size of target (10)
    2617. 

  2617. Warning (10230): Verilog HDL assignment warning at sine.hex(598): truncated value with size 12 to match size of target (10)
    2618. 

  2618. Warning (10230): Verilog HDL assignment warning at sine.hex(599): truncated value with size 12 to match size of target (10)
    2619. 

  2619. Warning (10230): Verilog HDL assignment warning at sine.hex(600): truncated value with size 12 to match size of target (10)
    2620. 

  2620. Warning (10230): Verilog HDL assignment warning at sine.hex(601): truncated value with size 12 to match size of target (10)
    2621. 

  2621. Warning (10230): Verilog HDL assignment warning at sine.hex(602): truncated value with size 12 to match size of target (10)
    2622. 

  2622. Warning (10230): Verilog HDL assignment warning at sine.hex(603): truncated value with size 12 to match size of target (10)
    2623. 

  2623. Warning (10230): Verilog HDL assignment warning at sine.hex(604): truncated value with size 12 to match size of target (10)
    2624. 

  2624. Warning (10230): Verilog HDL assignment warning at sine.hex(605): truncated value with size 12 to match size of target (10)
    2625. 

  2625. Warning (10230): Verilog HDL assignment warning at sine.hex(606): truncated value with size 12 to match size of target (10)
    2626. 

  2626. Warning (10230): Verilog HDL assignment warning at sine.hex(607): truncated value with size 12 to match size of target (10)
    2627. 

  2627. Warning (10230): Verilog HDL assignment warning at sine.hex(608): truncated value with size 12 to match size of target (10)
    2628. 

  2628. Warning (10230): Verilog HDL assignment warning at sine.hex(609): truncated value with size 12 to match size of target (10)
    2629. 

  2629. Warning (10230): Verilog HDL assignment warning at sine.hex(610): truncated value with size 12 to match size of target (10)
    2630. 

  2630. Warning (10230): Verilog HDL assignment warning at sine.hex(611): truncated value with size 12 to match size of target (10)
    2631. 

  2631. Warning (10230): Verilog HDL assignment warning at sine.hex(612): truncated value with size 12 to match size of target (10)
    2632. 

  2632. Warning (10230): Verilog HDL assignment warning at sine.hex(613): truncated value with size 12 to match size of target (10)
    2633. 

  2633. Warning (10230): Verilog HDL assignment warning at sine.hex(614): truncated value with size 12 to match size of target (10)
    2634. 

  2634. Warning (10230): Verilog HDL assignment warning at sine.hex(615): truncated value with size 12 to match size of target (10)
    2635. 

  2635. Warning (10230): Verilog HDL assignment warning at sine.hex(616): truncated value with size 12 to match size of target (10)
    2636. 

  2636. Warning (10230): Verilog HDL assignment warning at sine.hex(617): truncated value with size 12 to match size of target (10)
    2637. 

  2637. Warning (10230): Verilog HDL assignment warning at sine.hex(618): truncated value with size 12 to match size of target (10)
    2638. 

  2638. Warning (10230): Verilog HDL assignment warning at sine.hex(619): truncated value with size 12 to match size of target (10)
    2639. 

  2639. Warning (10230): Verilog HDL assignment warning at sine.hex(620): truncated value with size 12 to match size of target (10)
    2640. 

  2640. Warning (10230): Verilog HDL assignment warning at sine.hex(621): truncated value with size 12 to match size of target (10)
    2641. 

  2641. Warning (10230): Verilog HDL assignment warning at sine.hex(622): truncated value with size 12 to match size of target (10)
    2642. 

  2642. Warning (10230): Verilog HDL assignment warning at sine.hex(623): truncated value with size 12 to match size of target (10)
    2643. 

  2643. Warning (10230): Verilog HDL assignment warning at sine.hex(624): truncated value with size 12 to match size of target (10)
    2644. 

  2644. Warning (10230): Verilog HDL assignment warning at sine.hex(625): truncated value with size 12 to match size of target (10)
    2645. 

  2645. Warning (10230): Verilog HDL assignment warning at sine.hex(626): truncated value with size 12 to match size of target (10)
    2646. 

  2646. Warning (10230): Verilog HDL assignment warning at sine.hex(627): truncated value with size 12 to match size of target (10)
    2647. 

  2647. Warning (10230): Verilog HDL assignment warning at sine.hex(628): truncated value with size 12 to match size of target (10)
    2648. 

  2648. Warning (10230): Verilog HDL assignment warning at sine.hex(629): truncated value with size 12 to match size of target (10)
    2649. 

  2649. Warning (10230): Verilog HDL assignment warning at sine.hex(630): truncated value with size 12 to match size of target (10)
    2650. 

  2650. Warning (10230): Verilog HDL assignment warning at sine.hex(631): truncated value with size 12 to match size of target (10)
    2651. 

  2651. Warning (10230): Verilog HDL assignment warning at sine.hex(632): truncated value with size 12 to match size of target (10)
    2652. 

  2652. Warning (10230): Verilog HDL assignment warning at sine.hex(633): truncated value with size 12 to match size of target (10)
    2653. 

  2653. Warning (10230): Verilog HDL assignment warning at sine.hex(634): truncated value with size 12 to match size of target (10)
    2654. 

  2654. Warning (10230): Verilog HDL assignment warning at sine.hex(635): truncated value with size 12 to match size of target (10)
    2655. 

  2655. Warning (10230): Verilog HDL assignment warning at sine.hex(636): truncated value with size 12 to match size of target (10)
    2656. 

  2656. Warning (10230): Verilog HDL assignment warning at sine.hex(637): truncated value with size 12 to match size of target (10)
    2657. 

  2657. Warning (10230): Verilog HDL assignment warning at sine.hex(638): truncated value with size 12 to match size of target (10)
    2658. 

  2658. Warning (10230): Verilog HDL assignment warning at sine.hex(639): truncated value with size 12 to match size of target (10)
    2659. 

  2659. Warning (10230): Verilog HDL assignment warning at sine.hex(640): truncated value with size 12 to match size of target (10)
    2660. 

  2660. Warning (10230): Verilog HDL assignment warning at sine.hex(641): truncated value with size 12 to match size of target (10)
    2661. 

  2661. Warning (10230): Verilog HDL assignment warning at sine.hex(642): truncated value with size 12 to match size of target (10)
    2662. 

  2662. Warning (10230): Verilog HDL assignment warning at sine.hex(643): truncated value with size 12 to match size of target (10)
    2663. 

  2663. Warning (10230): Verilog HDL assignment warning at sine.hex(644): truncated value with size 12 to match size of target (10)
    2664. 

  2664. Warning (10230): Verilog HDL assignment warning at sine.hex(645): truncated value with size 12 to match size of target (10)
    2665. 

  2665. Warning (10230): Verilog HDL assignment warning at sine.hex(646): truncated value with size 12 to match size of target (10)
    2666. 

  2666. Warning (10230): Verilog HDL assignment warning at sine.hex(647): truncated value with size 12 to match size of target (10)
    2667. 

  2667. Warning (10230): Verilog HDL assignment warning at sine.hex(648): truncated value with size 12 to match size of target (10)
    2668. 

  2668. Warning (10230): Verilog HDL assignment warning at sine.hex(649): truncated value with size 12 to match size of target (10)
    2669. 

  2669. Warning (10230): Verilog HDL assignment warning at sine.hex(650): truncated value with size 12 to match size of target (10)
    2670. 

  2670. Warning (10230): Verilog HDL assignment warning at sine.hex(651): truncated value with size 12 to match size of target (10)
    2671. 

  2671. Warning (10230): Verilog HDL assignment warning at sine.hex(652): truncated value with size 12 to match size of target (10)
    2672. 

  2672. Warning (10230): Verilog HDL assignment warning at sine.hex(653): truncated value with size 12 to match size of target (10)
    2673. 

  2673. Warning (10230): Verilog HDL assignment warning at sine.hex(654): truncated value with size 12 to match size of target (10)
    2674. 

  2674. Warning (10230): Verilog HDL assignment warning at sine.hex(655): truncated value with size 12 to match size of target (10)
    2675. 

  2675. Warning (10230): Verilog HDL assignment warning at sine.hex(656): truncated value with size 12 to match size of target (10)
    2676. 

  2676. Warning (10230): Verilog HDL assignment warning at sine.hex(657): truncated value with size 12 to match size of target (10)
    2677. 

  2677. Warning (10230): Verilog HDL assignment warning at sine.hex(658): truncated value with size 12 to match size of target (10)
    2678. 

  2678. Warning (10230): Verilog HDL assignment warning at sine.hex(659): truncated value with size 12 to match size of target (10)
    2679. 

  2679. Warning (10230): Verilog HDL assignment warning at sine.hex(660): truncated value with size 12 to match size of target (10)
    2680. 

  2680. Warning (10230): Verilog HDL assignment warning at sine.hex(661): truncated value with size 12 to match size of target (10)
    2681. 

  2681. Warning (10230): Verilog HDL assignment warning at sine.hex(662): truncated value with size 12 to match size of target (10)
    2682. 

  2682. Warning (10230): Verilog HDL assignment warning at sine.hex(663): truncated value with size 12 to match size of target (10)
    2683. 

  2683. Warning (10230): Verilog HDL assignment warning at sine.hex(664): truncated value with size 12 to match size of target (10)
    2684. 

  2684. Warning (10230): Verilog HDL assignment warning at sine.hex(665): truncated value with size 12 to match size of target (10)
    2685. 

  2685. Warning (10230): Verilog HDL assignment warning at sine.hex(666): truncated value with size 12 to match size of target (10)
    2686. 

  2686. Warning (10230): Verilog HDL assignment warning at sine.hex(667): truncated value with size 12 to match size of target (10)
    2687. 

  2687. Warning (10230): Verilog HDL assignment warning at sine.hex(668): truncated value with size 12 to match size of target (10)
    2688. 

  2688. Warning (10230): Verilog HDL assignment warning at sine.hex(669): truncated value with size 12 to match size of target (10)
    2689. 

  2689. Warning (10230): Verilog HDL assignment warning at sine.hex(670): truncated value with size 12 to match size of target (10)
    2690. 

  2690. Warning (10230): Verilog HDL assignment warning at sine.hex(671): truncated value with size 12 to match size of target (10)
    2691. 

  2691. Warning (10230): Verilog HDL assignment warning at sine.hex(672): truncated value with size 12 to match size of target (10)
    2692. 

  2692. Warning (10230): Verilog HDL assignment warning at sine.hex(673): truncated value with size 12 to match size of target (10)
    2693. 

  2693. Warning (10230): Verilog HDL assignment warning at sine.hex(674): truncated value with size 12 to match size of target (10)
    2694. 

  2694. Warning (10230): Verilog HDL assignment warning at sine.hex(675): truncated value with size 12 to match size of target (10)
    2695. 

  2695. Warning (10230): Verilog HDL assignment warning at sine.hex(676): truncated value with size 12 to match size of target (10)
    2696. 

  2696. Warning (10230): Verilog HDL assignment warning at sine.hex(677): truncated value with size 12 to match size of target (10)
    2697. 

  2697. Warning (10230): Verilog HDL assignment warning at sine.hex(678): truncated value with size 12 to match size of target (10)
    2698. 

  2698. Warning (10230): Verilog HDL assignment warning at sine.hex(679): truncated value with size 12 to match size of target (10)
    2699. 

  2699. Warning (10230): Verilog HDL assignment warning at sine.hex(680): truncated value with size 12 to match size of target (10)
    2700. 

  2700. Warning (10230): Verilog HDL assignment warning at sine.hex(681): truncated value with size 12 to match size of target (10)
    2701. 

  2701. Warning (10230): Verilog HDL assignment warning at sine.hex(682): truncated value with size 12 to match size of target (10)
    2702. 

  2702. Warning (10230): Verilog HDL assignment warning at sine.hex(683): truncated value with size 12 to match size of target (10)
    2703. 

  2703. Warning (10230): Verilog HDL assignment warning at sine.hex(684): truncated value with size 12 to match size of target (10)
    2704. 

  2704. Warning (10230): Verilog HDL assignment warning at sine.hex(685): truncated value with size 12 to match size of target (10)
    2705. 

  2705. Warning (10230): Verilog HDL assignment warning at sine.hex(686): truncated value with size 12 to match size of target (10)
    2706. 

  2706. Warning (10230): Verilog HDL assignment warning at sine.hex(687): truncated value with size 12 to match size of target (10)
    2707. 

  2707. Warning (10230): Verilog HDL assignment warning at sine.hex(688): truncated value with size 12 to match size of target (10)
    2708. 

  2708. Warning (10230): Verilog HDL assignment warning at sine.hex(689): truncated value with size 12 to match size of target (10)
    2709. 

  2709. Warning (10230): Verilog HDL assignment warning at sine.hex(690): truncated value with size 12 to match size of target (10)
    2710. 

  2710. Warning (10230): Verilog HDL assignment warning at sine.hex(691): truncated value with size 12 to match size of target (10)
    2711. 

  2711. Warning (10230): Verilog HDL assignment warning at sine.hex(692): truncated value with size 12 to match size of target (10)
    2712. 

  2712. Warning (10230): Verilog HDL assignment warning at sine.hex(693): truncated value with size 12 to match size of target (10)
    2713. 

  2713. Warning (10230): Verilog HDL assignment warning at sine.hex(694): truncated value with size 12 to match size of target (10)
    2714. 

  2714. Warning (10230): Verilog HDL assignment warning at sine.hex(695): truncated value with size 12 to match size of target (10)
    2715. 

  2715. Warning (10230): Verilog HDL assignment warning at sine.hex(696): truncated value with size 12 to match size of target (10)
    2716. 

  2716. Warning (10230): Verilog HDL assignment warning at sine.hex(697): truncated value with size 12 to match size of target (10)
    2717. 

  2717. Warning (10230): Verilog HDL assignment warning at sine.hex(698): truncated value with size 12 to match size of target (10)
    2718. 

  2718. Warning (10230): Verilog HDL assignment warning at sine.hex(699): truncated value with size 12 to match size of target (10)
    2719. 

  2719. Warning (10230): Verilog HDL assignment warning at sine.hex(700): truncated value with size 12 to match size of target (10)
    2720. 

  2720. Warning (10230): Verilog HDL assignment warning at sine.hex(701): truncated value with size 12 to match size of target (10)
    2721. 

  2721. Warning (10230): Verilog HDL assignment warning at sine.hex(702): truncated value with size 12 to match size of target (10)
    2722. 

  2722. Warning (10230): Verilog HDL assignment warning at sine.hex(703): truncated value with size 12 to match size of target (10)
    2723. 

  2723. Warning (10230): Verilog HDL assignment warning at sine.hex(704): truncated value with size 12 to match size of target (10)
    2724. 

  2724. Warning (10230): Verilog HDL assignment warning at sine.hex(705): truncated value with size 12 to match size of target (10)
    2725. 

  2725. Warning (10230): Verilog HDL assignment warning at sine.hex(706): truncated value with size 12 to match size of target (10)
    2726. 

  2726. Warning (10230): Verilog HDL assignment warning at sine.hex(707): truncated value with size 12 to match size of target (10)
    2727. 

  2727. Warning (10230): Verilog HDL assignment warning at sine.hex(708): truncated value with size 12 to match size of target (10)
    2728. 

  2728. Warning (10230): Verilog HDL assignment warning at sine.hex(709): truncated value with size 12 to match size of target (10)
    2729. 

  2729. Warning (10230): Verilog HDL assignment warning at sine.hex(710): truncated value with size 12 to match size of target (10)
    2730. 

  2730. Warning (10230): Verilog HDL assignment warning at sine.hex(711): truncated value with size 12 to match size of target (10)
    2731. 

  2731. Warning (10230): Verilog HDL assignment warning at sine.hex(712): truncated value with size 12 to match size of target (10)
    2732. 

  2732. Warning (10230): Verilog HDL assignment warning at sine.hex(713): truncated value with size 12 to match size of target (10)
    2733. 

  2733. Warning (10230): Verilog HDL assignment warning at sine.hex(714): truncated value with size 12 to match size of target (10)
    2734. 

  2734. Warning (10230): Verilog HDL assignment warning at sine.hex(715): truncated value with size 12 to match size of target (10)
    2735. 

  2735. Warning (10230): Verilog HDL assignment warning at sine.hex(716): truncated value with size 12 to match size of target (10)
    2736. 

  2736. Warning (10230): Verilog HDL assignment warning at sine.hex(717): truncated value with size 12 to match size of target (10)
    2737. 

  2737. Warning (10230): Verilog HDL assignment warning at sine.hex(718): truncated value with size 12 to match size of target (10)
    2738. 

  2738. Warning (10230): Verilog HDL assignment warning at sine.hex(719): truncated value with size 12 to match size of target (10)
    2739. 

  2739. Warning (10230): Verilog HDL assignment warning at sine.hex(720): truncated value with size 12 to match size of target (10)
    2740. 

  2740. Warning (10230): Verilog HDL assignment warning at sine.hex(721): truncated value with size 12 to match size of target (10)
    2741. 

  2741. Warning (10230): Verilog HDL assignment warning at sine.hex(722): truncated value with size 12 to match size of target (10)
    2742. 

  2742. Warning (10230): Verilog HDL assignment warning at sine.hex(723): truncated value with size 12 to match size of target (10)
    2743. 

  2743. Warning (10230): Verilog HDL assignment warning at sine.hex(724): truncated value with size 12 to match size of target (10)
    2744. 

  2744. Warning (10230): Verilog HDL assignment warning at sine.hex(725): truncated value with size 12 to match size of target (10)
    2745. 

  2745. Warning (10230): Verilog HDL assignment warning at sine.hex(726): truncated value with size 12 to match size of target (10)
    2746. 

  2746. Warning (10230): Verilog HDL assignment warning at sine.hex(727): truncated value with size 12 to match size of target (10)
    2747. 

  2747. Warning (10230): Verilog HDL assignment warning at sine.hex(728): truncated value with size 12 to match size of target (10)
    2748. 

  2748. Warning (10230): Verilog HDL assignment warning at sine.hex(729): truncated value with size 12 to match size of target (10)
    2749. 

  2749. Warning (10230): Verilog HDL assignment warning at sine.hex(730): truncated value with size 12 to match size of target (10)
    2750. 

  2750. Warning (10230): Verilog HDL assignment warning at sine.hex(731): truncated value with size 12 to match size of target (10)
    2751. 

  2751. Warning (10230): Verilog HDL assignment warning at sine.hex(732): truncated value with size 12 to match size of target (10)
    2752. 

  2752. Warning (10230): Verilog HDL assignment warning at sine.hex(733): truncated value with size 12 to match size of target (10)
    2753. 

  2753. Warning (10230): Verilog HDL assignment warning at sine.hex(734): truncated value with size 12 to match size of target (10)
    2754. 

  2754. Warning (10230): Verilog HDL assignment warning at sine.hex(735): truncated value with size 12 to match size of target (10)
    2755. 

  2755. Warning (10230): Verilog HDL assignment warning at sine.hex(736): truncated value with size 12 to match size of target (10)
    2756. 

  2756. Warning (10230): Verilog HDL assignment warning at sine.hex(737): truncated value with size 12 to match size of target (10)
    2757. 

  2757. Warning (10230): Verilog HDL assignment warning at sine.hex(738): truncated value with size 12 to match size of target (10)
    2758. 

  2758. Warning (10230): Verilog HDL assignment warning at sine.hex(739): truncated value with size 12 to match size of target (10)
    2759. 

  2759. Warning (10230): Verilog HDL assignment warning at sine.hex(740): truncated value with size 12 to match size of target (10)
    2760. 

  2760. Warning (10230): Verilog HDL assignment warning at sine.hex(741): truncated value with size 12 to match size of target (10)
    2761. 

  2761. Warning (10230): Verilog HDL assignment warning at sine.hex(742): truncated value with size 12 to match size of target (10)
    2762. 

  2762. Warning (10230): Verilog HDL assignment warning at sine.hex(743): truncated value with size 12 to match size of target (10)
    2763. 

  2763. Warning (10230): Verilog HDL assignment warning at sine.hex(744): truncated value with size 12 to match size of target (10)
    2764. 

  2764. Warning (10230): Verilog HDL assignment warning at sine.hex(745): truncated value with size 12 to match size of target (10)
    2765. 

  2765. Warning (10230): Verilog HDL assignment warning at sine.hex(746): truncated value with size 12 to match size of target (10)
    2766. 

  2766. Warning (10230): Verilog HDL assignment warning at sine.hex(747): truncated value with size 12 to match size of target (10)
    2767. 

  2767. Warning (10230): Verilog HDL assignment warning at sine.hex(748): truncated value with size 12 to match size of target (10)
    2768. 

  2768. Warning (10230): Verilog HDL assignment warning at sine.hex(749): truncated value with size 12 to match size of target (10)
    2769. 

  2769. Warning (10230): Verilog HDL assignment warning at sine.hex(750): truncated value with size 12 to match size of target (10)
    2770. 

  2770. Warning (10230): Verilog HDL assignment warning at sine.hex(751): truncated value with size 12 to match size of target (10)
    2771. 

  2771. Warning (10230): Verilog HDL assignment warning at sine.hex(752): truncated value with size 12 to match size of target (10)
    2772. 

  2772. Warning (10230): Verilog HDL assignment warning at sine.hex(753): truncated value with size 12 to match size of target (10)
    2773. 

  2773. Warning (10230): Verilog HDL assignment warning at sine.hex(754): truncated value with size 12 to match size of target (10)
    2774. 

  2774. Warning (10230): Verilog HDL assignment warning at sine.hex(755): truncated value with size 12 to match size of target (10)
    2775. 

  2775. Warning (10230): Verilog HDL assignment warning at sine.hex(756): truncated value with size 12 to match size of target (10)
    2776. 

  2776. Warning (10230): Verilog HDL assignment warning at sine.hex(757): truncated value with size 12 to match size of target (10)
    2777. 

  2777. Warning (10230): Verilog HDL assignment warning at sine.hex(758): truncated value with size 12 to match size of target (10)
    2778. 

  2778. Warning (10230): Verilog HDL assignment warning at sine.hex(759): truncated value with size 12 to match size of target (10)
    2779. 

  2779. Warning (10230): Verilog HDL assignment warning at sine.hex(760): truncated value with size 12 to match size of target (10)
    2780. 

  2780. Warning (10230): Verilog HDL assignment warning at sine.hex(761): truncated value with size 12 to match size of target (10)
    2781. 

  2781. Warning (10230): Verilog HDL assignment warning at sine.hex(762): truncated value with size 12 to match size of target (10)
    2782. 

  2782. Warning (10230): Verilog HDL assignment warning at sine.hex(763): truncated value with size 12 to match size of target (10)
    2783. 

  2783. Warning (10230): Verilog HDL assignment warning at sine.hex(764): truncated value with size 12 to match size of target (10)
    2784. 

  2784. Warning (10230): Verilog HDL assignment warning at sine.hex(765): truncated value with size 12 to match size of target (10)
    2785. 

  2785. Warning (10230): Verilog HDL assignment warning at sine.hex(766): truncated value with size 12 to match size of target (10)
    2786. 

  2786. Warning (10230): Verilog HDL assignment warning at sine.hex(767): truncated value with size 12 to match size of target (10)
    2787. 

  2787. Warning (10230): Verilog HDL assignment warning at sine.hex(768): truncated value with size 12 to match size of target (10)
    2788. 

  2788. Warning (10230): Verilog HDL assignment warning at sine.hex(769): truncated value with size 12 to match size of target (10)
    2789. 

  2789. Warning (10230): Verilog HDL assignment warning at sine.hex(770): truncated value with size 12 to match size of target (10)
    2790. 

  2790. Warning (10230): Verilog HDL assignment warning at sine.hex(771): truncated value with size 12 to match size of target (10)
    2791. 

  2791. Warning (10230): Verilog HDL assignment warning at sine.hex(772): truncated value with size 12 to match size of target (10)
    2792. 

  2792. Warning (10230): Verilog HDL assignment warning at sine.hex(773): truncated value with size 12 to match size of target (10)
    2793. 

  2793. Warning (10230): Verilog HDL assignment warning at sine.hex(774): truncated value with size 12 to match size of target (10)
    2794. 

  2794. Warning (10230): Verilog HDL assignment warning at sine.hex(775): truncated value with size 12 to match size of target (10)
    2795. 

  2795. Warning (10230): Verilog HDL assignment warning at sine.hex(776): truncated value with size 12 to match size of target (10)
    2796. 

  2796. Warning (10230): Verilog HDL assignment warning at sine.hex(777): truncated value with size 12 to match size of target (10)
    2797. 

  2797. Warning (10230): Verilog HDL assignment warning at sine.hex(778): truncated value with size 12 to match size of target (10)
    2798. 

  2798. Warning (10230): Verilog HDL assignment warning at sine.hex(779): truncated value with size 12 to match size of target (10)
    2799. 

  2799. Warning (10230): Verilog HDL assignment warning at sine.hex(780): truncated value with size 12 to match size of target (10)
    2800. 

  2800. Warning (10230): Verilog HDL assignment warning at sine.hex(781): truncated value with size 12 to match size of target (10)
    2801. 

  2801. Warning (10230): Verilog HDL assignment warning at sine.hex(782): truncated value with size 12 to match size of target (10)
    2802. 

  2802. Warning (10230): Verilog HDL assignment warning at sine.hex(783): truncated value with size 12 to match size of target (10)
    2803. 

  2803. Warning (10230): Verilog HDL assignment warning at sine.hex(784): truncated value with size 12 to match size of target (10)
    2804. 

  2804. Warning (10230): Verilog HDL assignment warning at sine.hex(785): truncated value with size 12 to match size of target (10)
    2805. 

  2805. Warning (10230): Verilog HDL assignment warning at sine.hex(786): truncated value with size 12 to match size of target (10)
    2806. 

  2806. Warning (10230): Verilog HDL assignment warning at sine.hex(787): truncated value with size 12 to match size of target (10)
    2807. 

  2807. Warning (10230): Verilog HDL assignment warning at sine.hex(788): truncated value with size 12 to match size of target (10)
    2808. 

  2808. Warning (10230): Verilog HDL assignment warning at sine.hex(789): truncated value with size 12 to match size of target (10)
    2809. 

  2809. Warning (10230): Verilog HDL assignment warning at sine.hex(790): truncated value with size 12 to match size of target (10)
    2810. 

  2810. Warning (10230): Verilog HDL assignment warning at sine.hex(791): truncated value with size 12 to match size of target (10)
    2811. 

  2811. Warning (10230): Verilog HDL assignment warning at sine.hex(792): truncated value with size 12 to match size of target (10)
    2812. 

  2812. Warning (10230): Verilog HDL assignment warning at sine.hex(793): truncated value with size 12 to match size of target (10)
    2813. 

  2813. Warning (10230): Verilog HDL assignment warning at sine.hex(794): truncated value with size 12 to match size of target (10)
    2814. 

  2814. Warning (10230): Verilog HDL assignment warning at sine.hex(795): truncated value with size 12 to match size of target (10)
    2815. 

  2815. Warning (10230): Verilog HDL assignment warning at sine.hex(796): truncated value with size 12 to match size of target (10)
    2816. 

  2816. Warning (10230): Verilog HDL assignment warning at sine.hex(797): truncated value with size 12 to match size of target (10)
    2817. 

  2817. Warning (10230): Verilog HDL assignment warning at sine.hex(798): truncated value with size 12 to match size of target (10)
    2818. 

  2818. Warning (10230): Verilog HDL assignment warning at sine.hex(799): truncated value with size 12 to match size of target (10)
    2819. 

  2819. Warning (10230): Verilog HDL assignment warning at sine.hex(800): truncated value with size 12 to match size of target (10)
    2820. 

  2820. Warning (10230): Verilog HDL assignment warning at sine.hex(801): truncated value with size 12 to match size of target (10)
    2821. 

  2821. Warning (10230): Verilog HDL assignment warning at sine.hex(802): truncated value with size 12 to match size of target (10)
    2822. 

  2822. Warning (10230): Verilog HDL assignment warning at sine.hex(803): truncated value with size 12 to match size of target (10)
    2823. 

  2823. Warning (10230): Verilog HDL assignment warning at sine.hex(804): truncated value with size 12 to match size of target (10)
    2824. 

  2824. Warning (10230): Verilog HDL assignment warning at sine.hex(805): truncated value with size 12 to match size of target (10)
    2825. 

  2825. Warning (10230): Verilog HDL assignment warning at sine.hex(806): truncated value with size 12 to match size of target (10)
    2826. 

  2826. Warning (10230): Verilog HDL assignment warning at sine.hex(807): truncated value with size 12 to match size of target (10)
    2827. 

  2827. Warning (10230): Verilog HDL assignment warning at sine.hex(808): truncated value with size 12 to match size of target (10)
    2828. 

  2828. Warning (10230): Verilog HDL assignment warning at sine.hex(809): truncated value with size 12 to match size of target (10)
    2829. 

  2829. Warning (10230): Verilog HDL assignment warning at sine.hex(810): truncated value with size 12 to match size of target (10)
    2830. 

  2830. Warning (10230): Verilog HDL assignment warning at sine.hex(811): truncated value with size 12 to match size of target (10)
    2831. 

  2831. Warning (10230): Verilog HDL assignment warning at sine.hex(812): truncated value with size 12 to match size of target (10)
    2832. 

  2832. Warning (10230): Verilog HDL assignment warning at sine.hex(813): truncated value with size 12 to match size of target (10)
    2833. 

  2833. Warning (10230): Verilog HDL assignment warning at sine.hex(814): truncated value with size 12 to match size of target (10)
    2834. 

  2834. Warning (10230): Verilog HDL assignment warning at sine.hex(815): truncated value with size 12 to match size of target (10)
    2835. 

  2835. Warning (10230): Verilog HDL assignment warning at sine.hex(816): truncated value with size 12 to match size of target (10)
    2836. 

  2836. Warning (10230): Verilog HDL assignment warning at sine.hex(817): truncated value with size 12 to match size of target (10)
    2837. 

  2837. Warning (10230): Verilog HDL assignment warning at sine.hex(818): truncated value with size 12 to match size of target (10)
    2838. 

  2838. Warning (10230): Verilog HDL assignment warning at sine.hex(819): truncated value with size 12 to match size of target (10)
    2839. 

  2839. Warning (10230): Verilog HDL assignment warning at sine.hex(820): truncated value with size 12 to match size of target (10)
    2840. 

  2840. Warning (10230): Verilog HDL assignment warning at sine.hex(821): truncated value with size 12 to match size of target (10)
    2841. 

  2841. Warning (10230): Verilog HDL assignment warning at sine.hex(822): truncated value with size 12 to match size of target (10)
    2842. 

  2842. Warning (10230): Verilog HDL assignment warning at sine.hex(823): truncated value with size 12 to match size of target (10)
    2843. 

  2843. Warning (10230): Verilog HDL assignment warning at sine.hex(824): truncated value with size 12 to match size of target (10)
    2844. 

  2844. Warning (10230): Verilog HDL assignment warning at sine.hex(825): truncated value with size 12 to match size of target (10)
    2845. 

  2845. Warning (10230): Verilog HDL assignment warning at sine.hex(826): truncated value with size 12 to match size of target (10)
    2846. 

  2846. Warning (10230): Verilog HDL assignment warning at sine.hex(827): truncated value with size 12 to match size of target (10)
    2847. 

  2847. Warning (10230): Verilog HDL assignment warning at sine.hex(828): truncated value with size 12 to match size of target (10)
    2848. 

  2848. Warning (10230): Verilog HDL assignment warning at sine.hex(829): truncated value with size 12 to match size of target (10)
    2849. 

  2849. Warning (10230): Verilog HDL assignment warning at sine.hex(830): truncated value with size 12 to match size of target (10)
    2850. 

  2850. Warning (10230): Verilog HDL assignment warning at sine.hex(831): truncated value with size 12 to match size of target (10)
    2851. 

  2851. Warning (10230): Verilog HDL assignment warning at sine.hex(832): truncated value with size 12 to match size of target (10)
    2852. 

  2852. Warning (10230): Verilog HDL assignment warning at sine.hex(833): truncated value with size 12 to match size of target (10)
    2853. 

  2853. Warning (10230): Verilog HDL assignment warning at sine.hex(834): truncated value with size 12 to match size of target (10)
    2854. 

  2854. Warning (10230): Verilog HDL assignment warning at sine.hex(835): truncated value with size 12 to match size of target (10)
    2855. 

  2855. Warning (10230): Verilog HDL assignment warning at sine.hex(836): truncated value with size 12 to match size of target (10)
    2856. 

  2856. Warning (10230): Verilog HDL assignment warning at sine.hex(837): truncated value with size 12 to match size of target (10)
    2857. 

  2857. Warning (10230): Verilog HDL assignment warning at sine.hex(838): truncated value with size 12 to match size of target (10)
    2858. 

  2858. Warning (10230): Verilog HDL assignment warning at sine.hex(839): truncated value with size 12 to match size of target (10)
    2859. 

  2859. Warning (10230): Verilog HDL assignment warning at sine.hex(840): truncated value with size 12 to match size of target (10)
    2860. 

  2860. Warning (10230): Verilog HDL assignment warning at sine.hex(841): truncated value with size 12 to match size of target (10)
    2861. 

  2861. Warning (10230): Verilog HDL assignment warning at sine.hex(842): truncated value with size 12 to match size of target (10)
    2862. 

  2862. Warning (10230): Verilog HDL assignment warning at sine.hex(843): truncated value with size 12 to match size of target (10)
    2863. 

  2863. Warning (10230): Verilog HDL assignment warning at sine.hex(844): truncated value with size 12 to match size of target (10)
    2864. 

  2864. Warning (10230): Verilog HDL assignment warning at sine.hex(845): truncated value with size 12 to match size of target (10)
    2865. 

  2865. Warning (10230): Verilog HDL assignment warning at sine.hex(846): truncated value with size 12 to match size of target (10)
    2866. 

  2866. Warning (10230): Verilog HDL assignment warning at sine.hex(847): truncated value with size 12 to match size of target (10)
    2867. 

  2867. Warning (10230): Verilog HDL assignment warning at sine.hex(848): truncated value with size 12 to match size of target (10)
    2868. 

  2868. Warning (10230): Verilog HDL assignment warning at sine.hex(849): truncated value with size 12 to match size of target (10)
    2869. 

  2869. Warning (10230): Verilog HDL assignment warning at sine.hex(850): truncated value with size 12 to match size of target (10)
    2870. 

  2870. Warning (10230): Verilog HDL assignment warning at sine.hex(851): truncated value with size 12 to match size of target (10)
    2871. 

  2871. Warning (10230): Verilog HDL assignment warning at sine.hex(852): truncated value with size 12 to match size of target (10)
    2872. 

  2872. Warning (10230): Verilog HDL assignment warning at sine.hex(853): truncated value with size 12 to match size of target (10)
    2873. 

  2873. Warning (10230): Verilog HDL assignment warning at sine.hex(854): truncated value with size 12 to match size of target (10)
    2874. 

  2874. Warning (10230): Verilog HDL assignment warning at sine.hex(855): truncated value with size 12 to match size of target (10)
    2875. 

  2875. Warning (10230): Verilog HDL assignment warning at sine.hex(856): truncated value with size 12 to match size of target (10)
    2876. 

  2876. Warning (10230): Verilog HDL assignment warning at sine.hex(857): truncated value with size 12 to match size of target (10)
    2877. 

  2877. Warning (10230): Verilog HDL assignment warning at sine.hex(858): truncated value with size 12 to match size of target (10)
    2878. 

  2878. Warning (10230): Verilog HDL assignment warning at sine.hex(859): truncated value with size 12 to match size of target (10)
    2879. 

  2879. Warning (10230): Verilog HDL assignment warning at sine.hex(860): truncated value with size 12 to match size of target (10)
    2880. 

  2880. Warning (10230): Verilog HDL assignment warning at sine.hex(861): truncated value with size 12 to match size of target (10)
    2881. 

  2881. Warning (10230): Verilog HDL assignment warning at sine.hex(862): truncated value with size 12 to match size of target (10)
    2882. 

  2882. Warning (10230): Verilog HDL assignment warning at sine.hex(863): truncated value with size 12 to match size of target (10)
    2883. 

  2883. Warning (10230): Verilog HDL assignment warning at sine.hex(864): truncated value with size 12 to match size of target (10)
    2884. 

  2884. Warning (10230): Verilog HDL assignment warning at sine.hex(865): truncated value with size 12 to match size of target (10)
    2885. 

  2885. Warning (10230): Verilog HDL assignment warning at sine.hex(866): truncated value with size 12 to match size of target (10)
    2886. 

  2886. Warning (10230): Verilog HDL assignment warning at sine.hex(867): truncated value with size 12 to match size of target (10)
    2887. 

  2887. Warning (10230): Verilog HDL assignment warning at sine.hex(868): truncated value with size 12 to match size of target (10)
    2888. 

  2888. Warning (10230): Verilog HDL assignment warning at sine.hex(869): truncated value with size 12 to match size of target (10)
    2889. 

  2889. Warning (10230): Verilog HDL assignment warning at sine.hex(870): truncated value with size 12 to match size of target (10)
    2890. 

  2890. Warning (10230): Verilog HDL assignment warning at sine.hex(871): truncated value with size 12 to match size of target (10)
    2891. 

  2891. Warning (10230): Verilog HDL assignment warning at sine.hex(872): truncated value with size 12 to match size of target (10)
    2892. 

  2892. Warning (10230): Verilog HDL assignment warning at sine.hex(873): truncated value with size 12 to match size of target (10)
    2893. 

  2893. Warning (10230): Verilog HDL assignment warning at sine.hex(874): truncated value with size 12 to match size of target (10)
    2894. 

  2894. Warning (10230): Verilog HDL assignment warning at sine.hex(875): truncated value with size 12 to match size of target (10)
    2895. 

  2895. Warning (10230): Verilog HDL assignment warning at sine.hex(876): truncated value with size 12 to match size of target (10)
    2896. 

  2896. Warning (10230): Verilog HDL assignment warning at sine.hex(877): truncated value with size 12 to match size of target (10)
    2897. 

  2897. Warning (10230): Verilog HDL assignment warning at sine.hex(878): truncated value with size 12 to match size of target (10)
    2898. 

  2898. Warning (10230): Verilog HDL assignment warning at sine.hex(879): truncated value with size 12 to match size of target (10)
    2899. 

  2899. Warning (10230): Verilog HDL assignment warning at sine.hex(880): truncated value with size 12 to match size of target (10)
    2900. 

  2900. Warning (10230): Verilog HDL assignment warning at sine.hex(881): truncated value with size 12 to match size of target (10)
    2901. 

  2901. Warning (10230): Verilog HDL assignment warning at sine.hex(882): truncated value with size 12 to match size of target (10)
    2902. 

  2902. Warning (10230): Verilog HDL assignment warning at sine.hex(883): truncated value with size 12 to match size of target (10)
    2903. 

  2903. Warning (10230): Verilog HDL assignment warning at sine.hex(884): truncated value with size 12 to match size of target (10)
    2904. 

  2904. Warning (10230): Verilog HDL assignment warning at sine.hex(885): truncated value with size 12 to match size of target (10)
    2905. 

  2905. Warning (10230): Verilog HDL assignment warning at sine.hex(886): truncated value with size 12 to match size of target (10)
    2906. 

  2906. Warning (10230): Verilog HDL assignment warning at sine.hex(887): truncated value with size 12 to match size of target (10)
    2907. 

  2907. Warning (10230): Verilog HDL assignment warning at sine.hex(888): truncated value with size 12 to match size of target (10)
    2908. 

  2908. Warning (10230): Verilog HDL assignment warning at sine.hex(889): truncated value with size 12 to match size of target (10)
    2909. 

  2909. Warning (10230): Verilog HDL assignment warning at sine.hex(890): truncated value with size 12 to match size of target (10)
    2910. 

  2910. Warning (10230): Verilog HDL assignment warning at sine.hex(891): truncated value with size 12 to match size of target (10)
    2911. 

  2911. Warning (10230): Verilog HDL assignment warning at sine.hex(892): truncated value with size 12 to match size of target (10)
    2912. 

  2912. Warning (10230): Verilog HDL assignment warning at sine.hex(893): truncated value with size 12 to match size of target (10)
    2913. 

  2913. Warning (10230): Verilog HDL assignment warning at sine.hex(894): truncated value with size 12 to match size of target (10)
    2914. 

  2914. Warning (10230): Verilog HDL assignment warning at sine.hex(895): truncated value with size 12 to match size of target (10)
    2915. 

  2915. Warning (10230): Verilog HDL assignment warning at sine.hex(896): truncated value with size 12 to match size of target (10)
    2916. 

  2916. Warning (10230): Verilog HDL assignment warning at sine.hex(897): truncated value with size 12 to match size of target (10)
    2917. 

  2917. Warning (10230): Verilog HDL assignment warning at sine.hex(898): truncated value with size 12 to match size of target (10)
    2918. 

  2918. Warning (10230): Verilog HDL assignment warning at sine.hex(899): truncated value with size 12 to match size of target (10)
    2919. 

  2919. Warning (10230): Verilog HDL assignment warning at sine.hex(900): truncated value with size 12 to match size of target (10)
    2920. 

  2920. Warning (10230): Verilog HDL assignment warning at sine.hex(901): truncated value with size 12 to match size of target (10)
    2921. 

  2921. Warning (10230): Verilog HDL assignment warning at sine.hex(902): truncated value with size 12 to match size of target (10)
    2922. 

  2922. Warning (10230): Verilog HDL assignment warning at sine.hex(903): truncated value with size 12 to match size of target (10)
    2923. 

  2923. Warning (10230): Verilog HDL assignment warning at sine.hex(904): truncated value with size 12 to match size of target (10)
    2924. 

  2924. Warning (10230): Verilog HDL assignment warning at sine.hex(905): truncated value with size 12 to match size of target (10)
    2925. 

  2925. Warning (10230): Verilog HDL assignment warning at sine.hex(906): truncated value with size 12 to match size of target (10)
    2926. 

  2926. Warning (10230): Verilog HDL assignment warning at sine.hex(907): truncated value with size 12 to match size of target (10)
    2927. 

  2927. Warning (10230): Verilog HDL assignment warning at sine.hex(908): truncated value with size 12 to match size of target (10)
    2928. 

  2928. Warning (10230): Verilog HDL assignment warning at sine.hex(909): truncated value with size 12 to match size of target (10)
    2929. 

  2929. Warning (10230): Verilog HDL assignment warning at sine.hex(910): truncated value with size 12 to match size of target (10)
    2930. 

  2930. Warning (10230): Verilog HDL assignment warning at sine.hex(911): truncated value with size 12 to match size of target (10)
    2931. 

  2931. Warning (10230): Verilog HDL assignment warning at sine.hex(912): truncated value with size 12 to match size of target (10)
    2932. 

  2932. Warning (10230): Verilog HDL assignment warning at sine.hex(913): truncated value with size 12 to match size of target (10)
    2933. 

  2933. Warning (10230): Verilog HDL assignment warning at sine.hex(914): truncated value with size 12 to match size of target (10)
    2934. 

  2934. Warning (10230): Verilog HDL assignment warning at sine.hex(915): truncated value with size 12 to match size of target (10)
    2935. 

  2935. Warning (10230): Verilog HDL assignment warning at sine.hex(916): truncated value with size 12 to match size of target (10)
    2936. 

  2936. Warning (10230): Verilog HDL assignment warning at sine.hex(917): truncated value with size 12 to match size of target (10)
    2937. 

  2937. Warning (10230): Verilog HDL assignment warning at sine.hex(918): truncated value with size 12 to match size of target (10)
    2938. 

  2938. Warning (10230): Verilog HDL assignment warning at sine.hex(919): truncated value with size 12 to match size of target (10)
    2939. 

  2939. Warning (10230): Verilog HDL assignment warning at sine.hex(920): truncated value with size 12 to match size of target (10)
    2940. 

  2940. Warning (10230): Verilog HDL assignment warning at sine.hex(921): truncated value with size 12 to match size of target (10)
    2941. 

  2941. Warning (10230): Verilog HDL assignment warning at sine.hex(922): truncated value with size 12 to match size of target (10)
    2942. 

  2942. Warning (10230): Verilog HDL assignment warning at sine.hex(923): truncated value with size 12 to match size of target (10)
    2943. 

  2943. Warning (10230): Verilog HDL assignment warning at sine.hex(924): truncated value with size 12 to match size of target (10)
    2944. 

  2944. Warning (10230): Verilog HDL assignment warning at sine.hex(925): truncated value with size 12 to match size of target (10)
    2945. 

  2945. Warning (10230): Verilog HDL assignment warning at sine.hex(926): truncated value with size 12 to match size of target (10)
    2946. 

  2946. Warning (10230): Verilog HDL assignment warning at sine.hex(927): truncated value with size 12 to match size of target (10)
    2947. 

  2947. Warning (10230): Verilog HDL assignment warning at sine.hex(928): truncated value with size 12 to match size of target (10)
    2948. 

  2948. Warning (10230): Verilog HDL assignment warning at sine.hex(929): truncated value with size 12 to match size of target (10)
    2949. 

  2949. Warning (10230): Verilog HDL assignment warning at sine.hex(930): truncated value with size 12 to match size of target (10)
    2950. 

  2950. Warning (10230): Verilog HDL assignment warning at sine.hex(931): truncated value with size 12 to match size of target (10)
    2951. 

  2951. Warning (10230): Verilog HDL assignment warning at sine.hex(932): truncated value with size 12 to match size of target (10)
    2952. 

  2952. Warning (10230): Verilog HDL assignment warning at sine.hex(933): truncated value with size 12 to match size of target (10)
    2953. 

  2953. Warning (10230): Verilog HDL assignment warning at sine.hex(934): truncated value with size 12 to match size of target (10)
    2954. 

  2954. Warning (10230): Verilog HDL assignment warning at sine.hex(935): truncated value with size 12 to match size of target (10)
    2955. 

  2955. Warning (10230): Verilog HDL assignment warning at sine.hex(936): truncated value with size 12 to match size of target (10)
    2956. 

  2956. Warning (10230): Verilog HDL assignment warning at sine.hex(937): truncated value with size 12 to match size of target (10)
    2957. 

  2957. Warning (10230): Verilog HDL assignment warning at sine.hex(938): truncated value with size 12 to match size of target (10)
    2958. 

  2958. Warning (10230): Verilog HDL assignment warning at sine.hex(939): truncated value with size 12 to match size of target (10)
    2959. 

  2959. Warning (10230): Verilog HDL assignment warning at sine.hex(940): truncated value with size 12 to match size of target (10)
    2960. 

  2960. Warning (10230): Verilog HDL assignment warning at sine.hex(941): truncated value with size 12 to match size of target (10)
    2961. 

  2961. Warning (10230): Verilog HDL assignment warning at sine.hex(942): truncated value with size 12 to match size of target (10)
    2962. 

  2962. Warning (10230): Verilog HDL assignment warning at sine.hex(943): truncated value with size 12 to match size of target (10)
    2963. 

  2963. Warning (10230): Verilog HDL assignment warning at sine.hex(944): truncated value with size 12 to match size of target (10)
    2964. 

  2964. Warning (10230): Verilog HDL assignment warning at sine.hex(945): truncated value with size 12 to match size of target (10)
    2965. 

  2965. Warning (10230): Verilog HDL assignment warning at sine.hex(946): truncated value with size 12 to match size of target (10)
    2966. 

  2966. Warning (10230): Verilog HDL assignment warning at sine.hex(947): truncated value with size 12 to match size of target (10)
    2967. 

  2967. Warning (10230): Verilog HDL assignment warning at sine.hex(948): truncated value with size 12 to match size of target (10)
    2968. 

  2968. Warning (10230): Verilog HDL assignment warning at sine.hex(949): truncated value with size 12 to match size of target (10)
    2969. 

  2969. Warning (10230): Verilog HDL assignment warning at sine.hex(950): truncated value with size 12 to match size of target (10)
    2970. 

  2970. Warning (10230): Verilog HDL assignment warning at sine.hex(951): truncated value with size 12 to match size of target (10)
    2971. 

  2971. Warning (10230): Verilog HDL assignment warning at sine.hex(952): truncated value with size 12 to match size of target (10)
    2972. 

  2972. Warning (10230): Verilog HDL assignment warning at sine.hex(953): truncated value with size 12 to match size of target (10)
    2973. 

  2973. Warning (10230): Verilog HDL assignment warning at sine.hex(954): truncated value with size 12 to match size of target (10)
    2974. 

  2974. Warning (10230): Verilog HDL assignment warning at sine.hex(955): truncated value with size 12 to match size of target (10)
    2975. 

  2975. Warning (10230): Verilog HDL assignment warning at sine.hex(956): truncated value with size 12 to match size of target (10)
    2976. 

  2976. Warning (10230): Verilog HDL assignment warning at sine.hex(957): truncated value with size 12 to match size of target (10)
    2977. 

  2977. Warning (10230): Verilog HDL assignment warning at sine.hex(958): truncated value with size 12 to match size of target (10)
    2978. 

  2978. Warning (10230): Verilog HDL assignment warning at sine.hex(959): truncated value with size 12 to match size of target (10)
    2979. 

  2979. Warning (10230): Verilog HDL assignment warning at sine.hex(960): truncated value with size 12 to match size of target (10)
    2980. 

  2980. Warning (10230): Verilog HDL assignment warning at sine.hex(961): truncated value with size 12 to match size of target (10)
    2981. 

  2981. Warning (10230): Verilog HDL assignment warning at sine.hex(962): truncated value with size 12 to match size of target (10)
    2982. 

  2982. Warning (10230): Verilog HDL assignment warning at sine.hex(963): truncated value with size 12 to match size of target (10)
    2983. 

  2983. Warning (10230): Verilog HDL assignment warning at sine.hex(964): truncated value with size 12 to match size of target (10)
    2984. 

  2984. Warning (10230): Verilog HDL assignment warning at sine.hex(965): truncated value with size 12 to match size of target (10)
    2985. 

  2985. Warning (10230): Verilog HDL assignment warning at sine.hex(966): truncated value with size 12 to match size of target (10)
    2986. 

  2986. Warning (10230): Verilog HDL assignment warning at sine.hex(967): truncated value with size 12 to match size of target (10)
    2987. 

  2987. Warning (10230): Verilog HDL assignment warning at sine.hex(968): truncated value with size 12 to match size of target (10)
    2988. 

  2988. Warning (10230): Verilog HDL assignment warning at sine.hex(969): truncated value with size 12 to match size of target (10)
    2989. 

  2989. Warning (10230): Verilog HDL assignment warning at sine.hex(970): truncated value with size 12 to match size of target (10)
    2990. 

  2990. Warning (10230): Verilog HDL assignment warning at sine.hex(971): truncated value with size 12 to match size of target (10)
    2991. 

  2991. Warning (10230): Verilog HDL assignment warning at sine.hex(972): truncated value with size 12 to match size of target (10)
    2992. 

  2992. Warning (10230): Verilog HDL assignment warning at sine.hex(973): truncated value with size 12 to match size of target (10)
    2993. 

  2993. Warning (10230): Verilog HDL assignment warning at sine.hex(974): truncated value with size 12 to match size of target (10)
    2994. 

  2994. Warning (10230): Verilog HDL assignment warning at sine.hex(975): truncated value with size 12 to match size of target (10)
    2995. 

  2995. Warning (10230): Verilog HDL assignment warning at sine.hex(976): truncated value with size 12 to match size of target (10)
    2996. 

  2996. Warning (10230): Verilog HDL assignment warning at sine.hex(977): truncated value with size 12 to match size of target (10)
    2997. 

  2997. Warning (10230): Verilog HDL assignment warning at sine.hex(978): truncated value with size 12 to match size of target (10)
    2998. 

  2998. Warning (10230): Verilog HDL assignment warning at sine.hex(979): truncated value with size 12 to match size of target (10)
    2999. 

  2999. Warning (10230): Verilog HDL assignment warning at sine.hex(980): truncated value with size 12 to match size of target (10)
    3000. 

  3000. Warning (10230): Verilog HDL assignment warning at sine.hex(981): truncated value with size 12 to match size of target (10)
    3001. 

  3001. Warning (10230): Verilog HDL assignment warning at sine.hex(982): truncated value with size 12 to match size of target (10)
    3002. 

  3002. Warning (10230): Verilog HDL assignment warning at sine.hex(983): truncated value with size 12 to match size of target (10)
    3003. 

  3003. Warning (10230): Verilog HDL assignment warning at sine.hex(984): truncated value with size 12 to match size of target (10)
    3004. 

  3004. Warning (10230): Verilog HDL assignment warning at sine.hex(985): truncated value with size 12 to match size of target (10)
    3005. 

  3005. Warning (10230): Verilog HDL assignment warning at sine.hex(986): truncated value with size 12 to match size of target (10)
    3006. 

  3006. Warning (10230): Verilog HDL assignment warning at sine.hex(987): truncated value with size 12 to match size of target (10)
    3007. 

  3007. Warning (10230): Verilog HDL assignment warning at sine.hex(988): truncated value with size 12 to match size of target (10)
    3008. 

  3008. Warning (10230): Verilog HDL assignment warning at sine.hex(989): truncated value with size 12 to match size of target (10)
    3009. 

  3009. Warning (10230): Verilog HDL assignment warning at sine.hex(990): truncated value with size 12 to match size of target (10)
    3010. 

  3010. Warning (10230): Verilog HDL assignment warning at sine.hex(991): truncated value with size 12 to match size of target (10)
    3011. 

  3011. Warning (10230): Verilog HDL assignment warning at sine.hex(992): truncated value with size 12 to match size of target (10)
    3012. 

  3012. Warning (10230): Verilog HDL assignment warning at sine.hex(993): truncated value with size 12 to match size of target (10)
    3013. 

  3013. Warning (10230): Verilog HDL assignment warning at sine.hex(994): truncated value with size 12 to match size of target (10)
    3014. 

  3014. Warning (10230): Verilog HDL assignment warning at sine.hex(995): truncated value with size 12 to match size of target (10)
    3015. 

  3015. Warning (10230): Verilog HDL assignment warning at sine.hex(996): truncated value with size 12 to match size of target (10)
    3016. 

  3016. Warning (10230): Verilog HDL assignment warning at sine.hex(997): truncated value with size 12 to match size of target (10)
    3017. 

  3017. Warning (10230): Verilog HDL assignment warning at sine.hex(998): truncated value with size 12 to match size of target (10)
    3018. 

  3018. Warning (10230): Verilog HDL assignment warning at sine.hex(999): truncated value with size 12 to match size of target (10)
    3019. 

  3019. Warning (10230): Verilog HDL assignment warning at sine.hex(1000): truncated value with size 12 to match size of target (10)
    3020. 

  3020. Warning (10230): Verilog HDL assignment warning at sine.hex(1001): truncated value with size 12 to match size of target (10)
    3021. 

  3021. Warning (10230): Verilog HDL assignment warning at sine.hex(1002): truncated value with size 12 to match size of target (10)
    3022. 

  3022. Warning (10230): Verilog HDL assignment warning at sine.hex(1003): truncated value with size 12 to match size of target (10)
    3023. 

  3023. Warning (10230): Verilog HDL assignment warning at sine.hex(1004): truncated value with size 12 to match size of target (10)
    3024. 

  3024. Warning (10230): Verilog HDL assignment warning at sine.hex(1005): truncated value with size 12 to match size of target (10)
    3025. 

  3025. Warning (10230): Verilog HDL assignment warning at sine.hex(1006): truncated value with size 12 to match size of target (10)
    3026. 

  3026. Warning (10230): Verilog HDL assignment warning at sine.hex(1007): truncated value with size 12 to match size of target (10)
    3027. 

  3027. Warning (10230): Verilog HDL assignment warning at sine.hex(1008): truncated value with size 12 to match size of target (10)
    3028. 

  3028. Warning (10230): Verilog HDL assignment warning at sine.hex(1009): truncated value with size 12 to match size of target (10)
    3029. 

  3029. Warning (10230): Verilog HDL assignment warning at sine.hex(1010): truncated value with size 12 to match size of target (10)
    3030. 

  3030. Warning (10230): Verilog HDL assignment warning at sine.hex(1011): truncated value with size 12 to match size of target (10)
    3031. 

  3031. Warning (10230): Verilog HDL assignment warning at sine.hex(1012): truncated value with size 12 to match size of target (10)
    3032. 

  3032. Warning (10230): Verilog HDL assignment warning at sine.hex(1013): truncated value with size 12 to match size of target (10)
    3033. 

  3033. Warning (10230): Verilog HDL assignment warning at sine.hex(1014): truncated value with size 12 to match size of target (10)
    3034. 

  3034. Warning (10230): Verilog HDL assignment warning at sine.hex(1015): truncated value with size 12 to match size of target (10)
    3035. 

  3035. Warning (10230): Verilog HDL assignment warning at sine.hex(1016): truncated value with size 12 to match size of target (10)
    3036. 

  3036. Warning (10230): Verilog HDL assignment warning at sine.hex(1017): truncated value with size 12 to match size of target (10)
    3037. 

  3037. Warning (10230): Verilog HDL assignment warning at sine.hex(1018): truncated value with size 12 to match size of target (10)
    3038. 

  3038. Warning (10230): Verilog HDL assignment warning at sine.hex(1019): truncated value with size 12 to match size of target (10)
    3039. 

  3039. Warning (10230): Verilog HDL assignment warning at sine.hex(1020): truncated value with size 12 to match size of target (10)
    3040. 

  3040. Warning (10230): Verilog HDL assignment warning at sine.hex(1021): truncated value with size 12 to match size of target (10)
    3041. 

  3041. Warning (10230): Verilog HDL assignment warning at sine.hex(1022): truncated value with size 12 to match size of target (10)
    3042. 

  3042. Warning (10230): Verilog HDL assignment warning at sine.hex(1023): truncated value with size 12 to match size of target (10)
    3043. 

  3043. Warning (10230): Verilog HDL assignment warning at sine.hex(1024): truncated value with size 12 to match size of target (10)
    3044. 

  3044. Warning (10230): Verilog HDL assignment warning at analog_ip.v(678): truncated value with size 20 to match size of target (10)
    3045. 

  3045. Warning (10230): Verilog HDL assignment warning at analog_ip.v(686): truncated value with size 20 to match size of target (10)
    3046. 

  3046. Warning (10230): Verilog HDL assignment warning at analog_ip.v(691): truncated value with size 20 to match size of target (10)
    3047. 

  3047. Warning (10230): Verilog HDL assignment warning at analog_ip.v(699): truncated value with size 20 to match size of target (10)
    3048. 

  3048. Warning (10240): Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable "mult", which holds its previous value in one or more paths through the always construct
    3049. 

  3049. Warning (10240): Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable "step", which holds its previous value in one or more paths through the always construct
    3050. 

  3050. Warning (10030): Net "sine_rom.data_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
    3051. 

  3051. Warning (10030): Net "sine_rom.waddr_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
    3052. 

  3052. Warning (10030): Net "sine_rom.we_a" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'
    3053. 

  3053. Info (12128): Elaborating entity "alta_dac" for hierarchy "analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst"
    3054. 

  3054. Info (12128): Elaborating entity "baud_detect" for hierarchy "analog_ip:macro_inst|baud_detect:u_baud_detect"
    3055. 

  3055. Warning (10230): Verilog HDL assignment warning at baud_detect.v(33): truncated value with size 32 to match size of target (24)
    3056. 

  3056. Warning (10230): Verilog HDL assignment warning at baud_detect.v(35): truncated value with size 32 to match size of target (24)
    3057. 

  3057. Warning (10230): Verilog HDL assignment warning at baud_detect.v(40): truncated value with size 32 to match size of target (4)
    3058. 

  3058. Warning (10240): Verilog HDL Always Construct warning at baud_detect.v(28): inferring latch(es) for variable "min_time", which holds its previous value in one or more paths through the always construct
    3059. 

  3059. Warning (10230): Verilog HDL assignment warning at baud_detect.v(50): truncated value with size 32 to match size of target (24)
    3060. 

  3060. Info (12128): Elaborating entity "altsyncram" for hierarchy "analog_ip:macro_inst|altsyncram:u_dual_port_ram"
    3061. 

  3061. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|altsyncram:u_dual_port_ram"
    3062. 

  3062. Info (12133): Instantiated megafunction "analog_ip:macro_inst|altsyncram:u_dual_port_ram" with the following parameter:
    3063. 

  3063.     Info (12134): Parameter "byte_size" = "8"
    3064. 

  3064.     Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
    3065. 

  3065.     Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
    3066. 

  3066.     Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    3067. 

  3067.     Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
    3068. 

  3068.     Info (12134): Parameter "operation_mode" = "BIDIR_DUAL_PORT"
    3069. 

  3069.     Info (12134): Parameter "numwords_a" = "1024"
    3070. 

  3070.     Info (12134): Parameter "widthad_a" = "10"
    3071. 

  3071.     Info (12134): Parameter "width_a" = "16"
    3072. 

  3072.     Info (12134): Parameter "width_byteena_a" = "2"
    3073. 

  3073.     Info (12134): Parameter "outdata_aclr_a" = "NONE"
    3074. 

  3074.     Info (12134): Parameter "outdata_reg_a" = "UNREGISTERED"
    3075. 

  3075.     Info (12134): Parameter "numwords_b" = "1024"
    3076. 

  3076.     Info (12134): Parameter "widthad_b" = "10"
    3077. 

  3077.     Info (12134): Parameter "width_b" = "16"
    3078. 

  3078.     Info (12134): Parameter "width_byteena_b" = "2"
    3079. 

  3079.     Info (12134): Parameter "outdata_aclr_b" = "NONE"
    3080. 

  3080.     Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
    3081. 

  3081.     Info (12134): Parameter "ram_block_type" = "M9K"
    3082. 

  3082.     Info (12134): Parameter "read_during_write_mode_port_a" = "NEW_DATA_NO_NBE_READ"
    3083. 

  3083. Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sgu1.tdf
    3084. 

  3084.     Info (12023): Found entity 1: altsyncram_sgu1
    3085. 

  3085. Info (12128): Elaborating entity "altsyncram_sgu1" for hierarchy "analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated"
    3086. 

  3086. Info (12128): Elaborating entity "apb2ram" for hierarchy "analog_ip:macro_inst|apb2ram:u_apb2ram"
    3087. 

  3087. Warning (10230): Verilog HDL assignment warning at apb2ram.v(26): truncated value with size 15 to match size of target (10)
    3088. 

  3088. Info (12128): Elaborating entity "alta_rv32" for hierarchy "alta_rv32:rv32"
    3089. 

  3089. Warning (10034): Output port "gpio0_io_out_data" at alta_sim.v(3739) has no driver
    3090. 

  3090. Warning (10034): Output port "gpio0_io_out_en" at alta_sim.v(3740) has no driver
    3091. 

  3091. Warning (10034): Output port "gpio1_io_out_data" at alta_sim.v(3742) has no driver
    3092. 

  3092. Warning (10034): Output port "gpio1_io_out_en" at alta_sim.v(3743) has no driver
    3093. 

  3093. Warning (10034): Output port "gpio2_io_out_data" at alta_sim.v(3753) has no driver
    3094. 

  3094. Warning (10034): Output port "gpio2_io_out_en" at alta_sim.v(3754) has no driver
    3095. 

  3095. Warning (10034): Output port "gpio3_io_out_data" at alta_sim.v(3756) has no driver
    3096. 

  3096. Warning (10034): Output port "gpio3_io_out_en" at alta_sim.v(3757) has no driver
    3097. 

  3097. Warning (10034): Output port "gpio4_io_out_data" at alta_sim.v(3759) has no driver
    3098. 

  3098. Warning (10034): Output port "gpio4_io_out_en" at alta_sim.v(3760) has no driver
    3099. 

  3099. Warning (10034): Output port "gpio5_io_out_data" at alta_sim.v(3762) has no driver
    3100. 

  3100. Warning (10034): Output port "gpio5_io_out_en" at alta_sim.v(3763) has no driver
    3101. 

  3101. Warning (10034): Output port "gpio6_io_out_data" at alta_sim.v(3765) has no driver
    3102. 

  3102. Warning (10034): Output port "gpio6_io_out_en" at alta_sim.v(3766) has no driver
    3103. 

  3103. Warning (10034): Output port "gpio7_io_out_data" at alta_sim.v(3768) has no driver
    3104. 

  3104. Warning (10034): Output port "gpio7_io_out_en" at alta_sim.v(3769) has no driver
    3105. 

  3105. Warning (10034): Output port "gpio8_io_out_data" at alta_sim.v(3771) has no driver
    3106. 

  3106. Warning (10034): Output port "gpio8_io_out_en" at alta_sim.v(3772) has no driver
    3107. 

  3107. Warning (10034): Output port "gpio9_io_out_data" at alta_sim.v(3774) has no driver
    3108. 

  3108. Warning (10034): Output port "gpio9_io_out_en" at alta_sim.v(3775) has no driver
    3109. 

  3109. Warning (10034): Output port "swj_JTAGSTATE" at alta_sim.v(3780) has no driver
    3110. 

  3110. Warning (10034): Output port "swj_JTAGIR" at alta_sim.v(3781) has no driver
    3111. 

  3111. Warning (10034): Output port "dmactive" at alta_sim.v(3778) has no driver
    3112. 

  3112. Warning (10034): Output port "swj_JTAGNSW" at alta_sim.v(3779) has no driver
    3113. 

  3113. Info (12206): 4 design partitions require synthesis
    3114. 

  3114.     Info (12210): Partition "Top" requires synthesis because its netlist type is Source File
    3115. 

  3115.     Info (12210): Partition "macro_inst_apb_adc0_inst_adc_inst" requires synthesis because its netlist type is Source File
    3116. 

  3116.     Info (12210): Partition "macro_inst_apb_dac0_inst_dac_inst" requires synthesis because its netlist type is Source File
    3117. 

  3117.     Info (12210): Partition "rv32" requires synthesis because its netlist type is Source File
    3118. 

  3118. Info (12209): No design partitions will skip synthesis in the current incremental compilation
    3119. 

  3119. Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
    3120. 

  3120. Info (281037): Using 4 processors to synthesize 4 partitions in parallel
    3121. 

  3121. Info: *******************************************************************
    3122. 

  3122. Info: Running Quartus II 64-Bit Analysis & Synthesis
    3123. 

  3123.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    3124. 

  3124.     Info: Processing started: Sat May 09 14:18:37 2026
    3125. 

  3125. Info: Command: quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board
    3126. 

  3126. Info (278001): Inferred 3 megafunctions from design logic
    3127. 

  3127.     Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult0"
    3128. 

  3128.     Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult2"
    3129. 

  3129.     Info (278003): Inferred multiplier megafunction ("lpm_mult") from the following logic: "analog_ip:macro_inst|apb_dac:apb_dac0_inst|Mult3"
    3130. 

  3130. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0"
    3131. 

  3131. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0" with the following parameter:
    3132. 

  3132.     Info (12134): Parameter "LPM_WIDTHA" = "10"
    3133. 

  3133.     Info (12134): Parameter "LPM_WIDTHB" = "10"
    3134. 

  3134.     Info (12134): Parameter "LPM_WIDTHP" = "20"
    3135. 

  3135.     Info (12134): Parameter "LPM_WIDTHR" = "20"
    3136. 

  3136.     Info (12134): Parameter "LPM_WIDTHS" = "1"
    3137. 

  3137.     Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    3138. 

  3138.     Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    3139. 

  3139.     Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    3140. 

  3140.     Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
    3141. 

  3141. Info (12021): Found 1 design units, including 1 entities, in source file db/mult_oct.tdf
    3142. 

  3142.     Info (12023): Found entity 1: mult_oct
    3143. 

  3143. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2"
    3144. 

  3144. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2" with the following parameter:
    3145. 

  3145.     Info (12134): Parameter "LPM_WIDTHA" = "10"
    3146. 

  3146.     Info (12134): Parameter "LPM_WIDTHB" = "9"
    3147. 

  3147.     Info (12134): Parameter "LPM_WIDTHP" = "19"
    3148. 

  3148.     Info (12134): Parameter "LPM_WIDTHR" = "19"
    3149. 

  3149.     Info (12134): Parameter "LPM_WIDTHS" = "1"
    3150. 

  3150.     Info (12134): Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    3151. 

  3151.     Info (12134): Parameter "INPUT_A_IS_CONSTANT" = "NO"
    3152. 

  3152.     Info (12134): Parameter "INPUT_B_IS_CONSTANT" = "NO"
    3153. 

  3153.     Info (12134): Parameter "MAXIMIZE_SPEED" = "6"
    3154. 

  3154. Info (12021): Found 1 design units, including 1 entities, in source file db/mult_pbt.tdf
    3155. 

  3155.     Info (12023): Found entity 1: mult_pbt
    3156. 

  3156. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top
    3157. 

  3157. Info (270001): Converted 3 DSP block slices
    3158. 

  3158.     Info (270002): Used 3 DSP blocks before DSP block balancing
    3159. 

  3159.         Info (270003): Used 3 DSP block slices in "Simple Multiplier (18-bit)" mode implemented in approximately 3 DSP blocks
    3160. 

  3160.     Info (270013): Converted the following 3 DSP block slices to logic elements
    3161. 

  3161.         Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_out2"
    3162. 

  3162.             Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_out2"
    3163. 

  3163.             Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|mac_mult1"
    3164. 

  3164.         Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_out2"
    3165. 

  3165.             Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_out2"
    3166. 

  3166.             Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|mac_mult1"
    3167. 

  3167.         Info (270006): DSP block slice in "Simple Multiplier (18-bit)" mode with output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_out2"
    3168. 

  3168.             Info (270004): DSP block output node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_out2"
    3169. 

  3169.             Info (270005): DSP block multiplier node "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult0|mult_oct:auto_generated|mac_mult1"
    3170. 

  3170.     Info (270002): Used 0 DSP blocks after DSP block balancing
    3171. 

  3171. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
    3172. 

  3172. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
    3173. 

  3173. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1"
    3174. 

  3174. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_mult:mac_mult1" with the following parameter:
    3175. 

  3175.     Info (12134): Parameter "MULT_REPRESENTATION_A" = "UNSIGNED"
    3176. 

  3176.     Info (12134): Parameter "MULT_REPRESENTATION_B" = "UNSIGNED"
    3177. 

  3177.     Info (12134): Parameter "MULT_PIPELINE" = "0"
    3178. 

  3178.     Info (12134): Parameter "MULT_CLOCK" = "NONE"
    3179. 

  3179.     Info (12134): Parameter "MULT_CLEAR" = "NONE"
    3180. 

  3180.     Info (12134): Parameter "MULT_INPUT_A_IS_CONSTANT" = "NO"
    3181. 

  3181.     Info (12134): Parameter "MULT_INPUT_B_IS_CONSTANT" = "NO"
    3182. 

  3182.     Info (12134): Parameter "dataa_width" = "10"
    3183. 

  3183.     Info (12134): Parameter "datab_width" = "10"
    3184. 

  3184.     Info (12134): Parameter "output_width" = "20"
    3185. 

  3185.     Info (12134): Parameter "dataa_clock" = "NONE"
    3186. 

  3186.     Info (12134): Parameter "datab_clock" = "NONE"
    3187. 

  3187.     Info (12134): Parameter "signa_clock" = "NONE"
    3188. 

  3188.     Info (12134): Parameter "signb_clock" = "NONE"
    3189. 

  3189.     Info (12134): Parameter "output_clock" = "NONE"
    3190. 

  3190.     Info (12134): Parameter "dataa_clear" = "NONE"
    3191. 

  3191.     Info (12134): Parameter "datab_clear" = "NONE"
    3192. 

  3192.     Info (12134): Parameter "signa_clear" = "NONE"
    3193. 

  3193.     Info (12134): Parameter "signb_clear" = "NONE"
    3194. 

  3194.     Info (12134): Parameter "output_clear" = "NONE"
    3195. 

  3195. Info (12021): Found 1 design units, including 1 entities, in source file db/mac_mult_iug1.tdf
    3196. 

  3196.     Info (12023): Found entity 1: mac_mult_iug1
    3197. 

  3197. Info (12021): Found 1 design units, including 1 entities, in source file db/mult_aql.tdf
    3198. 

  3198.     Info (12023): Found entity 1: mult_aql
    3199. 

  3199. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2"
    3200. 

  3200. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult3|mult_oct:auto_generated|alt_mac_out:mac_out2" with the following parameter:
    3201. 

  3201.     Info (12134): Parameter "OPERATION_MODE" = "OUTPUT_ONLY"
    3202. 

  3202.     Info (12134): Parameter "dataa_width" = "20"
    3203. 

  3203.     Info (12134): Parameter "datab_width" = "0"
    3204. 

  3204.     Info (12134): Parameter "datac_width" = "0"
    3205. 

  3205.     Info (12134): Parameter "datad_width" = "0"
    3206. 

  3206.     Info (12134): Parameter "output_width" = "20"
    3207. 

  3207.     Info (12134): Parameter "signa_clock" = "NONE"
    3208. 

  3208.     Info (12134): Parameter "signb_clock" = "NONE"
    3209. 

  3209.     Info (12134): Parameter "addnsub0_clock" = "NONE"
    3210. 

  3210.     Info (12134): Parameter "addnsub1_clock" = "NONE"
    3211. 

  3211.     Info (12134): Parameter "zeroacc_clock" = "NONE"
    3212. 

  3212.     Info (12134): Parameter "first_adder0_clock" = "NONE"
    3213. 

  3213.     Info (12134): Parameter "first_adder1_clock" = "NONE"
    3214. 

  3214.     Info (12134): Parameter "output_clock" = "NONE"
    3215. 

  3215.     Info (12134): Parameter "signa_clear" = "NONE"
    3216. 

  3216.     Info (12134): Parameter "signb_clear" = "NONE"
    3217. 

  3217.     Info (12134): Parameter "addnsub0_clear" = "NONE"
    3218. 

  3218.     Info (12134): Parameter "addnsub1_clear" = "NONE"
    3219. 

  3219.     Info (12134): Parameter "zeroacc_clear" = "NONE"
    3220. 

  3220.     Info (12134): Parameter "first_adder0_clear" = "NONE"
    3221. 

  3221.     Info (12134): Parameter "first_adder1_clear" = "NONE"
    3222. 

  3222.     Info (12134): Parameter "output_clear" = "NONE"
    3223. 

  3223.     Info (12134): Parameter "signa_pipeline_clock" = "NONE"
    3224. 

  3224.     Info (12134): Parameter "signb_pipeline_clock" = "NONE"
    3225. 

  3225.     Info (12134): Parameter "addnsub0_pipeline_clock" = "NONE"
    3226. 

  3226.     Info (12134): Parameter "addnsub1_pipeline_clock" = "NONE"
    3227. 

  3227.     Info (12134): Parameter "zeroacc_pipeline_clock" = "NONE"
    3228. 

  3228.     Info (12134): Parameter "signa_pipeline_clear" = "NONE"
    3229. 

  3229.     Info (12134): Parameter "signb_pipeline_clear" = "NONE"
    3230. 

  3230.     Info (12134): Parameter "addnsub0_pipeline_clear" = "NONE"
    3231. 

  3231.     Info (12134): Parameter "addnsub1_pipeline_clear" = "NONE"
    3232. 

  3232.     Info (12134): Parameter "zeroacc_pipeline_clear" = "NONE"
    3233. 

  3233. Info (12021): Found 1 design units, including 1 entities, in source file db/mac_out_lr82.tdf
    3234. 

  3234.     Info (12023): Found entity 1: mac_out_lr82
    3235. 

  3235. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1"
    3236. 

  3236. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_mult:mac_mult1" with the following parameter:
    3237. 

  3237.     Info (12134): Parameter "MULT_REPRESENTATION_A" = "UNSIGNED"
    3238. 

  3238.     Info (12134): Parameter "MULT_REPRESENTATION_B" = "UNSIGNED"
    3239. 

  3239.     Info (12134): Parameter "MULT_PIPELINE" = "0"
    3240. 

  3240.     Info (12134): Parameter "MULT_CLOCK" = "NONE"
    3241. 

  3241.     Info (12134): Parameter "MULT_CLEAR" = "NONE"
    3242. 

  3242.     Info (12134): Parameter "MULT_INPUT_A_IS_CONSTANT" = "NO"
    3243. 

  3243.     Info (12134): Parameter "MULT_INPUT_B_IS_CONSTANT" = "NO"
    3244. 

  3244.     Info (12134): Parameter "dataa_width" = "10"
    3245. 

  3245.     Info (12134): Parameter "datab_width" = "9"
    3246. 

  3246.     Info (12134): Parameter "output_width" = "19"
    3247. 

  3247.     Info (12134): Parameter "dataa_clock" = "NONE"
    3248. 

  3248.     Info (12134): Parameter "datab_clock" = "NONE"
    3249. 

  3249.     Info (12134): Parameter "signa_clock" = "NONE"
    3250. 

  3250.     Info (12134): Parameter "signb_clock" = "NONE"
    3251. 

  3251.     Info (12134): Parameter "output_clock" = "NONE"
    3252. 

  3252.     Info (12134): Parameter "dataa_clear" = "NONE"
    3253. 

  3253.     Info (12134): Parameter "datab_clear" = "NONE"
    3254. 

  3254.     Info (12134): Parameter "signa_clear" = "NONE"
    3255. 

  3255.     Info (12134): Parameter "signb_clear" = "NONE"
    3256. 

  3256.     Info (12134): Parameter "output_clear" = "NONE"
    3257. 

  3257. Info (12021): Found 1 design units, including 1 entities, in source file db/mac_mult_jtg1.tdf
    3258. 

  3258.     Info (12023): Found entity 1: mac_mult_jtg1
    3259. 

  3259. Info (12021): Found 1 design units, including 1 entities, in source file db/mult_bpl.tdf
    3260. 

  3260.     Info (12023): Found entity 1: mult_bpl
    3261. 

  3261. Info (12130): Elaborated megafunction instantiation "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2"
    3262. 

  3262. Info (12133): Instantiated megafunction "analog_ip:macro_inst|apb_dac:apb_dac0_inst|lpm_mult:Mult2|mult_pbt:auto_generated|alt_mac_out:mac_out2" with the following parameter:
    3263. 

  3263.     Info (12134): Parameter "OPERATION_MODE" = "OUTPUT_ONLY"
    3264. 

  3264.     Info (12134): Parameter "dataa_width" = "19"
    3265. 

  3265.     Info (12134): Parameter "datab_width" = "0"
    3266. 

  3266.     Info (12134): Parameter "datac_width" = "0"
    3267. 

  3267.     Info (12134): Parameter "datad_width" = "0"
    3268. 

  3268.     Info (12134): Parameter "output_width" = "19"
    3269. 

  3269.     Info (12134): Parameter "signa_clock" = "NONE"
    3270. 

  3270.     Info (12134): Parameter "signb_clock" = "NONE"
    3271. 

  3271.     Info (12134): Parameter "addnsub0_clock" = "NONE"
    3272. 

  3272.     Info (12134): Parameter "addnsub1_clock" = "NONE"
    3273. 

  3273.     Info (12134): Parameter "zeroacc_clock" = "NONE"
    3274. 

  3274.     Info (12134): Parameter "first_adder0_clock" = "NONE"
    3275. 

  3275.     Info (12134): Parameter "first_adder1_clock" = "NONE"
    3276. 

  3276.     Info (12134): Parameter "output_clock" = "NONE"
    3277. 

  3277.     Info (12134): Parameter "signa_clear" = "NONE"
    3278. 

  3278.     Info (12134): Parameter "signb_clear" = "NONE"
    3279. 

  3279.     Info (12134): Parameter "addnsub0_clear" = "NONE"
    3280. 

  3280.     Info (12134): Parameter "addnsub1_clear" = "NONE"
    3281. 

  3281.     Info (12134): Parameter "zeroacc_clear" = "NONE"
    3282. 

  3282.     Info (12134): Parameter "first_adder0_clear" = "NONE"
    3283. 

  3283.     Info (12134): Parameter "first_adder1_clear" = "NONE"
    3284. 

  3284.     Info (12134): Parameter "output_clear" = "NONE"
    3285. 

  3285.     Info (12134): Parameter "signa_pipeline_clock" = "NONE"
    3286. 

  3286.     Info (12134): Parameter "signb_pipeline_clock" = "NONE"
    3287. 

  3287.     Info (12134): Parameter "addnsub0_pipeline_clock" = "NONE"
    3288. 

  3288.     Info (12134): Parameter "addnsub1_pipeline_clock" = "NONE"
    3289. 

  3289.     Info (12134): Parameter "zeroacc_pipeline_clock" = "NONE"
    3290. 

  3290.     Info (12134): Parameter "signa_pipeline_clear" = "NONE"
    3291. 

  3291.     Info (12134): Parameter "signb_pipeline_clear" = "NONE"
    3292. 

  3292.     Info (12134): Parameter "addnsub0_pipeline_clear" = "NONE"
    3293. 

  3293.     Info (12134): Parameter "addnsub1_pipeline_clear" = "NONE"
    3294. 

  3294.     Info (12134): Parameter "zeroacc_pipeline_clear" = "NONE"
    3295. 

  3295. Info (12021): Found 1 design units, including 1 entities, in source file db/mac_out_5s82.tdf
    3296. 

  3296.     Info (12023): Found entity 1: mac_out_5s82
    3297. 

  3297. Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition
    3298. 

  3298. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    3299. 

  3299. Info (13014): Ignored 585 buffer(s)
    3300. 

  3300.     Info (13016): Ignored 30 CARRY_SUM buffer(s)
    3301. 

  3301.     Info (13019): Ignored 555 SOFT buffer(s)
    3302. 

  3302. Warning (13039): The following bidir pins have no drivers
    3303. 

  3303.     Warning (13040): Bidir "BAUD_RATE" has no driver
    3304. 

  3304.     Warning (13040): Bidir "TEST_SINGLE" has no driver
    3305. 

  3305.     Warning (13040): Bidir "UART1_RX" has no driver
    3306. 

  3306.     Warning (13040): Bidir "so_io1" has no driver
    3307. 

  3307. Info (13000): Registers with preset signals will power-up high
    3308. 

  3308. Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
    3309. 

  3309. Warning (13008): TRI or OPNDRN buffers permanently disabled
    3310. 

  3310.     Warning (13010): Node "BAUD_RATE~synth"
    3311. 

  3311.     Warning (13010): Node "TEST_SINGLE~synth"
    3312. 

  3312.     Warning (13010): Node "UART1_RX~synth"
    3313. 

  3313.     Warning (13010): Node "so_io1~synth"
    3314. 

  3314. Info (286031): Timing-Driven Synthesis is running on partition "Top"
    3315. 

  3315. Info (17049): 3 registers lost all their fanouts during netlist optimizations.
    3316. 

  3316. Info (17016): Found the following redundant logic cells in design
    3317. 

  3317.     Info (17048): Logic cell "sys_ctrl_stop"
    3318. 

  3318.     Info (17048): Logic cell "gpio0_io_in[0]"
    3319. 

  3319.     Info (17048): Logic cell "gpio4_io_in[1]"
    3320. 

  3320.     Info (17048): Logic cell "gpio4_io_in[2]"
    3321. 

  3321.     Info (17048): Logic cell "gpio6_io_in[1]"
    3322. 

  3322.     Info (17048): Logic cell "gpio6_io_in[3]"
    3323. 

  3323.     Info (17048): Logic cell "gpio4_io_out_data[6]"
    3324. 

  3324.     Info (17048): Logic cell "gpio4_io_out_en[6]"
    3325. 

  3325.     Info (17048): Logic cell "gpio4_io_out_data[5]"
    3326. 

  3326.     Info (17048): Logic cell "gpio4_io_out_en[5]"
    3327. 

  3327.     Info (17048): Logic cell "gpio7_io_out_data[6]"
    3328. 

  3328.     Info (17048): Logic cell "gpio7_io_out_en[6]"
    3329. 

  3329.     Info (17048): Logic cell "sys_resetn"
    3330. 

  3330.     Info (17048): Logic cell "sys_ctrl_clkSource[0]"
    3331. 

  3331.     Info (17048): Logic cell "sys_ctrl_clkSource[1]"
    3332. 

  3332.     Info (17048): Logic cell "gpio4_io_out_data[1]"
    3333. 

  3333.     Info (17048): Logic cell "gpio4_io_out_en[1]"
    3334. 

  3334.     Info (17048): Logic cell "gpio4_io_out_data[2]"
    3335. 

  3335.     Info (17048): Logic cell "gpio4_io_out_en[2]"
    3336. 

  3336.     Info (17048): Logic cell "gpio0_io_out_data[0]"
    3337. 

  3337.     Info (17048): Logic cell "gpio0_io_out_en[0]"
    3338. 

  3338.     Info (17048): Logic cell "gpio8_io_out_data[0]"
    3339. 

  3339.     Info (17048): Logic cell "gpio8_io_out_en[0]"
    3340. 

  3340.     Info (17048): Logic cell "PLL_ENABLE"
    3341. 

  3341. Warning (15899): PLL "altpll:pll_inst|altpll_6o32:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
    3342. 

  3342. Info (128000): Starting physical synthesis optimizations for speed
    3343. 

  3343. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    3344. 

  3344. Info (332111): Found 4 clocks
    3345. 

  3345.     Info (332111):   Period   Clock Name
    3346. 

  3346.     Info (332111): ======== ============
    3347. 

  3347.     Info (332111):  125.000      PIN_HSE
    3348. 

  3348.     Info (332111):  100.000      PIN_HSI
    3349. 

  3349.     Info (332111):  125.000    PLL_CLKIN
    3350. 

  3350.     Info (332111):    9.615 pll_inst|auto_generated|pll1|clk[0]
    3351. 

  3351. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    3352. 

  3352. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    3353. 

  3353. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    3354. 

  3354. Info (21057): Implemented 1764 device resources after synthesis - the final resource count might be different
    3355. 

  3355.     Info (21058): Implemented 4 input pins
    3356. 

  3356.     Info (21059): Implemented 3 output pins
    3357. 

  3357.     Info (21060): Implemented 8 bidirectional pins
    3358. 

  3358.     Info (21061): Implemented 1728 logic cells
    3359. 

  3359.     Info (21064): Implemented 16 RAM segments
    3360. 

  3360.     Info (21065): Implemented 1 PLLs
    3361. 

  3361.     Info (21071): Implemented 3 partitions
    3362. 

  3362. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 11 warnings
    3363. 

  3363.     Info: Peak virtual memory: 4703 megabytes
    3364. 

  3364.     Info: Processing ended: Sat May 09 14:18:46 2026
    3365. 

  3365.     Info: Elapsed time: 00:00:09
    3366. 

  3366.     Info: Total CPU time (on all processors): 00:00:15
    3367. 

  3367. Info: *******************************************************************
    3368. 

  3368. Info: Running Quartus II 64-Bit Analysis & Synthesis
    3369. 

  3369.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    3370. 

  3370.     Info: Processing started: Sat May 09 14:18:37 2026
    3371. 

  3371. Info: Command: quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board
    3372. 

  3372. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
    3373. 

  3373. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
    3374. 

  3374. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst
    3375. 

  3375. Info (281019): Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_adc0_inst_adc_inst
    3376. 

  3376. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    3377. 

  3377. Info (128000): Starting physical synthesis optimizations for speed
    3378. 

  3378. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    3379. 

  3379. Info (332111): Found 3 clocks
    3380. 

  3380.     Info (332111):   Period   Clock Name
    3381. 

  3381.     Info (332111): ======== ============
    3382. 

  3382.     Info (332111):  100.000      PIN_HSI
    3383. 

  3383.     Info (332111):  125.000    PLL_CLKIN
    3384. 

  3384.     Info (332111):    9.615 pll_inst|auto_generated|pll1|clk[0]
    3385. 

  3385. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    3386. 

  3386. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    3387. 

  3387. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    3388. 

  3388. Info (21057): Implemented 21 device resources after synthesis - the final resource count might be different
    3389. 

  3389.     Info (21058): Implemented 8 input pins
    3390. 

  3390.     Info (21059): Implemented 13 output pins
    3391. 

  3391. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
    3392. 

  3392.     Info: Peak virtual memory: 4684 megabytes
    3393. 

  3393.     Info: Processing ended: Sat May 09 14:18:39 2026
    3394. 

  3394.     Info: Elapsed time: 00:00:02
    3395. 

  3395.     Info: Total CPU time (on all processors): 00:00:08
    3396. 

  3396. Info: *******************************************************************
    3397. 

  3397. Info: Running Quartus II 64-Bit Analysis & Synthesis
    3398. 

  3398.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    3399. 

  3399.     Info: Processing started: Sat May 09 14:18:37 2026
    3400. 

  3400. Info: Command: quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board
    3401. 

  3401. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
    3402. 

  3402. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
    3403. 

  3403. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst|apb_dac:apb_dac0_inst|alta_dac:dac_inst
    3404. 

  3404. Info (281019): Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_dac0_inst_dac_inst
    3405. 

  3405. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    3406. 

  3406. Info (128000): Starting physical synthesis optimizations for speed
    3407. 

  3407. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    3408. 

  3408. Info (332111): Found 3 clocks
    3409. 

  3409.     Info (332111):   Period   Clock Name
    3410. 

  3410.     Info (332111): ======== ============
    3411. 

  3411.     Info (332111):  100.000      PIN_HSI
    3412. 

  3412.     Info (332111):  125.000    PLL_CLKIN
    3413. 

  3413.     Info (332111):    9.615 pll_inst|auto_generated|pll1|clk[0]
    3414. 

  3414. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    3415. 

  3415. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    3416. 

  3416. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    3417. 

  3417. Info (21057): Implemented 14 device resources after synthesis - the final resource count might be different
    3418. 

  3418.     Info (21058): Implemented 13 input pins
    3419. 

  3419.     Info (21059): Implemented 1 output pins
    3420. 

  3420. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings
    3421. 

  3421.     Info: Peak virtual memory: 4684 megabytes
    3422. 

  3422.     Info: Processing ended: Sat May 09 14:18:39 2026
    3423. 

  3423.     Info: Elapsed time: 00:00:02
    3424. 

  3424.     Info: Total CPU time (on all processors): 00:00:08
    3425. 

  3425. Info: *******************************************************************
    3426. 

  3426. Info: Running Quartus II 64-Bit Analysis & Synthesis
    3427. 

  3427.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    3428. 

  3428.     Info: Processing started: Sat May 09 14:18:37 2026
    3429. 

  3429. Info: Command: quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board
    3430. 

  3430. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32
    3431. 

  3431. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
    3432. 

  3432. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
    3433. 

  3433. Info (281019): Starting Logic Optimization and Technology Mapping for Partition rv32
    3434. 

  3434. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    3435. 

  3435. Warning (13024): Output pins are stuck at VCC or GND
    3436. 

  3436.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[0]" is stuck at GND
    3437. 

  3437.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[1]" is stuck at GND
    3438. 

  3438.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[2]" is stuck at GND
    3439. 

  3439.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[3]" is stuck at GND
    3440. 

  3440.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[4]" is stuck at GND
    3441. 

  3441.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[5]" is stuck at GND
    3442. 

  3442.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[6]" is stuck at GND
    3443. 

  3443.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[7]" is stuck at GND
    3444. 

  3444.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[0]" is stuck at GND
    3445. 

  3445.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[1]" is stuck at GND
    3446. 

  3446.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[2]" is stuck at GND
    3447. 

  3447.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[3]" is stuck at GND
    3448. 

  3448.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[4]" is stuck at GND
    3449. 

  3449.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[5]" is stuck at GND
    3450. 

  3450.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[6]" is stuck at GND
    3451. 

  3451.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[7]" is stuck at GND
    3452. 

  3452.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[0]" is stuck at GND
    3453. 

  3453.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[1]" is stuck at GND
    3454. 

  3454.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[2]" is stuck at GND
    3455. 

  3455.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[3]" is stuck at GND
    3456. 

  3456.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[4]" is stuck at GND
    3457. 

  3457.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[5]" is stuck at GND
    3458. 

  3458.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[6]" is stuck at GND
    3459. 

  3459.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[7]" is stuck at GND
    3460. 

  3460.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[0]" is stuck at GND
    3461. 

  3461.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[1]" is stuck at GND
    3462. 

  3462.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[2]" is stuck at GND
    3463. 

  3463.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[3]" is stuck at GND
    3464. 

  3464.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[4]" is stuck at GND
    3465. 

  3465.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[5]" is stuck at GND
    3466. 

  3466.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[6]" is stuck at GND
    3467. 

  3467.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[7]" is stuck at GND
    3468. 

  3468.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[0]" is stuck at GND
    3469. 

  3469.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[1]" is stuck at GND
    3470. 

  3470.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[2]" is stuck at GND
    3471. 

  3471.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[3]" is stuck at GND
    3472. 

  3472.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[4]" is stuck at GND
    3473. 

  3473.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[5]" is stuck at GND
    3474. 

  3474.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[6]" is stuck at GND
    3475. 

  3475.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[7]" is stuck at GND
    3476. 

  3476.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[0]" is stuck at GND
    3477. 

  3477.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[1]" is stuck at GND
    3478. 

  3478.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[2]" is stuck at GND
    3479. 

  3479.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[3]" is stuck at GND
    3480. 

  3480.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[4]" is stuck at GND
    3481. 

  3481.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[5]" is stuck at GND
    3482. 

  3482.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[6]" is stuck at GND
    3483. 

  3483.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[7]" is stuck at GND
    3484. 

  3484.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[0]" is stuck at GND
    3485. 

  3485.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[1]" is stuck at GND
    3486. 

  3486.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[2]" is stuck at GND
    3487. 

  3487.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[3]" is stuck at GND
    3488. 

  3488.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[4]" is stuck at GND
    3489. 

  3489.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[5]" is stuck at GND
    3490. 

  3490.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[6]" is stuck at GND
    3491. 

  3491.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[7]" is stuck at GND
    3492. 

  3492.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[0]" is stuck at GND
    3493. 

  3493.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[1]" is stuck at GND
    3494. 

  3494.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[2]" is stuck at GND
    3495. 

  3495.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[3]" is stuck at GND
    3496. 

  3496.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[4]" is stuck at GND
    3497. 

  3497.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[5]" is stuck at GND
    3498. 

  3498.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[6]" is stuck at GND
    3499. 

  3499.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[7]" is stuck at GND
    3500. 

  3500.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[0]" is stuck at GND
    3501. 

  3501.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[1]" is stuck at GND
    3502. 

  3502.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[2]" is stuck at GND
    3503. 

  3503.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[3]" is stuck at GND
    3504. 

  3504.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[4]" is stuck at GND
    3505. 

  3505.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[5]" is stuck at GND
    3506. 

  3506.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[6]" is stuck at GND
    3507. 

  3507.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[7]" is stuck at GND
    3508. 

  3508.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[0]" is stuck at GND
    3509. 

  3509.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[1]" is stuck at GND
    3510. 

  3510.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[2]" is stuck at GND
    3511. 

  3511.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[3]" is stuck at GND
    3512. 

  3512.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[4]" is stuck at GND
    3513. 

  3513.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[5]" is stuck at GND
    3514. 

  3514.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[6]" is stuck at GND
    3515. 

  3515.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[7]" is stuck at GND
    3516. 

  3516.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[0]" is stuck at GND
    3517. 

  3517.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[1]" is stuck at GND
    3518. 

  3518.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[2]" is stuck at GND
    3519. 

  3519.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[3]" is stuck at GND
    3520. 

  3520.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[4]" is stuck at GND
    3521. 

  3521.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[5]" is stuck at GND
    3522. 

  3522.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[6]" is stuck at GND
    3523. 

  3523.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[7]" is stuck at GND
    3524. 

  3524.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[0]" is stuck at GND
    3525. 

  3525.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[1]" is stuck at GND
    3526. 

  3526.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[2]" is stuck at GND
    3527. 

  3527.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[3]" is stuck at GND
    3528. 

  3528.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[4]" is stuck at GND
    3529. 

  3529.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[5]" is stuck at GND
    3530. 

  3530.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[6]" is stuck at GND
    3531. 

  3531.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[7]" is stuck at GND
    3532. 

  3532.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[0]" is stuck at GND
    3533. 

  3533.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[1]" is stuck at GND
    3534. 

  3534.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[2]" is stuck at GND
    3535. 

  3535.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[3]" is stuck at GND
    3536. 

  3536.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[4]" is stuck at GND
    3537. 

  3537.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[5]" is stuck at GND
    3538. 

  3538.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[6]" is stuck at GND
    3539. 

  3539.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[7]" is stuck at GND
    3540. 

  3540.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[0]" is stuck at GND
    3541. 

  3541.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[1]" is stuck at GND
    3542. 

  3542.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[2]" is stuck at GND
    3543. 

  3543.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[3]" is stuck at GND
    3544. 

  3544.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[4]" is stuck at GND
    3545. 

  3545.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[5]" is stuck at GND
    3546. 

  3546.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[6]" is stuck at GND
    3547. 

  3547.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[7]" is stuck at GND
    3548. 

  3548.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[0]" is stuck at GND
    3549. 

  3549.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[1]" is stuck at GND
    3550. 

  3550.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[2]" is stuck at GND
    3551. 

  3551.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[3]" is stuck at GND
    3552. 

  3552.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[4]" is stuck at GND
    3553. 

  3553.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[5]" is stuck at GND
    3554. 

  3554.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[6]" is stuck at GND
    3555. 

  3555.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[7]" is stuck at GND
    3556. 

  3556.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[0]" is stuck at GND
    3557. 

  3557.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[1]" is stuck at GND
    3558. 

  3558.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[2]" is stuck at GND
    3559. 

  3559.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[3]" is stuck at GND
    3560. 

  3560.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[4]" is stuck at GND
    3561. 

  3561.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[5]" is stuck at GND
    3562. 

  3562.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[6]" is stuck at GND
    3563. 

  3563.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[7]" is stuck at GND
    3564. 

  3564.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[0]" is stuck at GND
    3565. 

  3565.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[1]" is stuck at GND
    3566. 

  3566.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[2]" is stuck at GND
    3567. 

  3567.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[3]" is stuck at GND
    3568. 

  3568.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[4]" is stuck at GND
    3569. 

  3569.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[5]" is stuck at GND
    3570. 

  3570.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[6]" is stuck at GND
    3571. 

  3571.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[7]" is stuck at GND
    3572. 

  3572.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[0]" is stuck at GND
    3573. 

  3573.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[1]" is stuck at GND
    3574. 

  3574.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[2]" is stuck at GND
    3575. 

  3575.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[3]" is stuck at GND
    3576. 

  3576.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[4]" is stuck at GND
    3577. 

  3577.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[5]" is stuck at GND
    3578. 

  3578.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[6]" is stuck at GND
    3579. 

  3579.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[7]" is stuck at GND
    3580. 

  3580.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[0]" is stuck at GND
    3581. 

  3581.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[1]" is stuck at GND
    3582. 

  3582.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[2]" is stuck at GND
    3583. 

  3583.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[3]" is stuck at GND
    3584. 

  3584.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[4]" is stuck at GND
    3585. 

  3585.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[5]" is stuck at GND
    3586. 

  3586.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[6]" is stuck at GND
    3587. 

  3587.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[7]" is stuck at GND
    3588. 

  3588.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[0]" is stuck at GND
    3589. 

  3589.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[1]" is stuck at GND
    3590. 

  3590.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[2]" is stuck at GND
    3591. 

  3591.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[3]" is stuck at GND
    3592. 

  3592.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[4]" is stuck at GND
    3593. 

  3593.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[5]" is stuck at GND
    3594. 

  3594.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[6]" is stuck at GND
    3595. 

  3595.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[7]" is stuck at GND
    3596. 

  3596.     Warning (13410): Pin "alta_rv32:rv32|dmactive" is stuck at GND
    3597. 

  3597.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGNSW" is stuck at GND
    3598. 

  3598.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[0]" is stuck at GND
    3599. 

  3599.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[1]" is stuck at GND
    3600. 

  3600.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[2]" is stuck at GND
    3601. 

  3601.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[3]" is stuck at GND
    3602. 

  3602.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[0]" is stuck at GND
    3603. 

  3603.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[1]" is stuck at GND
    3604. 

  3604.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[2]" is stuck at GND
    3605. 

  3605.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[3]" is stuck at GND
    3606. 

  3606. Info (128000): Starting physical synthesis optimizations for speed
    3607. 

  3607. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    3608. 

  3608. Info (332111): Found 3 clocks
    3609. 

  3609.     Info (332111):   Period   Clock Name
    3610. 

  3610.     Info (332111): ======== ============
    3611. 

  3611.     Info (332111):  100.000      PIN_HSI
    3612. 

  3612.     Info (332111):  125.000    PLL_CLKIN
    3613. 

  3613.     Info (332111):    9.615 pll_inst|auto_generated|pll1|clk[0]
    3614. 

  3614. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    3615. 

  3615. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    3616. 

  3616. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    3617. 

  3617. Info (21057): Implemented 520 device resources after synthesis - the final resource count might be different
    3618. 

  3618.     Info (21058): Implemented 224 input pins
    3619. 

  3619.     Info (21059): Implemented 295 output pins
    3620. 

  3620.     Info (21061): Implemented 1 logic cells
    3621. 

  3621. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings
    3622. 

  3622.     Info: Peak virtual memory: 4684 megabytes
    3623. 

  3623.     Info: Processing ended: Sat May 09 14:18:39 2026
    3624. 

  3624.     Info: Elapsed time: 00:00:02
    3625. 

  3625.     Info: Total CPU time (on all processors): 00:00:09
    3626. 

  3626. Info (281038): Finished parallel synthesis of all partitions
    3627. 

  3627. Info (144001): Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg
    3628. 

  3628. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1282 warnings
    3629. 

  3629.     Info: Peak virtual memory: 4640 megabytes
    3630. 

  3630.     Info: Processing ended: Sat May 09 14:18:46 2026
    3631. 

  3631.     Info: Elapsed time: 00:00:11
    3632. 

  3632.     Info: Total CPU time (on all processors): 00:00:18
    3633. 

  3633. 

  3634. 

  3635. +------------------------------------------+
    3636. 

  3636. ; Analysis & Synthesis Suppressed Messages ;
    3637. 

  3637. +------------------------------------------+
    3638. 

  3638. The suppressed messages can be found in D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg.
    3639. 

  3639. 

  3640.