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alta.cellmap

alta.cellmap 30 KB
文件歷史 原始文件

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  1. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    2. 

  2. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    3. 

  3. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    4. 

  4. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    5. 

  5. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    6. 

  6. macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
    7. 

  7. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    8. 

  8. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    9. 

  9. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    10. 

  10. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    11. 

  11. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    12. 

  12. macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
    13. 

  13. pll_inst|auto_generated|pll_lock_sync clken_ctrl_X46_Y1_N0
    14. 

  14. macro_inst|trig_ctrl_inst|ram_wr_data_b[6] clken_ctrl_X54_Y4_N0
    15. 

  15. macro_inst|trig_ctrl_inst|ram_wr_data_b[4] clken_ctrl_X54_Y4_N0
    16. 

  16. macro_inst|trig_ctrl_inst|ram_wr_data_b[0] clken_ctrl_X54_Y4_N0
    17. 

  17. macro_inst|trig_ctrl_inst|ram_wr_data_b[5] clken_ctrl_X54_Y4_N0
    18. 

  18. macro_inst|trig_ctrl_inst|ram_wr_data_b[11] clken_ctrl_X54_Y4_N0
    19. 

  19. macro_inst|trig_ctrl_inst|ram_wr_data_b[7] clken_ctrl_X54_Y4_N0
    20. 

  20. macro_inst|trig_ctrl_inst|ram_wr_data_b[8] clken_ctrl_X54_Y4_N0
    21. 

  21. macro_inst|trig_ctrl_inst|ram_wr_data_b[3] clken_ctrl_X54_Y4_N0
    22. 

  22. macro_inst|trig_ctrl_inst|ram_wr_data_b[1] clken_ctrl_X54_Y4_N0
    23. 

  23. macro_inst|trig_ctrl_inst|ram_wren_b clken_ctrl_X54_Y4_N1
    24. 

  24. macro_inst|trig_ctrl_inst|ram_wr_data_b[2] clken_ctrl_X54_Y4_N0
    25. 

  25. macro_inst|trig_ctrl_inst|ram_wr_data_b[10] clken_ctrl_X54_Y4_N0
    26. 

  26. macro_inst|trig_ctrl_inst|ram_wr_data_b[9] clken_ctrl_X54_Y4_N0
    27. 

  27. macro_inst|ahb2apb_inst|prdata[31] clken_ctrl_X56_Y10_N0
    28. 

  28. macro_inst|ahb2apb_inst|prdata[12] clken_ctrl_X56_Y10_N0
    29. 

  29. macro_inst|ahb2apb_inst|prdata[30] clken_ctrl_X56_Y10_N0
    30. 

  30. macro_inst|ahb2apb_inst|prdata[26] clken_ctrl_X56_Y10_N0
    31. 

  31. macro_inst|ahb2apb_inst|prdata[10] clken_ctrl_X56_Y10_N0
    32. 

  32. macro_inst|ahb2apb_inst|prdata[21] clken_ctrl_X56_Y10_N0
    33. 

  33. macro_inst|cfg_reg_inst|prdata[29] clken_ctrl_X56_Y10_N1
    34. 

  34. macro_inst|ahb2apb_inst|prdata[28] clken_ctrl_X56_Y10_N0
    35. 

  35. macro_inst|cfg_reg_inst|prdata[26] clken_ctrl_X56_Y10_N1
    36. 

  36. macro_inst|ahb2apb_inst|prdata[29] clken_ctrl_X56_Y10_N0
    37. 

  37. macro_inst|ahb2apb_inst|prdata[11] clken_ctrl_X56_Y10_N0
    38. 

  38. macro_inst|ahb2apb_inst|prdata[15] clken_ctrl_X56_Y10_N0
    39. 

  39. macro_inst|cfg_reg_inst|prdata[30] clken_ctrl_X56_Y10_N1
    40. 

  40. macro_inst|ahb2apb_inst|prdata[14] clken_ctrl_X56_Y10_N0
    41. 

  41. macro_inst|ahb2apb_inst|prdata[27] clken_ctrl_X56_Y10_N0
    42. 

  42. macro_inst|ahb2apb_inst|prdata[13] clken_ctrl_X56_Y10_N0
    43. 

  43. macro_inst|ahb2apb_inst|prdata[19] clken_ctrl_X56_Y11_N0
    44. 

  44. macro_inst|ahb2apb_inst|prdata[7] clken_ctrl_X56_Y11_N0
    45. 

  45. macro_inst|cfg_reg_inst|frequency[25] clken_ctrl_X56_Y11_N1
    46. 

  46. macro_inst|cfg_reg_inst|frequency[12] clken_ctrl_X56_Y11_N1
    47. 

  47. macro_inst|ahb2apb_inst|prdata[9] clken_ctrl_X56_Y11_N0
    48. 

  48. macro_inst|cfg_reg_inst|frequency[18] clken_ctrl_X56_Y11_N1
    49. 

  49. macro_inst|cfg_reg_inst|frequency[16] clken_ctrl_X56_Y11_N1
    50. 

  50. macro_inst|cfg_reg_inst|frequency[23] clken_ctrl_X56_Y11_N1
    51. 

  51. macro_inst|ahb2apb_inst|prdata[23] clken_ctrl_X56_Y11_N0
    52. 

  52. macro_inst|cfg_reg_inst|frequency[9] clken_ctrl_X56_Y11_N1
    53. 

  53. macro_inst|ahb2apb_inst|prdata[20] clken_ctrl_X56_Y11_N0
    54. 

  54. macro_inst|ahb2apb_inst|prdata[3] clken_ctrl_X56_Y11_N0
    55. 

  55. macro_inst|ahb2apb_inst|prdata[25] clken_ctrl_X56_Y11_N0
    56. 

  56. macro_inst|ahb2apb_inst|prdata[2] clken_ctrl_X56_Y11_N0
    57. 

  57. macro_inst|ahb2apb_inst|prdata[18] clken_ctrl_X56_Y11_N0
    58. 

  58. macro_inst|ahb2apb_inst|prdata[16] clken_ctrl_X56_Y11_N0
    59. 

  59. macro_inst|ahb2apb_inst|prdata[24] clken_ctrl_X56_Y12_N0
    60. 

  60. macro_inst|apb_adc0_inst|apb_db[7] clken_ctrl_X56_Y4_N0
    61. 

  61. macro_inst|apb_adc0_inst|apb_db[9] clken_ctrl_X56_Y4_N0
    62. 

  62. macro_inst|apb_adc0_inst|apb_eoc clken_ctrl_X56_Y4_N1
    63. 

  63. macro_inst|apb_adc0_inst|apb_db[5] clken_ctrl_X56_Y4_N0
    64. 

  64. macro_inst|trig_ctrl_inst|adc_eoc_sync1 clken_ctrl_X56_Y4_N1
    65. 

  65. macro_inst|apb_adc0_inst|apb_db[1] clken_ctrl_X56_Y4_N0
    66. 

  66. macro_inst|apb_adc0_inst|apb_db[3] clken_ctrl_X56_Y4_N0
    67. 

  67. macro_inst|apb_dac0_inst|max_vol_r[3] clken_ctrl_X56_Y8_N0
    68. 

  68. macro_inst|apb_dac0_inst|max_vol_r[6] clken_ctrl_X56_Y8_N0
    69. 

  69. macro_inst|apb_dac0_inst|max_vol_r[4] clken_ctrl_X56_Y8_N0
    70. 

  70. macro_inst|apb_dac0_inst|max_vol_r[0] clken_ctrl_X56_Y8_N0
    71. 

  71. macro_inst|cfg_reg_inst|frequency[26] clken_ctrl_X57_Y10_N0
    72. 

  72. macro_inst|cfg_reg_inst|prdata[12] clken_ctrl_X57_Y10_N1
    73. 

  73. macro_inst|cfg_reg_inst|prdata[15] clken_ctrl_X57_Y10_N1
    74. 

  74. macro_inst|cfg_reg_inst|frequency[28] clken_ctrl_X57_Y10_N0
    75. 

  75. macro_inst|cfg_reg_inst|frequency[13] clken_ctrl_X57_Y10_N0
    76. 

  76. macro_inst|cfg_reg_inst|frequency[29] clken_ctrl_X57_Y10_N0
    77. 

  77. macro_inst|cfg_reg_inst|frequency[31] clken_ctrl_X57_Y10_N0
    78. 

  78. macro_inst|cfg_reg_inst|prdata[21] clken_ctrl_X57_Y10_N1
    79. 

  79. macro_inst|cfg_reg_inst|frequency[27] clken_ctrl_X57_Y10_N0
    80. 

  80. macro_inst|cfg_reg_inst|prdata[13] clken_ctrl_X57_Y10_N1
    81. 

  81. macro_inst|cfg_reg_inst|prdata[27] clken_ctrl_X57_Y10_N1
    82. 

  82. macro_inst|cfg_reg_inst|prdata[28] clken_ctrl_X57_Y10_N1
    83. 

  83. macro_inst|cfg_reg_inst|frequency[30] clken_ctrl_X57_Y10_N0
    84. 

  84. macro_inst|cfg_reg_inst|prdata[31] clken_ctrl_X57_Y10_N1
    85. 

  85. macro_inst|cfg_reg_inst|max_vol[9] clken_ctrl_X57_Y11_N0
    86. 

  86. macro_inst|cfg_reg_inst|prdata[16] clken_ctrl_X57_Y11_N1
    87. 

  87. macro_inst|cfg_reg_inst|min_vol[4] clken_ctrl_X57_Y11_N0
    88. 

  88. macro_inst|cfg_reg_inst|min_vol[0] clken_ctrl_X57_Y11_N0
    89. 

  89. macro_inst|cfg_reg_inst|prdata[25] clken_ctrl_X57_Y11_N1
    90. 

  90. macro_inst|cfg_reg_inst|prdata[23] clken_ctrl_X57_Y11_N1
    91. 

  91. macro_inst|cfg_reg_inst|prdata[19] clken_ctrl_X57_Y11_N1
    92. 

  92. macro_inst|cfg_reg_inst|min_vol[3] clken_ctrl_X57_Y11_N0
    93. 

  93. macro_inst|cfg_reg_inst|max_vol[7] clken_ctrl_X57_Y11_N0
    94. 

  94. macro_inst|cfg_reg_inst|prdata[18] clken_ctrl_X57_Y11_N1
    95. 

  95. macro_inst|cfg_reg_inst|min_vol[2] clken_ctrl_X57_Y11_N0
    96. 

  96. macro_inst|cfg_reg_inst|min_vol[7] clken_ctrl_X57_Y11_N0
    97. 

  97. macro_inst|cfg_reg_inst|min_vol[9] clken_ctrl_X57_Y11_N0
    98. 

  98. macro_inst|cfg_reg_inst|prdata[20] clken_ctrl_X57_Y11_N1
    99. 

  99. macro_inst|cfg_reg_inst|frequency[19] clken_ctrl_X57_Y12_N0
    100. 

  100. macro_inst|cfg_reg_inst|frequency[20] clken_ctrl_X57_Y12_N0
    101. 

  101. macro_inst|cfg_reg_inst|min_vol[8] clken_ctrl_X57_Y12_N1
    102. 

  102. macro_inst|cfg_reg_inst|frequency[24] clken_ctrl_X57_Y12_N0
    103. 

  103. macro_inst|cfg_reg_inst|min_vol[6] clken_ctrl_X57_Y12_N1
    104. 

  104. macro_inst|cfg_reg_inst|frequency[21] clken_ctrl_X57_Y12_N0
    105. 

  105. macro_inst|cfg_reg_inst|frequency[22] clken_ctrl_X57_Y12_N0
    106. 

  106. macro_inst|cfg_reg_inst|min_vol[5] clken_ctrl_X57_Y12_N1
    107. 

  107. macro_inst|apb_dac0_inst|phase_r[9] clken_ctrl_X57_Y3_N0
    108. 

  108. macro_inst|apb_dac0_inst|phase_r[8] clken_ctrl_X57_Y3_N0
    109. 

  109. macro_inst|apb_adc0_inst|apb_db[0] clken_ctrl_X57_Y4_N0
    110. 

  110. macro_inst|cfg_reg_inst|trig_threshold[3] clken_ctrl_X57_Y4_N1
    111. 

  111. macro_inst|apb_adc0_inst|apb_db[4] clken_ctrl_X57_Y4_N0
    112. 

  112. macro_inst|cfg_reg_inst|trig_threshold[5] clken_ctrl_X57_Y4_N1
    113. 

  113. macro_inst|apb_adc0_inst|apb_db[6] clken_ctrl_X57_Y4_N0
    114. 

  114. macro_inst|cfg_reg_inst|trig_threshold[11] clken_ctrl_X57_Y4_N1
    115. 

  115. macro_inst|cfg_reg_inst|trig_threshold[7] clken_ctrl_X57_Y4_N1
    116. 

  116. macro_inst|apb_adc0_inst|apb_db[8] clken_ctrl_X57_Y4_N0
    117. 

  117. macro_inst|cfg_reg_inst|trig_threshold[9] clken_ctrl_X57_Y4_N1
    118. 

  118. macro_inst|apb_adc0_inst|apb_db[10] clken_ctrl_X57_Y4_N0
    119. 

  119. macro_inst|apb_adc0_inst|apb_db[11] clken_ctrl_X57_Y4_N0
    120. 

  120. macro_inst|cfg_reg_inst|trig_threshold[1] clken_ctrl_X57_Y4_N1
    121. 

  121. macro_inst|apb_adc0_inst|apb_db[2] clken_ctrl_X57_Y4_N0
    122. 

  122. macro_inst|apb_dac0_inst|phase_r[6] clken_ctrl_X57_Y6_N0
    123. 

  123. macro_inst|apb_dac0_inst|phase_r[5] clken_ctrl_X57_Y6_N0
    124. 

  124. macro_inst|cfg_reg_inst|prdata[11] clken_ctrl_X57_Y7_N0
    125. 

  125. macro_inst|cfg_reg_inst|prdata[9] clken_ctrl_X57_Y7_N0
    126. 

  126. macro_inst|apb_dac0_inst|min_vol_r[2] clken_ctrl_X57_Y7_N1
    127. 

  127. macro_inst|apb_dac0_inst|max_vol_r[9] clken_ctrl_X57_Y7_N1
    128. 

  128. macro_inst|cfg_reg_inst|prdata[10] clken_ctrl_X57_Y7_N0
    129. 

  129. macro_inst|apb_dac0_inst|max_vol_r[1] clken_ctrl_X57_Y8_N0
    130. 

  130. macro_inst|apb_dac0_inst|min_vol_r[7] clken_ctrl_X57_Y8_N0
    131. 

  131. macro_inst|apb_dac0_inst|min_vol_r[8] clken_ctrl_X57_Y8_N0
    132. 

  132. macro_inst|apb_dac0_inst|min_vol_r[9] clken_ctrl_X57_Y8_N0
    133. 

  133. macro_inst|apb_dac0_inst|min_vol_r[1] clken_ctrl_X57_Y8_N0
    134. 

  134. macro_inst|cfg_reg_inst|prdata[17] clken_ctrl_X57_Y8_N1
    135. 

  135. macro_inst|cfg_reg_inst|prdata[24] clken_ctrl_X57_Y8_N1
    136. 

  136. macro_inst|cfg_reg_inst|prdata[22] clken_ctrl_X57_Y8_N1
    137. 

  137. macro_inst|apb_dac0_inst|min_vol_r[0] clken_ctrl_X57_Y8_N0
    138. 

  138. macro_inst|apb_dac0_inst|min_vol_r[6] clken_ctrl_X57_Y8_N0
    139. 

  139. macro_inst|apb_dac0_inst|min_vol_r[5] clken_ctrl_X57_Y8_N0
    140. 

  140. macro_inst|apb_dac0_inst|min_vol_r[3] clken_ctrl_X57_Y8_N0
    141. 

  141. macro_inst|apb_dac0_inst|min_vol_r[4] clken_ctrl_X57_Y8_N0
    142. 

  142. macro_inst|apb_dac0_inst|max_vol_r[2] clken_ctrl_X57_Y9_N0
    143. 

  143. macro_inst|apb_dac0_inst|phase_r[4] clken_ctrl_X57_Y9_N0
    144. 

  144. macro_inst|apb_dac0_inst|max_vol_r[5] clken_ctrl_X57_Y9_N0
    145. 

  145. macro_inst|cfg_reg_inst|max_vol[8] clken_ctrl_X57_Y9_N1
    146. 

  146. macro_inst|apb_dac0_inst|phase_r[0] clken_ctrl_X57_Y9_N0
    147. 

  147. macro_inst|apb_dac0_inst|phase_r[7] clken_ctrl_X57_Y9_N0
    148. 

  148. macro_inst|cfg_reg_inst|max_vol[5] clken_ctrl_X57_Y9_N1
    149. 

  149. macro_inst|apb_dac0_inst|phase_r[1] clken_ctrl_X57_Y9_N0
    150. 

  150. macro_inst|apb_dac0_inst|max_vol_r[8] clken_ctrl_X57_Y9_N0
    151. 

  151. macro_inst|apb_dac0_inst|max_vol_r[7] clken_ctrl_X57_Y9_N0
    152. 

  152. macro_inst|apb_dac0_inst|phase_acc[16] clken_ctrl_X58_Y10_N0
    153. 

  153. macro_inst|apb_dac0_inst|phase_acc[21] clken_ctrl_X58_Y10_N0
    154. 

  154. macro_inst|apb_dac0_inst|phase_acc[22] clken_ctrl_X58_Y10_N0
    155. 

  155. macro_inst|apb_dac0_inst|phase_acc[23] clken_ctrl_X58_Y10_N0
    156. 

  156. macro_inst|apb_dac0_inst|phase_acc[24] clken_ctrl_X58_Y10_N0
    157. 

  157. macro_inst|apb_dac0_inst|phase_acc[25] clken_ctrl_X58_Y10_N0
    158. 

  158. macro_inst|apb_dac0_inst|phase_acc[17] clken_ctrl_X58_Y10_N0
    159. 

  159. macro_inst|apb_dac0_inst|phase_acc[26] clken_ctrl_X58_Y10_N0
    160. 

  160. macro_inst|apb_dac0_inst|phase_acc[27] clken_ctrl_X58_Y10_N0
    161. 

  161. macro_inst|apb_dac0_inst|phase_acc[28] clken_ctrl_X58_Y10_N0
    162. 

  162. macro_inst|apb_dac0_inst|phase_acc[29] clken_ctrl_X58_Y10_N0
    163. 

  163. macro_inst|apb_dac0_inst|phase_acc[30] clken_ctrl_X58_Y10_N0
    164. 

  164. macro_inst|apb_dac0_inst|phase_acc[31] clken_ctrl_X58_Y10_N0
    165. 

  165. macro_inst|apb_dac0_inst|phase_acc[18] clken_ctrl_X58_Y10_N0
    166. 

  166. macro_inst|apb_dac0_inst|phase_acc[19] clken_ctrl_X58_Y10_N0
    167. 

  167. macro_inst|apb_dac0_inst|phase_acc[20] clken_ctrl_X58_Y10_N0
    168. 

  168. macro_inst|apb_dac0_inst|phase_acc[0] clken_ctrl_X58_Y11_N0
    169. 

  169. macro_inst|apb_dac0_inst|phase_acc[5] clken_ctrl_X58_Y11_N0
    170. 

  170. macro_inst|apb_dac0_inst|phase_acc[6] clken_ctrl_X58_Y11_N0
    171. 

  171. macro_inst|apb_dac0_inst|phase_acc[7] clken_ctrl_X58_Y11_N0
    172. 

  172. macro_inst|apb_dac0_inst|phase_acc[8] clken_ctrl_X58_Y11_N0
    173. 

  173. macro_inst|apb_dac0_inst|phase_acc[9] clken_ctrl_X58_Y11_N0
    174. 

  174. macro_inst|apb_dac0_inst|phase_acc[1] clken_ctrl_X58_Y11_N0
    175. 

  175. macro_inst|apb_dac0_inst|phase_acc[10] clken_ctrl_X58_Y11_N0
    176. 

  176. macro_inst|apb_dac0_inst|phase_acc[11] clken_ctrl_X58_Y11_N0
    177. 

  177. macro_inst|apb_dac0_inst|phase_acc[12] clken_ctrl_X58_Y11_N0
    178. 

  178. macro_inst|apb_dac0_inst|phase_acc[13] clken_ctrl_X58_Y11_N0
    179. 

  179. macro_inst|apb_dac0_inst|phase_acc[14] clken_ctrl_X58_Y11_N0
    180. 

  180. macro_inst|apb_dac0_inst|phase_acc[15] clken_ctrl_X58_Y11_N0
    181. 

  181. macro_inst|apb_dac0_inst|phase_acc[2] clken_ctrl_X58_Y11_N0
    182. 

  182. macro_inst|apb_dac0_inst|phase_acc[3] clken_ctrl_X58_Y11_N0
    183. 

  183. macro_inst|apb_dac0_inst|phase_acc[4] clken_ctrl_X58_Y11_N0
    184. 

  184. macro_inst|ahb2apb_inst|pvalid clken_ctrl_X58_Y12_N0
    185. 

  185. macro_inst|ahb2apb_inst|apbState.apbIdle clken_ctrl_X58_Y12_N0
    186. 

  186. macro_inst|ahb2apb_inst|hreadyout clken_ctrl_X58_Y12_N0
    187. 

  187. macro_inst|ahb2apb_inst|penable clken_ctrl_X58_Y12_N0
    188. 

  188. macro_inst|ahb2apb_inst|apbState.apbSetup clken_ctrl_X58_Y12_N0
    189. 

  189. macro_inst|ahb2apb_inst|hdone clken_ctrl_X58_Y12_N0
    190. 

  190. macro_inst|pr_select[0] clken_ctrl_X58_Y12_N1
    191. 

  191. macro_inst|ahb2apb_inst|psel clken_ctrl_X58_Y12_N0
    192. 

  192. macro_inst|ahb2apb_inst|pdone clken_ctrl_X58_Y12_N0
    193. 

  193. macro_inst|pr_select[2] clken_ctrl_X58_Y12_N1
    194. 

  194. macro_inst|pr_select[1] clken_ctrl_X58_Y12_N1
    195. 

  195. macro_inst|pr_select[3] clken_ctrl_X58_Y12_N1
    196. 

  196. macro_inst|cfg_reg_inst|trig_threshold[4] clken_ctrl_X58_Y4_N0
    197. 

  197. macro_inst|trig_ctrl_inst|adc_data_prev[4] clken_ctrl_X58_Y4_N1
    198. 

  198. macro_inst|trig_ctrl_inst|adc_data_prev[1] clken_ctrl_X58_Y4_N1
    199. 

  199. macro_inst|trig_ctrl_inst|adc_data_prev[2] clken_ctrl_X58_Y4_N1
    200. 

  200. macro_inst|trig_ctrl_inst|adc_data_prev[6] clken_ctrl_X58_Y4_N1
    201. 

  201. macro_inst|cfg_reg_inst|trig_threshold[8] clken_ctrl_X58_Y4_N0
    202. 

  202. macro_inst|trig_ctrl_inst|adc_data_prev[9] clken_ctrl_X58_Y4_N1
    203. 

  203. macro_inst|trig_ctrl_inst|adc_data_prev[3] clken_ctrl_X58_Y4_N1
    204. 

  204. macro_inst|cfg_reg_inst|trig_threshold[10] clken_ctrl_X58_Y4_N0
    205. 

  205. macro_inst|trig_ctrl_inst|adc_data_prev[0] clken_ctrl_X58_Y4_N1
    206. 

  206. macro_inst|cfg_reg_inst|trig_threshold[0] clken_ctrl_X58_Y4_N0
    207. 

  207. macro_inst|cfg_reg_inst|trig_threshold[6] clken_ctrl_X58_Y4_N0
    208. 

  208. macro_inst|cfg_reg_inst|trig_threshold[2] clken_ctrl_X58_Y4_N0
    209. 

  209. macro_inst|trig_ctrl_inst|adc_data_prev[7] clken_ctrl_X58_Y4_N1
    210. 

  210. macro_inst|trig_ctrl_inst|adc_data_prev[5] clken_ctrl_X58_Y4_N1
    211. 

  211. macro_inst|trig_ctrl_inst|adc_data_prev[8] clken_ctrl_X58_Y4_N1
    212. 

  212. macro_inst|trig_ctrl_inst|auto_wait_cnt[0] clken_ctrl_X58_Y6_N1
    213. 

  213. macro_inst|trig_ctrl_inst|auto_wait_cnt[5] clken_ctrl_X58_Y6_N1
    214. 

  214. macro_inst|trig_ctrl_inst|auto_wait_cnt[6] clken_ctrl_X58_Y6_N1
    215. 

  215. macro_inst|trig_ctrl_inst|auto_wait_cnt[7] clken_ctrl_X58_Y6_N1
    216. 

  216. macro_inst|trig_ctrl_inst|auto_wait_cnt[8] clken_ctrl_X58_Y6_N1
    217. 

  217. macro_inst|trig_ctrl_inst|auto_wait_cnt[9] clken_ctrl_X58_Y6_N1
    218. 

  218. macro_inst|trig_ctrl_inst|auto_wait_cnt[1] clken_ctrl_X58_Y6_N1
    219. 

  219. macro_inst|trig_ctrl_inst|auto_wait_cnt[2] clken_ctrl_X58_Y6_N1
    220. 

  220. macro_inst|trig_ctrl_inst|auto_wait_cnt[3] clken_ctrl_X58_Y6_N1
    221. 

  221. macro_inst|trig_ctrl_inst|auto_wait_cnt[4] clken_ctrl_X58_Y6_N1
    222. 

  222. macro_inst|trig_ctrl_inst|pulse_cnt[0] clken_ctrl_X58_Y7_N1
    223. 

  223. macro_inst|trig_ctrl_inst|pulse_cnt[5] clken_ctrl_X58_Y7_N1
    224. 

  224. macro_inst|trig_ctrl_inst|pulse_cnt[6] clken_ctrl_X58_Y7_N1
    225. 

  225. macro_inst|trig_ctrl_inst|pulse_cnt[7] clken_ctrl_X58_Y7_N1
    226. 

  226. macro_inst|trig_ctrl_inst|pulse_cnt[8] clken_ctrl_X58_Y7_N1
    227. 

  227. macro_inst|trig_ctrl_inst|pulse_cnt[9] clken_ctrl_X58_Y7_N1
    228. 

  228. macro_inst|trig_ctrl_inst|pulse_cnt[1] clken_ctrl_X58_Y7_N1
    229. 

  229. macro_inst|trig_ctrl_inst|pulse_cnt[10] clken_ctrl_X58_Y7_N1
    230. 

  230. macro_inst|trig_ctrl_inst|pulse_cnt[11] clken_ctrl_X58_Y7_N1
    231. 

  231. macro_inst|trig_ctrl_inst|pulse_cnt[12] clken_ctrl_X58_Y7_N1
    232. 

  232. macro_inst|trig_ctrl_inst|pulse_cnt[13] clken_ctrl_X58_Y7_N1
    233. 

  233. macro_inst|trig_ctrl_inst|pulse_cnt[14] clken_ctrl_X58_Y7_N1
    234. 

  234. macro_inst|trig_ctrl_inst|pulse_cnt[15] clken_ctrl_X58_Y7_N1
    235. 

  235. macro_inst|trig_ctrl_inst|pulse_cnt[2] clken_ctrl_X58_Y7_N1
    236. 

  236. macro_inst|trig_ctrl_inst|pulse_cnt[3] clken_ctrl_X58_Y7_N1
    237. 

  237. macro_inst|trig_ctrl_inst|pulse_cnt[4] clken_ctrl_X58_Y7_N1
    238. 

  238. macro_inst|cfg_reg_inst|min_vol[1] clken_ctrl_X58_Y8_N0
    239. 

  239. macro_inst|cfg_reg_inst|wave_type[0] clken_ctrl_X58_Y8_N1
    240. 

  240. macro_inst|cfg_reg_inst|wave_type[1] clken_ctrl_X58_Y8_N1
    241. 

  241. macro_inst|cfg_reg_inst|max_vol[1] clken_ctrl_X58_Y8_N0
    242. 

  242. macro_inst|cfg_reg_inst|frequency[5] clken_ctrl_X58_Y9_N0
    243. 

  243. macro_inst|cfg_reg_inst|frequency[17] clken_ctrl_X58_Y9_N0
    244. 

  244. macro_inst|cfg_reg_inst|trig_auto_timeout[5] clken_ctrl_X58_Y9_N1
    245. 

  245. macro_inst|cfg_reg_inst|frequency[15] clken_ctrl_X58_Y9_N0
    246. 

  246. macro_inst|cfg_reg_inst|trig_auto_timeout[7] clken_ctrl_X58_Y9_N1
    247. 

  247. macro_inst|cfg_reg_inst|frequency[11] clken_ctrl_X58_Y9_N0
    248. 

  248. macro_inst|cfg_reg_inst|trig_auto_timeout[10] clken_ctrl_X58_Y9_N1
    249. 

  249. macro_inst|cfg_reg_inst|frequency[8] clken_ctrl_X58_Y9_N0
    250. 

  250. macro_inst|cfg_reg_inst|frequency[0] clken_ctrl_X58_Y9_N0
    251. 

  251. macro_inst|cfg_reg_inst|trig_auto_timeout[11] clken_ctrl_X58_Y9_N1
    252. 

  252. macro_inst|cfg_reg_inst|frequency[10] clken_ctrl_X58_Y9_N0
    253. 

  253. macro_inst|ahb2apb_inst|haddr[8] clken_ctrl_X59_Y10_N0
    254. 

  254. macro_inst|ahb2apb_inst|paddr[0] clken_ctrl_X59_Y10_N1
    255. 

  255. macro_inst|ahb2apb_inst|paddr[9] clken_ctrl_X59_Y10_N1
    256. 

  256. macro_inst|ahb2apb_inst|paddr[11] clken_ctrl_X59_Y10_N1
    257. 

  257. macro_inst|ahb2apb_inst|paddr[10] clken_ctrl_X59_Y10_N1
    258. 

  258. macro_inst|ahb2apb_inst|paddr[8] clken_ctrl_X59_Y10_N1
    259. 

  259. macro_inst|ahb2apb_inst|haddr[1] clken_ctrl_X59_Y10_N0
    260. 

  260. macro_inst|ahb2apb_inst|haddr[6] clken_ctrl_X59_Y10_N0
    261. 

  261. macro_inst|ahb2apb_inst|haddr[9] clken_ctrl_X59_Y10_N0
    262. 

  262. macro_inst|ahb2apb_inst|paddr[1] clken_ctrl_X59_Y10_N1
    263. 

  263. macro_inst|ahb2apb_inst|haddr[10] clken_ctrl_X59_Y10_N0
    264. 

  264. macro_inst|ahb2apb_inst|paddr[6] clken_ctrl_X59_Y10_N1
    265. 

  265. macro_inst|ahb2apb_inst|haddr[7] clken_ctrl_X59_Y10_N0
    266. 

  266. macro_inst|ahb2apb_inst|haddr[11] clken_ctrl_X59_Y10_N0
    267. 

  267. macro_inst|ahb2apb_inst|paddr[7] clken_ctrl_X59_Y10_N1
    268. 

  268. macro_inst|ahb2apb_inst|haddr[0] clken_ctrl_X59_Y10_N0
    269. 

  269. macro_inst|cfg_reg_inst|duty_cycle[3] clken_ctrl_X59_Y11_N0
    270. 

  270. macro_inst|cfg_reg_inst|duty_cycle[1] clken_ctrl_X59_Y11_N0
    271. 

  271. macro_inst|cfg_reg_inst|frequency[6] clken_ctrl_X59_Y11_N1
    272. 

  272. macro_inst|cfg_reg_inst|duty_cycle[0] clken_ctrl_X59_Y11_N0
    273. 

  273. macro_inst|cfg_reg_inst|duty_cycle[2] clken_ctrl_X59_Y11_N0
    274. 

  274. macro_inst|cfg_reg_inst|duty_cycle[5] clken_ctrl_X59_Y11_N0
    275. 

  275. macro_inst|cfg_reg_inst|frequency[1] clken_ctrl_X59_Y11_N1
    276. 

  276. macro_inst|cfg_reg_inst|duty_cycle[7] clken_ctrl_X59_Y11_N0
    277. 

  277. macro_inst|cfg_reg_inst|duty_cycle[4] clken_ctrl_X59_Y11_N0
    278. 

  278. macro_inst|cfg_reg_inst|frequency[3] clken_ctrl_X59_Y11_N1
    279. 

  279. macro_inst|cfg_reg_inst|frequency[2] clken_ctrl_X59_Y11_N1
    280. 

  280. macro_inst|cfg_reg_inst|frequency[7] clken_ctrl_X59_Y11_N1
    281. 

  281. macro_inst|cfg_reg_inst|duty_cycle[6] clken_ctrl_X59_Y11_N0
    282. 

  282. macro_inst|ahb2apb_inst|paddr[13] clken_ctrl_X59_Y12_N0
    283. 

  283. macro_inst|ahb2apb_inst|paddr[15] clken_ctrl_X59_Y12_N0
    284. 

  284. macro_inst|ahb2apb_inst|haddr[12] clken_ctrl_X59_Y12_N1
    285. 

  285. macro_inst|ahb2apb_inst|haddr[13] clken_ctrl_X59_Y12_N1
    286. 

  286. macro_inst|ahb2apb_inst|haddr[15] clken_ctrl_X59_Y12_N1
    287. 

  287. macro_inst|ahb2apb_inst|pwrite clken_ctrl_X59_Y12_N0
    288. 

  288. macro_inst|ahb2apb_inst|paddr[12] clken_ctrl_X59_Y12_N0
    289. 

  289. macro_inst|ahb2apb_inst|hwrite clken_ctrl_X59_Y12_N1
    290. 

  290. macro_inst|trig_ctrl_inst|eoc_cnt[0] clken_ctrl_X59_Y3_N1
    291. 

  291. macro_inst|trig_ctrl_inst|eoc_cnt[5] clken_ctrl_X59_Y3_N1
    292. 

  292. macro_inst|trig_ctrl_inst|eoc_cnt[6] clken_ctrl_X59_Y3_N1
    293. 

  293. macro_inst|trig_ctrl_inst|eoc_cnt[7] clken_ctrl_X59_Y3_N1
    294. 

  294. macro_inst|trig_ctrl_inst|eoc_cnt[8] clken_ctrl_X59_Y3_N1
    295. 

  295. macro_inst|trig_ctrl_inst|eoc_cnt[9] clken_ctrl_X59_Y3_N1
    296. 

  296. macro_inst|trig_ctrl_inst|eoc_cnt[1] clken_ctrl_X59_Y3_N1
    297. 

  297. macro_inst|trig_ctrl_inst|eoc_cnt[10] clken_ctrl_X59_Y3_N1
    298. 

  298. macro_inst|trig_ctrl_inst|eoc_cnt[11] clken_ctrl_X59_Y3_N1
    299. 

  299. macro_inst|trig_ctrl_inst|eoc_cnt[12] clken_ctrl_X59_Y3_N1
    300. 

  300. macro_inst|trig_ctrl_inst|eoc_cnt[13] clken_ctrl_X59_Y3_N1
    301. 

  301. macro_inst|trig_ctrl_inst|eoc_cnt[14] clken_ctrl_X59_Y3_N1
    302. 

  302. macro_inst|trig_ctrl_inst|eoc_cnt[15] clken_ctrl_X59_Y3_N1
    303. 

  303. macro_inst|trig_ctrl_inst|eoc_cnt[2] clken_ctrl_X59_Y3_N1
    304. 

  304. macro_inst|trig_ctrl_inst|eoc_cnt[3] clken_ctrl_X59_Y3_N1
    305. 

  305. macro_inst|trig_ctrl_inst|eoc_cnt[4] clken_ctrl_X59_Y3_N1
    306. 

  306. macro_inst|trig_ctrl_inst|adc_data_prev[11] clken_ctrl_X59_Y4_N0
    307. 

  307. macro_inst|trig_ctrl_inst|adc_data_prev[10] clken_ctrl_X59_Y4_N0
    308. 

  308. macro_inst|trig_ctrl_inst|gap_cnt_auto[0] clken_ctrl_X59_Y5_N1
    309. 

  309. macro_inst|trig_ctrl_inst|gap_cnt_auto[5] clken_ctrl_X59_Y5_N1
    310. 

  310. macro_inst|trig_ctrl_inst|gap_cnt_auto[6] clken_ctrl_X59_Y5_N1
    311. 

  311. macro_inst|trig_ctrl_inst|gap_cnt_auto[7] clken_ctrl_X59_Y5_N1
    312. 

  312. macro_inst|trig_ctrl_inst|gap_cnt_auto[8] clken_ctrl_X59_Y5_N1
    313. 

  313. macro_inst|trig_ctrl_inst|gap_cnt_auto[9] clken_ctrl_X59_Y5_N1
    314. 

  314. macro_inst|trig_ctrl_inst|gap_cnt_auto[1] clken_ctrl_X59_Y5_N1
    315. 

  315. macro_inst|trig_ctrl_inst|gap_cnt_auto[10] clken_ctrl_X59_Y5_N1
    316. 

  316. macro_inst|trig_ctrl_inst|gap_cnt_auto[2] clken_ctrl_X59_Y5_N1
    317. 

  317. macro_inst|trig_ctrl_inst|gap_cnt_auto[3] clken_ctrl_X59_Y5_N1
    318. 

  318. macro_inst|trig_ctrl_inst|gap_cnt_auto[4] clken_ctrl_X59_Y5_N1
    319. 

  319. macro_inst|cfg_reg_inst|trig_time_slot[0] clken_ctrl_X59_Y6_N0
    320. 

  320. macro_inst|cfg_reg_inst|trig_auto_timeout[8] clken_ctrl_X59_Y6_N1
    321. 

  321. macro_inst|cfg_reg_inst|trig_mode[1] clken_ctrl_X59_Y6_N0
    322. 

  322. macro_inst|cfg_reg_inst|trig_time_slot[4] clken_ctrl_X59_Y6_N0
    323. 

  323. macro_inst|cfg_reg_inst|trig_auto_timeout[4] clken_ctrl_X59_Y6_N1
    324. 

  324. macro_inst|cfg_reg_inst|trig_auto_timeout[3] clken_ctrl_X59_Y6_N1
    325. 

  325. macro_inst|cfg_reg_inst|trig_mode[0] clken_ctrl_X59_Y6_N0
    326. 

  326. macro_inst|trig_ctrl_inst|pulse_level clken_ctrl_X59_Y7_N0
    327. 

  327. macro_inst|trig_ctrl_inst|adc_rst_sync1 clken_ctrl_X59_Y7_N0
    328. 

  328. macro_inst|trig_ctrl_inst|adc_rst_sync2 clken_ctrl_X59_Y7_N0
    329. 

  329. macro_inst|trig_ctrl_inst|pulse_trigger clken_ctrl_X59_Y7_N0
    330. 

  330. macro_inst|trig_ctrl_inst|pulse_active clken_ctrl_X59_Y7_N0
    331. 

  331. macro_inst|trig_ctrl_inst|prdata[9] clken_ctrl_X59_Y8_N0
    332. 

  332. macro_inst|ahb2apb_inst|prdata[1] clken_ctrl_X59_Y8_N1
    333. 

  333. macro_inst|ahb2apb_inst|prdata[8] clken_ctrl_X59_Y8_N1
    334. 

  334. macro_inst|ahb2apb_inst|prdata[22] clken_ctrl_X59_Y8_N1
    335. 

  335. macro_inst|ahb2apb_inst|prdata[17] clken_ctrl_X59_Y8_N1
    336. 

  336. macro_inst|trig_ctrl_inst|prdata[4] clken_ctrl_X59_Y8_N0
    337. 

  337. macro_inst|trig_ctrl_inst|prdata[5] clken_ctrl_X59_Y8_N0
    338. 

  338. macro_inst|ahb2apb_inst|prdata[6] clken_ctrl_X59_Y8_N1
    339. 

  339. macro_inst|trig_ctrl_inst|prdata[6] clken_ctrl_X59_Y8_N0
    340. 

  340. macro_inst|ahb2apb_inst|prdata[5] clken_ctrl_X59_Y8_N1
    341. 

  341. macro_inst|ahb2apb_inst|prdata[0] clken_ctrl_X59_Y8_N1
    342. 

  342. macro_inst|ahb2apb_inst|prdata[4] clken_ctrl_X59_Y8_N1
    343. 

  343. macro_inst|cfg_reg_inst|prdata[4] clken_ctrl_X59_Y9_N0
    344. 

  344. macro_inst|cfg_reg_inst|prdata[14] clken_ctrl_X59_Y9_N0
    345. 

  345. macro_inst|cfg_reg_inst|prdata[8] clken_ctrl_X59_Y9_N0
    346. 

  346. macro_inst|cfg_reg_inst|prdata[7] clken_ctrl_X59_Y9_N0
    347. 

  347. macro_inst|cfg_reg_inst|frequency[4] clken_ctrl_X59_Y9_N1
    348. 

  348. macro_inst|cfg_reg_inst|prdata[5] clken_ctrl_X59_Y9_N0
    349. 

  349. macro_inst|cfg_reg_inst|frequency[14] clken_ctrl_X59_Y9_N1
    350. 

  350. macro_inst|ahb2apb_inst|paddr[5] clken_ctrl_X60_Y10_N0
    351. 

  351. macro_inst|ahb2apb_inst|paddr[3] clken_ctrl_X60_Y10_N0
    352. 

  352. macro_inst|ahb2apb_inst|haddr[14] clken_ctrl_X60_Y10_N1
    353. 

  353. macro_inst|ahb2apb_inst|haddr[5] clken_ctrl_X60_Y10_N1
    354. 

  354. macro_inst|ahb2apb_inst|haddr[2] clken_ctrl_X60_Y10_N1
    355. 

  355. macro_inst|ahb2apb_inst|paddr[2] clken_ctrl_X60_Y10_N0
    356. 

  356. macro_inst|ahb2apb_inst|paddr[4] clken_ctrl_X60_Y10_N0
    357. 

  357. macro_inst|ahb2apb_inst|haddr[3] clken_ctrl_X60_Y10_N1
    358. 

  358. macro_inst|ahb2apb_inst|haddr[4] clken_ctrl_X60_Y10_N1
    359. 

  359. macro_inst|cfg_reg_inst|adc_chnl_sel[2] clken_ctrl_X60_Y11_N0
    360. 

  360. macro_inst|cfg_reg_inst|prdata[1] clken_ctrl_X60_Y11_N1
    361. 

  361. macro_inst|cfg_reg_inst|adc_chnl_sel[0] clken_ctrl_X60_Y11_N0
    362. 

  362. macro_inst|cfg_reg_inst|adc_chnl_sel[1] clken_ctrl_X60_Y11_N0
    363. 

  363. macro_inst|cfg_reg_inst|prdata[3] clken_ctrl_X60_Y11_N1
    364. 

  364. macro_inst|cfg_reg_inst|prdata[2] clken_ctrl_X60_Y11_N1
    365. 

  365. macro_inst|ahb2apb_inst|paddr[14] clken_ctrl_X60_Y12_N0
    366. 

  366. macro_inst|trig_ctrl_inst|curr_state.SAMPLING clken_ctrl_X60_Y3_N0
    367. 

  367. macro_inst|cfg_reg_inst|adc_en clken_ctrl_X60_Y3_N1
    368. 

  368. macro_inst|trig_ctrl_inst|adc_eoc_sync2 clken_ctrl_X60_Y3_N0
    369. 

  369. macro_inst|trig_ctrl_inst|write_strobe clken_ctrl_X60_Y3_N0
    370. 

  370. macro_inst|trig_ctrl_inst|single_shot_lock clken_ctrl_X60_Y3_N0
    371. 

  371. macro_inst|trig_ctrl_inst|curr_state.PRE_FILL clken_ctrl_X60_Y3_N0
    372. 

  372. macro_inst|cfg_reg_inst|trig_time_slot[3] clken_ctrl_X60_Y4_N0
    373. 

  373. macro_inst|cfg_reg_inst|trig_time_slot[1] clken_ctrl_X60_Y4_N0
    374. 

  374. macro_inst|trig_ctrl_inst|trigger_ptr[1] clken_ctrl_X60_Y5_N0
    375. 

  375. macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] clken_ctrl_X60_Y5_N0
    376. 

  376. macro_inst|trig_ctrl_inst|trigger_ptr[0] clken_ctrl_X60_Y5_N0
    377. 

  377. macro_inst|trig_ctrl_inst|trigger_ptr[3] clken_ctrl_X60_Y5_N0
    378. 

  378. macro_inst|trig_ctrl_inst|trigger_ptr[5] clken_ctrl_X60_Y5_N0
    379. 

  379. macro_inst|trig_ctrl_inst|trigger_ptr[7] clken_ctrl_X60_Y5_N0
    380. 

  380. macro_inst|trig_ctrl_inst|trigger_ptr[9] clken_ctrl_X60_Y5_N0
    381. 

  381. macro_inst|trig_ctrl_inst|trig_hit_reg clken_ctrl_X60_Y5_N1
    382. 

  382. macro_inst|trig_ctrl_inst|trigger_ptr[4] clken_ctrl_X60_Y5_N0
    383. 

  383. macro_inst|trig_ctrl_inst|trigger_ptr[6] clken_ctrl_X60_Y5_N0
    384. 

  384. macro_inst|cfg_reg_inst|trig_edge[1] clken_ctrl_X60_Y6_N0
    385. 

  385. macro_inst|cfg_reg_inst|trig_auto_timeout[1] clken_ctrl_X60_Y6_N1
    386. 

  386. macro_inst|cfg_reg_inst|trig_edge[0] clken_ctrl_X60_Y6_N0
    387. 

  387. macro_inst|cfg_reg_inst|trig_time_slot[2] clken_ctrl_X60_Y6_N0
    388. 

  388. macro_inst|cfg_reg_inst|trig_auto_timeout[0] clken_ctrl_X60_Y6_N1
    389. 

  389. macro_inst|cfg_reg_inst|trig_auto_timeout[6] clken_ctrl_X60_Y6_N1
    390. 

  390. macro_inst|cfg_reg_inst|trig_pulse_width[13] clken_ctrl_X60_Y7_N0
    391. 

  391. macro_inst|cfg_reg_inst|trig_pulse_width[14] clken_ctrl_X60_Y7_N0
    392. 

  392. macro_inst|cfg_reg_inst|trig_pulse_width[15] clken_ctrl_X60_Y7_N0
    393. 

  393. macro_inst|cfg_reg_inst|trig_auto_timeout[9] clken_ctrl_X60_Y7_N1
    394. 

  394. macro_inst|cfg_reg_inst|trig_pulse_width[9] clken_ctrl_X60_Y7_N0
    395. 

  395. macro_inst|cfg_reg_inst|trig_auto_timeout[2] clken_ctrl_X60_Y7_N1
    396. 

  396. macro_inst|cfg_reg_inst|trig_auto_timeout[15] clken_ctrl_X60_Y7_N1
    397. 

  397. macro_inst|cfg_reg_inst|trig_auto_timeout[14] clken_ctrl_X60_Y7_N1
    398. 

  398. macro_inst|cfg_reg_inst|trig_auto_timeout[12] clken_ctrl_X60_Y7_N1
    399. 

  399. macro_inst|cfg_reg_inst|trig_auto_timeout[13] clken_ctrl_X60_Y7_N1
    400. 

  400. macro_inst|cfg_reg_inst|trig_pulse_width[8] clken_ctrl_X60_Y7_N0
    401. 

  401. macro_inst|cfg_reg_inst|trig_pulse_width[10] clken_ctrl_X60_Y7_N0
    402. 

  402. macro_inst|cfg_reg_inst|trig_pulse_width[11] clken_ctrl_X60_Y7_N0
    403. 

  403. macro_inst|cfg_reg_inst|trig_pulse_width[12] clken_ctrl_X60_Y7_N0
    404. 

  404. macro_inst|cfg_reg_inst|trig_pulse_width[4] clken_ctrl_X60_Y8_N0
    405. 

  405. macro_inst|cfg_reg_inst|trig_pulse_width[0] clken_ctrl_X60_Y8_N0
    406. 

  406. macro_inst|cfg_reg_inst|trig_pulse_width[3] clken_ctrl_X60_Y8_N0
    407. 

  407. macro_inst|cfg_reg_inst|trig_pulse_width[6] clken_ctrl_X60_Y8_N0
    408. 

  408. macro_inst|cfg_reg_inst|max_vol[0] clken_ctrl_X60_Y8_N1
    409. 

  409. macro_inst|cfg_reg_inst|trig_pulse_width[1] clken_ctrl_X60_Y8_N0
    410. 

  410. macro_inst|cfg_reg_inst|max_vol[4] clken_ctrl_X60_Y8_N1
    411. 

  411. macro_inst|cfg_reg_inst|trig_pulse_width[5] clken_ctrl_X60_Y8_N0
    412. 

  412. macro_inst|cfg_reg_inst|max_vol[6] clken_ctrl_X60_Y8_N1
    413. 

  413. macro_inst|cfg_reg_inst|trig_pulse_width[7] clken_ctrl_X60_Y8_N0
    414. 

  414. macro_inst|cfg_reg_inst|trig_pulse_width[2] clken_ctrl_X60_Y8_N0
    415. 

  415. macro_inst|cfg_reg_inst|max_vol[3] clken_ctrl_X60_Y8_N1
    416. 

  416. macro_inst|cfg_reg_inst|max_vol[2] clken_ctrl_X60_Y8_N1
    417. 

  417. macro_inst|cfg_reg_inst|adc_chnl_sel[3] clken_ctrl_X60_Y9_N0
    418. 

  418. macro_inst|cfg_reg_inst|adc_clk_div[7] clken_ctrl_X60_Y9_N1
    419. 

  419. macro_inst|cfg_reg_inst|adc_clk_div[5] clken_ctrl_X60_Y9_N1
    420. 

  420. macro_inst|cfg_reg_inst|adc_clk_div[3] clken_ctrl_X60_Y9_N1
    421. 

  421. macro_inst|cfg_reg_inst|adc_clk_div[4] clken_ctrl_X60_Y9_N1
    422. 

  422. macro_inst|cfg_reg_inst|adc_clk_div[2] clken_ctrl_X60_Y9_N1
    423. 

  423. macro_inst|cfg_reg_inst|adc_clk_div[6] clken_ctrl_X61_Y10_N1
    424. 

  424. macro_inst|cfg_reg_inst|adc_clk_div[1] clken_ctrl_X61_Y10_N1
    425. 

  425. macro_inst|cfg_reg_inst|adc_clk_div[0] clken_ctrl_X61_Y10_N1
    426. 

  426. macro_inst|apb_adc0_inst|sclk clken_ctrl_X61_Y10_N0
    427. 

  427. macro_inst|trig_ctrl_inst|trigger_ptr[8] clken_ctrl_X61_Y5_N0
    428. 

  428. macro_inst|trig_ctrl_inst|trigger_ptr[2] clken_ctrl_X61_Y5_N0
    429. 

  429. macro_inst|trig_ctrl_inst|curr_state.POST_TRIG clken_ctrl_X61_Y6_N0
    430. 

  430. macro_inst|trig_ctrl_inst|adc_rst_sync3 clken_ctrl_X61_Y6_N0
    431. 

  431. macro_inst|trig_ctrl_inst|curr_state.DONE clken_ctrl_X61_Y6_N0
    432. 

  432. macro_inst|trig_ctrl_inst|curr_state.IDLE clken_ctrl_X61_Y6_N0
    433. 

  433. macro_inst|cfg_reg_inst|adc_run clken_ctrl_X61_Y6_N1
    434. 

  434. macro_inst|trig_ctrl_inst|trig_done clken_ctrl_X61_Y6_N0
    435. 

  435. macro_inst|cfg_reg_inst|prdata[6] clken_ctrl_X61_Y8_N0
    436. 

  436. macro_inst|trig_ctrl_inst|prdata[2] clken_ctrl_X61_Y8_N1
    437. 

  437. macro_inst|trig_ctrl_inst|prdata[0] clken_ctrl_X61_Y8_N1
    438. 

  438. macro_inst|trig_ctrl_inst|prdata[3] clken_ctrl_X61_Y8_N1
    439. 

  439. macro_inst|cfg_reg_inst|prdata[0] clken_ctrl_X61_Y8_N0
    440. 

  440. macro_inst|trig_ctrl_inst|prdata[8] clken_ctrl_X61_Y8_N1
    441. 

  441. macro_inst|trig_ctrl_inst|prdata[1] clken_ctrl_X61_Y8_N1
    442. 

  442. macro_inst|trig_ctrl_inst|prdata[7] clken_ctrl_X61_Y8_N1
    443. 

  443. macro_inst|cfg_reg_inst|dac_run clken_ctrl_X61_Y9_N0
    444. 

  444. macro_inst|cfg_reg_inst|adc_restart clken_ctrl_X61_Y9_N1
    445. 

  445. macro_inst|cfg_reg_inst|dac_en clken_ctrl_X61_Y9_N0
    446. 

  446. macro_inst|apb_adc0_inst|sclk_counter[0] clken_ctrl_X62_Y10_N0
    447. 

  447. macro_inst|apb_adc0_inst|sclk_counter[5] clken_ctrl_X62_Y10_N0
    448. 

  448. macro_inst|apb_adc0_inst|sclk_counter[6] clken_ctrl_X62_Y10_N0
    449. 

  449. macro_inst|apb_adc0_inst|sclk_counter[7] clken_ctrl_X62_Y10_N0
    450. 

  450. macro_inst|apb_adc0_inst|sclk_counter[8] clken_ctrl_X62_Y10_N0
    451. 

  451. macro_inst|apb_adc0_inst|sclk_counter[9] clken_ctrl_X62_Y10_N0
    452. 

  452. macro_inst|apb_adc0_inst|sclk_counter[1] clken_ctrl_X62_Y10_N0
    453. 

  453. macro_inst|apb_adc0_inst|sclk_counter[10] clken_ctrl_X62_Y10_N0
    454. 

  454. macro_inst|apb_adc0_inst|sclk_counter[11] clken_ctrl_X62_Y10_N0
    455. 

  455. macro_inst|apb_adc0_inst|sclk_counter[12] clken_ctrl_X62_Y10_N0
    456. 

  456. macro_inst|apb_adc0_inst|sclk_counter[13] clken_ctrl_X62_Y10_N0
    457. 

  457. macro_inst|apb_adc0_inst|sclk_counter[14] clken_ctrl_X62_Y10_N0
    458. 

  458. macro_inst|apb_adc0_inst|sclk_counter[15] clken_ctrl_X62_Y10_N0
    459. 

  459. macro_inst|apb_adc0_inst|sclk_counter[2] clken_ctrl_X62_Y10_N0
    460. 

  460. macro_inst|apb_adc0_inst|sclk_counter[3] clken_ctrl_X62_Y10_N0
    461. 

  461. macro_inst|apb_adc0_inst|sclk_counter[4] clken_ctrl_X62_Y10_N0
    462. 

  462. macro_inst|trig_ctrl_inst|decim_factor[10] clken_ctrl_X62_Y3_N0
    463. 

  463. macro_inst|trig_ctrl_inst|decim_factor[14] clken_ctrl_X62_Y3_N0
    464. 

  464. macro_inst|trig_ctrl_inst|decim_factor[8] clken_ctrl_X62_Y3_N0
    465. 

  465. macro_inst|trig_ctrl_inst|decim_factor[9] clken_ctrl_X62_Y3_N0
    466. 

  466. macro_inst|trig_ctrl_inst|decim_factor[13] clken_ctrl_X62_Y3_N0
    467. 

  467. macro_inst|trig_ctrl_inst|decim_factor[11] clken_ctrl_X62_Y3_N0
    468. 

  468. macro_inst|trig_ctrl_inst|decim_factor[6] clken_ctrl_X62_Y4_N0
    469. 

  469. macro_inst|trig_ctrl_inst|decim_factor[0] clken_ctrl_X62_Y4_N0
    470. 

  470. macro_inst|trig_ctrl_inst|decim_factor[1] clken_ctrl_X62_Y4_N0
    471. 

  471. macro_inst|trig_ctrl_inst|decim_factor[2] clken_ctrl_X62_Y4_N0
    472. 

  472. macro_inst|trig_ctrl_inst|decim_factor[4] clken_ctrl_X62_Y4_N0
    473. 

  473. macro_inst|trig_ctrl_inst|decim_factor[5] clken_ctrl_X62_Y4_N0
    474. 

  474. macro_inst|trig_ctrl_inst|decim_factor[7] clken_ctrl_X62_Y4_N0
    475. 

  475. macro_inst|trig_ctrl_inst|decim_factor[3] clken_ctrl_X62_Y4_N0
    476. 

  476. macro_inst|trig_ctrl_inst|ram_wr_addr[0] clken_ctrl_X62_Y5_N1
    477. 

  477. macro_inst|trig_ctrl_inst|ram_wr_addr[1] clken_ctrl_X62_Y5_N1
    478. 

  478. macro_inst|trig_ctrl_inst|ram_wr_addr[2] clken_ctrl_X62_Y5_N1
    479. 

  479. macro_inst|trig_ctrl_inst|ram_wr_addr[3] clken_ctrl_X62_Y5_N1
    480. 

  480. macro_inst|trig_ctrl_inst|ram_wr_addr[4] clken_ctrl_X62_Y5_N1
    481. 

  481. macro_inst|trig_ctrl_inst|ram_wr_addr[5] clken_ctrl_X62_Y5_N1
    482. 

  482. macro_inst|trig_ctrl_inst|ram_wr_addr[6] clken_ctrl_X62_Y5_N1
    483. 

  483. macro_inst|trig_ctrl_inst|ram_wr_addr[7] clken_ctrl_X62_Y5_N1
    484. 

  484. macro_inst|trig_ctrl_inst|ram_wr_addr[8] clken_ctrl_X62_Y5_N1
    485. 

  485. macro_inst|trig_ctrl_inst|ram_wr_addr[9] clken_ctrl_X62_Y5_N1
    486. 

  486. macro_inst|trig_ctrl_inst|post_trig_cnt[2] clken_ctrl_X62_Y6_N1
    487. 

  487. macro_inst|trig_ctrl_inst|post_trig_cnt[3] clken_ctrl_X62_Y6_N1
    488. 

  488. macro_inst|trig_ctrl_inst|post_trig_cnt[4] clken_ctrl_X62_Y6_N1
    489. 

  489. macro_inst|trig_ctrl_inst|post_trig_cnt[5] clken_ctrl_X62_Y6_N1
    490. 

  490. macro_inst|trig_ctrl_inst|post_trig_cnt[6] clken_ctrl_X62_Y6_N1
    491. 

  491. macro_inst|trig_ctrl_inst|post_trig_cnt[7] clken_ctrl_X62_Y6_N1
    492. 

  492. macro_inst|trig_ctrl_inst|post_trig_cnt[8] clken_ctrl_X62_Y6_N1
    493. 

  493. macro_inst|trig_ctrl_inst|post_trig_cnt[0] clken_ctrl_X62_Y6_N1
    494. 

  494. macro_inst|trig_ctrl_inst|post_trig_cnt[1] clken_ctrl_X62_Y6_N1
    495. 

  495. macro_inst|apb_dac0_inst|phase_r[2] clken_ctrl_X62_Y9_N0
    496. 

  496. macro_inst|apb_dac0_inst|phase_r[3] clken_ctrl_X62_Y9_N0
    497.