macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~porta_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a9~portb_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a9
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~porta_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_address_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_datain_reg0 macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
macro_inst|u_dual_port_ram|auto_generated|ram_block1a0~portb_we_reg macro_inst|u_dual_port_ram|auto_generated|ram_block1a0
pll_inst|auto_generated|pll_lock_sync clken_ctrl_X46_Y1_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[6] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[4] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[0] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[5] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[11] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[7] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[8] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[3] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[1] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wren_b clken_ctrl_X54_Y4_N1
macro_inst|trig_ctrl_inst|ram_wr_data_b[2] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[10] clken_ctrl_X54_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_data_b[9] clken_ctrl_X54_Y4_N0
macro_inst|ahb2apb_inst|prdata[31] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[12] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[30] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[26] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[10] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[21] clken_ctrl_X56_Y10_N0
macro_inst|cfg_reg_inst|prdata[29] clken_ctrl_X56_Y10_N1
macro_inst|ahb2apb_inst|prdata[28] clken_ctrl_X56_Y10_N0
macro_inst|cfg_reg_inst|prdata[26] clken_ctrl_X56_Y10_N1
macro_inst|ahb2apb_inst|prdata[29] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[11] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[15] clken_ctrl_X56_Y10_N0
macro_inst|cfg_reg_inst|prdata[30] clken_ctrl_X56_Y10_N1
macro_inst|ahb2apb_inst|prdata[14] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[27] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[13] clken_ctrl_X56_Y10_N0
macro_inst|ahb2apb_inst|prdata[19] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[7] clken_ctrl_X56_Y11_N0
macro_inst|cfg_reg_inst|frequency[25] clken_ctrl_X56_Y11_N1
macro_inst|cfg_reg_inst|frequency[12] clken_ctrl_X56_Y11_N1
macro_inst|ahb2apb_inst|prdata[9] clken_ctrl_X56_Y11_N0
macro_inst|cfg_reg_inst|frequency[18] clken_ctrl_X56_Y11_N1
macro_inst|cfg_reg_inst|frequency[16] clken_ctrl_X56_Y11_N1
macro_inst|cfg_reg_inst|frequency[23] clken_ctrl_X56_Y11_N1
macro_inst|ahb2apb_inst|prdata[23] clken_ctrl_X56_Y11_N0
macro_inst|cfg_reg_inst|frequency[9] clken_ctrl_X56_Y11_N1
macro_inst|ahb2apb_inst|prdata[20] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[3] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[25] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[2] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[18] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[16] clken_ctrl_X56_Y11_N0
macro_inst|ahb2apb_inst|prdata[24] clken_ctrl_X56_Y12_N0
macro_inst|apb_adc0_inst|apb_db[7] clken_ctrl_X56_Y4_N0
macro_inst|apb_adc0_inst|apb_db[9] clken_ctrl_X56_Y4_N0
macro_inst|apb_adc0_inst|apb_eoc clken_ctrl_X56_Y4_N1
macro_inst|apb_adc0_inst|apb_db[5] clken_ctrl_X56_Y4_N0
macro_inst|trig_ctrl_inst|adc_eoc_sync1 clken_ctrl_X56_Y4_N1
macro_inst|apb_adc0_inst|apb_db[1] clken_ctrl_X56_Y4_N0
macro_inst|apb_adc0_inst|apb_db[3] clken_ctrl_X56_Y4_N0
macro_inst|apb_dac0_inst|max_vol_r[3] clken_ctrl_X56_Y8_N0
macro_inst|apb_dac0_inst|max_vol_r[6] clken_ctrl_X56_Y8_N0
macro_inst|apb_dac0_inst|max_vol_r[4] clken_ctrl_X56_Y8_N0
macro_inst|apb_dac0_inst|max_vol_r[0] clken_ctrl_X56_Y8_N0
macro_inst|cfg_reg_inst|frequency[26] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|prdata[12] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|prdata[15] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|frequency[28] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|frequency[13] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|frequency[29] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|frequency[31] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|prdata[21] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|frequency[27] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|prdata[13] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|prdata[27] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|prdata[28] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|frequency[30] clken_ctrl_X57_Y10_N0
macro_inst|cfg_reg_inst|prdata[31] clken_ctrl_X57_Y10_N1
macro_inst|cfg_reg_inst|max_vol[9] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|prdata[16] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|min_vol[4] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|min_vol[0] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|prdata[25] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|prdata[23] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|prdata[19] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|min_vol[3] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|max_vol[7] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|prdata[18] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|min_vol[2] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|min_vol[7] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|min_vol[9] clken_ctrl_X57_Y11_N0
macro_inst|cfg_reg_inst|prdata[20] clken_ctrl_X57_Y11_N1
macro_inst|cfg_reg_inst|frequency[19] clken_ctrl_X57_Y12_N0
macro_inst|cfg_reg_inst|frequency[20] clken_ctrl_X57_Y12_N0
macro_inst|cfg_reg_inst|min_vol[8] clken_ctrl_X57_Y12_N1
macro_inst|cfg_reg_inst|frequency[24] clken_ctrl_X57_Y12_N0
macro_inst|cfg_reg_inst|min_vol[6] clken_ctrl_X57_Y12_N1
macro_inst|cfg_reg_inst|frequency[21] clken_ctrl_X57_Y12_N0
macro_inst|cfg_reg_inst|frequency[22] clken_ctrl_X57_Y12_N0
macro_inst|cfg_reg_inst|min_vol[5] clken_ctrl_X57_Y12_N1
macro_inst|apb_dac0_inst|phase_r[9] clken_ctrl_X57_Y3_N0
macro_inst|apb_dac0_inst|phase_r[8] clken_ctrl_X57_Y3_N0
macro_inst|apb_adc0_inst|apb_db[0] clken_ctrl_X57_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[3] clken_ctrl_X57_Y4_N1
macro_inst|apb_adc0_inst|apb_db[4] clken_ctrl_X57_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[5] clken_ctrl_X57_Y4_N1
macro_inst|apb_adc0_inst|apb_db[6] clken_ctrl_X57_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[11] clken_ctrl_X57_Y4_N1
macro_inst|cfg_reg_inst|trig_threshold[7] clken_ctrl_X57_Y4_N1
macro_inst|apb_adc0_inst|apb_db[8] clken_ctrl_X57_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[9] clken_ctrl_X57_Y4_N1
macro_inst|apb_adc0_inst|apb_db[10] clken_ctrl_X57_Y4_N0
macro_inst|apb_adc0_inst|apb_db[11] clken_ctrl_X57_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[1] clken_ctrl_X57_Y4_N1
macro_inst|apb_adc0_inst|apb_db[2] clken_ctrl_X57_Y4_N0
macro_inst|apb_dac0_inst|phase_r[6] clken_ctrl_X57_Y6_N0
macro_inst|apb_dac0_inst|phase_r[5] clken_ctrl_X57_Y6_N0
macro_inst|cfg_reg_inst|prdata[11] clken_ctrl_X57_Y7_N0
macro_inst|cfg_reg_inst|prdata[9] clken_ctrl_X57_Y7_N0
macro_inst|apb_dac0_inst|min_vol_r[2] clken_ctrl_X57_Y7_N1
macro_inst|apb_dac0_inst|max_vol_r[9] clken_ctrl_X57_Y7_N1
macro_inst|cfg_reg_inst|prdata[10] clken_ctrl_X57_Y7_N0
macro_inst|apb_dac0_inst|max_vol_r[1] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[7] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[8] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[9] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[1] clken_ctrl_X57_Y8_N0
macro_inst|cfg_reg_inst|prdata[17] clken_ctrl_X57_Y8_N1
macro_inst|cfg_reg_inst|prdata[24] clken_ctrl_X57_Y8_N1
macro_inst|cfg_reg_inst|prdata[22] clken_ctrl_X57_Y8_N1
macro_inst|apb_dac0_inst|min_vol_r[0] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[6] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[5] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[3] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|min_vol_r[4] clken_ctrl_X57_Y8_N0
macro_inst|apb_dac0_inst|max_vol_r[2] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|phase_r[4] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|max_vol_r[5] clken_ctrl_X57_Y9_N0
macro_inst|cfg_reg_inst|max_vol[8] clken_ctrl_X57_Y9_N1
macro_inst|apb_dac0_inst|phase_r[0] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|phase_r[7] clken_ctrl_X57_Y9_N0
macro_inst|cfg_reg_inst|max_vol[5] clken_ctrl_X57_Y9_N1
macro_inst|apb_dac0_inst|phase_r[1] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|max_vol_r[8] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|max_vol_r[7] clken_ctrl_X57_Y9_N0
macro_inst|apb_dac0_inst|phase_acc[16] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[21] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[22] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[23] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[24] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[25] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[17] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[26] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[27] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[28] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[29] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[30] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[31] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[18] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[19] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[20] clken_ctrl_X58_Y10_N0
macro_inst|apb_dac0_inst|phase_acc[0] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[5] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[6] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[7] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[8] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[9] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[1] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[10] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[11] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[12] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[13] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[14] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[15] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[2] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[3] clken_ctrl_X58_Y11_N0
macro_inst|apb_dac0_inst|phase_acc[4] clken_ctrl_X58_Y11_N0
macro_inst|ahb2apb_inst|pvalid clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|apbState.apbIdle clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|hreadyout clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|penable clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|apbState.apbSetup clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|hdone clken_ctrl_X58_Y12_N0
macro_inst|pr_select[0] clken_ctrl_X58_Y12_N1
macro_inst|ahb2apb_inst|psel clken_ctrl_X58_Y12_N0
macro_inst|ahb2apb_inst|pdone clken_ctrl_X58_Y12_N0
macro_inst|pr_select[2] clken_ctrl_X58_Y12_N1
macro_inst|pr_select[1] clken_ctrl_X58_Y12_N1
macro_inst|pr_select[3] clken_ctrl_X58_Y12_N1
macro_inst|cfg_reg_inst|trig_threshold[4] clken_ctrl_X58_Y4_N0
macro_inst|trig_ctrl_inst|adc_data_prev[4] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[1] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[2] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[6] clken_ctrl_X58_Y4_N1
macro_inst|cfg_reg_inst|trig_threshold[8] clken_ctrl_X58_Y4_N0
macro_inst|trig_ctrl_inst|adc_data_prev[9] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[3] clken_ctrl_X58_Y4_N1
macro_inst|cfg_reg_inst|trig_threshold[10] clken_ctrl_X58_Y4_N0
macro_inst|trig_ctrl_inst|adc_data_prev[0] clken_ctrl_X58_Y4_N1
macro_inst|cfg_reg_inst|trig_threshold[0] clken_ctrl_X58_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[6] clken_ctrl_X58_Y4_N0
macro_inst|cfg_reg_inst|trig_threshold[2] clken_ctrl_X58_Y4_N0
macro_inst|trig_ctrl_inst|adc_data_prev[7] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[5] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|adc_data_prev[8] clken_ctrl_X58_Y4_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[0] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[5] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[6] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[7] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[8] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[9] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[1] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[2] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[3] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|auto_wait_cnt[4] clken_ctrl_X58_Y6_N1
macro_inst|trig_ctrl_inst|pulse_cnt[0] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[5] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[6] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[7] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[8] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[9] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[1] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[10] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[11] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[12] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[13] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[14] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[15] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[2] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[3] clken_ctrl_X58_Y7_N1
macro_inst|trig_ctrl_inst|pulse_cnt[4] clken_ctrl_X58_Y7_N1
macro_inst|cfg_reg_inst|min_vol[1] clken_ctrl_X58_Y8_N0
macro_inst|cfg_reg_inst|wave_type[0] clken_ctrl_X58_Y8_N1
macro_inst|cfg_reg_inst|wave_type[1] clken_ctrl_X58_Y8_N1
macro_inst|cfg_reg_inst|max_vol[1] clken_ctrl_X58_Y8_N0
macro_inst|cfg_reg_inst|frequency[5] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|frequency[17] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[5] clken_ctrl_X58_Y9_N1
macro_inst|cfg_reg_inst|frequency[15] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[7] clken_ctrl_X58_Y9_N1
macro_inst|cfg_reg_inst|frequency[11] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[10] clken_ctrl_X58_Y9_N1
macro_inst|cfg_reg_inst|frequency[8] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|frequency[0] clken_ctrl_X58_Y9_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[11] clken_ctrl_X58_Y9_N1
macro_inst|cfg_reg_inst|frequency[10] clken_ctrl_X58_Y9_N0
macro_inst|ahb2apb_inst|haddr[8] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|paddr[0] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|paddr[9] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|paddr[11] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|paddr[10] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|paddr[8] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|haddr[1] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|haddr[6] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|haddr[9] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|paddr[1] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|haddr[10] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|paddr[6] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|haddr[7] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|haddr[11] clken_ctrl_X59_Y10_N0
macro_inst|ahb2apb_inst|paddr[7] clken_ctrl_X59_Y10_N1
macro_inst|ahb2apb_inst|haddr[0] clken_ctrl_X59_Y10_N0
macro_inst|cfg_reg_inst|duty_cycle[3] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|duty_cycle[1] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|frequency[6] clken_ctrl_X59_Y11_N1
macro_inst|cfg_reg_inst|duty_cycle[0] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|duty_cycle[2] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|duty_cycle[5] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|frequency[1] clken_ctrl_X59_Y11_N1
macro_inst|cfg_reg_inst|duty_cycle[7] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|duty_cycle[4] clken_ctrl_X59_Y11_N0
macro_inst|cfg_reg_inst|frequency[3] clken_ctrl_X59_Y11_N1
macro_inst|cfg_reg_inst|frequency[2] clken_ctrl_X59_Y11_N1
macro_inst|cfg_reg_inst|frequency[7] clken_ctrl_X59_Y11_N1
macro_inst|cfg_reg_inst|duty_cycle[6] clken_ctrl_X59_Y11_N0
macro_inst|ahb2apb_inst|paddr[13] clken_ctrl_X59_Y12_N0
macro_inst|ahb2apb_inst|paddr[15] clken_ctrl_X59_Y12_N0
macro_inst|ahb2apb_inst|haddr[12] clken_ctrl_X59_Y12_N1
macro_inst|ahb2apb_inst|haddr[13] clken_ctrl_X59_Y12_N1
macro_inst|ahb2apb_inst|haddr[15] clken_ctrl_X59_Y12_N1
macro_inst|ahb2apb_inst|pwrite clken_ctrl_X59_Y12_N0
macro_inst|ahb2apb_inst|paddr[12] clken_ctrl_X59_Y12_N0
macro_inst|ahb2apb_inst|hwrite clken_ctrl_X59_Y12_N1
macro_inst|trig_ctrl_inst|eoc_cnt[0] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[5] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[6] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[7] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[8] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[9] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[1] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[10] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[11] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[12] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[13] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[14] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[15] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[2] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[3] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|eoc_cnt[4] clken_ctrl_X59_Y3_N1
macro_inst|trig_ctrl_inst|adc_data_prev[11] clken_ctrl_X59_Y4_N0
macro_inst|trig_ctrl_inst|adc_data_prev[10] clken_ctrl_X59_Y4_N0
macro_inst|trig_ctrl_inst|gap_cnt_auto[0] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[5] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[6] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[7] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[8] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[9] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[1] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[10] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[2] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[3] clken_ctrl_X59_Y5_N1
macro_inst|trig_ctrl_inst|gap_cnt_auto[4] clken_ctrl_X59_Y5_N1
macro_inst|cfg_reg_inst|trig_time_slot[0] clken_ctrl_X59_Y6_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[8] clken_ctrl_X59_Y6_N1
macro_inst|cfg_reg_inst|trig_mode[1] clken_ctrl_X59_Y6_N0
macro_inst|cfg_reg_inst|trig_time_slot[4] clken_ctrl_X59_Y6_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[4] clken_ctrl_X59_Y6_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[3] clken_ctrl_X59_Y6_N1
macro_inst|cfg_reg_inst|trig_mode[0] clken_ctrl_X59_Y6_N0
macro_inst|trig_ctrl_inst|pulse_level clken_ctrl_X59_Y7_N0
macro_inst|trig_ctrl_inst|adc_rst_sync1 clken_ctrl_X59_Y7_N0
macro_inst|trig_ctrl_inst|adc_rst_sync2 clken_ctrl_X59_Y7_N0
macro_inst|trig_ctrl_inst|pulse_trigger clken_ctrl_X59_Y7_N0
macro_inst|trig_ctrl_inst|pulse_active clken_ctrl_X59_Y7_N0
macro_inst|trig_ctrl_inst|prdata[9] clken_ctrl_X59_Y8_N0
macro_inst|ahb2apb_inst|prdata[1] clken_ctrl_X59_Y8_N1
macro_inst|ahb2apb_inst|prdata[8] clken_ctrl_X59_Y8_N1
macro_inst|ahb2apb_inst|prdata[22] clken_ctrl_X59_Y8_N1
macro_inst|ahb2apb_inst|prdata[17] clken_ctrl_X59_Y8_N1
macro_inst|trig_ctrl_inst|prdata[4] clken_ctrl_X59_Y8_N0
macro_inst|trig_ctrl_inst|prdata[5] clken_ctrl_X59_Y8_N0
macro_inst|ahb2apb_inst|prdata[6] clken_ctrl_X59_Y8_N1
macro_inst|trig_ctrl_inst|prdata[6] clken_ctrl_X59_Y8_N0
macro_inst|ahb2apb_inst|prdata[5] clken_ctrl_X59_Y8_N1
macro_inst|ahb2apb_inst|prdata[0] clken_ctrl_X59_Y8_N1
macro_inst|ahb2apb_inst|prdata[4] clken_ctrl_X59_Y8_N1
macro_inst|cfg_reg_inst|prdata[4] clken_ctrl_X59_Y9_N0
macro_inst|cfg_reg_inst|prdata[14] clken_ctrl_X59_Y9_N0
macro_inst|cfg_reg_inst|prdata[8] clken_ctrl_X59_Y9_N0
macro_inst|cfg_reg_inst|prdata[7] clken_ctrl_X59_Y9_N0
macro_inst|cfg_reg_inst|frequency[4] clken_ctrl_X59_Y9_N1
macro_inst|cfg_reg_inst|prdata[5] clken_ctrl_X59_Y9_N0
macro_inst|cfg_reg_inst|frequency[14] clken_ctrl_X59_Y9_N1
macro_inst|ahb2apb_inst|paddr[5] clken_ctrl_X60_Y10_N0
macro_inst|ahb2apb_inst|paddr[3] clken_ctrl_X60_Y10_N0
macro_inst|ahb2apb_inst|haddr[14] clken_ctrl_X60_Y10_N1
macro_inst|ahb2apb_inst|haddr[5] clken_ctrl_X60_Y10_N1
macro_inst|ahb2apb_inst|haddr[2] clken_ctrl_X60_Y10_N1
macro_inst|ahb2apb_inst|paddr[2] clken_ctrl_X60_Y10_N0
macro_inst|ahb2apb_inst|paddr[4] clken_ctrl_X60_Y10_N0
macro_inst|ahb2apb_inst|haddr[3] clken_ctrl_X60_Y10_N1
macro_inst|ahb2apb_inst|haddr[4] clken_ctrl_X60_Y10_N1
macro_inst|cfg_reg_inst|adc_chnl_sel[2] clken_ctrl_X60_Y11_N0
macro_inst|cfg_reg_inst|prdata[1] clken_ctrl_X60_Y11_N1
macro_inst|cfg_reg_inst|adc_chnl_sel[0] clken_ctrl_X60_Y11_N0
macro_inst|cfg_reg_inst|adc_chnl_sel[1] clken_ctrl_X60_Y11_N0
macro_inst|cfg_reg_inst|prdata[3] clken_ctrl_X60_Y11_N1
macro_inst|cfg_reg_inst|prdata[2] clken_ctrl_X60_Y11_N1
macro_inst|ahb2apb_inst|paddr[14] clken_ctrl_X60_Y12_N0
macro_inst|trig_ctrl_inst|curr_state.SAMPLING clken_ctrl_X60_Y3_N0
macro_inst|cfg_reg_inst|adc_en clken_ctrl_X60_Y3_N1
macro_inst|trig_ctrl_inst|adc_eoc_sync2 clken_ctrl_X60_Y3_N0
macro_inst|trig_ctrl_inst|write_strobe clken_ctrl_X60_Y3_N0
macro_inst|trig_ctrl_inst|single_shot_lock clken_ctrl_X60_Y3_N0
macro_inst|trig_ctrl_inst|curr_state.PRE_FILL clken_ctrl_X60_Y3_N0
macro_inst|cfg_reg_inst|trig_time_slot[3] clken_ctrl_X60_Y4_N0
macro_inst|cfg_reg_inst|trig_time_slot[1] clken_ctrl_X60_Y4_N0
macro_inst|trig_ctrl_inst|trigger_ptr[1] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[0] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[3] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[5] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[7] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[9] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trig_hit_reg clken_ctrl_X60_Y5_N1
macro_inst|trig_ctrl_inst|trigger_ptr[4] clken_ctrl_X60_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[6] clken_ctrl_X60_Y5_N0
macro_inst|cfg_reg_inst|trig_edge[1] clken_ctrl_X60_Y6_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[1] clken_ctrl_X60_Y6_N1
macro_inst|cfg_reg_inst|trig_edge[0] clken_ctrl_X60_Y6_N0
macro_inst|cfg_reg_inst|trig_time_slot[2] clken_ctrl_X60_Y6_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[0] clken_ctrl_X60_Y6_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[6] clken_ctrl_X60_Y6_N1
macro_inst|cfg_reg_inst|trig_pulse_width[13] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[14] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[15] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[9] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_pulse_width[9] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_auto_timeout[2] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[15] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[14] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[12] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_auto_timeout[13] clken_ctrl_X60_Y7_N1
macro_inst|cfg_reg_inst|trig_pulse_width[8] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[10] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[11] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[12] clken_ctrl_X60_Y7_N0
macro_inst|cfg_reg_inst|trig_pulse_width[4] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|trig_pulse_width[0] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|trig_pulse_width[3] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|trig_pulse_width[6] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|max_vol[0] clken_ctrl_X60_Y8_N1
macro_inst|cfg_reg_inst|trig_pulse_width[1] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|max_vol[4] clken_ctrl_X60_Y8_N1
macro_inst|cfg_reg_inst|trig_pulse_width[5] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|max_vol[6] clken_ctrl_X60_Y8_N1
macro_inst|cfg_reg_inst|trig_pulse_width[7] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|trig_pulse_width[2] clken_ctrl_X60_Y8_N0
macro_inst|cfg_reg_inst|max_vol[3] clken_ctrl_X60_Y8_N1
macro_inst|cfg_reg_inst|max_vol[2] clken_ctrl_X60_Y8_N1
macro_inst|cfg_reg_inst|adc_chnl_sel[3] clken_ctrl_X60_Y9_N0
macro_inst|cfg_reg_inst|adc_clk_div[7] clken_ctrl_X60_Y9_N1
macro_inst|cfg_reg_inst|adc_clk_div[5] clken_ctrl_X60_Y9_N1
macro_inst|cfg_reg_inst|adc_clk_div[3] clken_ctrl_X60_Y9_N1
macro_inst|cfg_reg_inst|adc_clk_div[4] clken_ctrl_X60_Y9_N1
macro_inst|cfg_reg_inst|adc_clk_div[2] clken_ctrl_X60_Y9_N1
macro_inst|cfg_reg_inst|adc_clk_div[6] clken_ctrl_X61_Y10_N1
macro_inst|cfg_reg_inst|adc_clk_div[1] clken_ctrl_X61_Y10_N1
macro_inst|cfg_reg_inst|adc_clk_div[0] clken_ctrl_X61_Y10_N1
macro_inst|apb_adc0_inst|sclk clken_ctrl_X61_Y10_N0
macro_inst|trig_ctrl_inst|trigger_ptr[8] clken_ctrl_X61_Y5_N0
macro_inst|trig_ctrl_inst|trigger_ptr[2] clken_ctrl_X61_Y5_N0
macro_inst|trig_ctrl_inst|curr_state.POST_TRIG clken_ctrl_X61_Y6_N0
macro_inst|trig_ctrl_inst|adc_rst_sync3 clken_ctrl_X61_Y6_N0
macro_inst|trig_ctrl_inst|curr_state.DONE clken_ctrl_X61_Y6_N0
macro_inst|trig_ctrl_inst|curr_state.IDLE clken_ctrl_X61_Y6_N0
macro_inst|cfg_reg_inst|adc_run clken_ctrl_X61_Y6_N1
macro_inst|trig_ctrl_inst|trig_done clken_ctrl_X61_Y6_N0
macro_inst|cfg_reg_inst|prdata[6] clken_ctrl_X61_Y8_N0
macro_inst|trig_ctrl_inst|prdata[2] clken_ctrl_X61_Y8_N1
macro_inst|trig_ctrl_inst|prdata[0] clken_ctrl_X61_Y8_N1
macro_inst|trig_ctrl_inst|prdata[3] clken_ctrl_X61_Y8_N1
macro_inst|cfg_reg_inst|prdata[0] clken_ctrl_X61_Y8_N0
macro_inst|trig_ctrl_inst|prdata[8] clken_ctrl_X61_Y8_N1
macro_inst|trig_ctrl_inst|prdata[1] clken_ctrl_X61_Y8_N1
macro_inst|trig_ctrl_inst|prdata[7] clken_ctrl_X61_Y8_N1
macro_inst|cfg_reg_inst|dac_run clken_ctrl_X61_Y9_N0
macro_inst|cfg_reg_inst|adc_restart clken_ctrl_X61_Y9_N1
macro_inst|cfg_reg_inst|dac_en clken_ctrl_X61_Y9_N0
macro_inst|apb_adc0_inst|sclk_counter[0] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[5] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[6] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[7] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[8] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[9] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[1] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[10] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[11] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[12] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[13] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[14] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[15] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[2] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[3] clken_ctrl_X62_Y10_N0
macro_inst|apb_adc0_inst|sclk_counter[4] clken_ctrl_X62_Y10_N0
macro_inst|trig_ctrl_inst|decim_factor[10] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[14] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[8] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[9] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[13] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[11] clken_ctrl_X62_Y3_N0
macro_inst|trig_ctrl_inst|decim_factor[6] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[0] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[1] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[2] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[4] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[5] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[7] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|decim_factor[3] clken_ctrl_X62_Y4_N0
macro_inst|trig_ctrl_inst|ram_wr_addr[0] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[1] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[2] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[3] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[4] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[5] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[6] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[7] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[8] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|ram_wr_addr[9] clken_ctrl_X62_Y5_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[2] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[3] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[4] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[5] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[6] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[7] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[8] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[0] clken_ctrl_X62_Y6_N1
macro_inst|trig_ctrl_inst|post_trig_cnt[1] clken_ctrl_X62_Y6_N1
macro_inst|apb_dac0_inst|phase_r[2] clken_ctrl_X62_Y9_N0
macro_inst|apb_dac0_inst|phase_r[3] clken_ctrl_X62_Y9_N0