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- Analysis & Synthesis report for fpga_boot
- Tue Jul 29 15:13:29 2025
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Partition for Top-Level Resource Utilization by Entity
- 7. Source assignments for Top-level Entity: |fpga_boot
- 8. Parameter Settings for User Entity Instance: altpll:pll_inst
- 9. Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst
- 10. Partition "rv32" Resource Utilization by Entity
- 11. Parameter Settings for User Entity Instance: alta_rv32:rv32
- 12. Port Connectivity Checks: "alta_rv32:rv32"
- 13. Port Connectivity Checks: "boot_ip:macro_inst"
- 14. Port Connectivity Checks: "alta_gclksw:gclksw_inst"
- 15. Analysis & Synthesis Messages
- 16. Analysis & Synthesis Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +----------------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +------------------------------------+---------------------------------------------+
- ; Analysis & Synthesis Status ; Failed - Tue Jul 29 15:13:29 2025 ;
- ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
- ; Revision Name ; fpga_boot ;
- ; Top-level Entity Name ; fpga_boot ;
- ; Family ; Cyclone IV E ;
- ; Total logic elements ; N/A until Partition Merge ;
- ; Total combinational functions ; N/A until Partition Merge ;
- ; Dedicated logic registers ; N/A until Partition Merge ;
- ; Total registers ; N/A until Partition Merge ;
- ; Total pins ; N/A until Partition Merge ;
- ; Total virtual pins ; N/A until Partition Merge ;
- ; Total memory bits ; N/A until Partition Merge ;
- ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ;
- ; Total PLLs ; N/A until Partition Merge ;
- +------------------------------------+---------------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- ; Device ; EP4CE75F29C8 ; ;
- ; Top-level entity name ; fpga_boot ; fpga_boot ;
- ; Family name ; Cyclone IV E ; Cyclone IV GX ;
- ; Maximum processors allowed for parallel compilation ; All ; ;
- ; Maximum DSP Block Usage ; 0 ; -1 (Unlimited) ;
- ; Auto Open-Drain Pins ; Off ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; On ; Off ;
- ; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks ; 4 ; -1 (Unlimited) ;
- ; Use smart compilation ; Off ; Off ;
- ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
- ; Enable compact report table ; Off ; Off ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
- ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Infer RAMs from Raw Logic ; On ; On ;
- ; Parallel Synthesis ; On ; On ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique ; Balanced ; Balanced ;
- ; Carry Chain Length ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto DSP Block Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Strict RAM Replacement ; Off ; Off ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto RAM Block Balancing ; On ; On ;
- ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Timing-Driven Synthesis ; On ; On ;
- ; Report Parameter Settings ; On ; On ;
- ; Report Source Assignments ; On ; On ;
- ; Report Connectivity Checks ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Synchronization Register Chain Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
- ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Auto Gated Clock Conversion ; Off ; Off ;
- ; Block Design Naming ; Auto ; Auto ;
- ; SDC constraint protection ; Off ; Off ;
- ; Synthesis Effort ; Auto ; Auto ;
- ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
- ; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
- ; Analysis & Synthesis Message Level ; Medium ; Medium ;
- ; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
- ; Resource Aware Inference For Block RAM ; On ; On ;
- ; Synthesis Seed ; 1 ; 1 ;
- +----------------------------------------------------------------------------+--------------------+--------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 8 ;
- ; Maximum allowed ; 4 ;
- ; ; ;
- ; Average used ; 1.00 ;
- ; Maximum used ; 1 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processors 2-8 ; 0.0% ;
- +----------------------------+-------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
- +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- ; fpga_boot.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v ; ;
- ; boot_ip.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_boot/logic/boot_ip.v ; ;
- ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; yes ; User Verilog HDL File ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; ;
- ; altpll.tdf ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf ; ;
- ; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc ; ;
- ; stratix_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc ; ;
- ; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ;
- ; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ;
- ; db/altpll_9g32.tdf ; yes ; Auto-Generated Megafunction ; D:/LYW/NEW_DECODE/2006_boot/logic/db/altpll_9g32.tdf ; ;
- +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition for Top-Level Resource Utilization by Entity ;
- +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
- ; |fpga_boot ; 31 (30) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot ; work ;
- ; |alta_gclksw:gclksw_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot|alta_gclksw:gclksw_inst ; work ;
- ; |altpll:pll_inst| ; 1 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot|altpll:pll_inst ; work ;
- ; |altpll_9g32:auto_generated| ; 1 (1) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot|altpll:pll_inst|altpll_9g32:auto_generated ; work ;
- +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +---------------------------------------------------------------------+
- ; Source assignments for Top-level Entity: |fpga_boot ;
- +------------------------------+-------+------+-----------------------+
- ; Assignment ; Value ; From ; To ;
- +------------------------------+-------+------+-----------------------+
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_ENABLE ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_ENABLE ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_LOCK ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_LOCK ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_resetn ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_resetn ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_stop ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_stop ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[0] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[7] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[7] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[6] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[6] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[5] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[5] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[4] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[4] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[3] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[3] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[2] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[2] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[1] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[1] ;
- ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[0] ;
- ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[0] ;
- +------------------------------+-------+------+-----------------------+
- +--------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: altpll:pll_inst ;
- +-------------------------------+-------------------+----------------+
- ; Parameter Name ; Value ; Type ;
- +-------------------------------+-------------------+----------------+
- ; OPERATION_MODE ; NORMAL ; Untyped ;
- ; PLL_TYPE ; AUTO ; Untyped ;
- ; LPM_HINT ; UNUSED ; Untyped ;
- ; QUALIFY_CONF_DONE ; OFF ; Untyped ;
- ; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
- ; SCAN_CHAIN ; LONG ; Untyped ;
- ; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
- ; INCLK0_INPUT_FREQUENCY ; 125000 ; Signed Integer ;
- ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
- ; GATE_LOCK_SIGNAL ; NO ; Untyped ;
- ; GATE_LOCK_COUNTER ; 0 ; Untyped ;
- ; LOCK_HIGH ; 1 ; Untyped ;
- ; LOCK_LOW ; 1 ; Untyped ;
- ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ;
- ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ;
- ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
- ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
- ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
- ; SKIP_VCO ; OFF ; Untyped ;
- ; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
- ; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
- ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
- ; BANDWIDTH ; 0 ; Untyped ;
- ; BANDWIDTH_TYPE ; AUTO ; Untyped ;
- ; SPREAD_FREQUENCY ; 0 ; Untyped ;
- ; DOWN_SPREAD ; 0 ; Untyped ;
- ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
- ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
- ; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
- ; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
- ; CLK4_MULTIPLY_BY ; 120 ; Signed Integer ;
- ; CLK3_MULTIPLY_BY ; 120 ; Signed Integer ;
- ; CLK2_MULTIPLY_BY ; 120 ; Signed Integer ;
- ; CLK1_MULTIPLY_BY ; 120 ; Signed Integer ;
- ; CLK0_MULTIPLY_BY ; 120 ; Signed Integer ;
- ; CLK9_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK8_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK7_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK6_DIVIDE_BY ; 0 ; Untyped ;
- ; CLK5_DIVIDE_BY ; 1 ; Untyped ;
- ; CLK4_DIVIDE_BY ; 4 ; Signed Integer ;
- ; CLK3_DIVIDE_BY ; 8 ; Signed Integer ;
- ; CLK2_DIVIDE_BY ; 4 ; Signed Integer ;
- ; CLK1_DIVIDE_BY ; 4 ; Signed Integer ;
- ; CLK0_DIVIDE_BY ; 4 ; Signed Integer ;
- ; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; CLK5_TIME_DELAY ; 0 ; Untyped ;
- ; CLK4_TIME_DELAY ; 0 ; Untyped ;
- ; CLK3_TIME_DELAY ; 0 ; Untyped ;
- ; CLK2_TIME_DELAY ; 0 ; Untyped ;
- ; CLK1_TIME_DELAY ; 0 ; Untyped ;
- ; CLK0_TIME_DELAY ; 0 ; Untyped ;
- ; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK0_DUTY_CYCLE ; 50 ; Untyped ;
- ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
- ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
- ; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
- ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
- ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
- ; DPA_MULTIPLY_BY ; 0 ; Untyped ;
- ; DPA_DIVIDE_BY ; 1 ; Untyped ;
- ; DPA_DIVIDER ; 0 ; Untyped ;
- ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
- ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
- ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
- ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
- ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
- ; VCO_MULTIPLY_BY ; 0 ; Untyped ;
- ; VCO_DIVIDE_BY ; 0 ; Untyped ;
- ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
- ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
- ; VCO_MIN ; 0 ; Untyped ;
- ; VCO_MAX ; 0 ; Untyped ;
- ; VCO_CENTER ; 0 ; Untyped ;
- ; PFD_MIN ; 0 ; Untyped ;
- ; PFD_MAX ; 0 ; Untyped ;
- ; M_INITIAL ; 0 ; Untyped ;
- ; M ; 0 ; Untyped ;
- ; N ; 1 ; Untyped ;
- ; M2 ; 1 ; Untyped ;
- ; N2 ; 1 ; Untyped ;
- ; SS ; 1 ; Untyped ;
- ; C0_HIGH ; 0 ; Untyped ;
- ; C1_HIGH ; 0 ; Untyped ;
- ; C2_HIGH ; 0 ; Untyped ;
- ; C3_HIGH ; 0 ; Untyped ;
- ; C4_HIGH ; 0 ; Untyped ;
- ; C5_HIGH ; 0 ; Untyped ;
- ; C6_HIGH ; 0 ; Untyped ;
- ; C7_HIGH ; 0 ; Untyped ;
- ; C8_HIGH ; 0 ; Untyped ;
- ; C9_HIGH ; 0 ; Untyped ;
- ; C0_LOW ; 0 ; Untyped ;
- ; C1_LOW ; 0 ; Untyped ;
- ; C2_LOW ; 0 ; Untyped ;
- ; C3_LOW ; 0 ; Untyped ;
- ; C4_LOW ; 0 ; Untyped ;
- ; C5_LOW ; 0 ; Untyped ;
- ; C6_LOW ; 0 ; Untyped ;
- ; C7_LOW ; 0 ; Untyped ;
- ; C8_LOW ; 0 ; Untyped ;
- ; C9_LOW ; 0 ; Untyped ;
- ; C0_INITIAL ; 0 ; Untyped ;
- ; C1_INITIAL ; 0 ; Untyped ;
- ; C2_INITIAL ; 0 ; Untyped ;
- ; C3_INITIAL ; 0 ; Untyped ;
- ; C4_INITIAL ; 0 ; Untyped ;
- ; C5_INITIAL ; 0 ; Untyped ;
- ; C6_INITIAL ; 0 ; Untyped ;
- ; C7_INITIAL ; 0 ; Untyped ;
- ; C8_INITIAL ; 0 ; Untyped ;
- ; C9_INITIAL ; 0 ; Untyped ;
- ; C0_MODE ; BYPASS ; Untyped ;
- ; C1_MODE ; BYPASS ; Untyped ;
- ; C2_MODE ; BYPASS ; Untyped ;
- ; C3_MODE ; BYPASS ; Untyped ;
- ; C4_MODE ; BYPASS ; Untyped ;
- ; C5_MODE ; BYPASS ; Untyped ;
- ; C6_MODE ; BYPASS ; Untyped ;
- ; C7_MODE ; BYPASS ; Untyped ;
- ; C8_MODE ; BYPASS ; Untyped ;
- ; C9_MODE ; BYPASS ; Untyped ;
- ; C0_PH ; 0 ; Untyped ;
- ; C1_PH ; 0 ; Untyped ;
- ; C2_PH ; 0 ; Untyped ;
- ; C3_PH ; 0 ; Untyped ;
- ; C4_PH ; 0 ; Untyped ;
- ; C5_PH ; 0 ; Untyped ;
- ; C6_PH ; 0 ; Untyped ;
- ; C7_PH ; 0 ; Untyped ;
- ; C8_PH ; 0 ; Untyped ;
- ; C9_PH ; 0 ; Untyped ;
- ; L0_HIGH ; 1 ; Untyped ;
- ; L1_HIGH ; 1 ; Untyped ;
- ; G0_HIGH ; 1 ; Untyped ;
- ; G1_HIGH ; 1 ; Untyped ;
- ; G2_HIGH ; 1 ; Untyped ;
- ; G3_HIGH ; 1 ; Untyped ;
- ; E0_HIGH ; 1 ; Untyped ;
- ; E1_HIGH ; 1 ; Untyped ;
- ; E2_HIGH ; 1 ; Untyped ;
- ; E3_HIGH ; 1 ; Untyped ;
- ; L0_LOW ; 1 ; Untyped ;
- ; L1_LOW ; 1 ; Untyped ;
- ; G0_LOW ; 1 ; Untyped ;
- ; G1_LOW ; 1 ; Untyped ;
- ; G2_LOW ; 1 ; Untyped ;
- ; G3_LOW ; 1 ; Untyped ;
- ; E0_LOW ; 1 ; Untyped ;
- ; E1_LOW ; 1 ; Untyped ;
- ; E2_LOW ; 1 ; Untyped ;
- ; E3_LOW ; 1 ; Untyped ;
- ; L0_INITIAL ; 1 ; Untyped ;
- ; L1_INITIAL ; 1 ; Untyped ;
- ; G0_INITIAL ; 1 ; Untyped ;
- ; G1_INITIAL ; 1 ; Untyped ;
- ; G2_INITIAL ; 1 ; Untyped ;
- ; G3_INITIAL ; 1 ; Untyped ;
- ; E0_INITIAL ; 1 ; Untyped ;
- ; E1_INITIAL ; 1 ; Untyped ;
- ; E2_INITIAL ; 1 ; Untyped ;
- ; E3_INITIAL ; 1 ; Untyped ;
- ; L0_MODE ; BYPASS ; Untyped ;
- ; L1_MODE ; BYPASS ; Untyped ;
- ; G0_MODE ; BYPASS ; Untyped ;
- ; G1_MODE ; BYPASS ; Untyped ;
- ; G2_MODE ; BYPASS ; Untyped ;
- ; G3_MODE ; BYPASS ; Untyped ;
- ; E0_MODE ; BYPASS ; Untyped ;
- ; E1_MODE ; BYPASS ; Untyped ;
- ; E2_MODE ; BYPASS ; Untyped ;
- ; E3_MODE ; BYPASS ; Untyped ;
- ; L0_PH ; 0 ; Untyped ;
- ; L1_PH ; 0 ; Untyped ;
- ; G0_PH ; 0 ; Untyped ;
- ; G1_PH ; 0 ; Untyped ;
- ; G2_PH ; 0 ; Untyped ;
- ; G3_PH ; 0 ; Untyped ;
- ; E0_PH ; 0 ; Untyped ;
- ; E1_PH ; 0 ; Untyped ;
- ; E2_PH ; 0 ; Untyped ;
- ; E3_PH ; 0 ; Untyped ;
- ; M_PH ; 0 ; Untyped ;
- ; C1_USE_CASC_IN ; OFF ; Untyped ;
- ; C2_USE_CASC_IN ; OFF ; Untyped ;
- ; C3_USE_CASC_IN ; OFF ; Untyped ;
- ; C4_USE_CASC_IN ; OFF ; Untyped ;
- ; C5_USE_CASC_IN ; OFF ; Untyped ;
- ; C6_USE_CASC_IN ; OFF ; Untyped ;
- ; C7_USE_CASC_IN ; OFF ; Untyped ;
- ; C8_USE_CASC_IN ; OFF ; Untyped ;
- ; C9_USE_CASC_IN ; OFF ; Untyped ;
- ; CLK0_COUNTER ; G0 ; Untyped ;
- ; CLK1_COUNTER ; G0 ; Untyped ;
- ; CLK2_COUNTER ; G0 ; Untyped ;
- ; CLK3_COUNTER ; G0 ; Untyped ;
- ; CLK4_COUNTER ; G0 ; Untyped ;
- ; CLK5_COUNTER ; G0 ; Untyped ;
- ; CLK6_COUNTER ; E0 ; Untyped ;
- ; CLK7_COUNTER ; E1 ; Untyped ;
- ; CLK8_COUNTER ; E2 ; Untyped ;
- ; CLK9_COUNTER ; E3 ; Untyped ;
- ; L0_TIME_DELAY ; 0 ; Untyped ;
- ; L1_TIME_DELAY ; 0 ; Untyped ;
- ; G0_TIME_DELAY ; 0 ; Untyped ;
- ; G1_TIME_DELAY ; 0 ; Untyped ;
- ; G2_TIME_DELAY ; 0 ; Untyped ;
- ; G3_TIME_DELAY ; 0 ; Untyped ;
- ; E0_TIME_DELAY ; 0 ; Untyped ;
- ; E1_TIME_DELAY ; 0 ; Untyped ;
- ; E2_TIME_DELAY ; 0 ; Untyped ;
- ; E3_TIME_DELAY ; 0 ; Untyped ;
- ; M_TIME_DELAY ; 0 ; Untyped ;
- ; N_TIME_DELAY ; 0 ; Untyped ;
- ; EXTCLK3_COUNTER ; E3 ; Untyped ;
- ; EXTCLK2_COUNTER ; E2 ; Untyped ;
- ; EXTCLK1_COUNTER ; E1 ; Untyped ;
- ; EXTCLK0_COUNTER ; E0 ; Untyped ;
- ; ENABLE0_COUNTER ; L0 ; Untyped ;
- ; ENABLE1_COUNTER ; L0 ; Untyped ;
- ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
- ; LOOP_FILTER_R ; 1.000000 ; Untyped ;
- ; LOOP_FILTER_C ; 5 ; Untyped ;
- ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
- ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
- ; VCO_POST_SCALE ; 0 ; Untyped ;
- ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
- ; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLK0 ; PORT_USED ; Untyped ;
- ; PORT_CLK1 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK2 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK3 ; PORT_USED ; Untyped ;
- ; PORT_CLK4 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
- ; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
- ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_INCLK0 ; PORT_USED ; Untyped ;
- ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ARESET ; PORT_USED ; Untyped ;
- ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_LOCKED ; PORT_USED ; Untyped ;
- ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
- ; M_TEST_SOURCE ; 5 ; Untyped ;
- ; C0_TEST_SOURCE ; 5 ; Untyped ;
- ; C1_TEST_SOURCE ; 5 ; Untyped ;
- ; C2_TEST_SOURCE ; 5 ; Untyped ;
- ; C3_TEST_SOURCE ; 5 ; Untyped ;
- ; C4_TEST_SOURCE ; 5 ; Untyped ;
- ; C5_TEST_SOURCE ; 5 ; Untyped ;
- ; C6_TEST_SOURCE ; 5 ; Untyped ;
- ; C7_TEST_SOURCE ; 5 ; Untyped ;
- ; C8_TEST_SOURCE ; 5 ; Untyped ;
- ; C9_TEST_SOURCE ; 5 ; Untyped ;
- ; CBXI_PARAMETER ; altpll_9g32 ; Untyped ;
- ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
- ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
- ; WIDTH_CLOCK ; 5 ; Signed Integer ;
- ; WIDTH_PHASECOUNTERSELECT ; 3 ; Signed Integer ;
- ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
- ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ;
- ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
- ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
- ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
- ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
- ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
- ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
- +-------------------------------+-------------------+----------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +----------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst ;
- +----------------+-------+---------------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+---------------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- ; ENA_REG_MODE ; 0 ; Unsigned Binary ;
- +----------------+-------+---------------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Partition "rv32" Resource Utilization by Entity ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
- ; |fpga_boot ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot ; work ;
- ; |alta_rv32:rv32| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |fpga_boot|alta_rv32:rv32 ; work ;
- +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: alta_rv32:rv32 ;
- +----------------+-------+------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+------------------------------------+
- ; coord_x ; 0 ; Signed Integer ;
- ; coord_y ; 0 ; Signed Integer ;
- ; coord_z ; 0 ; Signed Integer ;
- +----------------+-------+------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "alta_rv32:rv32" ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- ; ext_resetn ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; test_mode ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; usb0_xcvr_clk ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; usb0_id ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ;
- ; sys_ctrl_hseEnable ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_hseBypass ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_sleep ; Partition Output ; Info ; Explicitly unconnected ;
- ; sys_ctrl_standby ; Partition Output ; Info ; Explicitly unconnected ;
- ; dmactive ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGNSW ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGSTATE ; Partition Output ; Info ; Explicitly unconnected ;
- ; swj_JTAGIR ; Partition Output ; Info ; Explicitly unconnected ;
- ; ext_int ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio0_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio0_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio0_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio1_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio2_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- ; gpio3_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio3_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio4_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio5_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio5_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_data[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_data[3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_data[1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_en[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_en[3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio6_io_out_en[1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_data[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_en[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio7_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
- ; gpio8_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ;
- +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------+
- ; Port Connectivity Checks: "boot_ip:macro_inst" ;
- +---------------------+---------+------------------+--------------------------------------------------------+
- ; Port ; Type ; Severity ; Details ;
- +---------------------+---------+------------------+--------------------------------------------------------+
- ; SIM_CLK ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; SIM_IO ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; SIM_IO_12 ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; SIM_IO_13 ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; SIM_IO_14 ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; SIM_IO_15 ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; uart14_rx ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; uart14_tx ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; uart15_rx ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; uart15_tx ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; gpio_int_g0_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; gpio_int_g1_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; rxd_12_ip_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; rxd_13_ip_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; rxd_14_ip_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; rxd_15_ip_in ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_12_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_12_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_13_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_13_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_14_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_14_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_15_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txd_15_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_12_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_12_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_13_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_13_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_14_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_14_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_15_ip_out_data ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- ; txen_15_ip_out_en ; Unknown ; Critical Warning ; Named port was not declared by the instantiated entity ;
- +---------------------+---------+------------------+--------------------------------------------------------+
- +-----------------------------------------------------+
- ; Port Connectivity Checks: "alta_gclksw:gclksw_inst" ;
- +--------+-------+----------+-------------------------+
- ; Port ; Type ; Severity ; Details ;
- +--------+-------+----------+-------------------------+
- ; ena ; Input ; Info ; Stuck at VCC ;
- ; clkin3 ; Input ; Info ; Explicitly unconnected ;
- +--------+-------+----------+-------------------------+
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit Analysis & Synthesis
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Tue Jul 29 15:13:28 2025
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off fpga_boot -c fpga_boot
- Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
- Info (12021): Found 1 design units, including 1 entities, in source file fpga_boot.v
- Info (12023): Found entity 1: fpga_boot
- Info (12021): Found 1 design units, including 1 entities, in source file boot_ip.v
- Info (12023): Found entity 1: boot_ip
- Info (12021): Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v
- Info (12023): Found entity 1: alta_slice
- Info (12023): Found entity 2: alta_clkenctrl_rst
- Info (12023): Found entity 3: alta_clkenctrl
- Info (12023): Found entity 4: alta_asyncctrl
- Info (12023): Found entity 5: alta_syncctrl
- Info (12023): Found entity 6: alta_io_gclk
- Info (12023): Found entity 7: alta_gclksel
- Info (12023): Found entity 8: alta_gclkgen
- Info (12023): Found entity 9: alta_gclkgen0
- Info (12023): Found entity 10: alta_gclkgen2
- Info (12023): Found entity 11: alta_io
- Info (12023): Found entity 12: alta_rio
- Info (12023): Found entity 13: alta_srff
- Info (12023): Found entity 14: alta_dff
- Info (12023): Found entity 15: alta_ufm_gddd
- Info (12023): Found entity 16: alta_dff_stall
- Info (12023): Found entity 17: alta_srlat
- Info (12023): Found entity 18: alta_dio
- Info (12023): Found entity 19: alta_indel
- Info (12023): Found entity 20: alta_dpclkdel
- Info (12023): Found entity 21: alta_ufms
- Info (12023): Found entity 22: alta_ufms_sim
- Info (12023): Found entity 23: alta_pll
- Info (12023): Found entity 24: alta_pllx
- Info (12023): Found entity 25: pll_clk_trim
- Info (12023): Found entity 26: alta_pllv
- Info (12023): Found entity 27: alta_pllve
- Info (12023): Found entity 28: alta_sram
- Info (12023): Found entity 29: alta_dpram16x4
- Info (12023): Found entity 30: alta_spram16x4
- Info (12023): Found entity 31: alta_wram
- Info (12023): Found entity 32: alta_bram_pulse_generator
- Info (12023): Found entity 33: alta_bram
- Info (12023): Found entity 34: alta_boot
- Info (12023): Found entity 35: alta_osc
- Info (12023): Found entity 36: alta_ufml
- Info (12023): Found entity 37: alta_jtag
- Info (12023): Found entity 38: alta_mult
- Info (12023): Found entity 39: alta_dff_en
- Info (12023): Found entity 40: alta_multm_add
- Info (12023): Found entity 41: alta_multm
- Info (12023): Found entity 42: alta_i2c
- Info (12023): Found entity 43: alta_spi
- Info (12023): Found entity 44: alta_irda
- Info (12023): Found entity 45: alta_bram9k
- Info (12023): Found entity 46: alta_mcu
- Info (12023): Found entity 47: alta_mcu_m3
- Info (12023): Found entity 48: alta_remote
- Info (12023): Found entity 49: alta_saradc
- Info (12023): Found entity 50: alta_gclksw
- Info (12023): Found entity 51: alta_rv32
- Info (12023): Found entity 52: alta_mipi_clk
- Info (12023): Found entity 53: alta_adc
- Info (12023): Found entity 54: alta_dac
- Info (12023): Found entity 55: alta_cmp
- Info (12023): Found entity 56: alta_ram4k
- Info (12023): Found entity 57: alta_ram9k
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(145): created implicit net for "PIN_32_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(148): created implicit net for "PIN_33_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(156): created implicit net for "PIN_35_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(164): created implicit net for "PIN_38_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(182): created implicit net for "PIN_48_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(253): created implicit net for "PIN_95_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(261): created implicit net for "PIN_97_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(264): created implicit net for "PIN_98_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(270): created implicit net for "PIN_HSE_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(273): created implicit net for "PIN_HSI_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(276): created implicit net for "PIN_OSC_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(399): created implicit net for "usb0_xcvr_clk"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(418): created implicit net for "bus_clk"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(431): created implicit net for "sys_clk"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__5__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__4__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__3__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__2__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__1__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for "gpio_int_g0_in__0__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__5__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__4__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__3__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__2__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__1__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for "gpio_int_g1_in__0__"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(491): created implicit net for "rxd_12_ip_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(492): created implicit net for "rxd_13_ip_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(493): created implicit net for "rxd_14_ip_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(494): created implicit net for "rxd_15_ip_in"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(495): created implicit net for "txd_12_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(496): created implicit net for "txd_12_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(497): created implicit net for "txd_13_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(498): created implicit net for "txd_13_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(499): created implicit net for "txd_14_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(500): created implicit net for "txd_14_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(501): created implicit net for "txd_15_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(502): created implicit net for "txd_15_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(503): created implicit net for "txen_12_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(504): created implicit net for "txen_12_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(505): created implicit net for "txen_13_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(506): created implicit net for "txen_13_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(507): created implicit net for "txen_14_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(508): created implicit net for "txen_14_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(509): created implicit net for "txen_15_ip_out_data"
- Warning (10236): Verilog HDL Implicit Net warning at fpga_boot.v(510): created implicit net for "txen_15_ip_out_en"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for "ena_reg"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for "ena_int"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for "ena_reg"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for "outreg_h"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for "outreg_l"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for "oe_reg_h"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for "oe_reg_l"
- Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for "dffOut"
- Warning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
- Info (12127): Elaborating entity "fpga_boot" for the top level hierarchy
- Warning (10036): Verilog HDL or VHDL warning at fpga_boot.v(276): object "PIN_OSC_in" assigned a value but never read
- Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll_inst"
- Info (12130): Elaborated megafunction instantiation "altpll:pll_inst"
- Info (12133): Instantiated megafunction "altpll:pll_inst" with the following parameter:
- Info (12134): Parameter "bandwidth_type" = "AUTO"
- Info (12134): Parameter "clk0_divide_by" = "4"
- Info (12134): Parameter "clk0_multiply_by" = "120"
- Info (12134): Parameter "clk0_phase_shift" = "0"
- Info (12134): Parameter "clk1_divide_by" = "4"
- Info (12134): Parameter "clk1_multiply_by" = "120"
- Info (12134): Parameter "clk1_phase_shift" = "0"
- Info (12134): Parameter "clk2_divide_by" = "4"
- Info (12134): Parameter "clk2_multiply_by" = "120"
- Info (12134): Parameter "clk2_phase_shift" = "0"
- Info (12134): Parameter "clk3_divide_by" = "8"
- Info (12134): Parameter "clk3_multiply_by" = "120"
- Info (12134): Parameter "clk3_phase_shift" = "0"
- Info (12134): Parameter "clk4_divide_by" = "4"
- Info (12134): Parameter "clk4_multiply_by" = "120"
- Info (12134): Parameter "clk4_phase_shift" = "0"
- Info (12134): Parameter "compensate_clock" = "CLK0"
- Info (12134): Parameter "inclk0_input_frequency" = "125000"
- Info (12134): Parameter "lpm_type" = "altpll"
- Info (12134): Parameter "operation_mode" = "NORMAL"
- Info (12134): Parameter "pll_type" = "AUTO"
- Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
- Info (12134): Parameter "port_areset" = "PORT_USED"
- Info (12134): Parameter "port_inclk0" = "PORT_USED"
- Info (12134): Parameter "port_locked" = "PORT_USED"
- Info (12134): Parameter "port_clk0" = "PORT_USED"
- Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
- Info (12134): Parameter "port_clk3" = "PORT_USED"
- Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
- Info (12134): Parameter "width_clock" = "5"
- Info (12134): Parameter "width_phasecounterselect" = "3"
- Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9g32.tdf
- Info (12023): Found entity 1: altpll_9g32
- Info (12128): Elaborating entity "altpll_9g32" for hierarchy "altpll:pll_inst|altpll_9g32:auto_generated"
- Info (12128): Elaborating entity "alta_gclksw" for hierarchy "alta_gclksw:gclksw_inst"
- Info (12128): Elaborating entity "boot_ip" for hierarchy "boot_ip:macro_inst"
- Info (12128): Elaborating entity "alta_rv32" for hierarchy "alta_rv32:rv32"
- Warning (10034): Output port "gpio0_io_out_data" at alta_sim.v(3739) has no driver
- Warning (10034): Output port "gpio0_io_out_en" at alta_sim.v(3740) has no driver
- Warning (10034): Output port "gpio1_io_out_data" at alta_sim.v(3742) has no driver
- Warning (10034): Output port "gpio1_io_out_en" at alta_sim.v(3743) has no driver
- Warning (10034): Output port "gpio2_io_out_data" at alta_sim.v(3753) has no driver
- Warning (10034): Output port "gpio2_io_out_en" at alta_sim.v(3754) has no driver
- Warning (10034): Output port "gpio3_io_out_data" at alta_sim.v(3756) has no driver
- Warning (10034): Output port "gpio3_io_out_en" at alta_sim.v(3757) has no driver
- Warning (10034): Output port "gpio4_io_out_data" at alta_sim.v(3759) has no driver
- Warning (10034): Output port "gpio4_io_out_en" at alta_sim.v(3760) has no driver
- Warning (10034): Output port "gpio5_io_out_data" at alta_sim.v(3762) has no driver
- Warning (10034): Output port "gpio5_io_out_en" at alta_sim.v(3763) has no driver
- Warning (10034): Output port "gpio6_io_out_data" at alta_sim.v(3765) has no driver
- Warning (10034): Output port "gpio6_io_out_en" at alta_sim.v(3766) has no driver
- Warning (10034): Output port "gpio7_io_out_data" at alta_sim.v(3768) has no driver
- Warning (10034): Output port "gpio7_io_out_en" at alta_sim.v(3769) has no driver
- Warning (10034): Output port "gpio8_io_out_data" at alta_sim.v(3771) has no driver
- Warning (10034): Output port "gpio8_io_out_en" at alta_sim.v(3772) has no driver
- Warning (10034): Output port "gpio9_io_out_data" at alta_sim.v(3774) has no driver
- Warning (10034): Output port "gpio9_io_out_en" at alta_sim.v(3775) has no driver
- Warning (10034): Output port "swj_JTAGSTATE" at alta_sim.v(3780) has no driver
- Warning (10034): Output port "swj_JTAGIR" at alta_sim.v(3781) has no driver
- Warning (10034): Output port "dmactive" at alta_sim.v(3778) has no driver
- Warning (10034): Output port "swj_JTAGNSW" at alta_sim.v(3779) has no driver
- Error (12002): Port "SIM_CLK" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "SIM_IO" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "SIM_IO_12" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "SIM_IO_13" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "SIM_IO_14" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "SIM_IO_15" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "gpio_int_g0_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "gpio_int_g1_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "rxd_12_ip_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "rxd_13_ip_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "rxd_14_ip_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "rxd_15_ip_in" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_12_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_12_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_13_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_13_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_14_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_14_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_15_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txd_15_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_12_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_12_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_13_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_13_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_14_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_14_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_15_ip_out_data" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "txen_15_ip_out_en" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "uart14_rx" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "uart14_tx" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "uart15_rx" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Error (12002): Port "uart15_tx" does not exist in macrofunction "macro_inst" File: D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v Line: 543
- Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
- Info (144001): Generated suppressed messages file D:/LYW/NEW_DECODE/2006_boot/logic/quartus_logs/fpga_boot.map.smsg
- Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 32 errors, 81 warnings
- Error: Peak virtual memory: 4580 megabytes
- Error: Processing ended: Tue Jul 29 15:13:29 2025
- Error: Elapsed time: 00:00:01
- Error: Total CPU time (on all processors): 00:00:01
- +------------------------------------------+
- ; Analysis & Synthesis Suppressed Messages ;
- +------------------------------------------+
- The suppressed messages can be found in D:/LYW/NEW_DECODE/2006_boot/logic/quartus_logs/fpga_boot.map.smsg.
|
