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- Fmax report
- User constraint: 8.000MHz, Fmax: 145.033MHz, Clock: PIN_HSE
- User constraint: 10.000MHz, Fmax: 145.033MHz, Clock: PIN_HSI
- User constraint: 240.000MHz, Fmax: 249.314MHz, Clock: pll_inst|auto_generated|pll1|clk[0]
- User constraint: 120.000MHz, Fmax: 106.270MHz, Clock: pll_inst|auto_generated|pll1|clk[3]
- Setup from macro_inst|u_uart[0]|u_rx[0]|parity_error to macro_inst|u_uart[0]|u_regs|apb_prdata[1], clock pll_inst|auto_generated|pll1|clk[3], constraint 8.333, skew -0.066, data 9.015
- Slack: -1.077
- Arrival Time: 9.805
- 0.000 0.000 R Launch Clock Edge
- Launch Clock Path:
- 0.000 0.000 RR test_uart|PIN_HSE => PIN_HSE~input|padio
- 1.309 1.309 RR PIN_HSE~input|padio => PIN_HSE~input|combout
- 1.546 0.237 RR PIN_HSE~input|combout => pll_inst|auto_generated|pll1|clkin
- Compensation Path:
- -2.390 -3.936 RR pll_inst|auto_generated|pll1|clkfb => pll_inst|auto_generated|pll1|clkfbout
- -2.390 -0.000 RR pll_inst|auto_generated|pll1|clkfbout => pll_inst|auto_generated|pll1|clkfb
- Compensation Path End
- -1.410 0.980 RR pll_inst|auto_generated|pll1|clkin => pll_inst|auto_generated|pll1|clkout3 D
- -1.042 0.368 RR pll_inst|auto_generated|pll1|clkout3 => bus_clk_gclk|inclk D
- -1.042 0.000 RR bus_clk_gclk|inclk => bus_clk_gclk|outclk
- 0.509 1.551 RR bus_clk_gclk|outclk => clken_ctrl_X51_Y2_N0|ClkIn
- 0.657 0.148 RR clken_ctrl_X51_Y2_N0|ClkIn => clken_ctrl_X51_Y2_N0|ClkOut
- 0.790 0.133 RR clken_ctrl_X51_Y2_N0|ClkOut => macro_inst|u_uart[0]|u_rx[0]|parity_error|Clk
- Data Path:
- 1.025 0.235 RF macro_inst|u_uart[0]|u_rx[0]|parity_error|Clk => macro_inst|u_uart[0]|u_rx[0]|parity_error|Q D
- 2.773 1.748 FF macro_inst|u_uart[0]|u_rx[0]|parity_error|Q => macro_inst|u_ahb2apb|paddr[8]|A
- 3.255 0.482 FF macro_inst|u_ahb2apb|paddr[8]|A => macro_inst|u_ahb2apb|paddr[8]|LutOut
- 4.254 0.999 FF macro_inst|u_ahb2apb|paddr[8]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~5|D
- 4.358 0.104 FR macro_inst|u_uart[0]|u_regs|Selector11~5|D => macro_inst|u_uart[0]|u_regs|Selector11~5|LutOut
- 4.759 0.401 RR macro_inst|u_uart[0]|u_regs|Selector11~5|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~7|B
- 5.278 0.519 RR macro_inst|u_uart[0]|u_regs|Selector11~7|B => macro_inst|u_uart[0]|u_regs|Selector11~7|LutOut
- 5.679 0.401 RR macro_inst|u_uart[0]|u_regs|Selector11~7|LutOut => macro_inst|u_uart[0]|u_regs|ibrd[1]|A
- 6.209 0.530 RR macro_inst|u_uart[0]|u_regs|ibrd[1]|A => macro_inst|u_uart[0]|u_regs|ibrd[1]|LutOut
- 6.610 0.401 RR macro_inst|u_uart[0]|u_regs|ibrd[1]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~9|D
- 6.703 0.093 RF macro_inst|u_uart[0]|u_regs|Selector11~9|D => macro_inst|u_uart[0]|u_regs|Selector11~9|LutOut
- 7.702 0.999 FF macro_inst|u_uart[0]|u_regs|Selector11~9|LutOut => macro_inst|u_uart[1]|u_regs|ibrd[14]|D
- 7.810 0.108 FF macro_inst|u_uart[1]|u_regs|ibrd[14]|D => macro_inst|u_uart[1]|u_regs|ibrd[14]|LutOut
- 8.193 0.383 FF macro_inst|u_uart[1]|u_regs|ibrd[14]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~10|D
- 8.301 0.108 FF macro_inst|u_uart[0]|u_regs|Selector11~10|D => macro_inst|u_uart[0]|u_regs|Selector11~10|LutOut
- 9.300 0.999 FF macro_inst|u_uart[0]|u_regs|Selector11~10|LutOut => macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|D
- 9.404 0.104 FR macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|D => macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|LutOut
- 9.805 0.401 RR macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|LutOut => macro_inst|u_uart[0]|u_regs|apb_prdata[1]|D E
- Required Time: 8.728
- 8.333 8.333 R Latch Clock Edge
- Latch Clock Path:
- 8.333 0.000 RR test_uart|PIN_HSE => PIN_HSE~input|padio
- 9.642 1.309 RR PIN_HSE~input|padio => PIN_HSE~input|combout
- 9.869 0.227 RR PIN_HSE~input|combout => pll_inst|auto_generated|pll1|clkin
- Compensation Path:
- 5.933 -3.936 RR pll_inst|auto_generated|pll1|clkfb => pll_inst|auto_generated|pll1|clkfbout
- 5.933 -0.000 RR pll_inst|auto_generated|pll1|clkfbout => pll_inst|auto_generated|pll1|clkfb
- Compensation Path End
- 6.913 0.980 RR pll_inst|auto_generated|pll1|clkin => pll_inst|auto_generated|pll1|clkout3 D
- 7.268 0.355 RR pll_inst|auto_generated|pll1|clkout3 => bus_clk_gclk|inclk D
- 7.268 0.000 RR bus_clk_gclk|inclk => bus_clk_gclk|outclk
- 8.778 1.510 RR bus_clk_gclk|outclk => clken_ctrl_X58_Y4_N1|ClkIn
- 8.926 0.148 RR clken_ctrl_X58_Y4_N1|ClkIn => clken_ctrl_X58_Y4_N1|ClkOut
- 9.057 0.131 RR clken_ctrl_X58_Y4_N1|ClkOut => macro_inst|u_uart[0]|u_regs|apb_prdata[1]|Clk
- 8.705 -0.352 R Setup
- 8.728 0.023 Clock Variation
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