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2006_APP
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logic
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alta_db
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fmax.rpt

fmax.rpt 5.6 KB
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  1. Fmax report
    2. 

  2.   User constraint:   8.000MHz, Fmax: 145.033MHz, Clock: PIN_HSE
    3. 

  3.   User constraint:  10.000MHz, Fmax: 145.033MHz, Clock: PIN_HSI
    4. 

  4.   User constraint: 240.000MHz, Fmax: 249.314MHz, Clock: pll_inst|auto_generated|pll1|clk[0]
    5. 

  5.   User constraint: 120.000MHz, Fmax: 106.270MHz, Clock: pll_inst|auto_generated|pll1|clk[3]
    6. 

  6. 

  7. 

  8. 

  9. Setup from macro_inst|u_uart[0]|u_rx[0]|parity_error to macro_inst|u_uart[0]|u_regs|apb_prdata[1], clock pll_inst|auto_generated|pll1|clk[3], constraint 8.333, skew -0.066, data 9.015
    10. 

  10.   Slack:  -1.077
    11. 

  11.     Arrival Time:    9.805
    12. 

  12.         0.000    0.000   R                         Launch Clock Edge
    13. 

  13.       Launch Clock Path:
    14. 

  14.         0.000    0.000   RR                        test_uart|PIN_HSE =>                      PIN_HSE~input|padio 
    15. 

  15.         1.309    1.309   RR                      PIN_HSE~input|padio =>                    PIN_HSE~input|combout 
    16. 

  16.         1.546    0.237   RR                    PIN_HSE~input|combout =>       pll_inst|auto_generated|pll1|clkin 
    17. 

  17.       Compensation Path:
    18. 

  18.        -2.390   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
    19. 

  19.        -2.390   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
    20. 

  20.       Compensation Path End
    21. 

  21.        -1.410    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout3 D
    22. 

  22.        -1.042    0.368   RR     pll_inst|auto_generated|pll1|clkout3 =>                       bus_clk_gclk|inclk D
    23. 

  23.        -1.042    0.000   RR                       bus_clk_gclk|inclk =>                      bus_clk_gclk|outclk 
    24. 

  24.         0.509    1.551   RR                      bus_clk_gclk|outclk =>               clken_ctrl_X51_Y2_N0|ClkIn 
    25. 

  25.         0.657    0.148   RR               clken_ctrl_X51_Y2_N0|ClkIn =>              clken_ctrl_X51_Y2_N0|ClkOut 
    26. 

  26.         0.790    0.133   RR              clken_ctrl_X51_Y2_N0|ClkOut => macro_inst|u_uart[0]|u_rx[0]|parity_error|Clk 
    27. 

  27.       Data Path:
    28. 

  28.         1.025    0.235   RF macro_inst|u_uart[0]|u_rx[0]|parity_error|Clk => macro_inst|u_uart[0]|u_rx[0]|parity_error|Q D
    29. 

  29.         2.773    1.748   FF macro_inst|u_uart[0]|u_rx[0]|parity_error|Q =>          macro_inst|u_ahb2apb|paddr[8]|A 
    30. 

  30.         3.255    0.482   FF          macro_inst|u_ahb2apb|paddr[8]|A =>     macro_inst|u_ahb2apb|paddr[8]|LutOut 
    31. 

  31.         4.254    0.999   FF     macro_inst|u_ahb2apb|paddr[8]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~5|D 
    32. 

  32.         4.358    0.104   FR macro_inst|u_uart[0]|u_regs|Selector11~5|D => macro_inst|u_uart[0]|u_regs|Selector11~5|LutOut 
    33. 

  33.         4.759    0.401   RR macro_inst|u_uart[0]|u_regs|Selector11~5|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~7|B 
    34. 

  34.         5.278    0.519   RR macro_inst|u_uart[0]|u_regs|Selector11~7|B => macro_inst|u_uart[0]|u_regs|Selector11~7|LutOut 
    35. 

  35.         5.679    0.401   RR macro_inst|u_uart[0]|u_regs|Selector11~7|LutOut =>    macro_inst|u_uart[0]|u_regs|ibrd[1]|A 
    36. 

  36.         6.209    0.530   RR    macro_inst|u_uart[0]|u_regs|ibrd[1]|A => macro_inst|u_uart[0]|u_regs|ibrd[1]|LutOut 
    37. 

  37.         6.610    0.401   RR macro_inst|u_uart[0]|u_regs|ibrd[1]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~9|D 
    38. 

  38.         6.703    0.093   RF macro_inst|u_uart[0]|u_regs|Selector11~9|D => macro_inst|u_uart[0]|u_regs|Selector11~9|LutOut 
    39. 

  39.         7.702    0.999   FF macro_inst|u_uart[0]|u_regs|Selector11~9|LutOut =>   macro_inst|u_uart[1]|u_regs|ibrd[14]|D 
    40. 

  40.         7.810    0.108   FF   macro_inst|u_uart[1]|u_regs|ibrd[14]|D => macro_inst|u_uart[1]|u_regs|ibrd[14]|LutOut 
    41. 

  41.         8.193    0.383   FF macro_inst|u_uart[1]|u_regs|ibrd[14]|LutOut => macro_inst|u_uart[0]|u_regs|Selector11~10|D 
    42. 

  42.         8.301    0.108   FF macro_inst|u_uart[0]|u_regs|Selector11~10|D => macro_inst|u_uart[0]|u_regs|Selector11~10|LutOut 
    43. 

  43.         9.300    0.999   FF macro_inst|u_uart[0]|u_regs|Selector11~10|LutOut => macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|D 
    44. 

  44.         9.404    0.104   FR macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|D => macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|LutOut 
    45. 

  45.         9.805    0.401   RR macro_inst|u_uart[0]|u_regs|tx_dma_en[5]|LutOut => macro_inst|u_uart[0]|u_regs|apb_prdata[1]|D E
    46. 

  46.     Required Time:   8.728
    47. 

  47.         8.333    8.333   R                          Latch Clock Edge
    48. 

  48.       Latch Clock Path:
    49. 

  49.         8.333    0.000   RR                        test_uart|PIN_HSE =>                      PIN_HSE~input|padio 
    50. 

  50.         9.642    1.309   RR                      PIN_HSE~input|padio =>                    PIN_HSE~input|combout 
    51. 

  51.         9.869    0.227   RR                    PIN_HSE~input|combout =>       pll_inst|auto_generated|pll1|clkin 
    52. 

  52.       Compensation Path:
    53. 

  53.         5.933   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
    54. 

  54.         5.933   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
    55. 

  55.       Compensation Path End
    56. 

  56.         6.913    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout3 D
    57. 

  57.         7.268    0.355   RR     pll_inst|auto_generated|pll1|clkout3 =>                       bus_clk_gclk|inclk D
    58. 

  58.         7.268    0.000   RR                       bus_clk_gclk|inclk =>                      bus_clk_gclk|outclk 
    59. 

  59.         8.778    1.510   RR                      bus_clk_gclk|outclk =>               clken_ctrl_X58_Y4_N1|ClkIn 
    60. 

  60.         8.926    0.148   RR               clken_ctrl_X58_Y4_N1|ClkIn =>              clken_ctrl_X58_Y4_N1|ClkOut 
    61. 

  61.         9.057    0.131   RR              clken_ctrl_X58_Y4_N1|ClkOut => macro_inst|u_uart[0]|u_regs|apb_prdata[1]|Clk 
    62. 

  62.         8.705   -0.352   R                                     Setup
    63. 

  63.         8.728    0.023                               Clock Variation
    64. 

  64.