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alta.cellmap

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  1. macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] clken_ctrl_X43_Y1_N0
    2. 

  2. macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] clken_ctrl_X43_Y1_N0
    3. 

  3. macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY clken_ctrl_X43_Y1_N1
    4. 

  4. macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] clken_ctrl_X43_Y1_N1
    5. 

  5. macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA clken_ctrl_X43_Y1_N1
    6. 

  6. macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] clken_ctrl_X43_Y1_N0
    7. 

  7. macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START clken_ctrl_X43_Y1_N1
    8. 

  8. macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP clken_ctrl_X43_Y1_N1
    9. 

  9. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] clken_ctrl_X43_Y2_N0
    10. 

  10. macro_inst|u_uart[0]|u_rx[4]|rx_in[4] clken_ctrl_X43_Y2_N1
    11. 

  11. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] clken_ctrl_X43_Y2_N0
    12. 

  12. macro_inst|u_uart[0]|u_rx[4]|rx_in[2] clken_ctrl_X43_Y2_N1
    13. 

  13. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] clken_ctrl_X43_Y2_N0
    14. 

  14. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] clken_ctrl_X43_Y2_N0
    15. 

  15. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] clken_ctrl_X43_Y2_N0
    16. 

  16. macro_inst|u_uart[0]|u_rx[4]|rx_in[3] clken_ctrl_X43_Y2_N1
    17. 

  17. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] clken_ctrl_X43_Y2_N0
    18. 

  18. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] clken_ctrl_X43_Y2_N0
    19. 

  19. macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] clken_ctrl_X43_Y2_N0
    20. 

  20. macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] clken_ctrl_X43_Y3_N0
    21. 

  21. macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] clken_ctrl_X43_Y3_N0
    22. 

  22. macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] clken_ctrl_X43_Y3_N0
    23. 

  23. macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START clken_ctrl_X43_Y3_N1
    24. 

  24. macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] clken_ctrl_X43_Y3_N1
    25. 

  25. macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] clken_ctrl_X43_Y3_N1
    26. 

  26. macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] clken_ctrl_X43_Y3_N1
    27. 

  27. macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] clken_ctrl_X43_Y3_N1
    28. 

  28. macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] clken_ctrl_X43_Y3_N1
    29. 

  29. macro_inst|u_uart[0]|u_rx[5]|rx_bit clken_ctrl_X43_Y3_N1
    30. 

  30. macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY clken_ctrl_X43_Y4_N0
    31. 

  31. macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START clken_ctrl_X43_Y4_N0
    32. 

  32. macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA clken_ctrl_X43_Y4_N0
    33. 

  33. macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE clken_ctrl_X43_Y4_N0
    34. 

  34. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y1_N0
    35. 

  35. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y1_N0
    36. 

  36. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] clken_ctrl_X44_Y1_N1
    37. 

  37. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y1_N0
    38. 

  38. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y1_N0
    39. 

  39. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] clken_ctrl_X44_Y1_N1
    40. 

  40. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y1_N0
    41. 

  41. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] clken_ctrl_X44_Y1_N1
    42. 

  42. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y1_N0
    43. 

  43. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] clken_ctrl_X44_Y1_N1
    44. 

  44. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y2_N0
    45. 

  45. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] clken_ctrl_X44_Y2_N1
    46. 

  46. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y2_N1
    47. 

  47. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y2_N1
    48. 

  48. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y2_N1
    49. 

  49. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y2_N0
    50. 

  50. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y2_N1
    51. 

  51. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] clken_ctrl_X44_Y2_N0
    52. 

  52. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] clken_ctrl_X44_Y2_N1
    53. 

  53. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] clken_ctrl_X44_Y2_N0
    54. 

  54. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y2_N1
    55. 

  55. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y2_N1
    56. 

  56. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y2_N0
    57. 

  57. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y2_N0
    58. 

  58. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] clken_ctrl_X44_Y3_N0
    59. 

  59. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y3_N1
    60. 

  60. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] clken_ctrl_X44_Y3_N0
    61. 

  61. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] clken_ctrl_X44_Y3_N0
    62. 

  62. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] clken_ctrl_X44_Y3_N0
    63. 

  63. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] clken_ctrl_X44_Y3_N0
    64. 

  64. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y3_N1
    65. 

  65. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] clken_ctrl_X44_Y3_N0
    66. 

  66. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] clken_ctrl_X44_Y3_N0
    67. 

  67. macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] clken_ctrl_X44_Y3_N0
    68. 

  68. macro_inst|u_uart[0]|u_rx[5]|rx_parity clken_ctrl_X44_Y4_N0
    69. 

  69. macro_inst|u_uart[0]|u_rx[2]|rx_parity clken_ctrl_X45_Y1_N0
    70. 

  70. macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] clken_ctrl_X45_Y1_N0
    71. 

  71. macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] clken_ctrl_X45_Y1_N0
    72. 

  72. macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] clken_ctrl_X45_Y1_N0
    73. 

  73. macro_inst|u_uart[0]|u_tx[1]|tx_parity clken_ctrl_X45_Y1_N0
    74. 

  74. macro_inst|u_uart[0]|u_rx[1]|rx_in[0] clken_ctrl_X45_Y1_N1
    75. 

  75. macro_inst|u_uart[0]|u_tx[1]|uart_txd clken_ctrl_X45_Y1_N0
    76. 

  76. macro_inst|u_uart[0]|u_tx[5]|tx_bit clken_ctrl_X45_Y1_N0
    77. 

  77. macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA clken_ctrl_X45_Y1_N0
    78. 

  78. macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] clken_ctrl_X45_Y1_N0
    79. 

  79. macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] clken_ctrl_X45_Y2_N0
    80. 

  80. macro_inst|u_uart[0]|u_rx[4]|rx_parity clken_ctrl_X45_Y2_N0
    81. 

  81. macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START clken_ctrl_X45_Y2_N0
    82. 

  82. macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] clken_ctrl_X45_Y2_N0
    83. 

  83. macro_inst|u_uart[0]|u_rx[4]|break_error clken_ctrl_X45_Y2_N0
    84. 

  84. macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE clken_ctrl_X45_Y2_N0
    85. 

  85. macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] clken_ctrl_X45_Y2_N0
    86. 

  86. macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] clken_ctrl_X45_Y2_N0
    87. 

  87. macro_inst|u_uart[0]|u_rx[4]|rx_bit clken_ctrl_X45_Y2_N0
    88. 

  88. macro_inst|u_uart[0]|u_rx[5]|rx_in[3] clken_ctrl_X45_Y3_N0
    89. 

  89. macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP clken_ctrl_X45_Y3_N1
    90. 

  90. macro_inst|u_uart[0]|u_rx[1]|rx_in[1] clken_ctrl_X45_Y3_N0
    91. 

  91. macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA clken_ctrl_X45_Y3_N1
    92. 

  92. macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY clken_ctrl_X45_Y3_N1
    93. 

  93. macro_inst|u_uart[0]|u_rx[5]|rx_in[4] clken_ctrl_X45_Y3_N0
    94. 

  94. macro_inst|u_uart[0]|u_rx[1]|rx_in[4] clken_ctrl_X45_Y3_N0
    95. 

  95. macro_inst|u_uart[0]|u_rx[1]|rx_in[3] clken_ctrl_X45_Y3_N0
    96. 

  96. macro_inst|u_uart[0]|u_rx[5]|rx_in[2] clken_ctrl_X45_Y3_N0
    97. 

  97. macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE clken_ctrl_X45_Y3_N1
    98. 

  98. macro_inst|u_uart[0]|u_rx[1]|rx_in[2] clken_ctrl_X45_Y3_N0
    99. 

  99. macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] clken_ctrl_X45_Y4_N0
    100. 

  100. macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] clken_ctrl_X45_Y4_N0
    101. 

  101. macro_inst|u_uart[0]|u_regs|interrupts[1] clken_ctrl_X45_Y4_N1
    102. 

  102. macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY clken_ctrl_X46_Y1_N0
    103. 

  103. macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] clken_ctrl_X46_Y1_N0
    104. 

  104. macro_inst|u_uart[0]|u_rx[1]|rx_parity clken_ctrl_X46_Y1_N0
    105. 

  105. macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] clken_ctrl_X46_Y1_N1
    106. 

  106. macro_inst|u_uart[0]|u_tx[1]|tx_bit clken_ctrl_X46_Y1_N0
    107. 

  107. macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] clken_ctrl_X46_Y1_N1
    108. 

  108. macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP clken_ctrl_X46_Y1_N0
    109. 

  109. macro_inst|u_uart[0]|u_rx[3]|rx_parity clken_ctrl_X46_Y1_N0
    110. 

  110. macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] clken_ctrl_X46_Y1_N1
    111. 

  111. macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] clken_ctrl_X46_Y1_N0
    112. 

  112. macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] clken_ctrl_X46_Y1_N0
    113. 

  113. macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] clken_ctrl_X46_Y1_N0
    114. 

  114. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] clken_ctrl_X46_Y2_N0
    115. 

  115. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] clken_ctrl_X46_Y2_N0
    116. 

  116. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] clken_ctrl_X46_Y2_N0
    117. 

  117. macro_inst|u_uart[1]|u_regs|tx_dma_en[4] clken_ctrl_X46_Y2_N1
    118. 

  118. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] clken_ctrl_X46_Y2_N0
    119. 

  119. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] clken_ctrl_X46_Y2_N0
    120. 

  120. macro_inst|u_uart[1]|u_regs|rx_dma_en[4] clken_ctrl_X46_Y2_N1
    121. 

  121. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] clken_ctrl_X46_Y2_N0
    122. 

  122. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] clken_ctrl_X46_Y3_N0
    123. 

  123. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] clken_ctrl_X46_Y3_N0
    124. 

  124. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] clken_ctrl_X46_Y3_N0
    125. 

  125. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] clken_ctrl_X46_Y3_N1
    126. 

  126. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] clken_ctrl_X46_Y3_N0
    127. 

  127. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] clken_ctrl_X46_Y3_N1
    128. 

  128. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] clken_ctrl_X46_Y3_N0
    129. 

  129. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] clken_ctrl_X46_Y3_N1
    130. 

  130. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] clken_ctrl_X46_Y3_N0
    131. 

  131. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] clken_ctrl_X46_Y3_N0
    132. 

  132. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] clken_ctrl_X46_Y3_N1
    133. 

  133. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] clken_ctrl_X46_Y3_N1
    134. 

  134. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] clken_ctrl_X46_Y3_N1
    135. 

  135. macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] clken_ctrl_X46_Y3_N0
    136. 

  136. macro_inst|u_uart[0]|u_regs|tx_dma_en[3] clken_ctrl_X46_Y4_N0
    137. 

  137. macro_inst|u_uart[0]|u_regs|rx_dma_en[3] clken_ctrl_X46_Y4_N0
    138. 

  138. macro_inst|u_uart[0]|u_regs|rx_dma_en[2] clken_ctrl_X46_Y4_N1
    139. 

  139. macro_inst|u_uart[0]|u_regs|tx_dma_en[2] clken_ctrl_X46_Y4_N1
    140. 

  140. macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] clken_ctrl_X47_Y1_N0
    141. 

  141. macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] clken_ctrl_X47_Y1_N1
    142. 

  142. macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START clken_ctrl_X47_Y1_N1
    143. 

  143. macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] clken_ctrl_X47_Y1_N0
    144. 

  144. macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] clken_ctrl_X47_Y1_N0
    145. 

  145. macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] clken_ctrl_X47_Y1_N1
    146. 

  146. macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] clken_ctrl_X47_Y1_N1
    147. 

  147. macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] clken_ctrl_X47_Y1_N1
    148. 

  148. macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] clken_ctrl_X47_Y1_N1
    149. 

  149. macro_inst|u_uart[0]|u_regs|rx_reg[6] clken_ctrl_X47_Y2_N0
    150. 

  150. macro_inst|u_uart[0]|u_regs|rx_reg[5] clken_ctrl_X47_Y2_N0
    151. 

  151. macro_inst|u_uart[0]|u_regs|rx_reg[4] clken_ctrl_X47_Y2_N0
    152. 

  152. macro_inst|u_uart[0]|u_regs|rx_reg[2] clken_ctrl_X47_Y2_N0
    153. 

  153. macro_inst|u_uart[0]|u_regs|rx_reg[0] clken_ctrl_X47_Y2_N0
    154. 

  154. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] clken_ctrl_X47_Y2_N1
    155. 

  155. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] clken_ctrl_X47_Y2_N1
    156. 

  156. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] clken_ctrl_X47_Y2_N1
    157. 

  157. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] clken_ctrl_X47_Y2_N1
    158. 

  158. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] clken_ctrl_X47_Y2_N1
    159. 

  159. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] clken_ctrl_X47_Y2_N1
    160. 

  160. macro_inst|u_uart[0]|u_regs|rx_reg[3] clken_ctrl_X47_Y2_N0
    161. 

  161. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] clken_ctrl_X47_Y2_N1
    162. 

  162. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] clken_ctrl_X47_Y2_N1
    163. 

  163. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] clken_ctrl_X47_Y3_N0
    164. 

  164. macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY clken_ctrl_X47_Y3_N1
    165. 

  165. macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START clken_ctrl_X47_Y3_N1
    166. 

  166. macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE clken_ctrl_X47_Y3_N1
    167. 

  167. macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA clken_ctrl_X47_Y3_N1
    168. 

  168. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] clken_ctrl_X47_Y3_N0
    169. 

  169. macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP clken_ctrl_X47_Y3_N1
    170. 

  170. macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] clken_ctrl_X47_Y4_N0
    171. 

  171. macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA clken_ctrl_X47_Y4_N1
    172. 

  172. macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt clken_ctrl_X47_Y4_N1
    173. 

  173. macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP clken_ctrl_X47_Y4_N1
    174. 

  174. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] clken_ctrl_X48_Y1_N0
    175. 

  175. macro_inst|u_uart[0]|u_rx[3]|rx_in[4] clken_ctrl_X48_Y1_N1
    176. 

  176. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] clken_ctrl_X48_Y1_N0
    177. 

  177. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] clken_ctrl_X48_Y1_N0
    178. 

  178. macro_inst|u_uart[0]|u_rx[5]|rx_in[1] clken_ctrl_X48_Y1_N1
    179. 

  179. macro_inst|u_uart[0]|u_rx[3]|rx_in[2] clken_ctrl_X48_Y1_N1
    180. 

  180. macro_inst|u_uart[0]|u_rx[3]|rx_in[3] clken_ctrl_X48_Y1_N1
    181. 

  181. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] clken_ctrl_X48_Y1_N0
    182. 

  182. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] clken_ctrl_X48_Y1_N0
    183. 

  183. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] clken_ctrl_X48_Y1_N0
    184. 

  184. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] clken_ctrl_X48_Y1_N0
    185. 

  185. macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] clken_ctrl_X48_Y1_N0
    186. 

  186. macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP clken_ctrl_X48_Y2_N0
    187. 

  187. macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA clken_ctrl_X48_Y2_N0
    188. 

  188. macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE clken_ctrl_X48_Y2_N0
    189. 

  189. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] clken_ctrl_X48_Y2_N1
    190. 

  190. macro_inst|u_uart[0]|u_rx[3]|rx_bit clken_ctrl_X48_Y2_N0
    191. 

  191. macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY clken_ctrl_X48_Y2_N0
    192. 

  192. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] clken_ctrl_X48_Y2_N1
    193. 

  193. macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY clken_ctrl_X48_Y3_N0
    194. 

  194. macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA clken_ctrl_X48_Y3_N0
    195. 

  195. macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP clken_ctrl_X48_Y3_N0
    196. 

  196. macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] clken_ctrl_X48_Y4_N0
    197. 

  197. macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] clken_ctrl_X48_Y4_N0
    198. 

  198. macro_inst|u_uart[0]|u_regs|break_error_ie[1] clken_ctrl_X48_Y4_N1
    199. 

  199. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] clken_ctrl_X49_Y1_N0
    200. 

  200. macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] clken_ctrl_X49_Y1_N1
    201. 

  201. macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] clken_ctrl_X49_Y1_N1
    202. 

  202. macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] clken_ctrl_X49_Y1_N1
    203. 

  203. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] clken_ctrl_X49_Y1_N0
    204. 

  204. macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] clken_ctrl_X49_Y1_N1
    205. 

  205. macro_inst|u_uart[0]|u_rx[1]|rx_dma_req clken_ctrl_X49_Y2_N0
    206. 

  206. macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] clken_ctrl_X49_Y2_N0
    207. 

  207. macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] clken_ctrl_X49_Y2_N0
    208. 

  208. macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] clken_ctrl_X49_Y2_N0
    209. 

  209. macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] clken_ctrl_X49_Y2_N0
    210. 

  210. macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START clken_ctrl_X49_Y2_N0
    211. 

  211. macro_inst|u_uart[0]|u_rx[0]|rx_bit clken_ctrl_X49_Y2_N0
    212. 

  212. macro_inst|u_uart[0]|u_rx[0]|rx_in[3] clken_ctrl_X49_Y3_N0
    213. 

  213. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] clken_ctrl_X49_Y3_N1
    214. 

  214. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] clken_ctrl_X49_Y3_N1
    215. 

  215. macro_inst|u_uart[0]|u_rx[0]|rx_in[4] clken_ctrl_X49_Y3_N0
    216. 

  216. macro_inst|u_uart[0]|u_rx[0]|rx_in[1] clken_ctrl_X49_Y3_N0
    217. 

  217. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] clken_ctrl_X49_Y3_N1
    218. 

  218. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] clken_ctrl_X49_Y3_N1
    219. 

  219. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] clken_ctrl_X49_Y3_N1
    220. 

  220. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] clken_ctrl_X49_Y3_N1
    221. 

  221. macro_inst|u_uart[0]|u_rx[0]|rx_in[2] clken_ctrl_X49_Y3_N0
    222. 

  222. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] clken_ctrl_X49_Y3_N1
    223. 

  223. macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] clken_ctrl_X49_Y3_N1
    224. 

  224. macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] clken_ctrl_X49_Y4_N0
    225. 

  225. macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] clken_ctrl_X49_Y4_N0
    226. 

  226. macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] clken_ctrl_X49_Y4_N1
    227. 

  227. macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] clken_ctrl_X49_Y4_N1
    228. 

  228. macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] clken_ctrl_X49_Y4_N1
    229. 

  229. macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] clken_ctrl_X49_Y4_N0
    230. 

  230. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] clken_ctrl_X50_Y1_N0
    231. 

  231. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] clken_ctrl_X50_Y1_N0
    232. 

  232. macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] clken_ctrl_X50_Y1_N1
    233. 

  233. macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE clken_ctrl_X50_Y1_N1
    234. 

  234. macro_inst|u_uart[0]|u_rx[2]|rx_idle_en clken_ctrl_X50_Y1_N1
    235. 

  235. macro_inst|u_uart[0]|u_rx[2]|rx_bit clken_ctrl_X50_Y1_N1
    236. 

  236. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] clken_ctrl_X50_Y1_N0
    237. 

  237. macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] clken_ctrl_X50_Y1_N0
    238. 

  238. macro_inst|u_uart[0]|u_rx[2]|rx_idle clken_ctrl_X50_Y1_N1
    239. 

  239. macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] clken_ctrl_X50_Y2_N0
    240. 

  240. macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] clken_ctrl_X50_Y2_N0
    241. 

  241. macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] clken_ctrl_X50_Y2_N0
    242. 

  242. macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] clken_ctrl_X50_Y2_N0
    243. 

  243. macro_inst|u_uart[0]|u_rx[0]|rx_parity clken_ctrl_X50_Y2_N0
    244. 

  244. macro_inst|u_uart[0]|u_regs|rx_reg[1] clken_ctrl_X50_Y2_N0
    245. 

  245. macro_inst|u_uart[0]|u_rx[4]|rx_idle_en clken_ctrl_X50_Y2_N0
    246. 

  246. macro_inst|u_uart[0]|u_rx[1]|rx_bit clken_ctrl_X50_Y2_N0
    247. 

  247. macro_inst|u_ahb2apb|hdone clken_ctrl_X50_Y2_N1
    248. 

  248. macro_inst|u_uart[0]|u_regs|interrupts[2] clken_ctrl_X50_Y2_N0
    249. 

  249. macro_inst|u_ahb2apb|hreadyout clken_ctrl_X50_Y2_N1
    250. 

  250. macro_inst|u_uart[0]|u_rx[0]|break_error clken_ctrl_X50_Y2_N0
    251. 

  251. macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt clken_ctrl_X50_Y3_N0
    252. 

  252. macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA clken_ctrl_X50_Y3_N0
    253. 

  253. macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY clken_ctrl_X50_Y3_N0
    254. 

  254. macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] clken_ctrl_X50_Y3_N1
    255. 

  255. macro_inst|u_uart[1]|u_tx[5]|tx_bit clken_ctrl_X50_Y3_N0
    256. 

  256. macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP clken_ctrl_X50_Y3_N0
    257. 

  257. macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] clken_ctrl_X50_Y3_N1
    258. 

  258. macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] clken_ctrl_X50_Y3_N0
    259. 

  259. macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] clken_ctrl_X50_Y3_N1
    260. 

  260. macro_inst|u_uart[0]|u_regs|parity_error_ie[1] clken_ctrl_X50_Y4_N0
    261. 

  261. macro_inst|u_uart[0]|u_regs|framing_error_ie[1] clken_ctrl_X50_Y4_N0
    262. 

  262. macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] clken_ctrl_X51_Y1_N0
    263. 

  263. macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA clken_ctrl_X51_Y1_N1
    264. 

  264. macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] clken_ctrl_X51_Y1_N0
    265. 

  265. macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] clken_ctrl_X51_Y1_N0
    266. 

  266. macro_inst|u_uart[0]|u_tx[5]|uart_txd clken_ctrl_X51_Y1_N1
    267. 

  267. macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP clken_ctrl_X51_Y1_N1
    268. 

  268. macro_inst|u_uart[0]|u_tx[5]|tx_parity clken_ctrl_X51_Y1_N1
    269. 

  269. macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY clken_ctrl_X51_Y1_N1
    270. 

  270. macro_inst|u_uart[0]|u_tx[1]|tx_complete clken_ctrl_X51_Y2_N0
    271. 

  271. macro_inst|u_uart[0]|u_rx[1]|break_error clken_ctrl_X51_Y2_N0
    272. 

  272. macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE clken_ctrl_X51_Y2_N0
    273. 

  273. macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] clken_ctrl_X51_Y2_N1
    274. 

  274. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] clken_ctrl_X51_Y2_N0
    275. 

  275. macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] clken_ctrl_X51_Y2_N1
    276. 

  276. macro_inst|u_uart[0]|u_rx[0]|overrun_error clken_ctrl_X51_Y2_N0
    277. 

  277. macro_inst|u_uart[0]|u_rx[0]|parity_error clken_ctrl_X51_Y2_N0
    278. 

  278. macro_inst|u_uart[0]|u_rx[1]|parity_error clken_ctrl_X51_Y2_N0
    279. 

  279. macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] clken_ctrl_X51_Y2_N1
    280. 

  280. macro_inst|u_uart[0]|u_rx[1]|overrun_error clken_ctrl_X51_Y2_N0
    281. 

  281. macro_inst|sim_clk_cnt[1] clken_ctrl_X51_Y3_N0
    282. 

  282. macro_inst|sim_clk_cnt[2] clken_ctrl_X51_Y3_N0
    283. 

  283. macro_inst|sim_clk_cnt[3] clken_ctrl_X51_Y3_N0
    284. 

  284. macro_inst|sim_clk_cnt[4] clken_ctrl_X51_Y3_N0
    285. 

  285. macro_inst|sim_clk_cnt[5] clken_ctrl_X51_Y3_N0
    286. 

  286. macro_inst|sim_clk_cnt[6] clken_ctrl_X51_Y3_N0
    287. 

  287. macro_inst|sim_clk_cnt[7] clken_ctrl_X51_Y3_N0
    288. 

  288. macro_inst|sim_clk_reg clken_ctrl_X51_Y3_N0
    289. 

  289. macro_inst|sim_clk_cnt[0] clken_ctrl_X51_Y3_N0
    290. 

  290. macro_inst|u_uart[0]|u_regs|apb_prdata[0] clken_ctrl_X51_Y4_N0
    291. 

  291. macro_inst|u_uart[1]|u_regs|apb_prdata[0] clken_ctrl_X51_Y4_N1
    292. 

  292. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] clken_ctrl_X52_Y1_N0
    293. 

  293. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] clken_ctrl_X52_Y1_N0
    294. 

  294. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] clken_ctrl_X52_Y1_N0
    295. 

  295. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] clken_ctrl_X52_Y1_N1
    296. 

  296. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] clken_ctrl_X52_Y1_N1
    297. 

  297. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] clken_ctrl_X52_Y1_N1
    298. 

  298. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] clken_ctrl_X52_Y1_N1
    299. 

  299. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] clken_ctrl_X52_Y1_N1
    300. 

  300. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] clken_ctrl_X52_Y1_N0
    301. 

  301. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] clken_ctrl_X52_Y1_N0
    302. 

  302. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] clken_ctrl_X52_Y1_N1
    303. 

  303. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] clken_ctrl_X52_Y1_N0
    304. 

  304. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] clken_ctrl_X52_Y1_N1
    305. 

  305. macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] clken_ctrl_X52_Y1_N1
    306. 

  306. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] clken_ctrl_X52_Y1_N0
    307. 

  307. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] clken_ctrl_X52_Y1_N0
    308. 

  308. macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] clken_ctrl_X52_Y2_N0
    309. 

  309. macro_inst|u_uart[0]|u_regs|framing_error_ie[0] clken_ctrl_X52_Y2_N0
    310. 

  310. macro_inst|u_uart[0]|u_rx[1]|framing_error clken_ctrl_X52_Y2_N1
    311. 

  311. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] clken_ctrl_X52_Y2_N0
    312. 

  312. macro_inst|u_uart[0]|u_regs|parity_error_ie[0] clken_ctrl_X52_Y2_N0
    313. 

  313. macro_inst|u_uart[0]|u_regs|interrupts[0] clken_ctrl_X52_Y2_N1
    314. 

  314. macro_inst|u_uart[0]|u_regs|break_error_ie[0] clken_ctrl_X52_Y2_N0
    315. 

  315. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] clken_ctrl_X52_Y2_N0
    316. 

  316. macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] clken_ctrl_X52_Y2_N0
    317. 

  317. macro_inst|u_uart[0]|u_rx[0]|framing_error clken_ctrl_X52_Y2_N1
    318. 

  318. macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] clken_ctrl_X52_Y2_N0
    319. 

  319. macro_inst|u_uart[0]|u_tx[0]|tx_complete clken_ctrl_X52_Y2_N1
    320. 

  320. macro_inst|u_uart[0]|u_rx[1]|rx_idle clken_ctrl_X52_Y3_N0
    321. 

  321. macro_inst|u_uart[0]|u_regs|rx_read[0] clken_ctrl_X52_Y3_N0
    322. 

  322. macro_inst|u_uart[1]|u_rx[5]|rx_in[0] clken_ctrl_X52_Y3_N1
    323. 

  323. macro_inst|u_uart[1]|u_rx[1]|rx_bit clken_ctrl_X52_Y3_N0
    324. 

  324. macro_inst|u_uart[0]|u_rx[0]|rx_dma_req clken_ctrl_X52_Y3_N0
    325. 

  325. macro_inst|u_uart[0]|u_rx[1]|rx_idle_en clken_ctrl_X52_Y3_N0
    326. 

  326. macro_inst|u_uart[0]|u_rx[0]|rx_idle_en clken_ctrl_X52_Y3_N0
    327. 

  327. macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] clken_ctrl_X52_Y3_N0
    328. 

  328. macro_inst|u_uart[0]|u_rx[0]|rx_idle clken_ctrl_X52_Y3_N0
    329. 

  329. macro_inst|u_uart[1]|u_rx[5]|rx_in[1] clken_ctrl_X52_Y3_N1
    330. 

  330. macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY clken_ctrl_X52_Y4_N0
    331. 

  331. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] clken_ctrl_X52_Y4_N1
    332. 

  332. macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP clken_ctrl_X52_Y4_N0
    333. 

  333. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] clken_ctrl_X52_Y4_N1
    334. 

  334. macro_inst|u_uart[0]|u_tx[0]|uart_txd clken_ctrl_X53_Y1_N0
    335. 

  335. macro_inst|u_uart[0]|u_regs|status_reg[1] clken_ctrl_X53_Y1_N0
    336. 

  336. macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] clken_ctrl_X53_Y1_N0
    337. 

  337. macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] clken_ctrl_X53_Y1_N0
    338. 

  338. macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] clken_ctrl_X53_Y1_N0
    339. 

  339. macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] clken_ctrl_X53_Y1_N0
    340. 

  340. macro_inst|u_uart[0]|u_tx[0]|tx_bit clken_ctrl_X53_Y1_N0
    341. 

  341. macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] clken_ctrl_X53_Y1_N0
    342. 

  342. macro_inst|u_uart[0]|u_rx[0]|rx_in[0] clken_ctrl_X53_Y1_N1
    343. 

  343. macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] clken_ctrl_X53_Y2_N0
    344. 

  344. macro_inst|u_uart[0]|u_rx[3]|framing_error clken_ctrl_X53_Y2_N1
    345. 

  345. macro_inst|u_uart[0]|u_rx[3]|break_error clken_ctrl_X53_Y2_N1
    346. 

  346. macro_inst|u_uart[0]|u_rx[3]|parity_error clken_ctrl_X53_Y2_N1
    347. 

  347. macro_inst|u_uart[0]|u_regs|parity_error_ie[3] clken_ctrl_X53_Y2_N0
    348. 

  348. macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] clken_ctrl_X53_Y2_N0
    349. 

  349. macro_inst|u_uart[0]|u_rx[3]|rx_idle clken_ctrl_X53_Y2_N1
    350. 

  350. macro_inst|u_uart[0]|u_regs|interrupts[3] clken_ctrl_X53_Y2_N1
    351. 

  351. macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] clken_ctrl_X53_Y2_N0
    352. 

  352. macro_inst|u_uart[0]|u_rx[3]|overrun_error clken_ctrl_X53_Y2_N1
    353. 

  353. macro_inst|u_uart[0]|u_regs|break_error_ie[3] clken_ctrl_X53_Y2_N0
    354. 

  354. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] clken_ctrl_X53_Y2_N0
    355. 

  355. macro_inst|u_uart[0]|u_regs|framing_error_ie[3] clken_ctrl_X53_Y2_N0
    356. 

  356. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] clken_ctrl_X53_Y2_N0
    357. 

  357. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] clken_ctrl_X53_Y3_N0
    358. 

  358. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] clken_ctrl_X53_Y3_N0
    359. 

  359. macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE clken_ctrl_X53_Y3_N1
    360. 

  360. macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START clken_ctrl_X53_Y3_N1
    361. 

  361. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] clken_ctrl_X53_Y3_N1
    362. 

  362. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] clken_ctrl_X53_Y3_N0
    363. 

  363. macro_inst|u_uart[0]|u_baud|baud16 clken_ctrl_X53_Y3_N1
    364. 

  364. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] clken_ctrl_X53_Y3_N0
    365. 

  365. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] clken_ctrl_X53_Y3_N0
    366. 

  366. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] clken_ctrl_X53_Y3_N0
    367. 

  367. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] clken_ctrl_X53_Y3_N0
    368. 

  368. macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] clken_ctrl_X53_Y3_N0
    369. 

  369. macro_inst|u_uart[1]|u_rx[1]|rx_in[1] clken_ctrl_X53_Y4_N0
    370. 

  370. macro_inst|u_uart[1]|u_rx[4]|rx_in[3] clken_ctrl_X53_Y4_N0
    371. 

  371. macro_inst|u_uart[1]|u_rx[4]|rx_in[1] clken_ctrl_X53_Y4_N0
    372. 

  372. macro_inst|u_uart[1]|u_rx[3]|rx_in[1] clken_ctrl_X53_Y4_N0
    373. 

  373. macro_inst|u_uart[1]|u_rx[4]|rx_in[4] clken_ctrl_X53_Y4_N0
    374. 

  374. macro_inst|u_uart[0]|u_regs|interrupts[5] clken_ctrl_X53_Y4_N1
    375. 

  375. macro_inst|u_uart[1]|u_rx[3]|rx_in[0] clken_ctrl_X53_Y4_N0
    376. 

  376. macro_inst|u_uart[0]|u_regs|rx_read[1] clken_ctrl_X53_Y4_N1
    377. 

  377. macro_inst|u_uart[1]|u_rx[4]|rx_in[0] clken_ctrl_X53_Y4_N0
    378. 

  378. macro_inst|u_uart[0]|u_regs|rx_read[3] clken_ctrl_X53_Y4_N1
    379. 

  379. macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] clken_ctrl_X53_Y4_N1
    380. 

  380. macro_inst|u_uart[1]|u_rx[4]|rx_in[2] clken_ctrl_X53_Y4_N0
    381. 

  381. macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] clken_ctrl_X53_Y4_N1
    382. 

  382. macro_inst|u_uart[1]|u_rx[1]|rx_in[0] clken_ctrl_X53_Y4_N0
    383. 

  383. macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] clken_ctrl_X54_Y1_N0
    384. 

  384. macro_inst|u_uart[0]|u_tx[0]|tx_parity clken_ctrl_X54_Y1_N1
    385. 

  385. macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt clken_ctrl_X54_Y1_N1
    386. 

  386. macro_inst|u_uart[0]|u_regs|rx_read[2] clken_ctrl_X54_Y1_N1
    387. 

  387. macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP clken_ctrl_X54_Y1_N1
    388. 

  388. macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY clken_ctrl_X54_Y1_N1
    389. 

  389. macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] clken_ctrl_X54_Y1_N0
    390. 

  390. macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] clken_ctrl_X54_Y1_N0
    391. 

  391. macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA clken_ctrl_X54_Y1_N1
    392. 

  392. macro_inst|u_ahb2apb|haddr[12] clken_ctrl_X54_Y2_N0
    393. 

  393. macro_inst|u_uart[0]|u_regs|break_error_ie[2] clken_ctrl_X54_Y2_N1
    394. 

  394. macro_inst|u_ahb2apb|hwrite clken_ctrl_X54_Y2_N0
    395. 

  395. macro_inst|u_ahb2apb|haddr[7] clken_ctrl_X54_Y2_N0
    396. 

  396. macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] clken_ctrl_X54_Y2_N1
    397. 

  397. macro_inst|u_uart[0]|u_regs|parity_error_ie[2] clken_ctrl_X54_Y2_N1
    398. 

  398. macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] clken_ctrl_X54_Y2_N1
    399. 

  399. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] clken_ctrl_X54_Y2_N1
    400. 

  400. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] clken_ctrl_X54_Y2_N1
    401. 

  401. macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] clken_ctrl_X54_Y2_N1
    402. 

  402. macro_inst|u_uart[0]|u_regs|framing_error_ie[2] clken_ctrl_X54_Y2_N1
    403. 

  403. macro_inst|u_uart[0]|u_baud|i_cnt[0] clken_ctrl_X54_Y3_N0
    404. 

  404. macro_inst|u_uart[0]|u_baud|i_cnt[5] clken_ctrl_X54_Y3_N0
    405. 

  405. macro_inst|u_uart[0]|u_baud|i_cnt[6] clken_ctrl_X54_Y3_N0
    406. 

  406. macro_inst|u_uart[0]|u_baud|i_cnt[7] clken_ctrl_X54_Y3_N0
    407. 

  407. macro_inst|u_uart[0]|u_baud|i_cnt[8] clken_ctrl_X54_Y3_N0
    408. 

  408. macro_inst|u_uart[0]|u_baud|i_cnt[9] clken_ctrl_X54_Y3_N0
    409. 

  409. macro_inst|u_uart[0]|u_baud|i_cnt[1] clken_ctrl_X54_Y3_N0
    410. 

  410. macro_inst|u_uart[0]|u_baud|i_cnt[10] clken_ctrl_X54_Y3_N0
    411. 

  411. macro_inst|u_uart[0]|u_baud|i_cnt[11] clken_ctrl_X54_Y3_N0
    412. 

  412. macro_inst|u_uart[0]|u_baud|i_cnt[12] clken_ctrl_X54_Y3_N0
    413. 

  413. macro_inst|u_uart[0]|u_baud|i_cnt[13] clken_ctrl_X54_Y3_N0
    414. 

  414. macro_inst|u_uart[0]|u_baud|i_cnt[14] clken_ctrl_X54_Y3_N0
    415. 

  415. macro_inst|u_uart[0]|u_baud|i_cnt[15] clken_ctrl_X54_Y3_N0
    416. 

  416. macro_inst|u_uart[0]|u_baud|i_cnt[2] clken_ctrl_X54_Y3_N0
    417. 

  417. macro_inst|u_uart[0]|u_baud|i_cnt[3] clken_ctrl_X54_Y3_N0
    418. 

  418. macro_inst|u_uart[0]|u_baud|i_cnt[4] clken_ctrl_X54_Y3_N0
    419. 

  419. macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] clken_ctrl_X54_Y4_N0
    420. 

  420. macro_inst|u_uart[1]|u_regs|tx_write[2] clken_ctrl_X54_Y4_N1
    421. 

  421. macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] clken_ctrl_X54_Y4_N0
    422. 

  422. macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] clken_ctrl_X54_Y4_N0
    423. 

  423. macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] clken_ctrl_X54_Y4_N1
    424. 

  424. macro_inst|u_uart[1]|u_rx[0]|rx_parity clken_ctrl_X54_Y4_N1
    425. 

  425. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] clken_ctrl_X56_Y10_N0
    426. 

  426. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] clken_ctrl_X56_Y10_N1
    427. 

  427. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] clken_ctrl_X56_Y10_N0
    428. 

  428. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] clken_ctrl_X56_Y10_N0
    429. 

  429. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] clken_ctrl_X56_Y10_N1
    430. 

  430. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] clken_ctrl_X56_Y10_N1
    431. 

  431. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] clken_ctrl_X56_Y10_N0
    432. 

  432. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] clken_ctrl_X56_Y10_N1
    433. 

  433. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] clken_ctrl_X56_Y10_N0
    434. 

  434. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] clken_ctrl_X56_Y10_N1
    435. 

  435. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] clken_ctrl_X56_Y10_N1
    436. 

  436. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] clken_ctrl_X56_Y10_N0
    437. 

  437. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] clken_ctrl_X56_Y10_N1
    438. 

  438. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] clken_ctrl_X56_Y10_N1
    439. 

  439. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] clken_ctrl_X56_Y10_N0
    440. 

  440. macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] clken_ctrl_X56_Y10_N0
    441. 

  441. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] clken_ctrl_X56_Y11_N0
    442. 

  442. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] clken_ctrl_X56_Y11_N0
    443. 

  443. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] clken_ctrl_X56_Y11_N1
    444. 

  444. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] clken_ctrl_X56_Y11_N0
    445. 

  445. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] clken_ctrl_X56_Y11_N1
    446. 

  446. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] clken_ctrl_X56_Y11_N0
    447. 

  447. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] clken_ctrl_X56_Y11_N1
    448. 

  448. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] clken_ctrl_X56_Y11_N1
    449. 

  449. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] clken_ctrl_X56_Y11_N0
    450. 

  450. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] clken_ctrl_X56_Y11_N1
    451. 

  451. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] clken_ctrl_X56_Y11_N1
    452. 

  452. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] clken_ctrl_X56_Y11_N0
    453. 

  453. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] clken_ctrl_X56_Y11_N1
    454. 

  454. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] clken_ctrl_X56_Y11_N0
    455. 

  455. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] clken_ctrl_X56_Y11_N1
    456. 

  456. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] clken_ctrl_X56_Y12_N0
    457. 

  457. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] clken_ctrl_X56_Y12_N1
    458. 

  458. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] clken_ctrl_X56_Y12_N1
    459. 

  459. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] clken_ctrl_X56_Y12_N1
    460. 

  460. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] clken_ctrl_X56_Y12_N0
    461. 

  461. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] clken_ctrl_X56_Y12_N1
    462. 

  462. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] clken_ctrl_X56_Y12_N1
    463. 

  463. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] clken_ctrl_X56_Y12_N0
    464. 

  464. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] clken_ctrl_X56_Y12_N1
    465. 

  465. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] clken_ctrl_X56_Y12_N0
    466. 

  466. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] clken_ctrl_X56_Y12_N1
    467. 

  467. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] clken_ctrl_X56_Y12_N0
    468. 

  468. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] clken_ctrl_X56_Y12_N0
    469. 

  469. macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] clken_ctrl_X56_Y12_N1
    470. 

  470. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] clken_ctrl_X56_Y12_N0
    471. 

  471. macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] clken_ctrl_X56_Y12_N0
    472. 

  472. macro_inst|u_uart[0]|u_rx[2]|break_error clken_ctrl_X56_Y1_N0
    473. 

  473. macro_inst|u_uart[0]|u_rx[5]|rx_in[0] clken_ctrl_X56_Y1_N1
    474. 

  474. macro_inst|u_uart[0]|u_rx[3]|rx_idle_en clken_ctrl_X56_Y1_N0
    475. 

  475. macro_inst|u_uart[0]|u_rx[2]|overrun_error clken_ctrl_X56_Y1_N0
    476. 

  476. macro_inst|u_uart[0]|u_tx[0]|tx_dma_req clken_ctrl_X56_Y1_N0
    477. 

  477. macro_inst|u_uart[0]|u_rx[2]|framing_error clken_ctrl_X56_Y1_N0
    478. 

  478. macro_inst|u_uart[0]|u_rx[3]|rx_in[1] clken_ctrl_X56_Y1_N1
    479. 

  479. macro_inst|u_uart[0]|u_rx[2]|rx_in[3] clken_ctrl_X56_Y1_N1
    480. 

  480. macro_inst|u_uart[0]|u_rx[2]|rx_in[0] clken_ctrl_X56_Y1_N1
    481. 

  481. macro_inst|u_uart[0]|u_rx[2]|rx_in[4] clken_ctrl_X56_Y1_N1
    482. 

  482. macro_inst|u_uart[0]|u_rx[2]|rx_in[2] clken_ctrl_X56_Y1_N1
    483. 

  483. macro_inst|u_uart[0]|u_rx[2]|rx_in[1] clken_ctrl_X56_Y1_N1
    484. 

  484. macro_inst|u_uart[0]|u_tx[3]|tx_complete clken_ctrl_X56_Y1_N0
    485. 

  485. macro_inst|u_uart[0]|u_rx[3]|rx_in[0] clken_ctrl_X56_Y1_N1
    486. 

  486. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] clken_ctrl_X56_Y2_N0
    487. 

  487. macro_inst|u_uart[0]|u_regs|apb_prdata[5] clken_ctrl_X56_Y2_N1
    488. 

  488. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] clken_ctrl_X56_Y2_N0
    489. 

  489. macro_inst|u_uart[0]|u_rx[4]|rx_idle clken_ctrl_X56_Y3_N0
    490. 

  490. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] clken_ctrl_X56_Y3_N1
    491. 

  491. macro_inst|u_ahb2apb|apbState.apbSetup clken_ctrl_X56_Y3_N0
    492. 

  492. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] clken_ctrl_X56_Y3_N1
    493. 

  493. macro_inst|u_ahb2apb|pvalid clken_ctrl_X56_Y3_N0
    494. 

  494. macro_inst|u_uart[0]|u_regs|tx_write[0] clken_ctrl_X56_Y3_N0
    495. 

  495. macro_inst|u_uart[0]|u_rx[5]|rx_idle clken_ctrl_X56_Y3_N0
    496. 

  496. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] clken_ctrl_X56_Y3_N1
    497. 

  497. macro_inst|u_ahb2apb|apbState.apbIdle clken_ctrl_X56_Y3_N0
    498. 

  498. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] clken_ctrl_X56_Y3_N1
    499. 

  499. macro_inst|u_ahb2apb|apbState.apbAccess clken_ctrl_X56_Y3_N0
    500. 

  500. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] clken_ctrl_X56_Y3_N1
    501. 

  501. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] clken_ctrl_X56_Y3_N1
    502. 

  502. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] clken_ctrl_X56_Y3_N1
    503. 

  503. macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] clken_ctrl_X56_Y3_N1
    504. 

  504. macro_inst|u_uart[1]|u_regs|tx_dma_en[2] clken_ctrl_X56_Y4_N0
    505. 

  505. macro_inst|u_uart[1]|u_regs|rx_dma_en[2] clken_ctrl_X56_Y4_N0
    506. 

  506. macro_inst|u_uart[1]|u_regs|tx_dma_en[3] clken_ctrl_X56_Y4_N1
    507. 

  507. macro_inst|u_uart[1]|u_regs|rx_dma_en[3] clken_ctrl_X56_Y4_N1
    508. 

  508. macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START clken_ctrl_X56_Y5_N0
    509. 

  509. macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt clken_ctrl_X56_Y5_N0
    510. 

  510. macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE clken_ctrl_X56_Y5_N0
    511. 

  511. macro_inst|u_uart[1]|u_regs|status_reg[4] clken_ctrl_X56_Y5_N0
    512. 

  512. macro_inst|u_uart[1]|u_regs|status_reg[2] clken_ctrl_X56_Y5_N0
    513. 

  513. macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE clken_ctrl_X56_Y5_N0
    514. 

  514. macro_inst|u_uart[0]|u_regs|rx_reg[7] clken_ctrl_X56_Y5_N0
    515. 

  515. macro_inst|u_uart[1]|u_tx[5]|uart_txd clken_ctrl_X56_Y5_N0
    516. 

  516. macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] clken_ctrl_X56_Y6_N0
    517. 

  517. macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] clken_ctrl_X56_Y6_N1
    518. 

  518. macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] clken_ctrl_X56_Y6_N1
    519. 

  519. macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] clken_ctrl_X56_Y6_N1
    520. 

  520. macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] clken_ctrl_X56_Y6_N1
    521. 

  521. macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] clken_ctrl_X56_Y6_N0
    522. 

  522. macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA clken_ctrl_X56_Y6_N1
    523. 

  523. macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] clken_ctrl_X56_Y6_N1
    524. 

  524. macro_inst|u_uart[1]|u_regs|tx_write[0] clken_ctrl_X56_Y7_N0
    525. 

  525. macro_inst|u_uart[1]|u_tx[1]|uart_txd clken_ctrl_X56_Y7_N0
    526. 

  526. macro_inst|u_uart[1]|u_tx[1]|tx_parity clken_ctrl_X56_Y7_N0
    527. 

  527. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] clken_ctrl_X56_Y7_N0
    528. 

  528. macro_inst|u_uart[1]|u_tx[0]|uart_txd clken_ctrl_X56_Y7_N0
    529. 

  529. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] clken_ctrl_X56_Y7_N1
    530. 

  530. macro_inst|u_uart[1]|u_rx[1]|rx_parity clken_ctrl_X56_Y7_N0
    531. 

  531. macro_inst|u_uart[1]|u_rx[2]|rx_idle_en clken_ctrl_X56_Y7_N0
    532. 

  532. macro_inst|u_uart[1]|u_rx[2]|rx_bit clken_ctrl_X56_Y7_N0
    533. 

  533. macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt clken_ctrl_X56_Y7_N0
    534. 

  534. macro_inst|u_uart[1]|u_rx[0]|rx_idle_en clken_ctrl_X56_Y7_N0
    535. 

  535. macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START clken_ctrl_X56_Y8_N0
    536. 

  536. macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] clken_ctrl_X56_Y8_N1
    537. 

  537. macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] clken_ctrl_X56_Y8_N0
    538. 

  538. macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] clken_ctrl_X56_Y8_N0
    539. 

  539. macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] clken_ctrl_X56_Y8_N0
    540. 

  540. macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] clken_ctrl_X56_Y8_N1
    541. 

  541. macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] clken_ctrl_X56_Y8_N0
    542. 

  542. macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] clken_ctrl_X56_Y8_N1
    543. 

  543. macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP clken_ctrl_X56_Y8_N0
    544. 

  544. macro_inst|u_uart[1]|u_tx[1]|tx_bit clken_ctrl_X56_Y8_N0
    545. 

  545. macro_inst|u_uart[1]|u_rx[2]|rx_parity clken_ctrl_X56_Y8_N0
    546. 

  546. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] clken_ctrl_X56_Y9_N0
    547. 

  547. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] clken_ctrl_X56_Y9_N0
    548. 

  548. macro_inst|u_uart[1]|u_rx[1]|rx_in[4] clken_ctrl_X56_Y9_N1
    549. 

  549. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] clken_ctrl_X56_Y9_N0
    550. 

  550. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] clken_ctrl_X56_Y9_N0
    551. 

  551. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] clken_ctrl_X56_Y9_N0
    552. 

  552. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] clken_ctrl_X56_Y9_N0
    553. 

  553. macro_inst|u_uart[1]|u_rx[1]|rx_in[2] clken_ctrl_X56_Y9_N1
    554. 

  554. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] clken_ctrl_X56_Y9_N0
    555. 

  555. macro_inst|u_uart[1]|u_rx[1]|rx_in[3] clken_ctrl_X56_Y9_N1
    556. 

  556. macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] clken_ctrl_X56_Y9_N0
    557. 

  557. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] clken_ctrl_X57_Y10_N0
    558. 

  558. macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY clken_ctrl_X57_Y10_N1
    559. 

  559. macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA clken_ctrl_X57_Y10_N1
    560. 

  560. macro_inst|u_uart[1]|u_tx[2]|tx_bit clken_ctrl_X57_Y10_N1
    561. 

  561. macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP clken_ctrl_X57_Y10_N1
    562. 

  562. macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START clken_ctrl_X57_Y10_N1
    563. 

  563. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] clken_ctrl_X57_Y10_N0
    564. 

  564. macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt clken_ctrl_X57_Y10_N1
    565. 

  565. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] clken_ctrl_X57_Y10_N0
    566. 

  566. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] clken_ctrl_X57_Y10_N0
    567. 

  567. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] clken_ctrl_X57_Y11_N0
    568. 

  568. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] clken_ctrl_X57_Y11_N0
    569. 

  569. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] clken_ctrl_X57_Y11_N1
    570. 

  570. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] clken_ctrl_X57_Y11_N1
    571. 

  571. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] clken_ctrl_X57_Y11_N1
    572. 

  572. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] clken_ctrl_X57_Y11_N0
    573. 

  573. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] clken_ctrl_X57_Y11_N1
    574. 

  574. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] clken_ctrl_X57_Y11_N1
    575. 

  575. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] clken_ctrl_X57_Y11_N0
    576. 

  576. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] clken_ctrl_X57_Y11_N1
    577. 

  577. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] clken_ctrl_X57_Y11_N0
    578. 

  578. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] clken_ctrl_X57_Y11_N0
    579. 

  579. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] clken_ctrl_X57_Y11_N1
    580. 

  580. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] clken_ctrl_X57_Y11_N0
    581. 

  581. macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] clken_ctrl_X57_Y11_N0
    582. 

  582. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] clken_ctrl_X57_Y11_N1
    583. 

  583. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] clken_ctrl_X57_Y12_N0
    584. 

  584. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] clken_ctrl_X57_Y12_N1
    585. 

  585. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] clken_ctrl_X57_Y12_N1
    586. 

  586. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] clken_ctrl_X57_Y12_N0
    587. 

  587. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] clken_ctrl_X57_Y12_N1
    588. 

  588. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] clken_ctrl_X57_Y12_N0
    589. 

  589. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] clken_ctrl_X57_Y12_N1
    590. 

  590. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] clken_ctrl_X57_Y12_N0
    591. 

  591. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] clken_ctrl_X57_Y12_N0
    592. 

  592. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] clken_ctrl_X57_Y12_N1
    593. 

  593. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] clken_ctrl_X57_Y12_N0
    594. 

  594. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] clken_ctrl_X57_Y12_N1
    595. 

  595. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] clken_ctrl_X57_Y12_N1
    596. 

  596. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] clken_ctrl_X57_Y12_N0
    597. 

  597. macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] clken_ctrl_X57_Y12_N1
    598. 

  598. macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] clken_ctrl_X57_Y12_N0
    599. 

  599. macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START clken_ctrl_X57_Y1_N0
    600. 

  600. macro_inst|u_uart[0]|u_regs|tx_dma_en[4] clken_ctrl_X57_Y1_N1
    601. 

  601. macro_inst|u_uart[0]|u_regs|rx_dma_en[4] clken_ctrl_X57_Y1_N1
    602. 

  602. macro_inst|u_uart[0]|u_tx[5]|tx_complete clken_ctrl_X57_Y1_N0
    603. 

  603. macro_inst|u_uart[0]|u_tx[2]|tx_complete clken_ctrl_X57_Y1_N0
    604. 

  604. macro_inst|u_uart[0]|u_rx[2]|parity_error clken_ctrl_X57_Y1_N0
    605. 

  605. macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] clken_ctrl_X57_Y1_N0
    606. 

  606. macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt clken_ctrl_X57_Y1_N0
    607. 

  607. macro_inst|u_uart[0]|u_rx[5]|rx_idle_en clken_ctrl_X57_Y1_N0
    608. 

  608. macro_inst|u_uart[0]|u_regs|rx_read[4] clken_ctrl_X57_Y1_N0
    609. 

  609. macro_inst|u_uart[0]|u_rx[5]|overrun_error clken_ctrl_X57_Y1_N0
    610. 

  610. macro_inst|u_uart[0]|u_regs|rx_read[5] clken_ctrl_X57_Y1_N0
    611. 

  611. macro_inst|u_uart[0]|u_regs|tx_write[5] clken_ctrl_X57_Y1_N0
    612. 

  612. macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] clken_ctrl_X57_Y1_N0
    613. 

  613. macro_inst|u_uart[0]|u_regs|rx_dma_en[0] clken_ctrl_X57_Y2_N0
    614. 

  614. macro_inst|u_uart[0]|u_regs|rx_dma_en[1] clken_ctrl_X57_Y2_N1
    615. 

  615. macro_inst|u_uart[0]|u_regs|tx_dma_en[0] clken_ctrl_X57_Y2_N0
    616. 

  616. macro_inst|u_uart[0]|u_regs|tx_dma_en[1] clken_ctrl_X57_Y2_N1
    617. 

  617. macro_inst|u_uart[0]|u_rx[4]|overrun_error clken_ctrl_X57_Y3_N0
    618. 

  618. macro_inst|u_uart[0]|u_regs|break_error_ie[4] clken_ctrl_X57_Y3_N1
    619. 

  619. macro_inst|u_uart[0]|u_regs|parity_error_ie[4] clken_ctrl_X57_Y3_N1
    620. 

  620. macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] clken_ctrl_X57_Y3_N1
    621. 

  621. macro_inst|u_uart[0]|u_regs|interrupts[4] clken_ctrl_X57_Y3_N0
    622. 

  622. macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] clken_ctrl_X57_Y3_N1
    623. 

  623. macro_inst|u_uart[0]|u_rx[4]|parity_error clken_ctrl_X57_Y3_N0
    624. 

  624. macro_inst|u_uart[0]|u_regs|status_reg[4] clken_ctrl_X57_Y3_N0
    625. 

  625. macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] clken_ctrl_X57_Y3_N1
    626. 

  626. macro_inst|u_uart[0]|u_tx[4]|tx_complete clken_ctrl_X57_Y3_N0
    627. 

  627. macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] clken_ctrl_X57_Y3_N1
    628. 

  628. macro_inst|u_uart[0]|u_regs|framing_error_ie[4] clken_ctrl_X57_Y3_N1
    629. 

  629. macro_inst|u_uart[0]|u_rx[4]|framing_error clken_ctrl_X57_Y3_N0
    630. 

  630. macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] clken_ctrl_X57_Y3_N1
    631. 

  631. macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] clken_ctrl_X57_Y4_N1
    632. 

  632. macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] clken_ctrl_X57_Y4_N0
    633. 

  633. macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] clken_ctrl_X57_Y4_N0
    634. 

  634. macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] clken_ctrl_X57_Y4_N1
    635. 

  635. macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA clken_ctrl_X57_Y4_N1
    636. 

  636. macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] clken_ctrl_X57_Y4_N1
    637. 

  637. macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] clken_ctrl_X57_Y4_N0
    638. 

  638. macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] clken_ctrl_X57_Y4_N1
    639. 

  639. macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] clken_ctrl_X57_Y4_N1
    640. 

  640. macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START clken_ctrl_X57_Y4_N1
    641. 

  641. pll_inst|auto_generated|pll_lock_sync clken_ctrl_X57_Y5_N0
    642. 

  642. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] clken_ctrl_X57_Y6_N0
    643. 

  643. macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] clken_ctrl_X57_Y6_N1
    644. 

  644. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] clken_ctrl_X57_Y6_N0
    645. 

  645. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] clken_ctrl_X57_Y6_N0
    646. 

  646. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] clken_ctrl_X57_Y7_N0
    647. 

  647. macro_inst|u_uart[1]|u_regs|rx_read[2] clken_ctrl_X57_Y7_N1
    648. 

  648. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
    649. 

  649. macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA clken_ctrl_X57_Y7_N1
    650. 

  650. macro_inst|u_uart[1]|u_regs|interrupts[1] clken_ctrl_X57_Y7_N1
    651. 

  651. macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
    652. 

  652. macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
    653. 

  653. macro_inst|u_uart[1]|u_regs|rx_read[3] clken_ctrl_X57_Y7_N1
    654. 

  654. macro_inst|u_uart[1]|u_rx[2]|rx_idle clken_ctrl_X57_Y7_N1
    655. 

  655. macro_inst|u_uart[1]|u_regs|rx_read[0] clken_ctrl_X57_Y7_N1
    656. 

  656. macro_inst|u_uart[1]|u_regs|status_reg[0] clken_ctrl_X57_Y7_N1
    657. 

  657. macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE clken_ctrl_X57_Y7_N1
    658. 

  658. macro_inst|u_uart[1]|u_rx[0]|rx_in[4] clken_ctrl_X57_Y8_N0
    659. 

  659. macro_inst|u_uart[1]|u_rx[0]|rx_in[3] clken_ctrl_X57_Y8_N0
    660. 

  660. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] clken_ctrl_X57_Y8_N1
    661. 

  661. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] clken_ctrl_X57_Y8_N1
    662. 

  662. macro_inst|u_uart[1]|u_rx[0]|rx_in[0] clken_ctrl_X57_Y8_N0
    663. 

  663. macro_inst|u_uart[1]|u_rx[0]|rx_in[2] clken_ctrl_X57_Y8_N0
    664. 

  664. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] clken_ctrl_X57_Y8_N1
    665. 

  665. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] clken_ctrl_X57_Y8_N1
    666. 

  666. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] clken_ctrl_X57_Y8_N1
    667. 

  667. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] clken_ctrl_X57_Y8_N1
    668. 

  668. macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] clken_ctrl_X57_Y8_N1
    669. 

  669. macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP clken_ctrl_X57_Y9_N0
    670. 

  670. macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY clken_ctrl_X57_Y9_N0
    671. 

  671. macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] clken_ctrl_X57_Y9_N1
    672. 

  672. macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] clken_ctrl_X57_Y9_N0
    673. 

  673. macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] clken_ctrl_X57_Y9_N0
    674. 

  674. macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] clken_ctrl_X57_Y9_N0
    675. 

  675. macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA clken_ctrl_X57_Y9_N0
    676. 

  676. macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] clken_ctrl_X57_Y9_N0
    677. 

  677. macro_inst|u_uart[1]|u_tx[0]|tx_bit clken_ctrl_X57_Y9_N0
    678. 

  678. macro_inst|u_uart[1]|u_tx[0]|tx_parity clken_ctrl_X57_Y9_N0
    679. 

  679. macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START clken_ctrl_X57_Y9_N0
    680. 

  680. macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] clken_ctrl_X57_Y9_N1
    681. 

  681. macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] clken_ctrl_X57_Y9_N1
    682. 

  682. macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] clken_ctrl_X58_Y10_N1
    683. 

  683. macro_inst|u_uart[1]|u_tx[2]|uart_txd clken_ctrl_X58_Y10_N0
    684. 

  684. macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] clken_ctrl_X58_Y10_N1
    685. 

  685. macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] clken_ctrl_X58_Y10_N0
    686. 

  686. macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] clken_ctrl_X58_Y10_N0
    687. 

  687. macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] clken_ctrl_X58_Y10_N0
    688. 

  688. macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] clken_ctrl_X58_Y10_N0
    689. 

  689. macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] clken_ctrl_X58_Y10_N1
    690. 

  690. macro_inst|u_uart[1]|u_tx[2]|tx_parity clken_ctrl_X58_Y10_N0
    691. 

  691. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] clken_ctrl_X58_Y11_N0
    692. 

  692. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] clken_ctrl_X58_Y11_N0
    693. 

  693. macro_inst|u_uart[1]|u_regs|rx_reg[0] clken_ctrl_X58_Y11_N1
    694. 

  694. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] clken_ctrl_X58_Y11_N0
    695. 

  695. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] clken_ctrl_X58_Y11_N0
    696. 

  696. macro_inst|u_uart[1]|u_regs|rx_reg[6] clken_ctrl_X58_Y11_N1
    697. 

  697. macro_inst|u_uart[1]|u_regs|rx_reg[5] clken_ctrl_X58_Y11_N1
    698. 

  698. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] clken_ctrl_X58_Y11_N0
    699. 

  699. macro_inst|u_uart[1]|u_regs|rx_reg[1] clken_ctrl_X58_Y11_N1
    700. 

  700. macro_inst|u_uart[1]|u_regs|rx_reg[4] clken_ctrl_X58_Y11_N1
    701. 

  701. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] clken_ctrl_X58_Y11_N0
    702. 

  702. macro_inst|u_uart[1]|u_regs|rx_reg[7] clken_ctrl_X58_Y11_N1
    703. 

  703. macro_inst|u_uart[1]|u_regs|rx_reg[3] clken_ctrl_X58_Y11_N1
    704. 

  704. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] clken_ctrl_X58_Y11_N0
    705. 

  705. macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] clken_ctrl_X58_Y11_N0
    706. 

  706. macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA clken_ctrl_X58_Y12_N0
    707. 

  707. macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] clken_ctrl_X58_Y12_N0
    708. 

  708. macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] clken_ctrl_X58_Y12_N0
    709. 

  709. macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] clken_ctrl_X58_Y12_N0
    710. 

  710. macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] clken_ctrl_X58_Y12_N0
    711. 

  711. macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START clken_ctrl_X58_Y12_N0
    712. 

  712. macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE clken_ctrl_X58_Y12_N0
    713. 

  713. macro_inst|u_uart[1]|u_rx[4]|rx_bit clken_ctrl_X58_Y12_N0
    714. 

  714. macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] clken_ctrl_X58_Y1_N0
    715. 

  715. macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] clken_ctrl_X58_Y1_N0
    716. 

  716. macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE clken_ctrl_X58_Y1_N1
    717. 

  717. macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA clken_ctrl_X58_Y1_N1
    718. 

  718. macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY clken_ctrl_X58_Y1_N1
    719. 

  719. macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START clken_ctrl_X58_Y1_N1
    720. 

  720. macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt clken_ctrl_X58_Y1_N1
    721. 

  721. macro_inst|u_uart[0]|u_regs|status_reg[0] clken_ctrl_X58_Y1_N1
    722. 

  722. macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP clken_ctrl_X58_Y1_N1
    723. 

  723. macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] clken_ctrl_X58_Y1_N0
    724. 

  724. macro_inst|u_uart[0]|u_regs|ibrd[2] clken_ctrl_X58_Y2_N0
    725. 

  725. macro_inst|u_uart[1]|u_regs|ibrd[1] clken_ctrl_X58_Y2_N1
    726. 

  726. macro_inst|u_uart[0]|u_regs|ibrd[1] clken_ctrl_X58_Y2_N0
    727. 

  727. macro_inst|u_uart[0]|u_regs|ibrd[3] clken_ctrl_X58_Y2_N0
    728. 

  728. macro_inst|u_uart[0]|u_regs|ibrd[10] clken_ctrl_X58_Y2_N0
    729. 

  729. macro_inst|u_uart[0]|u_regs|apb_pready clken_ctrl_X58_Y3_N1
    730. 

  730. macro_inst|u_uart[1]|u_rx[2]|rx_in[0] clken_ctrl_X58_Y3_N0
    731. 

  731. macro_inst|u_uart[0]|u_rx[5]|framing_error clken_ctrl_X58_Y3_N1
    732. 

  732. macro_inst|u_uart[0]|u_rx[5]|break_error clken_ctrl_X58_Y3_N1
    733. 

  733. macro_inst|u_uart[1]|u_regs|apb_pready clken_ctrl_X58_Y3_N1
    734. 

  734. macro_inst|u_uart[0]|u_regs|status_reg[2] clken_ctrl_X58_Y3_N1
    735. 

  735. macro_inst|u_ahb2apb|penable clken_ctrl_X58_Y3_N1
    736. 

  736. macro_inst|u_uart[1]|u_rx[1]|parity_error clken_ctrl_X58_Y3_N1
    737. 

  737. macro_inst|u_uart[0]|u_rx[5]|parity_error clken_ctrl_X58_Y3_N1
    738. 

  738. macro_inst|u_uart[1]|u_rx[0]|parity_error clken_ctrl_X58_Y3_N1
    739. 

  739. macro_inst|u_ahb2apb|pdone clken_ctrl_X58_Y3_N1
    740. 

  740. macro_inst|u_ahb2apb|psel clken_ctrl_X58_Y3_N1
    741. 

  741. macro_inst|u_uart[0]|u_regs|rx_dma_en[5] clken_ctrl_X58_Y4_N0
    742. 

  742. macro_inst|u_uart[0]|u_regs|tx_dma_en[5] clken_ctrl_X58_Y4_N0
    743. 

  743. macro_inst|u_uart[0]|u_regs|apb_prdata[1] clken_ctrl_X58_Y4_N1
    744. 

  744. macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP clken_ctrl_X58_Y5_N0
    745. 

  745. macro_inst|u_uart[0]|u_regs|uart_en clken_ctrl_X58_Y5_N0
    746. 

  746. macro_inst|u_uart[1]|u_regs|fbrd[0] clken_ctrl_X58_Y5_N1
    747. 

  747. macro_inst|u_uart[1]|u_rx[2]|break_error clken_ctrl_X58_Y5_N0
    748. 

  748. macro_inst|u_uart[1]|u_tx[2]|tx_complete clken_ctrl_X58_Y5_N0
    749. 

  749. macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY clken_ctrl_X58_Y5_N0
    750. 

  750. macro_inst|u_uart[1]|u_rx[2]|overrun_error clken_ctrl_X58_Y5_N0
    751. 

  751. macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY clken_ctrl_X58_Y6_N0
    752. 

  752. macro_inst|u_uart[1]|u_tx[0]|tx_complete clken_ctrl_X58_Y6_N0
    753. 

  753. macro_inst|u_uart[1]|u_rx[1]|rx_idle clken_ctrl_X58_Y6_N0
    754. 

  754. macro_inst|u_uart[1]|u_rx[0]|rx_idle clken_ctrl_X58_Y6_N0
    755. 

  755. macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP clken_ctrl_X58_Y6_N0
    756. 

  756. macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] clken_ctrl_X58_Y6_N1
    757. 

  757. macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] clken_ctrl_X58_Y7_N0
    758. 

  758. macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] clken_ctrl_X58_Y7_N0
    759. 

  759. macro_inst|u_uart[1]|u_rx[0]|overrun_error clken_ctrl_X58_Y7_N1
    760. 

  760. macro_inst|u_uart[1]|u_rx[2]|parity_error clken_ctrl_X58_Y7_N1
    761. 

  761. macro_inst|u_uart[1]|u_regs|framing_error_ie[2] clken_ctrl_X58_Y7_N0
    762. 

  762. macro_inst|u_uart[1]|u_regs|break_error_ie[2] clken_ctrl_X58_Y7_N0
    763. 

  763. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] clken_ctrl_X58_Y7_N0
    764. 

  764. macro_inst|u_uart[1]|u_regs|interrupts[0] clken_ctrl_X58_Y7_N1
    765. 

  765. macro_inst|u_uart[1]|u_regs|parity_error_ie[2] clken_ctrl_X58_Y7_N0
    766. 

  766. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] clken_ctrl_X58_Y7_N0
    767. 

  767. macro_inst|u_uart[1]|u_regs|interrupts[2] clken_ctrl_X58_Y7_N1
    768. 

  768. macro_inst|u_uart[1]|u_rx[3]|overrun_error clken_ctrl_X58_Y7_N1
    769. 

  769. macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE clken_ctrl_X58_Y8_N0
    770. 

  770. macro_inst|u_uart[1]|u_rx[3]|rx_idle_en clken_ctrl_X58_Y8_N0
    771. 

  771. macro_inst|u_uart[1]|u_rx[4]|framing_error clken_ctrl_X58_Y8_N0
    772. 

  772. macro_inst|u_uart[1]|u_rx[4]|break_error clken_ctrl_X58_Y8_N0
    773. 

  773. macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] clken_ctrl_X58_Y8_N0
    774. 

  774. macro_inst|u_uart[1]|u_rx[4]|parity_error clken_ctrl_X58_Y8_N0
    775. 

  775. macro_inst|u_uart[1]|u_rx[4]|rx_idle_en clken_ctrl_X58_Y8_N0
    776. 

  776. macro_inst|u_uart[1]|u_rx[4]|rx_parity clken_ctrl_X58_Y8_N0
    777. 

  777. macro_inst|u_uart[1]|u_rx[0]|rx_bit clken_ctrl_X58_Y8_N0
    778. 

  778. macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] clken_ctrl_X58_Y8_N0
    779. 

  779. macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] clken_ctrl_X58_Y8_N0
    780. 

  780. macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] clken_ctrl_X58_Y8_N0
    781. 

  781. macro_inst|u_uart[1]|u_regs|tx_write[4] clken_ctrl_X58_Y9_N0
    782. 

  782. macro_inst|u_uart[1]|u_rx[1]|overrun_error clken_ctrl_X58_Y9_N0
    783. 

  783. macro_inst|u_uart[1]|u_rx[2]|rx_in[1] clken_ctrl_X58_Y9_N1
    784. 

  784. macro_inst|u_uart[1]|u_regs|tx_write[1] clken_ctrl_X58_Y9_N0
    785. 

  785. macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] clken_ctrl_X58_Y9_N0
    786. 

  786. macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE clken_ctrl_X58_Y9_N0
    787. 

  787. macro_inst|u_uart[1]|u_regs|rx_read[1] clken_ctrl_X58_Y9_N0
    788. 

  788. macro_inst|u_uart[1]|u_tx[1]|tx_complete clken_ctrl_X58_Y9_N0
    789. 

  789. macro_inst|u_uart[1]|u_regs|rx_read[4] clken_ctrl_X58_Y9_N0
    790. 

  790. macro_inst|u_uart[1]|u_rx[1]|rx_idle_en clken_ctrl_X58_Y9_N0
    791. 

  791. macro_inst|u_uart[1]|u_rx[1]|framing_error clken_ctrl_X58_Y9_N0
    792. 

  792. macro_inst|u_uart[1]|u_regs|rx_read[5] clken_ctrl_X58_Y9_N0
    793. 

  793. macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] clken_ctrl_X58_Y9_N0
    794. 

  794. macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP clken_ctrl_X59_Y10_N0
    795. 

  795. macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] clken_ctrl_X59_Y10_N1
    796. 

  796. macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] clken_ctrl_X59_Y10_N1
    797. 

  797. macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] clken_ctrl_X59_Y10_N1
    798. 

  798. macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY clken_ctrl_X59_Y10_N0
    799. 

  799. macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] clken_ctrl_X59_Y10_N0
    800. 

  800. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] clken_ctrl_X59_Y11_N0
    801. 

  801. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] clken_ctrl_X59_Y11_N0
    802. 

  802. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] clken_ctrl_X59_Y11_N0
    803. 

  803. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] clken_ctrl_X59_Y11_N0
    804. 

  804. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] clken_ctrl_X59_Y11_N1
    805. 

  805. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] clken_ctrl_X59_Y11_N1
    806. 

  806. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] clken_ctrl_X59_Y11_N0
    807. 

  807. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] clken_ctrl_X59_Y11_N0
    808. 

  808. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] clken_ctrl_X59_Y11_N1
    809. 

  809. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] clken_ctrl_X59_Y11_N1
    810. 

  810. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] clken_ctrl_X59_Y11_N1
    811. 

  811. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] clken_ctrl_X59_Y11_N0
    812. 

  812. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] clken_ctrl_X59_Y11_N1
    813. 

  813. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] clken_ctrl_X59_Y11_N1
    814. 

  814. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] clken_ctrl_X59_Y11_N1
    815. 

  815. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] clken_ctrl_X59_Y11_N0
    816. 

  816. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] clken_ctrl_X59_Y12_N0
    817. 

  817. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] clken_ctrl_X59_Y12_N0
    818. 

  818. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] clken_ctrl_X59_Y12_N0
    819. 

  819. macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP clken_ctrl_X59_Y12_N1
    820. 

  820. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] clken_ctrl_X59_Y12_N0
    821. 

  821. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] clken_ctrl_X59_Y12_N0
    822. 

  822. macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY clken_ctrl_X59_Y12_N1
    823. 

  823. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] clken_ctrl_X59_Y12_N0
    824. 

  824. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] clken_ctrl_X59_Y12_N0
    825. 

  825. macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] clken_ctrl_X59_Y12_N0
    826. 

  826. macro_inst|u_uart[0]|u_regs|lcr_sps clken_ctrl_X59_Y1_N0
    827. 

  827. macro_inst|u_uart[0]|u_tx[2]|tx_parity clken_ctrl_X59_Y1_N1
    828. 

  828. macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY clken_ctrl_X59_Y1_N1
    829. 

  829. macro_inst|u_uart[0]|u_regs|lcr_pen clken_ctrl_X59_Y1_N0
    830. 

  830. macro_inst|u_uart[0]|u_tx[4]|uart_txd clken_ctrl_X59_Y1_N1
    831. 

  831. macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt clken_ctrl_X59_Y1_N1
    832. 

  832. macro_inst|u_uart[0]|u_regs|lcr_eps clken_ctrl_X59_Y1_N0
    833. 

  833. macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP clken_ctrl_X59_Y1_N1
    834. 

  834. macro_inst|u_uart[0]|u_tx[4]|tx_parity clken_ctrl_X59_Y1_N1
    835. 

  835. macro_inst|u_uart[0]|u_regs|lcr_stp2 clken_ctrl_X59_Y1_N0
    836. 

  836. macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE clken_ctrl_X59_Y1_N1
    837. 

  837. macro_inst|u_ahb2apb|paddr[8] clken_ctrl_X59_Y2_N0
    838. 

  838. macro_inst|u_ahb2apb|haddr[9] clken_ctrl_X59_Y2_N1
    839. 

  839. macro_inst|u_ahb2apb|paddr[9] clken_ctrl_X59_Y2_N0
    840. 

  840. macro_inst|u_ahb2apb|paddr[4] clken_ctrl_X59_Y2_N0
    841. 

  841. macro_inst|u_ahb2apb|paddr[5] clken_ctrl_X59_Y2_N0
    842. 

  842. macro_inst|u_ahb2apb|haddr[2] clken_ctrl_X59_Y2_N1
    843. 

  843. macro_inst|u_ahb2apb|haddr[3] clken_ctrl_X59_Y2_N1
    844. 

  844. macro_inst|u_ahb2apb|haddr[6] clken_ctrl_X59_Y2_N1
    845. 

  845. macro_inst|u_ahb2apb|haddr[8] clken_ctrl_X59_Y2_N1
    846. 

  846. macro_inst|u_ahb2apb|paddr[3] clken_ctrl_X59_Y2_N0
    847. 

  847. macro_inst|u_ahb2apb|haddr[10] clken_ctrl_X59_Y2_N1
    848. 

  848. macro_inst|u_ahb2apb|haddr[5] clken_ctrl_X59_Y2_N1
    849. 

  849. macro_inst|u_ahb2apb|paddr[10] clken_ctrl_X59_Y2_N0
    850. 

  850. macro_inst|u_ahb2apb|haddr[4] clken_ctrl_X59_Y2_N1
    851. 

  851. macro_inst|u_uart[0]|u_regs|ibrd[6] clken_ctrl_X59_Y3_N0
    852. 

  852. macro_inst|u_uart[0]|u_regs|ibrd[15] clken_ctrl_X59_Y3_N0
    853. 

  853. macro_inst|u_ahb2apb|paddr[7] clken_ctrl_X59_Y3_N1
    854. 

  854. macro_inst|u_ahb2apb|pwrite clken_ctrl_X59_Y3_N1
    855. 

  855. macro_inst|u_ahb2apb|paddr[6] clken_ctrl_X59_Y3_N1
    856. 

  856. macro_inst|u_ahb2apb|paddr[12] clken_ctrl_X59_Y3_N1
    857. 

  857. macro_inst|u_uart[0]|u_regs|ibrd[8] clken_ctrl_X59_Y3_N0
    858. 

  858. macro_inst|u_ahb2apb|paddr[2] clken_ctrl_X59_Y3_N1
    859. 

  859. macro_inst|u_uart[0]|u_regs|ibrd[11] clken_ctrl_X59_Y3_N0
    860. 

  860. macro_inst|u_uart[1]|u_regs|ibrd[14] clken_ctrl_X59_Y4_N0
    861. 

  861. macro_inst|u_uart[0]|u_regs|ibrd[14] clken_ctrl_X59_Y4_N1
    862. 

  862. macro_inst|u_uart[1]|u_regs|ibrd[3] clken_ctrl_X59_Y4_N0
    863. 

  863. macro_inst|u_uart[0]|u_regs|ibrd[13] clken_ctrl_X59_Y5_N0
    864. 

  864. macro_inst|u_uart[1]|u_regs|ibrd[7] clken_ctrl_X59_Y5_N1
    865. 

  865. macro_inst|u_uart[1]|u_regs|ibrd[0] clken_ctrl_X59_Y5_N1
    866. 

  866. macro_inst|u_uart[0]|u_regs|ibrd[0] clken_ctrl_X59_Y5_N0
    867. 

  867. macro_inst|u_uart[1]|u_regs|ibrd[2] clken_ctrl_X59_Y5_N1
    868. 

  868. macro_inst|u_uart[1]|u_regs|ibrd[13] clken_ctrl_X59_Y5_N1
    869. 

  869. macro_inst|u_uart[1]|u_rx[0]|framing_error clken_ctrl_X59_Y6_N0
    870. 

  870. macro_inst|u_uart[1]|u_rx[3]|framing_error clken_ctrl_X59_Y6_N0
    871. 

  871. macro_inst|u_uart[1]|u_rx[0]|break_error clken_ctrl_X59_Y6_N0
    872. 

  872. macro_inst|u_uart[1]|u_rx[3]|rx_idle clken_ctrl_X59_Y6_N0
    873. 

  873. macro_inst|u_uart[1]|u_regs|rx_reg[2] clken_ctrl_X59_Y6_N0
    874. 

  874. macro_inst|u_uart[1]|u_rx[1]|break_error clken_ctrl_X59_Y6_N0
    875. 

  875. macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] clken_ctrl_X59_Y6_N1
    876. 

  876. macro_inst|u_uart[1]|u_rx[2]|framing_error clken_ctrl_X59_Y6_N0
    877. 

  877. macro_inst|u_uart[1]|u_rx[3]|break_error clken_ctrl_X59_Y6_N0
    878. 

  878. macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] clken_ctrl_X59_Y7_N0
    879. 

  879. macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] clken_ctrl_X59_Y7_N1
    880. 

  880. macro_inst|u_uart[1]|u_regs|framing_error_ie[0] clken_ctrl_X59_Y7_N0
    881. 

  881. macro_inst|u_uart[1]|u_regs|break_error_ie[0] clken_ctrl_X59_Y7_N0
    882. 

  882. macro_inst|u_uart[1]|u_regs|framing_error_ie[1] clken_ctrl_X59_Y7_N1
    883. 

  883. macro_inst|u_uart[1]|u_regs|parity_error_ie[0] clken_ctrl_X59_Y7_N0
    884. 

  884. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] clken_ctrl_X59_Y7_N0
    885. 

  885. macro_inst|u_uart[1]|u_regs|parity_error_ie[1] clken_ctrl_X59_Y7_N1
    886. 

  886. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] clken_ctrl_X59_Y7_N0
    887. 

  887. macro_inst|u_uart[1]|u_regs|break_error_ie[1] clken_ctrl_X59_Y7_N1
    888. 

  888. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] clken_ctrl_X59_Y7_N1
    889. 

  889. macro_inst|u_uart[1]|u_regs|rx_dma_en[1] clken_ctrl_X59_Y8_N0
    890. 

  890. macro_inst|u_uart[1]|u_regs|tx_dma_en[1] clken_ctrl_X59_Y8_N0
    891. 

  891. macro_inst|u_uart[1]|u_regs|rx_dma_en[0] clken_ctrl_X59_Y8_N1
    892. 

  892. macro_inst|u_uart[1]|u_regs|tx_dma_en[0] clken_ctrl_X59_Y8_N1
    893. 

  893. macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] clken_ctrl_X59_Y9_N0
    894. 

  894. macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] clken_ctrl_X59_Y9_N1
    895. 

  895. macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] clken_ctrl_X59_Y9_N0
    896. 

  896. macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] clken_ctrl_X59_Y9_N1
    897. 

  897. macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] clken_ctrl_X59_Y9_N0
    898. 

  898. macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] clken_ctrl_X60_Y10_N1
    899. 

  899. macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] clken_ctrl_X60_Y10_N1
    900. 

  900. macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] clken_ctrl_X60_Y10_N1
    901. 

  901. macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] clken_ctrl_X60_Y10_N1
    902. 

  902. macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA clken_ctrl_X60_Y10_N1
    903. 

  903. macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE clken_ctrl_X60_Y10_N1
    904. 

  904. macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] clken_ctrl_X60_Y10_N0
    905. 

  905. macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START clken_ctrl_X60_Y10_N1
    906. 

  906. macro_inst|u_uart[1]|u_rx[3]|rx_bit clken_ctrl_X60_Y10_N1
    907. 

  907. macro_inst|u_uart[1]|u_rx[0]|rx_in[1] clken_ctrl_X60_Y11_N0
    908. 

  908. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] clken_ctrl_X60_Y11_N1
    909. 

  909. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] clken_ctrl_X60_Y11_N1
    910. 

  910. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] clken_ctrl_X60_Y11_N1
    911. 

  911. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] clken_ctrl_X60_Y11_N1
    912. 

  912. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] clken_ctrl_X60_Y11_N1
    913. 

  913. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] clken_ctrl_X60_Y11_N1
    914. 

  914. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] clken_ctrl_X60_Y11_N1
    915. 

  915. macro_inst|u_uart[1]|u_rx[5]|rx_in[2] clken_ctrl_X60_Y11_N0
    916. 

  916. macro_inst|u_uart[1]|u_rx[5]|rx_in[3] clken_ctrl_X60_Y11_N0
    917. 

  917. macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] clken_ctrl_X60_Y11_N1
    918. 

  918. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] clken_ctrl_X60_Y12_N0
    919. 

  919. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] clken_ctrl_X60_Y12_N1
    920. 

  920. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] clken_ctrl_X60_Y12_N1
    921. 

  921. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] clken_ctrl_X60_Y12_N0
    922. 

  922. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] clken_ctrl_X60_Y12_N1
    923. 

  923. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] clken_ctrl_X60_Y12_N0
    924. 

  924. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] clken_ctrl_X60_Y12_N0
    925. 

  925. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] clken_ctrl_X60_Y12_N1
    926. 

  926. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] clken_ctrl_X60_Y12_N1
    927. 

  927. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] clken_ctrl_X60_Y12_N0
    928. 

  928. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] clken_ctrl_X60_Y12_N1
    929. 

  929. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] clken_ctrl_X60_Y12_N1
    930. 

  930. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] clken_ctrl_X60_Y12_N0
    931. 

  931. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] clken_ctrl_X60_Y12_N0
    932. 

  932. macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] clken_ctrl_X60_Y12_N0
    933. 

  933. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] clken_ctrl_X60_Y12_N1
    934. 

  934. macro_inst|u_uart[0]|u_regs|fbrd[2] clken_ctrl_X60_Y1_N0
    935. 

  935. macro_inst|u_uart[0]|u_regs|fbrd[4] clken_ctrl_X60_Y1_N0
    936. 

  936. macro_inst|u_uart[0]|u_regs|tx_write[2] clken_ctrl_X60_Y1_N1
    937. 

  937. macro_inst|u_uart[0]|u_regs|fbrd[3] clken_ctrl_X60_Y1_N0
    938. 

  938. macro_inst|u_uart[0]|u_baud|f_del clken_ctrl_X60_Y1_N1
    939. 

  939. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] clken_ctrl_X60_Y1_N1
    940. 

  940. macro_inst|u_uart[0]|u_regs|fbrd[5] clken_ctrl_X60_Y1_N0
    941. 

  941. macro_inst|u_uart[0]|u_regs|fbrd[1] clken_ctrl_X60_Y1_N0
    942. 

  942. macro_inst|u_uart[0]|u_tx[2]|uart_txd clken_ctrl_X60_Y1_N1
    943. 

  943. macro_inst|u_uart[0]|u_regs|apb_prdata[9] clken_ctrl_X60_Y2_N0
    944. 

  944. macro_inst|u_uart[0]|u_regs|framing_error_ie[5] clken_ctrl_X60_Y2_N1
    945. 

  945. macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] clken_ctrl_X60_Y2_N1
    946. 

  946. macro_inst|u_uart[0]|u_regs|apb_prdata[12] clken_ctrl_X60_Y2_N0
    947. 

  947. macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] clken_ctrl_X60_Y2_N1
    948. 

  948. macro_inst|u_uart[0]|u_regs|break_error_ie[5] clken_ctrl_X60_Y2_N1
    949. 

  949. macro_inst|u_uart[0]|u_regs|apb_prdata[11] clken_ctrl_X60_Y2_N0
    950. 

  950. macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] clken_ctrl_X60_Y2_N1
    951. 

  951. macro_inst|u_uart[0]|u_regs|apb_prdata[10] clken_ctrl_X60_Y2_N0
    952. 

  952. macro_inst|u_uart[0]|u_regs|parity_error_ie[5] clken_ctrl_X60_Y2_N1
    953. 

  953. macro_inst|u_uart[0]|u_regs|apb_prdata[8] clken_ctrl_X60_Y2_N0
    954. 

  954. macro_inst|u_ahb2apb|prdata[1] clken_ctrl_X60_Y3_N0
    955. 

  955. macro_inst|u_uart[0]|u_regs|apb_prdata[6] clken_ctrl_X60_Y3_N1
    956. 

  956. macro_inst|u_ahb2apb|prdata[13] clken_ctrl_X60_Y3_N0
    957. 

  957. macro_inst|u_ahb2apb|prdata[0] clken_ctrl_X60_Y3_N0
    958. 

  958. macro_inst|u_ahb2apb|prdata[5] clken_ctrl_X60_Y3_N0
    959. 

  959. macro_inst|u_ahb2apb|prdata[7] clken_ctrl_X60_Y3_N0
    960. 

  960. macro_inst|u_ahb2apb|prdata[15] clken_ctrl_X60_Y3_N0
    961. 

  961. macro_inst|u_ahb2apb|prdata[2] clken_ctrl_X60_Y3_N0
    962. 

  962. macro_inst|u_uart[0]|u_regs|apb_prdata[13] clken_ctrl_X60_Y3_N1
    963. 

  963. macro_inst|u_ahb2apb|prdata[6] clken_ctrl_X60_Y3_N0
    964. 

  964. macro_inst|u_ahb2apb|prdata[14] clken_ctrl_X60_Y3_N0
    965. 

  965. macro_inst|u_uart[0]|u_regs|apb_prdata[15] clken_ctrl_X60_Y3_N1
    966. 

  966. macro_inst|u_uart[0]|u_regs|apb_prdata[14] clken_ctrl_X60_Y3_N1
    967. 

  967. macro_inst|u_uart[1]|u_regs|rx_dma_en[5] clken_ctrl_X60_Y4_N0
    968. 

  968. macro_inst|u_uart[1]|u_regs|apb_prdata[15] clken_ctrl_X60_Y4_N1
    969. 

  969. macro_inst|u_uart[1]|u_regs|apb_prdata[3] clken_ctrl_X60_Y4_N1
    970. 

  970. macro_inst|u_uart[1]|u_regs|apb_prdata[14] clken_ctrl_X60_Y4_N1
    971. 

  971. macro_inst|u_uart[1]|u_regs|apb_prdata[1] clken_ctrl_X60_Y4_N1
    972. 

  972. macro_inst|u_uart[1]|u_regs|apb_prdata[5] clken_ctrl_X60_Y4_N1
    973. 

  973. macro_inst|u_uart[1]|u_regs|tx_dma_en[5] clken_ctrl_X60_Y4_N0
    974. 

  974. macro_inst|u_uart[1]|u_regs|apb_prdata[7] clken_ctrl_X60_Y5_N0
    975. 

  975. macro_inst|u_uart[1]|u_regs|apb_prdata[6] clken_ctrl_X60_Y5_N0
    976. 

  976. macro_inst|u_uart[0]|u_regs|apb_prdata[7] clken_ctrl_X60_Y5_N1
    977. 

  977. macro_inst|u_uart[1]|u_regs|apb_prdata[2] clken_ctrl_X60_Y5_N0
    978. 

  978. macro_inst|u_uart[1]|u_regs|apb_prdata[4] clken_ctrl_X60_Y5_N0
    979. 

  979. macro_inst|u_uart[1]|u_regs|apb_prdata[13] clken_ctrl_X60_Y5_N0
    980. 

  980. macro_inst|u_uart[0]|u_regs|apb_prdata[2] clken_ctrl_X60_Y5_N1
    981. 

  981. macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] clken_ctrl_X60_Y6_N0
    982. 

  982. macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] clken_ctrl_X60_Y6_N1
    983. 

  983. macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] clken_ctrl_X60_Y6_N0
    984. 

  984. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] clken_ctrl_X60_Y6_N0
    985. 

  985. macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] clken_ctrl_X60_Y6_N1
    986. 

  986. macro_inst|u_uart[1]|u_regs|break_error_ie[3] clken_ctrl_X60_Y7_N0
    987. 

  987. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] clken_ctrl_X60_Y7_N0
    988. 

  988. macro_inst|u_uart[1]|u_regs|framing_error_ie[3] clken_ctrl_X60_Y7_N0
    989. 

  989. macro_inst|u_uart[1]|u_regs|interrupts[3] clken_ctrl_X60_Y7_N1
    990. 

  990. macro_inst|u_uart[1]|u_rx[3]|parity_error clken_ctrl_X60_Y7_N1
    991. 

  991. macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE clken_ctrl_X60_Y7_N1
    992. 

  992. macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] clken_ctrl_X60_Y7_N0
    993. 

  993. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] clken_ctrl_X60_Y7_N0
    994. 

  994. macro_inst|u_uart[1]|u_tx[3]|tx_complete clken_ctrl_X60_Y7_N1
    995. 

  995. macro_inst|u_uart[1]|u_tx[5]|tx_complete clken_ctrl_X60_Y7_N1
    996. 

  996. macro_inst|u_uart[1]|u_regs|parity_error_ie[3] clken_ctrl_X60_Y7_N0
    997. 

  997. macro_inst|u_uart[1]|u_rx[5]|rx_idle clken_ctrl_X60_Y7_N1
    998. 

  998. macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] clken_ctrl_X60_Y7_N1
    999. 

  999. macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] clken_ctrl_X60_Y7_N0
    1000. 

  1000. macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] clken_ctrl_X60_Y8_N0
    1001. 

  1001. macro_inst|u_uart[1]|u_rx[4]|overrun_error clken_ctrl_X60_Y8_N1
    1002. 

  1002. macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] clken_ctrl_X60_Y8_N0
    1003. 

  1003. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] clken_ctrl_X60_Y8_N0
    1004. 

  1004. macro_inst|u_uart[1]|u_regs|break_error_ie[4] clken_ctrl_X60_Y8_N0
    1005. 

  1005. macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] clken_ctrl_X60_Y8_N0
    1006. 

  1006. macro_inst|u_uart[1]|u_regs|uart_en clken_ctrl_X60_Y8_N1
    1007. 

  1007. macro_inst|u_uart[1]|u_rx[4]|rx_idle clken_ctrl_X60_Y8_N1
    1008. 

  1008. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] clken_ctrl_X60_Y8_N0
    1009. 

  1009. macro_inst|u_uart[1]|u_rx[5]|overrun_error clken_ctrl_X60_Y8_N1
    1010. 

  1010. macro_inst|u_uart[1]|u_regs|framing_error_ie[4] clken_ctrl_X60_Y8_N0
    1011. 

  1011. macro_inst|u_uart[1]|u_tx[4]|tx_complete clken_ctrl_X60_Y8_N1
    1012. 

  1012. macro_inst|u_uart[1]|u_regs|interrupts[4] clken_ctrl_X60_Y8_N1
    1013. 

  1013. macro_inst|u_uart[1]|u_regs|parity_error_ie[4] clken_ctrl_X60_Y8_N0
    1014. 

  1014. macro_inst|u_uart[1]|u_rx[3]|rx_in[3] clken_ctrl_X60_Y9_N0
    1015. 

  1015. macro_inst|u_uart[1]|u_tx[3]|uart_txd clken_ctrl_X60_Y9_N1
    1016. 

  1016. macro_inst|u_uart[1]|u_tx[5]|tx_parity clken_ctrl_X60_Y9_N1
    1017. 

  1017. macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] clken_ctrl_X60_Y9_N1
    1018. 

  1018. macro_inst|u_uart[1]|u_rx[5]|break_error clken_ctrl_X60_Y9_N1
    1019. 

  1019. macro_inst|u_uart[1]|u_rx[5]|rx_in[4] clken_ctrl_X60_Y9_N0
    1020. 

  1020. macro_inst|u_uart[1]|u_rx[5]|framing_error clken_ctrl_X60_Y9_N1
    1021. 

  1021. macro_inst|u_uart[1]|u_rx[3]|rx_parity clken_ctrl_X60_Y9_N1
    1022. 

  1022. macro_inst|u_uart[1]|u_rx[3]|rx_in[2] clken_ctrl_X60_Y9_N0
    1023. 

  1023. macro_inst|u_uart[1]|u_rx[3]|rx_in[4] clken_ctrl_X60_Y9_N0
    1024. 

  1024. macro_inst|u_uart[1]|u_rx[2]|rx_in[4] clken_ctrl_X60_Y9_N0
    1025. 

  1025. macro_inst|u_uart[1]|u_tx[3]|tx_parity clken_ctrl_X60_Y9_N1
    1026. 

  1026. macro_inst|u_uart[1]|u_rx[2]|rx_in[3] clken_ctrl_X60_Y9_N0
    1027. 

  1027. macro_inst|u_uart[1]|u_rx[2]|rx_in[2] clken_ctrl_X60_Y9_N0
    1028. 

  1028. macro_inst|u_uart[1]|u_rx[5]|rx_parity clken_ctrl_X61_Y10_N0
    1029. 

  1029. macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt clken_ctrl_X61_Y10_N0
    1030. 

  1030. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] clken_ctrl_X61_Y10_N0
    1031. 

  1031. macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START clken_ctrl_X61_Y10_N0
    1032. 

  1032. macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] clken_ctrl_X61_Y10_N0
    1033. 

  1033. macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE clken_ctrl_X61_Y10_N0
    1034. 

  1034. macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] clken_ctrl_X61_Y10_N0
    1035. 

  1035. macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] clken_ctrl_X61_Y10_N0
    1036. 

  1036. macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] clken_ctrl_X61_Y10_N0
    1037. 

  1037. macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START clken_ctrl_X61_Y11_N0
    1038. 

  1038. macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY clken_ctrl_X61_Y11_N0
    1039. 

  1039. macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA clken_ctrl_X61_Y11_N0
    1040. 

  1040. macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP clken_ctrl_X61_Y11_N0
    1041. 

  1041. macro_inst|u_uart[1]|u_rx[5]|rx_bit clken_ctrl_X61_Y11_N0
    1042. 

  1042. macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE clken_ctrl_X61_Y11_N0
    1043. 

  1043. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] clken_ctrl_X61_Y12_N0
    1044. 

  1044. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] clken_ctrl_X61_Y12_N1
    1045. 

  1045. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] clken_ctrl_X61_Y12_N0
    1046. 

  1046. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] clken_ctrl_X61_Y12_N1
    1047. 

  1047. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] clken_ctrl_X61_Y12_N1
    1048. 

  1048. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] clken_ctrl_X61_Y12_N0
    1049. 

  1049. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] clken_ctrl_X61_Y12_N0
    1050. 

  1050. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] clken_ctrl_X61_Y12_N0
    1051. 

  1051. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] clken_ctrl_X61_Y12_N1
    1052. 

  1052. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] clken_ctrl_X61_Y12_N0
    1053. 

  1053. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] clken_ctrl_X61_Y12_N1
    1054. 

  1054. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] clken_ctrl_X61_Y12_N0
    1055. 

  1055. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] clken_ctrl_X61_Y12_N1
    1056. 

  1056. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] clken_ctrl_X61_Y12_N0
    1057. 

  1057. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] clken_ctrl_X61_Y12_N1
    1058. 

  1058. macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] clken_ctrl_X61_Y12_N1
    1059. 

  1059. macro_inst|u_uart[0]|u_baud|f_cnt[0] clken_ctrl_X61_Y1_N0
    1060. 

  1060. macro_inst|u_uart[0]|u_baud|f_cnt[5] clken_ctrl_X61_Y1_N0
    1061. 

  1061. macro_inst|u_uart[0]|u_tx[2]|tx_bit clken_ctrl_X61_Y1_N0
    1062. 

  1062. macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt clken_ctrl_X61_Y1_N0
    1063. 

  1063. macro_inst|u_uart[0]|u_regs|tx_write[1] clken_ctrl_X61_Y1_N0
    1064. 

  1064. macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE clken_ctrl_X61_Y1_N0
    1065. 

  1065. macro_inst|u_uart[0]|u_baud|f_cnt[1] clken_ctrl_X61_Y1_N0
    1066. 

  1066. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] clken_ctrl_X61_Y1_N0
    1067. 

  1067. macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START clken_ctrl_X61_Y1_N0
    1068. 

  1068. macro_inst|u_uart[0]|u_tx[1]|tx_dma_req clken_ctrl_X61_Y1_N0
    1069. 

  1069. macro_inst|u_uart[0]|u_baud|f_cnt[2] clken_ctrl_X61_Y1_N0
    1070. 

  1070. macro_inst|u_uart[0]|u_baud|f_cnt[3] clken_ctrl_X61_Y1_N0
    1071. 

  1071. macro_inst|u_uart[0]|u_baud|f_cnt[4] clken_ctrl_X61_Y1_N0
    1072. 

  1072. macro_inst|u_uart[0]|u_regs|apb_prdata[3] clken_ctrl_X61_Y2_N0
    1073. 

  1073. macro_inst|u_uart[0]|u_regs|ibrd[5] clken_ctrl_X61_Y2_N1
    1074. 

  1074. macro_inst|u_uart[0]|u_regs|apb_prdata[4] clken_ctrl_X61_Y2_N0
    1075. 

  1075. macro_inst|u_uart[0]|u_regs|ibrd[4] clken_ctrl_X61_Y2_N1
    1076. 

  1076. macro_inst|u_uart[0]|u_regs|ibrd[9] clken_ctrl_X61_Y2_N1
    1077. 

  1077. macro_inst|u_uart[0]|u_regs|ibrd[7] clken_ctrl_X61_Y2_N1
    1078. 

  1078. macro_inst|u_uart[0]|u_regs|ibrd[12] clken_ctrl_X61_Y2_N1
    1079. 

  1079. macro_inst|u_ahb2apb|prdata[12] clken_ctrl_X61_Y3_N0
    1080. 

  1080. macro_inst|u_ahb2apb|prdata[9] clken_ctrl_X61_Y3_N0
    1081. 

  1081. macro_inst|u_ahb2apb|prdata[8] clken_ctrl_X61_Y3_N0
    1082. 

  1082. macro_inst|u_apb_mux|pr_select[1] clken_ctrl_X61_Y3_N1
    1083. 

  1083. macro_inst|u_ahb2apb|prdata[11] clken_ctrl_X61_Y3_N0
    1084. 

  1084. macro_inst|u_ahb2apb|prdata[10] clken_ctrl_X61_Y3_N0
    1085. 

  1085. macro_inst|u_ahb2apb|prdata[3] clken_ctrl_X61_Y3_N0
    1086. 

  1086. macro_inst|u_ahb2apb|prdata[4] clken_ctrl_X61_Y3_N0
    1087. 

  1087. macro_inst|u_apb_mux|pr_select[0] clken_ctrl_X61_Y3_N1
    1088. 

  1088. macro_inst|u_uart[1]|u_baud|f_del clken_ctrl_X61_Y4_N0
    1089. 

  1089. macro_inst|u_uart[0]|u_tx[3]|uart_txd clken_ctrl_X61_Y4_N0
    1090. 

  1090. macro_inst|u_uart[1]|u_regs|fbrd[5] clken_ctrl_X61_Y4_N1
    1091. 

  1091. macro_inst|u_uart[1]|u_regs|status_reg[1] clken_ctrl_X61_Y4_N0
    1092. 

  1092. macro_inst|u_uart[1]|u_regs|fbrd[1] clken_ctrl_X61_Y4_N1
    1093. 

  1093. macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] clken_ctrl_X61_Y4_N0
    1094. 

  1094. macro_inst|u_uart[0]|u_regs|tx_write[3] clken_ctrl_X61_Y4_N0
    1095. 

  1095. macro_inst|u_uart[0]|u_tx[3]|tx_parity clken_ctrl_X61_Y4_N0
    1096. 

  1096. macro_inst|u_uart[1]|u_regs|fbrd[2] clken_ctrl_X61_Y4_N1
    1097. 

  1097. macro_inst|u_uart[1]|u_regs|fbrd[3] clken_ctrl_X61_Y4_N1
    1098. 

  1098. macro_inst|u_uart[1]|u_regs|fbrd[4] clken_ctrl_X61_Y4_N1
    1099. 

  1099. macro_inst|u_uart[1]|u_regs|ibrd[11] clken_ctrl_X61_Y5_N0
    1100. 

  1100. macro_inst|u_uart[1]|u_regs|ibrd[8] clken_ctrl_X61_Y5_N0
    1101. 

  1101. macro_inst|u_uart[1]|u_regs|ibrd[10] clken_ctrl_X61_Y5_N0
    1102. 

  1102. macro_inst|u_uart[0]|u_regs|fbrd[0] clken_ctrl_X61_Y5_N1
    1103. 

  1103. macro_inst|u_uart[1]|u_regs|ibrd[6] clken_ctrl_X61_Y5_N0
    1104. 

  1104. macro_inst|u_uart[1]|u_regs|ibrd[4] clken_ctrl_X61_Y5_N0
    1105. 

  1105. macro_inst|u_uart[1]|u_regs|ibrd[12] clken_ctrl_X61_Y5_N0
    1106. 

  1106. macro_inst|u_uart[1]|u_regs|ibrd[9] clken_ctrl_X61_Y5_N0
    1107. 

  1107. macro_inst|u_uart[1]|u_regs|ibrd[15] clken_ctrl_X61_Y5_N0
    1108. 

  1108. macro_inst|u_uart[1]|u_regs|ibrd[5] clken_ctrl_X61_Y5_N0
    1109. 

  1109. macro_inst|u_uart[1]|u_regs|break_error_ie[5] clken_ctrl_X61_Y6_N0
    1110. 

  1110. macro_inst|u_uart[1]|u_regs|apb_prdata[10] clken_ctrl_X61_Y6_N1
    1111. 

  1111. macro_inst|u_uart[1]|u_regs|parity_error_ie[5] clken_ctrl_X61_Y6_N0
    1112. 

  1112. macro_inst|u_uart[1]|u_regs|apb_prdata[12] clken_ctrl_X61_Y6_N1
    1113. 

  1113. macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] clken_ctrl_X61_Y6_N0
    1114. 

  1114. macro_inst|u_uart[1]|u_regs|apb_prdata[8] clken_ctrl_X61_Y6_N1
    1115. 

  1115. macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] clken_ctrl_X61_Y6_N0
    1116. 

  1116. macro_inst|u_uart[1]|u_regs|apb_prdata[9] clken_ctrl_X61_Y6_N1
    1117. 

  1117. macro_inst|u_uart[1]|u_regs|apb_prdata[11] clken_ctrl_X61_Y6_N1
    1118. 

  1118. macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] clken_ctrl_X61_Y6_N0
    1119. 

  1119. macro_inst|u_uart[1]|u_regs|tx_write[3] clken_ctrl_X61_Y7_N0
    1120. 

  1120. macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START clken_ctrl_X61_Y7_N0
    1121. 

  1121. macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] clken_ctrl_X61_Y7_N1
    1122. 

  1122. macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY clken_ctrl_X61_Y7_N0
    1123. 

  1123. macro_inst|u_uart[1]|u_regs|framing_error_ie[5] clken_ctrl_X61_Y7_N1
    1124. 

  1124. macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] clken_ctrl_X61_Y7_N1
    1125. 

  1125. macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE clken_ctrl_X61_Y7_N0
    1126. 

  1126. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] clken_ctrl_X61_Y7_N0
    1127. 

  1127. macro_inst|u_uart[1]|u_regs|interrupts[5] clken_ctrl_X61_Y7_N0
    1128. 

  1128. macro_inst|u_uart[1]|u_regs|tx_write[5] clken_ctrl_X61_Y7_N0
    1129. 

  1129. macro_inst|u_uart[1]|u_baud|f_cnt[1] clken_ctrl_X61_Y8_N0
    1130. 

  1130. macro_inst|u_uart[1]|u_baud|f_cnt[2] clken_ctrl_X61_Y8_N0
    1131. 

  1131. macro_inst|u_uart[1]|u_baud|f_cnt[3] clken_ctrl_X61_Y8_N0
    1132. 

  1132. macro_inst|u_uart[1]|u_baud|f_cnt[4] clken_ctrl_X61_Y8_N0
    1133. 

  1133. macro_inst|u_uart[1]|u_baud|f_cnt[5] clken_ctrl_X61_Y8_N0
    1134. 

  1134. macro_inst|u_uart[1]|u_rx[5]|parity_error clken_ctrl_X61_Y8_N0
    1135. 

  1135. macro_inst|u_uart[1]|u_baud|baud16 clken_ctrl_X61_Y8_N0
    1136. 

  1136. macro_inst|u_uart[1]|u_rx[5]|rx_idle_en clken_ctrl_X61_Y8_N0
    1137. 

  1137. macro_inst|u_uart[1]|u_baud|f_cnt[0] clken_ctrl_X61_Y8_N0
    1138. 

  1138. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] clken_ctrl_X61_Y9_N0
    1139. 

  1139. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] clken_ctrl_X61_Y9_N1
    1140. 

  1140. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] clken_ctrl_X61_Y9_N0
    1141. 

  1141. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] clken_ctrl_X61_Y9_N1
    1142. 

  1142. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] clken_ctrl_X61_Y9_N1
    1143. 

  1143. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] clken_ctrl_X61_Y9_N0
    1144. 

  1144. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] clken_ctrl_X61_Y9_N0
    1145. 

  1145. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] clken_ctrl_X61_Y9_N0
    1146. 

  1146. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] clken_ctrl_X61_Y9_N0
    1147. 

  1147. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] clken_ctrl_X61_Y9_N0
    1148. 

  1148. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] clken_ctrl_X61_Y9_N1
    1149. 

  1149. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] clken_ctrl_X61_Y9_N1
    1150. 

  1150. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] clken_ctrl_X61_Y9_N1
    1151. 

  1151. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] clken_ctrl_X61_Y9_N1
    1152. 

  1152. macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] clken_ctrl_X61_Y9_N1
    1153. 

  1153. macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] clken_ctrl_X61_Y9_N0
    1154. 

  1154. macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] clken_ctrl_X62_Y10_N1
    1155. 

  1155. macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] clken_ctrl_X62_Y10_N1
    1156. 

  1156. macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] clken_ctrl_X62_Y10_N0
    1157. 

  1157. macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] clken_ctrl_X62_Y10_N0
    1158. 

  1158. macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] clken_ctrl_X62_Y10_N0
    1159. 

  1159. macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] clken_ctrl_X62_Y10_N0
    1160. 

  1160. macro_inst|u_uart[1]|u_tx[4]|tx_bit clken_ctrl_X62_Y10_N0
    1161. 

  1161. macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START clken_ctrl_X62_Y10_N0
    1162. 

  1162. macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] clken_ctrl_X62_Y10_N1
    1163. 

  1163. macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] clken_ctrl_X62_Y11_N0
    1164. 

  1164. macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] clken_ctrl_X62_Y11_N1
    1165. 

  1165. macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] clken_ctrl_X62_Y11_N0
    1166. 

  1166. macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] clken_ctrl_X62_Y11_N0
    1167. 

  1167. macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] clken_ctrl_X62_Y11_N1
    1168. 

  1168. macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] clken_ctrl_X62_Y11_N1
    1169. 

  1169. macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] clken_ctrl_X62_Y11_N1
    1170. 

  1170. macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] clken_ctrl_X62_Y11_N1
    1171. 

  1171. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y12_N0
    1172. 

  1172. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y12_N0
    1173. 

  1173. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y12_N0
    1174. 

  1174. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] clken_ctrl_X62_Y12_N1
    1175. 

  1175. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] clken_ctrl_X62_Y12_N1
    1176. 

  1176. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y12_N0
    1177. 

  1177. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y12_N0
    1178. 

  1178. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y12_N0
    1179. 

  1179. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] clken_ctrl_X62_Y12_N1
    1180. 

  1180. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y12_N0
    1181. 

  1181. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] clken_ctrl_X62_Y12_N1
    1182. 

  1182. macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y12_N0
    1183. 

  1183. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] clken_ctrl_X62_Y12_N1
    1184. 

  1184. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] clken_ctrl_X62_Y12_N1
    1185. 

  1185. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] clken_ctrl_X62_Y12_N1
    1186. 

  1186. macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] clken_ctrl_X62_Y12_N1
    1187. 

  1187. macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE clken_ctrl_X62_Y1_N0
    1188. 

  1188. macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] clken_ctrl_X62_Y1_N1
    1189. 

  1189. macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] clken_ctrl_X62_Y1_N0
    1190. 

  1190. macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] clken_ctrl_X62_Y1_N0
    1191. 

  1191. macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] clken_ctrl_X62_Y1_N0
    1192. 

  1192. macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] clken_ctrl_X62_Y1_N0
    1193. 

  1193. macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] clken_ctrl_X62_Y1_N1
    1194. 

  1194. macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START clken_ctrl_X62_Y1_N0
    1195. 

  1195. macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA clken_ctrl_X62_Y1_N0
    1196. 

  1196. macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] clken_ctrl_X62_Y1_N1
    1197. 

  1197. macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] clken_ctrl_X62_Y2_N0
    1198. 

  1198. macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] clken_ctrl_X62_Y2_N0
    1199. 

  1199. macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] clken_ctrl_X62_Y2_N0
    1200. 

  1200. macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] clken_ctrl_X62_Y2_N0
    1201. 

  1201. macro_inst|u_uart[0]|u_rx[4]|rx_in[0] clken_ctrl_X62_Y2_N1
    1202. 

  1202. macro_inst|u_uart[0]|u_tx[4]|tx_bit clken_ctrl_X62_Y2_N0
    1203. 

  1203. macro_inst|u_uart[0]|u_rx[4]|rx_in[1] clken_ctrl_X62_Y2_N1
    1204. 

  1204. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] clken_ctrl_X62_Y2_N0
    1205. 

  1205. macro_inst|u_uart[0]|u_regs|tx_write[4] clken_ctrl_X62_Y2_N0
    1206. 

  1206. macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE clken_ctrl_X62_Y2_N0
    1207. 

  1207. macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP clken_ctrl_X62_Y2_N0
    1208. 

  1208. macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY clken_ctrl_X62_Y3_N0
    1209. 

  1209. macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] clken_ctrl_X62_Y3_N1
    1210. 

  1210. macro_inst|u_uart[0]|u_tx[3]|tx_bit clken_ctrl_X62_Y3_N0
    1211. 

  1211. macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA clken_ctrl_X62_Y3_N0
    1212. 

  1212. macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] clken_ctrl_X62_Y3_N0
    1213. 

  1213. macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START clken_ctrl_X62_Y3_N0
    1214. 

  1214. macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] clken_ctrl_X62_Y3_N0
    1215. 

  1215. macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] clken_ctrl_X62_Y3_N0
    1216. 

  1216. macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] clken_ctrl_X62_Y3_N0
    1217. 

  1217. macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] clken_ctrl_X62_Y3_N1
    1218. 

  1218. macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] clken_ctrl_X62_Y3_N1
    1219. 

  1219. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y4_N0
    1220. 

  1220. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y4_N0
    1221. 

  1221. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y4_N0
    1222. 

  1222. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] clken_ctrl_X62_Y4_N1
    1223. 

  1223. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] clken_ctrl_X62_Y4_N1
    1224. 

  1224. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] clken_ctrl_X62_Y4_N1
    1225. 

  1225. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y4_N0
    1226. 

  1226. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y4_N0
    1227. 

  1227. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] clken_ctrl_X62_Y4_N1
    1228. 

  1228. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y4_N0
    1229. 

  1229. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] clken_ctrl_X62_Y4_N1
    1230. 

  1230. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y4_N0
    1231. 

  1231. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] clken_ctrl_X62_Y4_N1
    1232. 

  1232. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] clken_ctrl_X62_Y4_N1
    1233. 

  1233. macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y4_N0
    1234. 

  1234. macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] clken_ctrl_X62_Y4_N1
    1235. 

  1235. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y5_N0
    1236. 

  1236. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] clken_ctrl_X62_Y5_N1
    1237. 

  1237. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y5_N0
    1238. 

  1238. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] clken_ctrl_X62_Y5_N1
    1239. 

  1239. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y5_N0
    1240. 

  1240. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y5_N0
    1241. 

  1241. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y5_N0
    1242. 

  1242. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y5_N0
    1243. 

  1243. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] clken_ctrl_X62_Y5_N1
    1244. 

  1244. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y5_N0
    1245. 

  1245. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] clken_ctrl_X62_Y5_N1
    1246. 

  1246. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] clken_ctrl_X62_Y5_N1
    1247. 

  1247. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] clken_ctrl_X62_Y5_N1
    1248. 

  1248. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] clken_ctrl_X62_Y5_N1
    1249. 

  1249. macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y5_N0
    1250. 

  1250. macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] clken_ctrl_X62_Y5_N1
    1251. 

  1251. macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA clken_ctrl_X62_Y6_N0
    1252. 

  1252. macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt clken_ctrl_X62_Y6_N0
    1253. 

  1253. macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP clken_ctrl_X62_Y6_N0
    1254. 

  1254. macro_inst|u_uart[1]|u_regs|lcr_sps clken_ctrl_X62_Y6_N1
    1255. 

  1255. macro_inst|u_uart[1]|u_tx[4]|uart_txd clken_ctrl_X62_Y6_N0
    1256. 

  1256. macro_inst|u_uart[1]|u_regs|lcr_stp2 clken_ctrl_X62_Y6_N1
    1257. 

  1257. macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY clken_ctrl_X62_Y6_N0
    1258. 

  1258. macro_inst|u_uart[1]|u_regs|lcr_eps clken_ctrl_X62_Y6_N1
    1259. 

  1259. macro_inst|u_uart[1]|u_regs|lcr_pen clken_ctrl_X62_Y6_N1
    1260. 

  1260. macro_inst|u_uart[1]|u_tx[4]|tx_parity clken_ctrl_X62_Y6_N0
    1261. 

  1261. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] clken_ctrl_X62_Y7_N0
    1262. 

  1262. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] clken_ctrl_X62_Y7_N0
    1263. 

  1263. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y7_N1
    1264. 

  1264. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y7_N1
    1265. 

  1265. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y7_N1
    1266. 

  1266. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y7_N1
    1267. 

  1267. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] clken_ctrl_X62_Y7_N0
    1268. 

  1268. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y7_N1
    1269. 

  1269. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] clken_ctrl_X62_Y7_N0
    1270. 

  1270. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] clken_ctrl_X62_Y7_N0
    1271. 

  1271. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] clken_ctrl_X62_Y7_N0
    1272. 

  1272. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y7_N1
    1273. 

  1273. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] clken_ctrl_X62_Y7_N0
    1274. 

  1274. macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] clken_ctrl_X62_Y7_N0
    1275. 

  1275. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y7_N1
    1276. 

  1276. macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y7_N1
    1277. 

  1277. macro_inst|u_uart[1]|u_baud|i_cnt[0] clken_ctrl_X62_Y8_N0
    1278. 

  1278. macro_inst|u_uart[1]|u_baud|i_cnt[5] clken_ctrl_X62_Y8_N0
    1279. 

  1279. macro_inst|u_uart[1]|u_baud|i_cnt[6] clken_ctrl_X62_Y8_N0
    1280. 

  1280. macro_inst|u_uart[1]|u_baud|i_cnt[7] clken_ctrl_X62_Y8_N0
    1281. 

  1281. macro_inst|u_uart[1]|u_baud|i_cnt[8] clken_ctrl_X62_Y8_N0
    1282. 

  1282. macro_inst|u_uart[1]|u_baud|i_cnt[9] clken_ctrl_X62_Y8_N0
    1283. 

  1283. macro_inst|u_uart[1]|u_baud|i_cnt[1] clken_ctrl_X62_Y8_N0
    1284. 

  1284. macro_inst|u_uart[1]|u_baud|i_cnt[10] clken_ctrl_X62_Y8_N0
    1285. 

  1285. macro_inst|u_uart[1]|u_baud|i_cnt[11] clken_ctrl_X62_Y8_N0
    1286. 

  1286. macro_inst|u_uart[1]|u_baud|i_cnt[12] clken_ctrl_X62_Y8_N0
    1287. 

  1287. macro_inst|u_uart[1]|u_baud|i_cnt[13] clken_ctrl_X62_Y8_N0
    1288. 

  1288. macro_inst|u_uart[1]|u_baud|i_cnt[14] clken_ctrl_X62_Y8_N0
    1289. 

  1289. macro_inst|u_uart[1]|u_baud|i_cnt[15] clken_ctrl_X62_Y8_N0
    1290. 

  1290. macro_inst|u_uart[1]|u_baud|i_cnt[2] clken_ctrl_X62_Y8_N0
    1291. 

  1291. macro_inst|u_uart[1]|u_baud|i_cnt[3] clken_ctrl_X62_Y8_N0
    1292. 

  1292. macro_inst|u_uart[1]|u_baud|i_cnt[4] clken_ctrl_X62_Y8_N0
    1293. 

  1293. macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP clken_ctrl_X62_Y9_N0
    1294. 

  1294. macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] clken_ctrl_X62_Y9_N1
    1295. 

  1295. macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] clken_ctrl_X62_Y9_N0
    1296. 

  1296. macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] clken_ctrl_X62_Y9_N0
    1297. 

  1297. macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] clken_ctrl_X62_Y9_N0
    1298. 

  1298. macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] clken_ctrl_X62_Y9_N0
    1299. 

  1299. macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY clken_ctrl_X62_Y9_N0
    1300. 

  1300. macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] clken_ctrl_X62_Y9_N1
    1301. 

  1301. macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] clken_ctrl_X62_Y9_N1
    1302. 

  1302. macro_inst|u_uart[1]|u_tx[3]|tx_bit clken_ctrl_X62_Y9_N0
    1303. 

  1303. macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA clken_ctrl_X62_Y9_N0
    1304.