macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] clken_ctrl_X43_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] clken_ctrl_X43_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY clken_ctrl_X43_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] clken_ctrl_X43_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA clken_ctrl_X43_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] clken_ctrl_X43_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START clken_ctrl_X43_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP clken_ctrl_X43_Y1_N1
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_in[4] clken_ctrl_X43_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_in[2] clken_ctrl_X43_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_in[3] clken_ctrl_X43_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] clken_ctrl_X43_Y2_N0
macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] clken_ctrl_X43_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] clken_ctrl_X43_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] clken_ctrl_X43_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] clken_ctrl_X43_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_bit clken_ctrl_X43_Y3_N1
macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY clken_ctrl_X43_Y4_N0
macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START clken_ctrl_X43_Y4_N0
macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA clken_ctrl_X43_Y4_N0
macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE clken_ctrl_X43_Y4_N0
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] clken_ctrl_X44_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] clken_ctrl_X44_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] clken_ctrl_X44_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] clken_ctrl_X44_Y1_N1
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] clken_ctrl_X44_Y2_N1
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] clken_ctrl_X44_Y2_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] clken_ctrl_X44_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] clken_ctrl_X44_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] clken_ctrl_X44_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_parity clken_ctrl_X44_Y4_N0
macro_inst|u_uart[0]|u_rx[2]|rx_parity clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_parity clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_rx[1]|rx_in[0] clken_ctrl_X45_Y1_N1
macro_inst|u_uart[0]|u_tx[1]|uart_txd clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_bit clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] clken_ctrl_X45_Y1_N0
macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_parity clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|break_error clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_bit clken_ctrl_X45_Y2_N0
macro_inst|u_uart[0]|u_rx[5]|rx_in[3] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP clken_ctrl_X45_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_in[1] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA clken_ctrl_X45_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY clken_ctrl_X45_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|rx_in[4] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_in[4] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_in[3] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_in[2] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE clken_ctrl_X45_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_in[2] clken_ctrl_X45_Y3_N0
macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] clken_ctrl_X45_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] clken_ctrl_X45_Y4_N0
macro_inst|u_uart[0]|u_regs|interrupts[1] clken_ctrl_X45_Y4_N1
macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_rx[1]|rx_parity clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] clken_ctrl_X46_Y1_N1
macro_inst|u_uart[0]|u_tx[1]|tx_bit clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] clken_ctrl_X46_Y1_N1
macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_parity clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] clken_ctrl_X46_Y1_N1
macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] clken_ctrl_X46_Y1_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[1]|u_regs|tx_dma_en[4] clken_ctrl_X46_Y2_N1
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[1]|u_regs|rx_dma_en[4] clken_ctrl_X46_Y2_N1
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] clken_ctrl_X46_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] clken_ctrl_X46_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] clken_ctrl_X46_Y3_N0
macro_inst|u_uart[0]|u_regs|tx_dma_en[3] clken_ctrl_X46_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_dma_en[3] clken_ctrl_X46_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_dma_en[2] clken_ctrl_X46_Y4_N1
macro_inst|u_uart[0]|u_regs|tx_dma_en[2] clken_ctrl_X46_Y4_N1
macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] clken_ctrl_X47_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] clken_ctrl_X47_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] clken_ctrl_X47_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] clken_ctrl_X47_Y1_N1
macro_inst|u_uart[0]|u_regs|rx_reg[6] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_reg[5] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_reg[4] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_reg[2] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_reg[0] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_regs|rx_reg[3] clken_ctrl_X47_Y2_N0
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] clken_ctrl_X47_Y2_N1
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] clken_ctrl_X47_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY clken_ctrl_X47_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START clken_ctrl_X47_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE clken_ctrl_X47_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA clken_ctrl_X47_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] clken_ctrl_X47_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP clken_ctrl_X47_Y3_N1
macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] clken_ctrl_X47_Y4_N0
macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA clken_ctrl_X47_Y4_N1
macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt clken_ctrl_X47_Y4_N1
macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP clken_ctrl_X47_Y4_N1
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_in[4] clken_ctrl_X48_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[5]|rx_in[1] clken_ctrl_X48_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_in[2] clken_ctrl_X48_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_in[3] clken_ctrl_X48_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] clken_ctrl_X48_Y1_N0
macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP clken_ctrl_X48_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA clken_ctrl_X48_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE clken_ctrl_X48_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] clken_ctrl_X48_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|rx_bit clken_ctrl_X48_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY clken_ctrl_X48_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] clken_ctrl_X48_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY clken_ctrl_X48_Y3_N0
macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA clken_ctrl_X48_Y3_N0
macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP clken_ctrl_X48_Y3_N0
macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] clken_ctrl_X48_Y4_N0
macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] clken_ctrl_X48_Y4_N0
macro_inst|u_uart[0]|u_regs|break_error_ie[1] clken_ctrl_X48_Y4_N1
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] clken_ctrl_X49_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] clken_ctrl_X49_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] clken_ctrl_X49_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] clken_ctrl_X49_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] clken_ctrl_X49_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] clken_ctrl_X49_Y1_N1
macro_inst|u_uart[0]|u_rx[1]|rx_dma_req clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_bit clken_ctrl_X49_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_in[3] clken_ctrl_X49_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_in[4] clken_ctrl_X49_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_in[1] clken_ctrl_X49_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_in[2] clken_ctrl_X49_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] clken_ctrl_X49_Y3_N1
macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] clken_ctrl_X49_Y4_N0
macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] clken_ctrl_X49_Y4_N0
macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] clken_ctrl_X49_Y4_N1
macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] clken_ctrl_X49_Y4_N1
macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] clken_ctrl_X49_Y4_N1
macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] clken_ctrl_X49_Y4_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] clken_ctrl_X50_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] clken_ctrl_X50_Y1_N0
macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] clken_ctrl_X50_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE clken_ctrl_X50_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_idle_en clken_ctrl_X50_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_bit clken_ctrl_X50_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] clken_ctrl_X50_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] clken_ctrl_X50_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_idle clken_ctrl_X50_Y1_N1
macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_parity clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_reg[1] clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_idle_en clken_ctrl_X50_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|rx_bit clken_ctrl_X50_Y2_N0
macro_inst|u_ahb2apb|hdone clken_ctrl_X50_Y2_N1
macro_inst|u_uart[0]|u_regs|interrupts[2] clken_ctrl_X50_Y2_N0
macro_inst|u_ahb2apb|hreadyout clken_ctrl_X50_Y2_N1
macro_inst|u_uart[0]|u_rx[0]|break_error clken_ctrl_X50_Y2_N0
macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] clken_ctrl_X50_Y3_N1
macro_inst|u_uart[1]|u_tx[5]|tx_bit clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] clken_ctrl_X50_Y3_N1
macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] clken_ctrl_X50_Y3_N0
macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] clken_ctrl_X50_Y3_N1
macro_inst|u_uart[0]|u_regs|parity_error_ie[1] clken_ctrl_X50_Y4_N0
macro_inst|u_uart[0]|u_regs|framing_error_ie[1] clken_ctrl_X50_Y4_N0
macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] clken_ctrl_X51_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA clken_ctrl_X51_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] clken_ctrl_X51_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] clken_ctrl_X51_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|uart_txd clken_ctrl_X51_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP clken_ctrl_X51_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_parity clken_ctrl_X51_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY clken_ctrl_X51_Y1_N1
macro_inst|u_uart[0]|u_tx[1]|tx_complete clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|break_error clken_ctrl_X51_Y2_N0
macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] clken_ctrl_X51_Y2_N1
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] clken_ctrl_X51_Y2_N1
macro_inst|u_uart[0]|u_rx[0]|overrun_error clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|parity_error clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|parity_error clken_ctrl_X51_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] clken_ctrl_X51_Y2_N1
macro_inst|u_uart[0]|u_rx[1]|overrun_error clken_ctrl_X51_Y2_N0
macro_inst|sim_clk_cnt[1] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[2] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[3] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[4] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[5] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[6] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[7] clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_reg clken_ctrl_X51_Y3_N0
macro_inst|sim_clk_cnt[0] clken_ctrl_X51_Y3_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[0] clken_ctrl_X51_Y4_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[0] clken_ctrl_X51_Y4_N1
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] clken_ctrl_X52_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] clken_ctrl_X52_Y1_N0
macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_regs|framing_error_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_rx[1]|framing_error clken_ctrl_X52_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_regs|parity_error_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_regs|interrupts[0] clken_ctrl_X52_Y2_N1
macro_inst|u_uart[0]|u_regs|break_error_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_rx[0]|framing_error clken_ctrl_X52_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] clken_ctrl_X52_Y2_N0
macro_inst|u_uart[0]|u_tx[0]|tx_complete clken_ctrl_X52_Y2_N1
macro_inst|u_uart[0]|u_rx[1]|rx_idle clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_regs|rx_read[0] clken_ctrl_X52_Y3_N0
macro_inst|u_uart[1]|u_rx[5]|rx_in[0] clken_ctrl_X52_Y3_N1
macro_inst|u_uart[1]|u_rx[1]|rx_bit clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_dma_req clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_rx[1]|rx_idle_en clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_idle_en clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] clken_ctrl_X52_Y3_N0
macro_inst|u_uart[0]|u_rx[0]|rx_idle clken_ctrl_X52_Y3_N0
macro_inst|u_uart[1]|u_rx[5]|rx_in[1] clken_ctrl_X52_Y3_N1
macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY clken_ctrl_X52_Y4_N0
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] clken_ctrl_X52_Y4_N1
macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP clken_ctrl_X52_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] clken_ctrl_X52_Y4_N1
macro_inst|u_uart[0]|u_tx[0]|uart_txd clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_regs|status_reg[1] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_bit clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] clken_ctrl_X53_Y1_N0
macro_inst|u_uart[0]|u_rx[0]|rx_in[0] clken_ctrl_X53_Y1_N1
macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_rx[3]|framing_error clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|break_error clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_rx[3]|parity_error clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_regs|parity_error_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_rx[3]|rx_idle clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_regs|interrupts[3] clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_rx[3]|overrun_error clken_ctrl_X53_Y2_N1
macro_inst|u_uart[0]|u_regs|break_error_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_regs|framing_error_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] clken_ctrl_X53_Y2_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE clken_ctrl_X53_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START clken_ctrl_X53_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] clken_ctrl_X53_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_baud|baud16 clken_ctrl_X53_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] clken_ctrl_X53_Y3_N0
macro_inst|u_uart[1]|u_rx[1]|rx_in[1] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[1]|u_rx[4]|rx_in[3] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[1]|u_rx[4]|rx_in[1] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[1]|u_rx[3]|rx_in[1] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[1]|u_rx[4]|rx_in[4] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[0]|u_regs|interrupts[5] clken_ctrl_X53_Y4_N1
macro_inst|u_uart[1]|u_rx[3]|rx_in[0] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_read[1] clken_ctrl_X53_Y4_N1
macro_inst|u_uart[1]|u_rx[4]|rx_in[0] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[0]|u_regs|rx_read[3] clken_ctrl_X53_Y4_N1
macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] clken_ctrl_X53_Y4_N1
macro_inst|u_uart[1]|u_rx[4]|rx_in[2] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] clken_ctrl_X53_Y4_N1
macro_inst|u_uart[1]|u_rx[1]|rx_in[0] clken_ctrl_X53_Y4_N0
macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] clken_ctrl_X54_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_parity clken_ctrl_X54_Y1_N1
macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt clken_ctrl_X54_Y1_N1
macro_inst|u_uart[0]|u_regs|rx_read[2] clken_ctrl_X54_Y1_N1
macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP clken_ctrl_X54_Y1_N1
macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY clken_ctrl_X54_Y1_N1
macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] clken_ctrl_X54_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] clken_ctrl_X54_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA clken_ctrl_X54_Y1_N1
macro_inst|u_ahb2apb|haddr[12] clken_ctrl_X54_Y2_N0
macro_inst|u_uart[0]|u_regs|break_error_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_ahb2apb|hwrite clken_ctrl_X54_Y2_N0
macro_inst|u_ahb2apb|haddr[7] clken_ctrl_X54_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|parity_error_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_regs|framing_error_ie[2] clken_ctrl_X54_Y2_N1
macro_inst|u_uart[0]|u_baud|i_cnt[0] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[5] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[6] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[7] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[8] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[9] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[1] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[10] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[11] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[12] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[13] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[14] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[15] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[2] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[3] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[0]|u_baud|i_cnt[4] clken_ctrl_X54_Y3_N0
macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] clken_ctrl_X54_Y4_N0
macro_inst|u_uart[1]|u_regs|tx_write[2] clken_ctrl_X54_Y4_N1
macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] clken_ctrl_X54_Y4_N0
macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] clken_ctrl_X54_Y4_N0
macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] clken_ctrl_X54_Y4_N1
macro_inst|u_uart[1]|u_rx[0]|rx_parity clken_ctrl_X54_Y4_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] clken_ctrl_X56_Y10_N1
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] clken_ctrl_X56_Y10_N0
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] clken_ctrl_X56_Y11_N0
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] clken_ctrl_X56_Y11_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] clken_ctrl_X56_Y12_N1
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] clken_ctrl_X56_Y12_N0
macro_inst|u_uart[0]|u_rx[2]|break_error clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_rx[5]|rx_in[0] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[3]|rx_idle_en clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|overrun_error clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_tx[0]|tx_dma_req clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|framing_error clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_in[1] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_in[3] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_in[0] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_in[4] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_in[2] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_rx[2]|rx_in[1] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_tx[3]|tx_complete clken_ctrl_X56_Y1_N0
macro_inst|u_uart[0]|u_rx[3]|rx_in[0] clken_ctrl_X56_Y1_N1
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] clken_ctrl_X56_Y2_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[5] clken_ctrl_X56_Y2_N1
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] clken_ctrl_X56_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_idle clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] clken_ctrl_X56_Y3_N1
macro_inst|u_ahb2apb|apbState.apbSetup clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] clken_ctrl_X56_Y3_N1
macro_inst|u_ahb2apb|pvalid clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_regs|tx_write[0] clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|rx_idle clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] clken_ctrl_X56_Y3_N1
macro_inst|u_ahb2apb|apbState.apbIdle clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] clken_ctrl_X56_Y3_N1
macro_inst|u_ahb2apb|apbState.apbAccess clken_ctrl_X56_Y3_N0
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] clken_ctrl_X56_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] clken_ctrl_X56_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] clken_ctrl_X56_Y3_N1
macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] clken_ctrl_X56_Y3_N1
macro_inst|u_uart[1]|u_regs|tx_dma_en[2] clken_ctrl_X56_Y4_N0
macro_inst|u_uart[1]|u_regs|rx_dma_en[2] clken_ctrl_X56_Y4_N0
macro_inst|u_uart[1]|u_regs|tx_dma_en[3] clken_ctrl_X56_Y4_N1
macro_inst|u_uart[1]|u_regs|rx_dma_en[3] clken_ctrl_X56_Y4_N1
macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START clken_ctrl_X56_Y5_N0
macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_regs|status_reg[4] clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_regs|status_reg[2] clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE clken_ctrl_X56_Y5_N0
macro_inst|u_uart[0]|u_regs|rx_reg[7] clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_tx[5]|uart_txd clken_ctrl_X56_Y5_N0
macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] clken_ctrl_X56_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] clken_ctrl_X56_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] clken_ctrl_X56_Y6_N1
macro_inst|u_uart[1]|u_regs|tx_write[0] clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[1]|uart_txd clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[1]|tx_parity clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[0]|uart_txd clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] clken_ctrl_X56_Y7_N1
macro_inst|u_uart[1]|u_rx[1]|rx_parity clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_rx[2]|rx_idle_en clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_rx[2]|rx_bit clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_rx[0]|rx_idle_en clken_ctrl_X56_Y7_N0
macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] clken_ctrl_X56_Y8_N1
macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] clken_ctrl_X56_Y8_N1
macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] clken_ctrl_X56_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_tx[1]|tx_bit clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_rx[2]|rx_parity clken_ctrl_X56_Y8_N0
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_in[4] clken_ctrl_X56_Y9_N1
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_in[2] clken_ctrl_X56_Y9_N1
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_in[3] clken_ctrl_X56_Y9_N1
macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] clken_ctrl_X56_Y9_N0
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] clken_ctrl_X57_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_bit clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] clken_ctrl_X57_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt clken_ctrl_X57_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] clken_ctrl_X57_Y10_N0
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] clken_ctrl_X57_Y10_N0
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] clken_ctrl_X57_Y11_N0
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] clken_ctrl_X57_Y11_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] clken_ctrl_X57_Y12_N1
macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] clken_ctrl_X57_Y12_N0
macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_regs|tx_dma_en[4] clken_ctrl_X57_Y1_N1
macro_inst|u_uart[0]|u_regs|rx_dma_en[4] clken_ctrl_X57_Y1_N1
macro_inst|u_uart[0]|u_tx[5]|tx_complete clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_complete clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_rx[2]|parity_error clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_rx[5]|rx_idle_en clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_regs|rx_read[4] clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_rx[5]|overrun_error clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_regs|rx_read[5] clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_regs|tx_write[5] clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] clken_ctrl_X57_Y1_N0
macro_inst|u_uart[0]|u_regs|rx_dma_en[0] clken_ctrl_X57_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_dma_en[1] clken_ctrl_X57_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_dma_en[0] clken_ctrl_X57_Y2_N0
macro_inst|u_uart[0]|u_regs|tx_dma_en[1] clken_ctrl_X57_Y2_N1
macro_inst|u_uart[0]|u_rx[4]|overrun_error clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|break_error_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_regs|parity_error_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_regs|interrupts[4] clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_rx[4]|parity_error clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|status_reg[4] clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_tx[4]|tx_complete clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_regs|framing_error_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[0]|u_rx[4]|framing_error clken_ctrl_X57_Y3_N0
macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] clken_ctrl_X57_Y3_N1
macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] clken_ctrl_X57_Y4_N0
macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] clken_ctrl_X57_Y4_N0
macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] clken_ctrl_X57_Y4_N0
macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] clken_ctrl_X57_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START clken_ctrl_X57_Y4_N1
pll_inst|auto_generated|pll_lock_sync clken_ctrl_X57_Y5_N0
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] clken_ctrl_X57_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] clken_ctrl_X57_Y6_N1
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] clken_ctrl_X57_Y6_N0
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] clken_ctrl_X57_Y6_N0
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] clken_ctrl_X57_Y7_N0
macro_inst|u_uart[1]|u_regs|rx_read[2] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_regs|interrupts[1] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_read[3] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_rx[2]|rx_idle clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_read[0] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_regs|status_reg[0] clken_ctrl_X57_Y7_N1
macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE clken_ctrl_X57_Y7_N1
macro_inst|u_uart[1]|u_rx[0]|rx_in[4] clken_ctrl_X57_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_in[3] clken_ctrl_X57_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_in[0] clken_ctrl_X57_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_in[2] clken_ctrl_X57_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] clken_ctrl_X57_Y8_N1
macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] clken_ctrl_X57_Y9_N1
macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_bit clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_parity clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START clken_ctrl_X57_Y9_N0
macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] clken_ctrl_X57_Y9_N1
macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] clken_ctrl_X57_Y9_N1
macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] clken_ctrl_X58_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|uart_txd clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] clken_ctrl_X58_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] clken_ctrl_X58_Y10_N1
macro_inst|u_uart[1]|u_tx[2]|tx_parity clken_ctrl_X58_Y10_N0
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_regs|rx_reg[0] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_regs|rx_reg[6] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_regs|rx_reg[5] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_regs|rx_reg[1] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_regs|rx_reg[4] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_regs|rx_reg[7] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_regs|rx_reg[3] clken_ctrl_X58_Y11_N1
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] clken_ctrl_X58_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE clken_ctrl_X58_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_bit clken_ctrl_X58_Y12_N0
macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] clken_ctrl_X58_Y1_N0
macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] clken_ctrl_X58_Y1_N0
macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_regs|status_reg[0] clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP clken_ctrl_X58_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] clken_ctrl_X58_Y1_N0
macro_inst|u_uart[0]|u_regs|ibrd[2] clken_ctrl_X58_Y2_N0
macro_inst|u_uart[1]|u_regs|ibrd[1] clken_ctrl_X58_Y2_N1
macro_inst|u_uart[0]|u_regs|ibrd[1] clken_ctrl_X58_Y2_N0
macro_inst|u_uart[0]|u_regs|ibrd[3] clken_ctrl_X58_Y2_N0
macro_inst|u_uart[0]|u_regs|ibrd[10] clken_ctrl_X58_Y2_N0
macro_inst|u_uart[0]|u_regs|apb_pready clken_ctrl_X58_Y3_N1
macro_inst|u_uart[1]|u_rx[2]|rx_in[0] clken_ctrl_X58_Y3_N0
macro_inst|u_uart[0]|u_rx[5]|framing_error clken_ctrl_X58_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|break_error clken_ctrl_X58_Y3_N1
macro_inst|u_uart[1]|u_regs|apb_pready clken_ctrl_X58_Y3_N1
macro_inst|u_uart[0]|u_regs|status_reg[2] clken_ctrl_X58_Y3_N1
macro_inst|u_ahb2apb|penable clken_ctrl_X58_Y3_N1
macro_inst|u_uart[1]|u_rx[1]|parity_error clken_ctrl_X58_Y3_N1
macro_inst|u_uart[0]|u_rx[5]|parity_error clken_ctrl_X58_Y3_N1
macro_inst|u_uart[1]|u_rx[0]|parity_error clken_ctrl_X58_Y3_N1
macro_inst|u_ahb2apb|pdone clken_ctrl_X58_Y3_N1
macro_inst|u_ahb2apb|psel clken_ctrl_X58_Y3_N1
macro_inst|u_uart[0]|u_regs|rx_dma_en[5] clken_ctrl_X58_Y4_N0
macro_inst|u_uart[0]|u_regs|tx_dma_en[5] clken_ctrl_X58_Y4_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[1] clken_ctrl_X58_Y4_N1
macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP clken_ctrl_X58_Y5_N0
macro_inst|u_uart[0]|u_regs|uart_en clken_ctrl_X58_Y5_N0
macro_inst|u_uart[1]|u_regs|fbrd[0] clken_ctrl_X58_Y5_N1
macro_inst|u_uart[1]|u_rx[2]|break_error clken_ctrl_X58_Y5_N0
macro_inst|u_uart[1]|u_tx[2]|tx_complete clken_ctrl_X58_Y5_N0
macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY clken_ctrl_X58_Y5_N0
macro_inst|u_uart[1]|u_rx[2]|overrun_error clken_ctrl_X58_Y5_N0
macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY clken_ctrl_X58_Y6_N0
macro_inst|u_uart[1]|u_tx[0]|tx_complete clken_ctrl_X58_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|rx_idle clken_ctrl_X58_Y6_N0
macro_inst|u_uart[1]|u_rx[0]|rx_idle clken_ctrl_X58_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP clken_ctrl_X58_Y6_N0
macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] clken_ctrl_X58_Y6_N1
macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_rx[0]|overrun_error clken_ctrl_X58_Y7_N1
macro_inst|u_uart[1]|u_rx[2]|parity_error clken_ctrl_X58_Y7_N1
macro_inst|u_uart[1]|u_regs|framing_error_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|break_error_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|interrupts[0] clken_ctrl_X58_Y7_N1
macro_inst|u_uart[1]|u_regs|parity_error_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] clken_ctrl_X58_Y7_N0
macro_inst|u_uart[1]|u_regs|interrupts[2] clken_ctrl_X58_Y7_N1
macro_inst|u_uart[1]|u_rx[3]|overrun_error clken_ctrl_X58_Y7_N1
macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[3]|rx_idle_en clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|framing_error clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|break_error clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|parity_error clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|rx_idle_en clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|rx_parity clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_bit clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] clken_ctrl_X58_Y8_N0
macro_inst|u_uart[1]|u_regs|tx_write[4] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|overrun_error clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[2]|rx_in[1] clken_ctrl_X58_Y9_N1
macro_inst|u_uart[1]|u_regs|tx_write[1] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_regs|rx_read[1] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_tx[1]|tx_complete clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_regs|rx_read[4] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|rx_idle_en clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[1]|framing_error clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_regs|rx_read[5] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] clken_ctrl_X58_Y9_N0
macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP clken_ctrl_X59_Y10_N0
macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] clken_ctrl_X59_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] clken_ctrl_X59_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] clken_ctrl_X59_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY clken_ctrl_X59_Y10_N0
macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] clken_ctrl_X59_Y10_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] clken_ctrl_X59_Y11_N1
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] clken_ctrl_X59_Y11_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP clken_ctrl_X59_Y12_N1
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY clken_ctrl_X59_Y12_N1
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] clken_ctrl_X59_Y12_N0
macro_inst|u_uart[0]|u_regs|lcr_sps clken_ctrl_X59_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_parity clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_regs|lcr_pen clken_ctrl_X59_Y1_N0
macro_inst|u_uart[0]|u_tx[4]|uart_txd clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_regs|lcr_eps clken_ctrl_X59_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_parity clken_ctrl_X59_Y1_N1
macro_inst|u_uart[0]|u_regs|lcr_stp2 clken_ctrl_X59_Y1_N0
macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE clken_ctrl_X59_Y1_N1
macro_inst|u_ahb2apb|paddr[8] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|haddr[9] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|paddr[9] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|paddr[4] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|paddr[5] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|haddr[2] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|haddr[3] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|haddr[6] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|haddr[8] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|paddr[3] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|haddr[10] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|haddr[5] clken_ctrl_X59_Y2_N1
macro_inst|u_ahb2apb|paddr[10] clken_ctrl_X59_Y2_N0
macro_inst|u_ahb2apb|haddr[4] clken_ctrl_X59_Y2_N1
macro_inst|u_uart[0]|u_regs|ibrd[6] clken_ctrl_X59_Y3_N0
macro_inst|u_uart[0]|u_regs|ibrd[15] clken_ctrl_X59_Y3_N0
macro_inst|u_ahb2apb|paddr[7] clken_ctrl_X59_Y3_N1
macro_inst|u_ahb2apb|pwrite clken_ctrl_X59_Y3_N1
macro_inst|u_ahb2apb|paddr[6] clken_ctrl_X59_Y3_N1
macro_inst|u_ahb2apb|paddr[12] clken_ctrl_X59_Y3_N1
macro_inst|u_uart[0]|u_regs|ibrd[8] clken_ctrl_X59_Y3_N0
macro_inst|u_ahb2apb|paddr[2] clken_ctrl_X59_Y3_N1
macro_inst|u_uart[0]|u_regs|ibrd[11] clken_ctrl_X59_Y3_N0
macro_inst|u_uart[1]|u_regs|ibrd[14] clken_ctrl_X59_Y4_N0
macro_inst|u_uart[0]|u_regs|ibrd[14] clken_ctrl_X59_Y4_N1
macro_inst|u_uart[1]|u_regs|ibrd[3] clken_ctrl_X59_Y4_N0
macro_inst|u_uart[0]|u_regs|ibrd[13] clken_ctrl_X59_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[7] clken_ctrl_X59_Y5_N1
macro_inst|u_uart[1]|u_regs|ibrd[0] clken_ctrl_X59_Y5_N1
macro_inst|u_uart[0]|u_regs|ibrd[0] clken_ctrl_X59_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[2] clken_ctrl_X59_Y5_N1
macro_inst|u_uart[1]|u_regs|ibrd[13] clken_ctrl_X59_Y5_N1
macro_inst|u_uart[1]|u_rx[0]|framing_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_rx[3]|framing_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_rx[0]|break_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_rx[3]|rx_idle clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_regs|rx_reg[2] clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_rx[1]|break_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] clken_ctrl_X59_Y6_N1
macro_inst|u_uart[1]|u_rx[2]|framing_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_rx[3]|break_error clken_ctrl_X59_Y6_N0
macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] clken_ctrl_X59_Y7_N1
macro_inst|u_uart[1]|u_regs|framing_error_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|break_error_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|framing_error_ie[1] clken_ctrl_X59_Y7_N1
macro_inst|u_uart[1]|u_regs|parity_error_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|parity_error_ie[1] clken_ctrl_X59_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] clken_ctrl_X59_Y7_N0
macro_inst|u_uart[1]|u_regs|break_error_ie[1] clken_ctrl_X59_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] clken_ctrl_X59_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_dma_en[1] clken_ctrl_X59_Y8_N0
macro_inst|u_uart[1]|u_regs|tx_dma_en[1] clken_ctrl_X59_Y8_N0
macro_inst|u_uart[1]|u_regs|rx_dma_en[0] clken_ctrl_X59_Y8_N1
macro_inst|u_uart[1]|u_regs|tx_dma_en[0] clken_ctrl_X59_Y8_N1
macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] clken_ctrl_X59_Y9_N0
macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] clken_ctrl_X59_Y9_N1
macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] clken_ctrl_X59_Y9_N0
macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] clken_ctrl_X59_Y9_N1
macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] clken_ctrl_X59_Y9_N0
macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] clken_ctrl_X60_Y10_N0
macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[3]|rx_bit clken_ctrl_X60_Y10_N1
macro_inst|u_uart[1]|u_rx[0]|rx_in[1] clken_ctrl_X60_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_in[2] clken_ctrl_X60_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_in[3] clken_ctrl_X60_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] clken_ctrl_X60_Y11_N1
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] clken_ctrl_X60_Y12_N0
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] clken_ctrl_X60_Y12_N1
macro_inst|u_uart[0]|u_regs|fbrd[2] clken_ctrl_X60_Y1_N0
macro_inst|u_uart[0]|u_regs|fbrd[4] clken_ctrl_X60_Y1_N0
macro_inst|u_uart[0]|u_regs|tx_write[2] clken_ctrl_X60_Y1_N1
macro_inst|u_uart[0]|u_regs|fbrd[3] clken_ctrl_X60_Y1_N0
macro_inst|u_uart[0]|u_baud|f_del clken_ctrl_X60_Y1_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] clken_ctrl_X60_Y1_N1
macro_inst|u_uart[0]|u_regs|fbrd[5] clken_ctrl_X60_Y1_N0
macro_inst|u_uart[0]|u_regs|fbrd[1] clken_ctrl_X60_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|uart_txd clken_ctrl_X60_Y1_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[9] clken_ctrl_X60_Y2_N0
macro_inst|u_uart[0]|u_regs|framing_error_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[12] clken_ctrl_X60_Y2_N0
macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|break_error_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[11] clken_ctrl_X60_Y2_N0
macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[10] clken_ctrl_X60_Y2_N0
macro_inst|u_uart[0]|u_regs|parity_error_ie[5] clken_ctrl_X60_Y2_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[8] clken_ctrl_X60_Y2_N0
macro_inst|u_ahb2apb|prdata[1] clken_ctrl_X60_Y3_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[6] clken_ctrl_X60_Y3_N1
macro_inst|u_ahb2apb|prdata[13] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[0] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[5] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[7] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[15] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[2] clken_ctrl_X60_Y3_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[13] clken_ctrl_X60_Y3_N1
macro_inst|u_ahb2apb|prdata[6] clken_ctrl_X60_Y3_N0
macro_inst|u_ahb2apb|prdata[14] clken_ctrl_X60_Y3_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[15] clken_ctrl_X60_Y3_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[14] clken_ctrl_X60_Y3_N1
macro_inst|u_uart[1]|u_regs|rx_dma_en[5] clken_ctrl_X60_Y4_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[15] clken_ctrl_X60_Y4_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[3] clken_ctrl_X60_Y4_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[14] clken_ctrl_X60_Y4_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[1] clken_ctrl_X60_Y4_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[5] clken_ctrl_X60_Y4_N1
macro_inst|u_uart[1]|u_regs|tx_dma_en[5] clken_ctrl_X60_Y4_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[7] clken_ctrl_X60_Y5_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[6] clken_ctrl_X60_Y5_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[7] clken_ctrl_X60_Y5_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[2] clken_ctrl_X60_Y5_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[4] clken_ctrl_X60_Y5_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[13] clken_ctrl_X60_Y5_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[2] clken_ctrl_X60_Y5_N1
macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] clken_ctrl_X60_Y6_N0
macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] clken_ctrl_X60_Y6_N1
macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] clken_ctrl_X60_Y6_N0
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] clken_ctrl_X60_Y6_N0
macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] clken_ctrl_X60_Y6_N1
macro_inst|u_uart[1]|u_regs|break_error_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_regs|framing_error_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_regs|interrupts[3] clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_rx[3]|parity_error clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_tx[3]|tx_complete clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_complete clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_regs|parity_error_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_rx[5]|rx_idle clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] clken_ctrl_X60_Y7_N1
macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] clken_ctrl_X60_Y7_N0
macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_rx[4]|overrun_error clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_regs|break_error_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_regs|uart_en clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_rx[4]|rx_idle clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_rx[5]|overrun_error clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_regs|framing_error_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_tx[4]|tx_complete clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_regs|interrupts[4] clken_ctrl_X60_Y8_N1
macro_inst|u_uart[1]|u_regs|parity_error_ie[4] clken_ctrl_X60_Y8_N0
macro_inst|u_uart[1]|u_rx[3]|rx_in[3] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|uart_txd clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_tx[5]|tx_parity clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[5]|break_error clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[5]|rx_in[4] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_rx[5]|framing_error clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[3]|rx_parity clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[3]|rx_in[2] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_rx[3]|rx_in[4] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_rx[2]|rx_in[4] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_parity clken_ctrl_X60_Y9_N1
macro_inst|u_uart[1]|u_rx[2]|rx_in[3] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_rx[2]|rx_in[2] clken_ctrl_X60_Y9_N0
macro_inst|u_uart[1]|u_rx[5]|rx_parity clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] clken_ctrl_X61_Y10_N0
macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START clken_ctrl_X61_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY clken_ctrl_X61_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA clken_ctrl_X61_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP clken_ctrl_X61_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_bit clken_ctrl_X61_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE clken_ctrl_X61_Y11_N0
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] clken_ctrl_X61_Y12_N0
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] clken_ctrl_X61_Y12_N1
macro_inst|u_uart[0]|u_baud|f_cnt[0] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_baud|f_cnt[5] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_bit clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_regs|tx_write[1] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_baud|f_cnt[1] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_tx[1]|tx_dma_req clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_baud|f_cnt[2] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_baud|f_cnt[3] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_baud|f_cnt[4] clken_ctrl_X61_Y1_N0
macro_inst|u_uart[0]|u_regs|apb_prdata[3] clken_ctrl_X61_Y2_N0
macro_inst|u_uart[0]|u_regs|ibrd[5] clken_ctrl_X61_Y2_N1
macro_inst|u_uart[0]|u_regs|apb_prdata[4] clken_ctrl_X61_Y2_N0
macro_inst|u_uart[0]|u_regs|ibrd[4] clken_ctrl_X61_Y2_N1
macro_inst|u_uart[0]|u_regs|ibrd[9] clken_ctrl_X61_Y2_N1
macro_inst|u_uart[0]|u_regs|ibrd[7] clken_ctrl_X61_Y2_N1
macro_inst|u_uart[0]|u_regs|ibrd[12] clken_ctrl_X61_Y2_N1
macro_inst|u_ahb2apb|prdata[12] clken_ctrl_X61_Y3_N0
macro_inst|u_ahb2apb|prdata[9] clken_ctrl_X61_Y3_N0
macro_inst|u_ahb2apb|prdata[8] clken_ctrl_X61_Y3_N0
macro_inst|u_apb_mux|pr_select[1] clken_ctrl_X61_Y3_N1
macro_inst|u_ahb2apb|prdata[11] clken_ctrl_X61_Y3_N0
macro_inst|u_ahb2apb|prdata[10] clken_ctrl_X61_Y3_N0
macro_inst|u_ahb2apb|prdata[3] clken_ctrl_X61_Y3_N0
macro_inst|u_ahb2apb|prdata[4] clken_ctrl_X61_Y3_N0
macro_inst|u_apb_mux|pr_select[0] clken_ctrl_X61_Y3_N1
macro_inst|u_uart[1]|u_baud|f_del clken_ctrl_X61_Y4_N0
macro_inst|u_uart[0]|u_tx[3]|uart_txd clken_ctrl_X61_Y4_N0
macro_inst|u_uart[1]|u_regs|fbrd[5] clken_ctrl_X61_Y4_N1
macro_inst|u_uart[1]|u_regs|status_reg[1] clken_ctrl_X61_Y4_N0
macro_inst|u_uart[1]|u_regs|fbrd[1] clken_ctrl_X61_Y4_N1
macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] clken_ctrl_X61_Y4_N0
macro_inst|u_uart[0]|u_regs|tx_write[3] clken_ctrl_X61_Y4_N0
macro_inst|u_uart[0]|u_tx[3]|tx_parity clken_ctrl_X61_Y4_N0
macro_inst|u_uart[1]|u_regs|fbrd[2] clken_ctrl_X61_Y4_N1
macro_inst|u_uart[1]|u_regs|fbrd[3] clken_ctrl_X61_Y4_N1
macro_inst|u_uart[1]|u_regs|fbrd[4] clken_ctrl_X61_Y4_N1
macro_inst|u_uart[1]|u_regs|ibrd[11] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[8] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[10] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[0]|u_regs|fbrd[0] clken_ctrl_X61_Y5_N1
macro_inst|u_uart[1]|u_regs|ibrd[6] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[4] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[12] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[9] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[15] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|ibrd[5] clken_ctrl_X61_Y5_N0
macro_inst|u_uart[1]|u_regs|break_error_ie[5] clken_ctrl_X61_Y6_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[10] clken_ctrl_X61_Y6_N1
macro_inst|u_uart[1]|u_regs|parity_error_ie[5] clken_ctrl_X61_Y6_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[12] clken_ctrl_X61_Y6_N1
macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] clken_ctrl_X61_Y6_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[8] clken_ctrl_X61_Y6_N1
macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] clken_ctrl_X61_Y6_N0
macro_inst|u_uart[1]|u_regs|apb_prdata[9] clken_ctrl_X61_Y6_N1
macro_inst|u_uart[1]|u_regs|apb_prdata[11] clken_ctrl_X61_Y6_N1
macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] clken_ctrl_X61_Y6_N0
macro_inst|u_uart[1]|u_regs|tx_write[3] clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] clken_ctrl_X61_Y7_N1
macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_regs|framing_error_ie[5] clken_ctrl_X61_Y7_N1
macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] clken_ctrl_X61_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_regs|interrupts[5] clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_regs|tx_write[5] clken_ctrl_X61_Y7_N0
macro_inst|u_uart[1]|u_baud|f_cnt[1] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|f_cnt[2] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|f_cnt[3] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|f_cnt[4] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|f_cnt[5] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_rx[5]|parity_error clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|baud16 clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_rx[5]|rx_idle_en clken_ctrl_X61_Y8_N0
macro_inst|u_uart[1]|u_baud|f_cnt[0] clken_ctrl_X61_Y8_N0
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] clken_ctrl_X61_Y9_N1
macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] clken_ctrl_X61_Y9_N0
macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] clken_ctrl_X62_Y10_N1
macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] clken_ctrl_X62_Y10_N1
macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_bit clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START clken_ctrl_X62_Y10_N0
macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] clken_ctrl_X62_Y10_N1
macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] clken_ctrl_X62_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] clken_ctrl_X62_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] clken_ctrl_X62_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] clken_ctrl_X62_Y11_N0
macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] clken_ctrl_X62_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] clken_ctrl_X62_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] clken_ctrl_X62_Y11_N1
macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] clken_ctrl_X62_Y11_N1
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y12_N0
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] clken_ctrl_X62_Y12_N1
macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] clken_ctrl_X62_Y1_N1
macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] clken_ctrl_X62_Y1_N1
macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA clken_ctrl_X62_Y1_N0
macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] clken_ctrl_X62_Y1_N1
macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_in[0] clken_ctrl_X62_Y2_N1
macro_inst|u_uart[0]|u_tx[4]|tx_bit clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_rx[4]|rx_in[1] clken_ctrl_X62_Y2_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_regs|tx_write[4] clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP clken_ctrl_X62_Y2_N0
macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] clken_ctrl_X62_Y3_N1
macro_inst|u_uart[0]|u_tx[3]|tx_bit clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] clken_ctrl_X62_Y3_N0
macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] clken_ctrl_X62_Y3_N1
macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] clken_ctrl_X62_Y3_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y4_N0
macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] clken_ctrl_X62_Y4_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y5_N0
macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] clken_ctrl_X62_Y5_N1
macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_regs|lcr_sps clken_ctrl_X62_Y6_N1
macro_inst|u_uart[1]|u_tx[4]|uart_txd clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_regs|lcr_stp2 clken_ctrl_X62_Y6_N1
macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_regs|lcr_eps clken_ctrl_X62_Y6_N1
macro_inst|u_uart[1]|u_regs|lcr_pen clken_ctrl_X62_Y6_N1
macro_inst|u_uart[1]|u_tx[4]|tx_parity clken_ctrl_X62_Y6_N0
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] clken_ctrl_X62_Y7_N0
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] clken_ctrl_X62_Y7_N1
macro_inst|u_uart[1]|u_baud|i_cnt[0] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[5] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[6] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[7] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[8] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[9] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[1] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[10] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[11] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[12] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[13] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[14] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[15] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[2] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[3] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_baud|i_cnt[4] clken_ctrl_X62_Y8_N0
macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] clken_ctrl_X62_Y9_N1
macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] clken_ctrl_X62_Y9_N1
macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] clken_ctrl_X62_Y9_N1
macro_inst|u_uart[1]|u_tx[3]|tx_bit clken_ctrl_X62_Y9_N0
macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA clken_ctrl_X62_Y9_N0