| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705 |
- TimeQuest Timing Analyzer report for fpga_boot
- Sat May 09 16:12:21 2026
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. SDC File List
- 5. Clocks
- 6. Slow 1200mV 85C Model Fmax Summary
- 7. Timing Closure Recommendations
- 8. Slow 1200mV 85C Model Setup Summary
- 9. Slow 1200mV 85C Model Hold Summary
- 10. Slow 1200mV 85C Model Recovery Summary
- 11. Slow 1200mV 85C Model Removal Summary
- 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
- 13. Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN'
- 14. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI'
- 15. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE'
- 16. Clock to Output Times
- 17. Minimum Clock to Output Times
- 18. Slow 1200mV 85C Model Metastability Report
- 19. Slow 1200mV 0C Model Fmax Summary
- 20. Slow 1200mV 0C Model Setup Summary
- 21. Slow 1200mV 0C Model Hold Summary
- 22. Slow 1200mV 0C Model Recovery Summary
- 23. Slow 1200mV 0C Model Removal Summary
- 24. Slow 1200mV 0C Model Minimum Pulse Width Summary
- 25. Slow 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN'
- 26. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
- 27. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
- 28. Clock to Output Times
- 29. Minimum Clock to Output Times
- 30. Slow 1200mV 0C Model Metastability Report
- 31. Fast 1200mV 0C Model Setup Summary
- 32. Fast 1200mV 0C Model Hold Summary
- 33. Fast 1200mV 0C Model Recovery Summary
- 34. Fast 1200mV 0C Model Removal Summary
- 35. Fast 1200mV 0C Model Minimum Pulse Width Summary
- 36. Fast 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN'
- 37. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
- 38. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
- 39. Clock to Output Times
- 40. Minimum Clock to Output Times
- 41. Fast 1200mV 0C Model Metastability Report
- 42. Multicorner Timing Analysis Summary
- 43. Clock to Output Times
- 44. Minimum Clock to Output Times
- 45. Board Trace Model Assignments
- 46. Input Transition Times
- 47. Signal Integrity Metrics (Slow 1200mv 0c Model)
- 48. Signal Integrity Metrics (Slow 1200mv 85c Model)
- 49. Signal Integrity Metrics (Fast 1200mv 0c Model)
- 50. Clock Transfers
- 51. Report TCCS
- 52. Report RSKM
- 53. Unconstrained Paths
- 54. TimeQuest Timing Analyzer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------------------------------------+
- ; TimeQuest Timing Analyzer Summary ;
- +--------------------+-----------------------------------------------------+
- ; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Full Version ;
- ; Revision Name ; fpga_boot ;
- ; Device Family ; Cyclone IV E ;
- ; Device Name ; EP4CE75F29C8 ;
- ; Timing Models ; Final ;
- ; Delay Model ; Combined ;
- ; Rise/Fall Delays ; Enabled ;
- +--------------------+-----------------------------------------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 8 ;
- ; Maximum allowed ; 4 ;
- ; ; ;
- ; Average used ; 1.00 ;
- ; Maximum used ; 4 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processors 2-4 ; < 0.1% ;
- ; Processors 5-8 ; 0.0% ;
- +----------------------------+-------------+
- +---------------------------------------------------+
- ; SDC File List ;
- +---------------+--------+--------------------------+
- ; SDC File Path ; Status ; Read at ;
- +---------------+--------+--------------------------+
- ; fpga_boot.sdc ; OK ; Sat May 09 16:12:20 2026 ;
- +---------------+--------+--------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Clocks ;
- +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+
- ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
- +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+
- ; PIN_HSE ; Base ; 125.000 ; 8.0 MHz ; 0.000 ; 62.500 ; ; ; ; ; ; ; ; ; ; ; { PIN_HSE } ;
- ; PIN_HSI ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { PIN_HSI } ;
- ; PLL_CLKIN ; Base ; 125.000 ; 8.0 MHz ; 0.000 ; 62.500 ; ; ; ; ; ; ; ; ; ; ; { PLL_CLKIN } ;
- ; pll_inst|auto_generated|pll1|clk[0] ; Generated ; 9.615 ; 104.0 MHz ; 0.000 ; 4.807 ; 50.00 ; 1 ; 13 ; ; ; ; ; false ; PLL_CLKIN ; pll_inst|auto_generated|pll1|inclk[0] ; { pll_inst|auto_generated|pll1|clk[0] } ;
- +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+
- --------------------------------------
- ; Slow 1200mV 85C Model Fmax Summary ;
- --------------------------------------
- No paths to report.
- ----------------------------------
- ; Timing Closure Recommendations ;
- ----------------------------------
- HTML report is unavailable in plain text report export.
- ---------------------------------------
- ; Slow 1200mV 85C Model Setup Summary ;
- ---------------------------------------
- No paths to report.
- --------------------------------------
- ; Slow 1200mV 85C Model Hold Summary ;
- --------------------------------------
- No paths to report.
- ------------------------------------------
- ; Slow 1200mV 85C Model Recovery Summary ;
- ------------------------------------------
- No paths to report.
- -----------------------------------------
- ; Slow 1200mV 85C Model Removal Summary ;
- -----------------------------------------
- No paths to report.
- +---------------------------------------------------+
- ; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
- +-----------+---------+-----------------------------+
- ; Clock ; Slack ; End Point TNS ;
- +-----------+---------+-----------------------------+
- ; PLL_CLKIN ; 62.371 ; 0.000 ;
- ; PIN_HSI ; 96.000 ; 0.000 ;
- ; PIN_HSE ; 121.000 ; 0.000 ;
- +-----------+---------+-----------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------+
- ; Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN' ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; 62.371 ; 62.371 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 62.371 ; 62.371 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 62.391 ; 62.391 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 62.419 ; 62.419 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 62.580 ; 62.580 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 62.609 ; 62.609 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 62.627 ; 62.627 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 62.627 ; 62.627 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- +-------------------------------------------------------------------------------------+
- ; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI' ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; 96.000 ; 100.000 ; 4.000 ; Port Rate ; PIN_HSI ; Rise ; PIN_HSI ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- +--------------------------------------------------------------------------------------+
- ; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE' ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- +--------------------------------------------------------------------------------------------------------------------------+
- ; Clock to Output Times ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 3.031 ; 3.092 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 3.031 ; 3.092 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.220 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.149 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------+
- ; Minimum Clock to Output Times ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.942 ; 3.005 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.942 ; 3.005 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.286 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.353 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ----------------------------------------------
- ; Slow 1200mV 85C Model Metastability Report ;
- ----------------------------------------------
- No synchronizer chains to report.
- -------------------------------------
- ; Slow 1200mV 0C Model Fmax Summary ;
- -------------------------------------
- No paths to report.
- --------------------------------------
- ; Slow 1200mV 0C Model Setup Summary ;
- --------------------------------------
- No paths to report.
- -------------------------------------
- ; Slow 1200mV 0C Model Hold Summary ;
- -------------------------------------
- No paths to report.
- -----------------------------------------
- ; Slow 1200mV 0C Model Recovery Summary ;
- -----------------------------------------
- No paths to report.
- ----------------------------------------
- ; Slow 1200mV 0C Model Removal Summary ;
- ----------------------------------------
- No paths to report.
- +--------------------------------------------------+
- ; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
- +-----------+---------+----------------------------+
- ; Clock ; Slack ; End Point TNS ;
- +-----------+---------+----------------------------+
- ; PLL_CLKIN ; 62.365 ; 0.000 ;
- ; PIN_HSI ; 96.000 ; 0.000 ;
- ; PIN_HSE ; 121.000 ; 0.000 ;
- +-----------+---------+----------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------+
- ; Slow 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; 62.365 ; 62.365 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 62.365 ; 62.365 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 62.404 ; 62.404 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 62.423 ; 62.423 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 62.576 ; 62.576 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 62.596 ; 62.596 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 62.635 ; 62.635 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 62.635 ; 62.635 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- +-------------------------------------------------------------------------------------+
- ; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; 96.000 ; 100.000 ; 4.000 ; Port Rate ; PIN_HSI ; Rise ; PIN_HSI ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- +--------------------------------------------------------------------------------------+
- ; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- +--------------------------------------------------------------------------------------------------------------------------+
- ; Clock to Output Times ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.775 ; 2.811 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.775 ; 2.811 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.341 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.252 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------+
- ; Minimum Clock to Output Times ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.696 ; 2.734 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.696 ; 2.734 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.103 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.188 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ---------------------------------------------
- ; Slow 1200mV 0C Model Metastability Report ;
- ---------------------------------------------
- No synchronizer chains to report.
- --------------------------------------
- ; Fast 1200mV 0C Model Setup Summary ;
- --------------------------------------
- No paths to report.
- -------------------------------------
- ; Fast 1200mV 0C Model Hold Summary ;
- -------------------------------------
- No paths to report.
- -----------------------------------------
- ; Fast 1200mV 0C Model Recovery Summary ;
- -----------------------------------------
- No paths to report.
- ----------------------------------------
- ; Fast 1200mV 0C Model Removal Summary ;
- ----------------------------------------
- No paths to report.
- +--------------------------------------------------+
- ; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
- +-----------+---------+----------------------------+
- ; Clock ; Slack ; End Point TNS ;
- +-----------+---------+----------------------------+
- ; PLL_CLKIN ; 61.901 ; 0.000 ;
- ; PIN_HSI ; 96.000 ; 0.000 ;
- ; PIN_HSE ; 121.000 ; 0.000 ;
- +-----------+---------+----------------------------+
- +-------------------------------------------------------------------------------------------------------------------------------------+
- ; Fast 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- ; 61.901 ; 61.901 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 61.901 ; 61.901 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 61.948 ; 61.948 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 61.952 ; 61.952 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ;
- ; 63.048 ; 63.048 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ;
- ; 63.052 ; 63.052 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ;
- ; 63.095 ; 63.095 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; 63.095 ; 63.095 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ;
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ;
- +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
- +-------------------------------------------------------------------------------------+
- ; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- ; 96.000 ; 100.000 ; 4.000 ; Port Rate ; PIN_HSI ; Rise ; PIN_HSI ;
- +--------+--------------+----------------+-----------+---------+------------+---------+
- +--------------------------------------------------------------------------------------+
- ; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ;
- +---------+--------------+----------------+-----------+---------+------------+---------+
- +----------------------------------------------------------------------------------------------------------------------------+
- ; Clock to Output Times ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.374 ; 1.940 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.374 ; 1.940 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.056 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.033 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------+
- ; Minimum Clock to Output Times ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.330 ; 1.896 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.330 ; 1.896 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.303 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.281 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ---------------------------------------------
- ; Fast 1200mV 0C Model Metastability Report ;
- ---------------------------------------------
- No synchronizer chains to report.
- +----------------------------------------------------------------------------+
- ; Multicorner Timing Analysis Summary ;
- +------------------+-------+------+----------+---------+---------------------+
- ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
- +------------------+-------+------+----------+---------+---------------------+
- ; Worst-case Slack ; N/A ; N/A ; N/A ; N/A ; 61.901 ;
- ; PIN_HSE ; N/A ; N/A ; N/A ; N/A ; 121.000 ;
- ; PIN_HSI ; N/A ; N/A ; N/A ; N/A ; 96.000 ;
- ; PLL_CLKIN ; N/A ; N/A ; N/A ; N/A ; 61.901 ;
- ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ;
- ; PIN_HSE ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
- ; PIN_HSI ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
- ; PLL_CLKIN ; N/A ; N/A ; N/A ; N/A ; 0.000 ;
- +------------------+-------+------+----------+---------+---------------------+
- +--------------------------------------------------------------------------------------------------------------------------+
- ; Clock to Output Times ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 3.031 ; 3.092 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 3.031 ; 3.092 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.341 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.252 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+-------+-------+------------+-------------------------------------+
- +----------------------------------------------------------------------------------------------------------------------------+
- ; Minimum Clock to Output Times ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.330 ; 1.896 ; Rise ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.330 ; 1.896 ; Fall ; PIN_HSI ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.303 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ;
- ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.353 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ;
- +------------------------------------------+------------+--------+--------+------------+-------------------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Board Trace Model Assignments ;
- +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
- ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
- +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
- ; SPI0_CSN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; SPI0_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; BAUD_RATE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; GPIO4_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; GPIO4_2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; TEST_SINGLE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; UART1_RX ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; UART1_TX ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; so_io1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
- +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
- +----------------------------------------------------------------------------+
- ; Input Transition Times ;
- +-------------------------+--------------+-----------------+-----------------+
- ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
- +-------------------------+--------------+-----------------+-----------------+
- ; PIN_HSE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; BAUD_RATE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; GPIO4_1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; GPIO4_2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; TEST_SINGLE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; UART1_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; UART1_TX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; so_io1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; UART0_UARTRXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; PIN_HSI ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; PLL_CLKIN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- ; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ;
- +-------------------------+--------------+-----------------+-----------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Signal Integrity Metrics (Slow 1200mv 0c Model) ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ;
- ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ;
- ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.38e-09 V ; 3.13 V ; -0.117 V ; 0.15 V ; 0.263 V ; 6.31e-10 s ; 4.46e-10 s ; No ; No ; 3.08 V ; 6.38e-09 V ; 3.13 V ; -0.117 V ; 0.15 V ; 0.263 V ; 6.31e-10 s ; 4.46e-10 s ; No ; No ;
- ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ;
- ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ;
- ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Signal Integrity Metrics (Slow 1200mv 85c Model) ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ;
- ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ;
- ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0624 V ; 0.233 V ; 0.172 V ; 6.86e-10 s ; 6.33e-10 s ; Yes ; No ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0624 V ; 0.233 V ; 0.172 V ; 6.86e-10 s ; 6.33e-10 s ; Yes ; No ;
- ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ;
- ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ;
- ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Signal Integrity Metrics (Fast 1200mv 0c Model) ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ;
- ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ;
- ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.6 V ; -0.127 V ; 0.302 V ; 0.21 V ; 4.55e-10 s ; 4.11e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.6 V ; -0.127 V ; 0.302 V ; 0.21 V ; 4.55e-10 s ; 4.11e-10 s ; No ; No ;
- ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ;
- ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ;
- ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ;
- +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
- -------------------
- ; Clock Transfers ;
- -------------------
- Nothing to report.
- ---------------
- ; Report TCCS ;
- ---------------
- No dedicated SERDES Transmitter circuitry present in device or used in design
- ---------------
- ; Report RSKM ;
- ---------------
- No dedicated SERDES Receiver circuitry present in device or used in design
- +------------------------------------------------+
- ; Unconstrained Paths ;
- +---------------------------------+-------+------+
- ; Property ; Setup ; Hold ;
- +---------------------------------+-------+------+
- ; Illegal Clocks ; 0 ; 0 ;
- ; Unconstrained Clocks ; 0 ; 0 ;
- ; Unconstrained Input Ports ; 1 ; 1 ;
- ; Unconstrained Input Port Paths ; 1 ; 1 ;
- ; Unconstrained Output Ports ; 1 ; 1 ;
- ; Unconstrained Output Port Paths ; 3 ; 3 ;
- +---------------------------------+-------+------+
- +------------------------------------+
- ; TimeQuest Timing Analyzer Messages ;
- +------------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Sat May 09 16:12:19 2026
- Info: Command: quartus_sta fpga_boot -c fpga_boot
- Info: qsta_default_script.tcl version: #1
- Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
- Info (21077): Low junction temperature is 0 degrees C
- Info (21077): High junction temperature is 85 degrees C
- Info (332104): Reading SDC File: 'fpga_boot.sdc'
- Info (332110): Deriving PLL clocks
- Info (332110): create_clock -period 125.000 -waveform {0.000 62.500} -name PLL_CLKIN PLL_CLKIN
- Info (332110): create_generated_clock -source {pll_inst|auto_generated|pll1|inclk[0]} -multiply_by 13 -duty_cycle 50.00 -name {pll_inst|auto_generated|pll1|clk[0]} {pll_inst|auto_generated|pll1|clk[0]}
- Warning (332174): Ignored filter at fpga_boot.sdc(13): rv32|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition
- Warning (332049): Ignored set_false_path at fpga_boot.sdc(13): Argument <from> is not an object ID
- Info (332050): set_false_path -from rv32|resetn_out
- Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
- Info: Analyzing Slow 1200mV 85C Model
- Info (332140): No fmax paths to report
- Info (332140): No Setup paths to report
- Info (332140): No Hold paths to report
- Info (332140): No Recovery paths to report
- Info (332140): No Removal paths to report
- Info (332146): Worst-case minimum pulse width slack is 62.371
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= ============= =====================
- Info (332119): 62.371 0.000 PLL_CLKIN
- Info (332119): 96.000 0.000 PIN_HSI
- Info (332119): 121.000 0.000 PIN_HSE
- Info: Analyzing Slow 1200mV 0C Model
- Info (334003): Started post-fitting delay annotation
- Info (334004): Delay annotation completed successfully
- Info (332140): No fmax paths to report
- Info (332140): No Setup paths to report
- Info (332140): No Hold paths to report
- Info (332140): No Recovery paths to report
- Info (332140): No Removal paths to report
- Info (332146): Worst-case minimum pulse width slack is 62.365
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= ============= =====================
- Info (332119): 62.365 0.000 PLL_CLKIN
- Info (332119): 96.000 0.000 PIN_HSI
- Info (332119): 121.000 0.000 PIN_HSE
- Info: Analyzing Fast 1200mV 0C Model
- Info (332140): No Setup paths to report
- Info (332140): No Hold paths to report
- Info (332140): No Recovery paths to report
- Info (332140): No Removal paths to report
- Info (332146): Worst-case minimum pulse width slack is 61.901
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= ============= =====================
- Info (332119): 61.901 0.000 PLL_CLKIN
- Info (332119): 96.000 0.000 PIN_HSI
- Info (332119): 121.000 0.000 PIN_HSE
- Info (332102): Design is not fully constrained for setup requirements
- Info (332102): Design is not fully constrained for hold requirements
- Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 4694 megabytes
- Info: Processing ended: Sat May 09 16:12:21 2026
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
|
