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- Flow report for fpga_boot
- Sat May 09 16:12:23 2026
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +----------------------------------------------------------------------------------+
- ; Flow Summary ;
- +------------------------------------+---------------------------------------------+
- ; Flow Status ; Successful - Sat May 09 16:12:23 2026 ;
- ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
- ; Revision Name ; fpga_boot ;
- ; Top-level Entity Name ; fpga_boot ;
- ; Family ; Cyclone IV E ;
- ; Device ; EP4CE75F29C8 ;
- ; Timing Models ; Final ;
- ; Total logic elements ; 44 / 75,408 ( < 1 % ) ;
- ; Total combinational functions ; 44 / 75,408 ( < 1 % ) ;
- ; Dedicated logic registers ; 1 / 75,408 ( < 1 % ) ;
- ; Total registers ; 1 ;
- ; Total pins ; 15 / 427 ( 4 % ) ;
- ; Total virtual pins ; 1 ;
- ; Total memory bits ; 0 / 2,810,880 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 400 ( 0 % ) ;
- ; Total PLLs ; 1 / 4 ( 25 % ) ;
- +------------------------------------+---------------------------------------------+
- +-----------------------------------------+
- ; Flow Settings ;
- +-------------------+---------------------+
- ; Option ; Setting ;
- +-------------------+---------------------+
- ; Start date & time ; 05/09/2026 16:11:46 ;
- ; Main task ; Compilation ;
- ; Revision Name ; fpga_boot ;
- +-------------------+---------------------+
- +------------------------------------------------------------------------------------------------------------------------------------+
- ; Flow Non-Default Global Settings ;
- +--------------------------------------------+---------------------------------------+----------------+-------------+----------------+
- ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
- +--------------------------------------------+---------------------------------------+----------------+-------------+----------------+
- ; ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ; On ; Off ; -- ; -- ;
- ; AUTO_OPEN_DRAIN_PINS ; Off ; On ; -- ; -- ;
- ; COMPILER_SIGNATURE_ID ; 145862330523166.177831430636004 ; -- ; -- ; -- ;
- ; ECO_OPTIMIZE_TIMING ; On ; Off ; -- ; -- ;
- ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
- ; EDA_SIMULATION_TOOL ; ModelSim (Verilog) ; <None> ; -- ; -- ;
- ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
- ; FINAL_PLACEMENT_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
- ; FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ; Always ; Automatically ; -- ; -- ;
- ; FITTER_EFFORT ; Standard Fit ; Auto Fit ; -- ; -- ;
- ; FLOW_DISABLE_ASSEMBLER ; On ; Off ; -- ; -- ;
- ; FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ; On ; Off ; -- ; -- ;
- ; MAX_BALANCING_DSP_BLOCKS ; 0 ; -1 (Unlimited) ; -- ; -- ;
- ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
- ; MAX_GLOBAL_CLOCKS_ALLOWED ; 6 ; -1 (Unlimited) ; -- ; -- ;
- ; MAX_RAM_BLOCKS_M4K ; 4 ; -1 (Unlimited) ; -- ; -- ;
- ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
- ; NUM_PARALLEL_PROCESSORS ; All ; -- ; -- ; -- ;
- ; OPTIMIZE_HOLD_TIMING ; IO Paths and Minimum TPD Paths ; All Paths ; -- ; -- ;
- ; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
- ; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ;
- ; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
- ; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;
- ; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;
- ; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
- ; PLACEMENT_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ;
- ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
- ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
- ; PROJECT_OUTPUT_DIRECTORY ; ./quartus_logs ; -- ; -- ; -- ;
- ; ROUTER_EFFORT_MULTIPLIER ; 10 ; 1.0 ; -- ; -- ;
- ; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
- ; ROUTING_BACK_ANNOTATION_MODE ; Off ; -- ; -- ; -- ;
- ; SEARCH_PATH ; boot_ip ; -- ; -- ; -- ;
- +--------------------------------------------+---------------------------------------+----------------+-------------+----------------+
- +-------------------------------------------------------------------------------------------------------------------------------+
- ; Flow Elapsed Time ;
- +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
- ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
- +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
- ; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 4718 MB ; 00:00:02 ;
- ; Analysis & Synthesis ; 00:00:04 ; 1.8 ; 4624 MB ; 00:00:05 ;
- ; Partition Merge ; 00:00:01 ; 1.0 ; 4633 MB ; 00:00:01 ;
- ; I/O Assignment Analysis ; 00:00:04 ; 1.0 ; 4890 MB ; 00:00:03 ;
- ; Fitter ; 00:00:18 ; 2.4 ; 5437 MB ; 00:00:22 ;
- ; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 4694 MB ; 00:00:02 ;
- ; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 4539 MB ; 00:00:01 ;
- ; Total ; 00:00:32 ; -- ; -- ; 00:00:36 ;
- +---------------------------+--------------+-------------------------+---------------------+------------------------------------+
- +----------------------------------------------------------------------------------------+
- ; Flow OS Summary ;
- +---------------------------+------------------+-----------+------------+----------------+
- ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
- +---------------------------+------------------+-----------+------------+----------------+
- ; Analysis & Synthesis ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; Analysis & Synthesis ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; Partition Merge ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; I/O Assignment Analysis ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; Fitter ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; TimeQuest Timing Analyzer ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- ; EDA Netlist Writer ; DESKTOP-CBFDJ0B ; Windows 7 ; 6.2 ; x86_64 ;
- +---------------------------+------------------+-----------+------------+----------------+
- ------------
- ; Flow Log ;
- ------------
- quartus_map --read_settings_files=on --write_settings_files=off fpga_boot -c fpga_boot
- quartus_map --read_settings_files=on --write_settings_files=off fpga_boot -c fpga_boot
- quartus_cdb --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot --merge=on
- quartus_fit --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot --check_ios
- quartus_fit --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot
- quartus_sta fpga_boot -c fpga_boot
- quartus_eda --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot
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