9102_BOOT/logic/alta_logs/run.log

> alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
Cmd : C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/bin/af.exe 2025.06.b0(3f05be1c)
> alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
Args : -X "set QUARTUS_SDC true" -X "set FITTING Auto" -X "set FITTER full" -X "set EFFORT high" -X "set HOLDX default" -X "set SKEW   basic" -X "set MODE QUARTUS" -X "set FLOW ALL" -F ./af_run.tcl
> 
> set_seed_rand $SEED
> set ar_timing_derate ${TIMING_DERATE}
> 
> date_time
Sat May 09 16:12:48 2026
> if { [file exists [file join . ${DESIGN}.pre.asf]] } {
  alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
  source [file join . ${DESIGN}.pre.asf]
}
Using pre-ASF file fpga_boot.pre.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> set BOARD_PLL_CLKIN PIN_OSC
> set db_io_name_priority False
> set ip_pll_vco_lowpower true
> set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "ON"
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> 
> set LOAD_DB    false
> set LOAD_PLACE false
> set LOAD_ROUTE false
> set LOAD_PACK false
> if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
  set LOAD_ROUTE true
} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
} elseif { $FLOW == "PR" || $FLOW == "PLACE_AND_ROUTE" } {
  set LOAD_DB    false
  set LOAD_PACK  true
}
> 
> set ORIGINAL_QSF "./fpga_boot.qsf"
> set ORIGINAL_PIN ""
> 
> #################################################################################
> 
> # The default SDC file is ${DESIGN}.sdc 
> set sdc_file $SDC_FILE
> if { $sdc_file == "" } {
  set sdc_file [file join . ${DESIGN}.adc]
  if { ! [file exists $sdc_file] } { set sdc_file [file join . ${DESIGN}.sdc]; }
}
> # No default VE file is not specified
> set ve_file $VEX_FILE
> 
> while (1) {

if { $FLOW == "SKIP" } { break }

if { [info exists CORNER] } { set_mode -corner $CORNER; }

eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
foreach ip_file $IP_FILES { read_ip $ip_file; }


if { $FLOW == "GEN" } {
  if { ! [info exists CONFIG_BITS] } {
    set CONFIG_BITS [file join ${RESULT_DIR} ${DESIGN}.bin]
  }
  if { [llength $CONFIG_BITS] > 1 } {
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY [file join ${RESULT_DIR} ${DESIGN}_boot.bin]
    }
    if { ! [info exists CONFIG_ADDRESSES] } {
      set CONFIG_ADDRESSES ""
    }
    generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
  } else {
    set CONFIG_ROOT   [file rootname [lindex $CONFIG_BITS 0]]
    set SLAVE_RBF     "${CONFIG_ROOT}_slave.rbf"
    set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
    if { [file exists [lindex $CONFIG_BITS 0]] } {
      generate_binary -slave  $SLAVE_RBF     -inputs [lindex $CONFIG_BITS 0] -reverse
      generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
    }
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY $MASTER_BINARY
    }
  }
  set PRG_FILE [file rootname $BOOT_BINARY].prg
  set AS_FILE  [file rootname $BOOT_BINARY]_as.prg
  generate_programming_file $BOOT_BINARY -erase $ERASE \
                            -program $PROGRAM -verify $VERIFY -offset $OFFSET \
                            -prg $PRG_FILE -as $AS_FILE
  break
}

if { $LOAD_DB } {
  load_db -top ${TOP_MODULE}
  if { [file exists $sdc_file] } { read_sdc $sdc_file; }

} elseif { $MODE == "QUARTUS" } {
  set verilog ${DESIGN}.vo
  set is_migrated false
  if { ! [file exists $verilog] } {
    set verilog [file join . simulation modelsim ${DESIGN}.vo]
    set is_migrated true
  }
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }
  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $ve_file != "" && ! [file exists $ve_file] } {
    alta::tcl_warn "Can not find design VE file $ve_file"
    set ve_file ""
  } else {
    alta::tcl_highlight "Using design VE file $ve_file.\n"
  }
  set ret [read_design -top ${TOP_MODULE} -ve $ve_file -qsf $ORIGINAL_QSF $verilog -hierachy 1]
  if { !$ret } { exit -1; }

  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    alta::tcl_highlight "Using design SDC file $sdc_file.\n"
    read_sdc $sdc_file
  }

} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
  set_hierarchy_separator .
  set db_gclk_assignment_level 2
  set verilog ${DESIGN}.vqm
  set is_migrated false
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }

  if { $VEX_FILE != "" } {
    if { $VEX_FILE == "-" } {
      set VEX_FILE ""
    } elseif { ! [file exists $VEX_FILE] } {
      error "Can not find design VE file $VEX_FILE"
    }
  }
  if { $AGF_FILE != "" } {
    if { $AGF_FILE == "-" } {
      set AGF_FILE ""
    } elseif { ! [file exists $AGF_FILE] } {
      error "Can not find design AGF file $AGF_FILE"
    }
  }

  set alta0_asf [file join $::alta_work alta0.asf]
  set alta0_apf [file join $::alta_work alta0.apf]
  file delete -force $alta0_asf
  file delete -force $alta0_apf
  if { $AGF_FILE != "" || $VEX_FILE != "" } {
    alta::convert_pio_settings_cmd $VEX_FILE $AGF_FILE $alta0_asf $alta0_apf
  }

  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    alta::tcl_highlight "Using design SDC file $sdc_file.\n"
  }
  set load_pack ""
  if { $LOAD_PACK  } { set load_pack  "-load_pack"; }
  set ret [eval "read_design_and_pack $load_pack -sdc {$sdc_file} -top ${TOP_MODULE} -type vqm -gclk_level 2 $verilog"]

  set FITTER "full"
  if { !$ret } { exit -1; }

} else {
  error "Unsupported mode $MODE"
}

if { $FLOW == "PACK" } { break }

if { [info exists FITTING] } {
  if { $FITTING == "Auto" } { set FITTING auto; }
  set_mode -fitting $FITTING
}
if { [info exists FITTER] } {
  if { $FITTER == "Auto" } {
    if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; }
  }
  if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; }
  set_mode -fitter $FITTER
}
if { [info exists EFFORT] } { set_mode -effort $EFFORT; }
if { [info exists SKEW  ] } { set_mode -skew   $SKEW  ; }
if { [info exists SKOPE ] } { set_mode -skope  $SKOPE ; }
if { [info exists HOLDX ] } { set_mode -holdx  $HOLDX; }
if { [info exists TUNING] } { set_mode -tuning $TUNING; }
if { [info exists TARGET] } { set_mode -target $TARGET; }
if { [info exists PRESET] } { set_mode -preset $PRESET; }
if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; }

set alta_aqf [file join $::alta_work alta.aqf]
if { $LOAD_DB } {
  # Empty
} else {
  file delete -force $alta_aqf
  if { true } {
    if { $ORIGINAL_PIN != "" } {
      if { [file exists $VE_FILE] } {
        set ORIGINAL_PIN ""
      } elseif { $ORIGINAL_PIN == "-" } {
        set ORIGINAL_PIN ""
      } elseif { ! [file exists $ORIGINAL_PIN] } {
        if { $is_migrated } {
          error "Can not find design PIN file $ORIGINAL_PIN, please compile design first"
        }
        set ORIGINAL_PIN ""
      }
    }
    if { $ORIGINAL_QSF != "" } {
      if { $ORIGINAL_QSF == "-" } {
        set ORIGINAL_QSF ""
      } elseif { ! [file exists $ORIGINAL_QSF] } {
        if { $is_migrated } {
          error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first"
        }
      }
    }
    if { $ORIGINAL_QSF != "" || $ORIGINAL_PIN != "" } {
      alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf
    }
  }
}
if { [file exists "$alta_aqf"] } {
  alta::tcl_highlight "Using AQF file $alta_aqf.\n"
  source "$alta_aqf"
}
if { [file exists [file join . ${DESIGN}.asf]] } {
  alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n"
  source [file join . ${DESIGN}.asf]
}

if { $FLOW == "PROBE" } {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk"]
  if { !$ret } { exit -1 }

  set force ""
  if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" }
  eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}"

} elseif { $FLOW == "CHECK" } {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk"]
  if { !$ret } { exit -1 }

  if { [file exists [file join . ${DESIGN}.chk]] } {
    alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n"
    source [file join . ${DESIGN}.chk]
    place_design -dry
    check_design -rule led_guide
  } else {
    error "Can not find design CHECK file ${DESIGN}.chk"
  }

} else {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk -warn_io"]
  if { !$ret } { exit -1 }

  set org_place ""
  set load_place ""
  set load_route ""
  set quiet ""
  if {  $ORG_PLACE } { set  org_place "-org_place" ; }
  if { $LOAD_PLACE } { set load_place "-load_place"; }
  if { $LOAD_ROUTE } { set load_route "-load_route"; }
  eval "place_and_route_design $org_place $load_place $load_route \
                               -retry $RETRY $seed_rand $quiet"
}

date_time
if { $FLOW != "CHECK" } {
if { $FLOW != "PROBE" } {
report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
report_timing -verbose 1 -setup -file $::alta_work/setup_summary.rpt
report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
report_timing -verbose 1 -hold -file $::alta_work/hold_summary.rpt

set ta_report_auto_constraints 0
report_timing -fmax -file $::alta_work/fmax.rpt
report_timing -xfer -file $::alta_work/xfer.rpt
set ta_report_auto_constraints $ta_report_auto

set ta_dump_uncovered 1
report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
set ta_dump_uncovered -1


if { ! [info exists rt_report_timing_fast] } {
  set rt_report_timing_fast false
}
if { $rt_report_timing_fast } {
  set_timing_corner fast
  route_delay -quiet
  report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz
  report_timing -verbose 1 -setup -file $::alta_work/setup_fast_summary.rpt
  report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz
  report_timing -verbose 1 -hold -file $::alta_work/hold_fast_summary.rpt
  set ta_report_auto_constraints 0
  report_timing -fmax -file $::alta_work/fmax_fast.rpt
  report_timing -xfer -file $::alta_work/xfer_fast.rpt
  set ta_report_auto_constraints $ta_report_auto
}

write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
}

bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
if { true } {
alta::bin_to_asc "${RESULT_DIR}/${RESULT}.bin" "${RESULT_DIR}/${RESULT}.inc"
set python_exe [expr {$tcl_platform(platform) eq "unix" ? "python3" : "python.exe"}]
if { ! [ info exist BATCH_ARG ] } {
  set BATCH_ARG ""
}
set LOGIC_COMPRESS [alta::get_global_assignment_cmd ON_CHIP_BITSTREAM_DECOMPRESSION false]
if { [string toupper $LOGIC_COMPRESS] != "OFF" } {
  set BATCH_ARG "$BATCH_ARG --logic-compress"
}
set BATCH_MCU 0xbff5105000730062aa234371030002b7
if { [info exists BATCH_HSE] } {
  set BATCH_MCU 0xbff5105000730062a62343110062aa234371030002b7
}
set GEN_BATCH "{[alta::prog_home]/python_dist/$python_exe} {[alta::prog_home]/pio/gen_batch}\
  -d [[alta::get_device_info_cmd $DEVICE] device_id]\
  -i $BATCH_MCU\
  -o ${RESULT_DIR}/${RESULT}_batch.bin\
  --logic-config ${RESULT_DIR}/${RESULT}.bin\
  --logic-address 0x80007000\
  $BATCH_ARG"
alta::tcl_highlight "Generating batch file: $GEN_BATCH\n"
eval "exec $GEN_BATCH"
} else {
bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
                -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
                -inputs "${RESULT_DIR}/${RESULT}.bin"
generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
  -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"
}
}
break
}
Total IO  : 150
Total Pin : 128/17
Top array is built.
Loading architect libraries...
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 52MB (52MB)
Loading route table...
## CPU time: 0:0:2, REAL time: 0:0:2
## Memory Usage: 317MB (317MB)
Using design verilog file ./simulation/modelsim/fpga_boot.vo.
Using design VE file fpga_boot.vex.
Preparing design...
Info: Rename duplicated module cell alta_rv32 to alta_rv32_duplicated at ./alta_db/flatten.vx:1.
Info: Removing bbox feeder slice gpio0_io_in[0] driving BBOX rv32|gpio0_io_in[0].
Info: Removing bbox feeder slice gpio0_io_out_data[0] driven by BBOX rv32|gpio0_io_out_data[0].
Info: Removing bbox feeder slice gpio0_io_out_en[0] driven by BBOX rv32|gpio0_io_out_en[0].
Info: Removing bbox feeder slice gpio4_io_in[1] driving BBOX rv32|gpio4_io_in[1].
Info: Removing bbox feeder slice gpio4_io_in[2] driving BBOX rv32|gpio4_io_in[2].
Info: Removing bbox feeder slice gpio4_io_out_data[1] driven by BBOX rv32|gpio4_io_out_data[1].
Info: Removing bbox feeder slice gpio4_io_out_data[2] driven by BBOX rv32|gpio4_io_out_data[2].
Info: Removing bbox feeder slice gpio4_io_out_data[5] driven by BBOX rv32|gpio4_io_out_data[5].
Info: Removing bbox feeder slice gpio4_io_out_data[6] driven by BBOX rv32|gpio4_io_out_data[6].
Info: Removing bbox feeder slice gpio4_io_out_en[1] driven by BBOX rv32|gpio4_io_out_en[1].
Info: Removing bbox feeder slice gpio4_io_out_en[2] driven by BBOX rv32|gpio4_io_out_en[2].
Info: Removing bbox feeder slice gpio4_io_out_en[5] driven by BBOX rv32|gpio4_io_out_en[5].
Info: Removing bbox feeder slice gpio4_io_out_en[6] driven by BBOX rv32|gpio4_io_out_en[6].
Info: Removing bbox feeder slice gpio6_io_in[1] driving BBOX rv32|gpio6_io_in[1].
Info: Removing bbox feeder slice gpio7_io_out_data[6] driven by BBOX rv32|gpio7_io_out_data[6].
Info: Removing bbox feeder slice gpio7_io_out_en[6] driven by BBOX rv32|gpio7_io_out_en[6].
Info: Removing bbox feeder slice sys_ctrl_clkSource[0] driven by BBOX rv32|sys_ctrl_clkSource[0].
Info: Removing bbox feeder slice sys_ctrl_clkSource[1] driven by BBOX rv32|sys_ctrl_clkSource[1].
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 336MB (336MB)
Pseudo pack design...
Using location file fpga_boot.vex
VCO frequency: 416.000 Mhz
  clkout0: Enabled , 104.000 Mhz
  clkout1: Disabled, 0.812 Mhz
  clkout2: Disabled, 0.812 Mhz
  clkout3: Disabled, 0.812 Mhz
  clkout4: Disabled, 0.812 Mhz
Info: Instance gclksw_inst|gclk_switch is identified as a clock switch.
Packing Statistics
 Total      Logics : 25/2112 (  1%)
 Total        LUTs : 25/2112 (  1%)
 Total   Registers :  1/2112 (  0%)
 Total  Block Rams :  0/   4 (  0%)
 Total        PLLs :  1/   1 (100%)
 Total        Pins : 15/ 128 ( 11%)
 Global    Signals :  2/   5 ( 40%)
                           PLL_ENABLE~clkctrl_outclk (from:                               PLL_ENABLE~combout)
      auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp (from:   auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp)
 Total Lonely   Datain   : 1
 Total Lonely   Register : 0
 Total LUT-FF   Pairs    : 0
 Total Register Packings : 0
 Registers with synchronous    reset : 0
 Registers with asynchronous   reset : 1
 Registers with sync and async reset : 0
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 334MB (336MB)
Filter verilog...
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 334MB (336MB)
Reading DB design...
## CPU time: 0:0:0, REAL time: 0:0:1
## Memory Usage: 334MB (336MB)
Processing design...
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to TEST_SINGLE~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to BAUD_RATE~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SPI0_SCK~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO4_1~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SPI0_CSN~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO4_2~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to UART0_UARTTXD~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SPI0_SI_IO0~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to so_io1~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to UART1_TX~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to UART1_RX~output false
> set_instance_assignment -extension -name CLKIN_FREQ -to pll_inst|auto_generated|pll1 8
> set_instance_assignment -extension -name FIXED_COORD -to gclksw_inst|gclk_switch__alta_gclksw {22 4 0}
> set_instance_assignment -extension -name FIXED_COORD -to gclksw_inst|gclk_switch {22 4 5}
> set_location_assignment -to BAUD_RATE PIN_18
> set_location_assignment -to GPIO4_1 PIN_29
> set_location_assignment -to GPIO4_2 PIN_10
> set_location_assignment -to PIN_HSE PIN_HSE
> set_location_assignment -to PIN_HSI PIN_HSI
> set_location_assignment -to PLL_CLKIN PIN_OSC
> set_location_assignment -to SPI0_CSN PIN_3
> set_location_assignment -to SPI0_SCK PIN_2
> set_location_assignment -to SPI0_SI_IO0 PIN_31
> set_location_assignment -to TEST_SINGLE PIN_13
> set_location_assignment -to UART0_UARTRXD PIN_21
> set_location_assignment -to UART0_UARTTXD PIN_20
> set_location_assignment -to UART1_RX PIN_9
> set_location_assignment -to UART1_TX PIN_8
> set_location_assignment -to so_io1 PIN_1
Info: Found GCLK net auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp (1).
Info: Found GCLK net PLL_ENABLE~clkctrl_outclk (1).
Info: Fixing net rv32.resetn_out, from rv32|resetn_out to gclksw_inst|gclk_switch__alta_gclksw|resetn.
Info: Fixing net PIN_HSE~input_o, from PIN_HSE~input|combout to gclksw_inst|gclk_switch__alta_gclksw|clkin1.
Info: Fixing net gclksw_inst|gclk_switch__alta_gclksw__clkout, from gclksw_inst|gclk_switch__alta_gclksw|clkout to rv32|sys_clk.
Info: Fixing net auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp, from pll_inst|auto_generated|pll1|lock to rv32|sys_ctrl_pllReady.
Info: Slice gpio4_io_in[5] is removed.
Info: Slice gpio4_io_in[0] is removed.
Info: Slice gpio0_io_in[4] is removed.
Info: Slice ~VCC is removed.
Info: Slice gpio0_io_in[7] is removed.
Info: Slice gpio0_io_in[5] is removed.
Info: Slice gpio0_io_in[6] is removed.
Info: Slice gpio0_io_in[3] is removed.
Info: Slice gpio0_io_in[1] is removed.
Info: Slice gpio0_io_in[2] is removed.
Info: Slice gpio6_io_in[2] is removed.
Info: Slice gpio6_io_in[6] is removed.
Info: Slice gpio6_io_in[7] is removed.
Info: Slice gpio6_io_in[3] is removed.
Info: Slice gpio6_io_in[4] is removed.
Info: Slice gpio4_io_in[3] is removed.
Info: Slice gpio6_io_in[5] is removed.
Info: Slice gpio4_io_in[7] is removed.
Info: Slice gpio4_io_in[6] is removed.
Info: Slice gpio6_io_in[0] is removed.
Info: Slice gpio4_io_in[4] is removed.
Info: Slice ~GND is removed.
Info: The input of IO BAUD_RATE is disabled since all input pins are unused.
Info: The input of IO TEST_SINGLE is disabled since all input pins are unused.
Info: The input of IO UART1_RX is disabled since all input pins are unused.
Info: The input of IO UART1_TX is disabled since all input pins are unused.
Info: The input of IO so_io1 is disabled since all input pins are unused.
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 335MB (336MB)
Using design SDC file ./fpga_boot.sdc.
# pio_begin
if { ! [info exists ::HSI_PERIOD] } {
  set ::HSI_PERIOD 100.0
}
create_clock -name PIN_HSI -period $::HSI_PERIOD [get_ports PIN_HSI]
set_clock_groups -asynchronous -group PIN_HSI
if { ! [info exists ::HSE_PERIOD] } {
  set ::HSE_PERIOD 125.0
}
create_clock -name PIN_HSE -period $::HSE_PERIOD [get_ports PIN_HSE]
set_clock_groups -asynchronous -group PIN_HSE
derive_pll_clocks -create_base_clocks
Info: Auto constraint PLL: create_clock -name PLL_CLKIN -period 125.000 PLL_CLKIN.
Info: Auto constraint PLL: create_generated_clock -name pll_inst|auto_generated|pll1|clk[0] -multiply_by 13 -add -source PLL_CLKIN -master_clock PLL_CLKIN pll_inst|auto_generated|pll1|clkout0.
set_false_path -from rv32|resetn_out
# pio_end
##

derive_pll_clocks -create_base_clocks
>  set pl_criticality_wratio  "2.50 2.50 2.50 1.00"
> #set pl_max_iter_eco        "10 20 300 40 3  100 100 1"
> ##et pl_eco_slack_crit      "99999. 1.00  0.10 7 0.03 30 0.01 150"
> 
> ##et pl_priority_compare  "2 2 2 3"
> #set pl_priority_result   "2 1 1 0"
> #set pl_priority_pass     "2 1 1 0"
> #set pl_swap_cost_margin       "200.0  0.0  200.0  0.0  200.0  0.0   0.00  0.0"
>  set pl_swap_wirelength_margin "200.0  0.0  200.0  0.0  200.0  0.0   020.0 -0.3  2000. 1.50"
>  set pl_swap_congestion_margin "100.0  0.0  100.0  0.0  100.0  0.0   010.0 -0.3  1000. 1.25"
> #set pl_criticality_beta "1.0 3.0 1.0  1.0 3.0 1.0  1.0 3.0 1.0  99999 3.0 3.0"
> #set pl_oci_iter "1 1 100 1"
> 
>  set rt_retiming_idx         5
>  set rt_converge_accelerator "2 1 0 3"
> #set rt_pres_cost_ratio      "1.00 1.50  2.00 2.50"
>  set rt_dly_ratio            "0.55 0.35 0.30  0.50 0.50 0.30"
>  set rt_reroute_max_iter     "6  5 6  7 9  12"
>  set rt_reroute_start_iter   "0  1 2  2 4  0 "
>  set rt_quick_converge_ratio 0.25
>  set pl_reuse_existing_placement false
>  set pl_fix_bram_cells 0
>  set pl_fix_mult_cells 0
>  set pl_neighbor_swap_range "3  6  6  3 "
>  set pl_pass_result "1 1 1 1"
>  set pl_max_pass    "1 1 1 1 1"
>  set pl_max_iter       10
>  set pl_max_iter_part  20
>  set pl_max_iter_final 20
>  set pl_max_iter_legal 10
>  set pl_max_iter_touch 00
> #set pl_neighbor_swap_range "2  6  6  3 "
> #set pl_spread_swap_max_iter "3 5  5 4"
> #set pl_use_initial_place_once 0
>  set rt_min_converge "5"
>  set rt_optimize_max "3"
>  set pl_useful_skew_level -1
>  set rt_useful_skew_level 0
>  set rt_useful_skew_bram         true
>  set rt_useful_skew_io           false
>  set rt_useful_skew_io_ireg      false
>  set rt_useful_skew_io_oreg      false
>  set rt_useful_skew_output_io    false
>  set rt_useful_skew_input_io     false
>  set rt_useful_skew_unconstraint "false false"
>  set rt_useful_skew_max                "0 100"
>  set rt_skew_crit_minmax               "0.00 1.00"
> #set rt_useful_skew_setup_slac_margin  "1.00 1.00  1.00 1.00  1.00 0.10 0.50 0.10 0.70 0.10  1.00"
> #set rt_useful_skew_hold_slack_margin  "0.10 0.10  0.30 0.30  0.30 0.30"
> #set rt_useful_skew_hold_slack_ratio   "0.05 0.05  0.10 0.10  0.10 0.10"
> # Minimal logical slice hold fix, only by routing to bram/mult, no IO delay
> 
>  set ta_cross_clock_slack "2 0"
> 
> #set pl_max_iter_hold_fix "30 1 3"
> #set pl_hold_slack_margin  0.2
> #set pl_setup_slack_margin "0.5 -1000."
> #set pl_net_hold_fix_target "alta_bram alta_bram9k alta_mult"
> 
>  set rt_hold_slack_margin  "0.2 0.2    0.2 0.2    0.2 0.7   -1000. 0.0"
>  set rt_setup_slack_margin "0.5 -1000. 0.5 -1000. 0.0 -1000."
> #set rt_net_hold_crit_minmax "0.5 0.5"
>  set rt_net_hold_budget_method 0
>  set rt_net_hold_fix_target "alta_bram alta_bram9k alta_mult"
> 
> #set pl_net_hold_fix_clock false
> #set pl_net_hold_fix_auto  false
> #set pl_net_hold_fix_io    false
> #set rt_net_hold_fix_start false
> #set rt_net_hold_fix_clock false
> #set rt_net_hold_fix_auto  false
> #set rt_net_hold_fix_io    false
Using AQF file ./alta_db/alta.aqf.
> set_global_assignment -name DEVICE_IO_STANDARD "3.3-V LVTTL"
Using ASF file fpga_boot.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> if { [info exists BOARD_PLL_CLKIN] } {
  if { $BOARD_PLL_CLKIN == "PIN_OSC" } {
    set_config -loc 18 0 0 CFG_RCOSC_EN 1'b1
  }
}
> if { [info exists USB0_MODE] } {
  alta::tcl_info "USB0_MODE = $USB0_MODE"
  set_config -loc 0 1 3 CFG_PULLUP_ENB 1'b0
  set_config -loc 0 1 3 CFG_PULLDN_ENB 1'b0
}
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
Info: The input of IO BAUD_RATE is disabled since all input pins are unused.
Info: The input of IO TEST_SINGLE is disabled since all input pins are unused.
Info: The input of IO UART1_RX is disabled since all input pins are unused.
Info: The input of IO UART1_TX is disabled since all input pins are unused.
Info: The input of IO so_io1 is disabled since all input pins are unused.
Info: The input of IO BAUD_RATE is disabled since all input pins are unused.
Info: The input of IO TEST_SINGLE is disabled since all input pins are unused.
Info: The input of IO UART1_RX is disabled since all input pins are unused.
Info: The input of IO UART1_TX is disabled since all input pins are unused.
Info: The input of IO so_io1 is disabled since all input pins are unused.
Placement Statistics
 Total  Logic    Counts  : 3/2112 (0.1%)
 Total  Logic    Tiles   : 1/132 (0.8%)
 Total  Valid    Nets    : 25 (22+3)
 Total  Valid    Fanouts : 53 (47+6)
 Total  Tile     Fanouts : 23
 Tile   Zip      Fanins  : 2 (2:2)
 Tile   Zip      Fanouts : 2 (2:2)
 Total  Ignored  Nets    : 299
 Total  Valid    Blocks  : 10 (1/7)
 Total  Ignored  Blocks  : 3
 Total  Zip Complexities : 10/21 1.60/16.00
 Avg    Zip   Bottleneck : 0.00 0.00
 Avg    Net   Bottleneck : 0.00 0.00
Iter #1/1 ...
Pass 1 #1/1 ...
Partitioning...
 step = 0, partition : 20,12

 step = 1, partition : 10,7
....................
 step = 2, partition : 5,3
....................
 step = 3, partition : 2,2
....................
 step = 4, partition : 2,2
....................

## CPU time: 0:0:0, REAL time: 0:0:0
Pass 2 #1/1 ...
Legalization and Swapping...
..........

## CPU time: 0:0:0, REAL time: 0:0:0
Pass 3 #1/1 ...
Touchup...


## CPU time: 0:0:0, REAL time: 0:0:0
Pass 4 #1/1 ...
Optimization...
............................................................
Finishing...

## CPU time: 0:0:0, REAL time: 0:0:0
Total wire cost after placement: 0:0:0(0:0) 42.439(0.799004)+234(0)+2 227.606(26.8771)+221.25

*** Post Placement Timing Report ***
=== User constraints ===
=== Auto constraints ===
Coverage report
  User constraints covered 5 connections out of 27 total, coverage: 18.5%
  Auto constraints covered 5 connections out of 27 total, coverage: 18.5%
*** End Timing Report ***

route_design -dump ./alta_db/route.tx -replace ./alta_db/replace.tx 
Route Design Statistics
 Total Routing Nets : 25
 Fanout     Average : 1.12 (1..2)
 Max   Fanout  Net  : PLL_ENABLE~combout
 Logic       Slices : 3/2112 (0.1%)

Routing...
 Budget Useful Skew...
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 1/1, route#: 25, violation# : 4, overflow# : 4, conflict# : 4, node#: 148
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 2/2, route#: 25, violation# : 2, overflow# : 2, conflict# : 2, node#: 153
## CPU time: 0:0:0, REAL time: 0:0:0
 iter = 3/3, route#: 25, violation# : 0, overflow# : 0, conflict# : 0, node#: 155
Optimizing...
...

Done

*** Post Routing Timing Report ***
=== User constraints ===
=== Auto constraints ===
Coverage report
  User constraints covered 5 connections out of 27 total, coverage: 18.5%
  Auto constraints covered 5 connections out of 27 total, coverage: 18.5%
*** End Timing Report ***

Sat May 09 16:12:53 2026
Warn: User constraints coverage is too low at 18.5%.
Generating batch file: {C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/python_dist/python.exe} {C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/pio/gen_batch} -d 1075838977 -i 0xbff5105000730062aa234371030002b7 -o ./fpga_boot_batch.bin --logic-config ./fpga_boot.bin --logic-address 0x80007000  --logic-compress
> 
> if { [file exists "./${DESIGN}.post.asf"] } {
  alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n"
  source "./${DESIGN}.post.asf"
}
Using post-ASF file fpga_boot.post.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> date_time
Sat May 09 16:12:53 2026
> exit

Total 0 fatals, 0 errors, 1 warnings, 65 infos.