9102_BOOT/logic/alta_db/flatten.vx

`timescale 1 ps/ 1 ps

module fpga_boot(
	BAUD_RATE,
	GPIO4_1,
	GPIO4_2,
	PIN_HSE,
	PIN_HSI,
	PLL_CLKIN,
	SPI0_CSN,
	SPI0_SCK,
	SPI0_SI_IO0,
	TEST_SINGLE,
	UART0_UARTRXD,
	UART0_UARTTXD,
	UART1_RX,
	UART1_TX,
	so_io1);
inout	BAUD_RATE;
inout	GPIO4_1;
inout	GPIO4_2;
input	PIN_HSE;
input	PIN_HSI;
input	PLL_CLKIN;
output	SPI0_CSN;
output	SPI0_SCK;
inout	SPI0_SI_IO0;
inout	TEST_SINGLE;
input	UART0_UARTRXD;
output	UART0_UARTTXD;
inout	UART1_RX;
inout	UART1_TX;
inout	so_io1;

// module alta_rv32
// Design Ports Information

// module fpga_boot
// Design Ports Information
// PIN_HSE	=>  Location: PIN_AB17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// SPI0_CSN	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SPI0_SCK	=>  Location: PIN_AE13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART0_UARTTXD	=>  Location: PIN_AC15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// BAUD_RATE	=>  Location: PIN_F10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO4_1	=>  Location: PIN_AE14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO4_2	=>  Location: PIN_AB13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SPI0_SI_IO0	=>  Location: PIN_AA15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// TEST_SINGLE	=>  Location: PIN_H5,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART1_RX	=>  Location: PIN_AG26,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART1_TX	=>  Location: PIN_B3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// so_io1	=>  Location: PIN_AB16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART0_UARTRXD	=>  Location: PIN_AG12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PIN_HSI	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PLL_CLKIN	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default

// module hard_block
// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA

//wire	gnd;
//wire	gnd;
//wire	vcc;
//wire	vcc;
//wire	unknown;
//wire	unknown;
//wire	\BAUD_RATE~output_o ;
wire	\BAUD_RATE~input_o ;
//wire	\GPIO4_1~output_o ;
wire	\GPIO4_1~input_o ;
//wire	\GPIO4_2~output_o ;
wire	\GPIO4_2~input_o ;
wire	\PIN_HSE~input_o ;
//wire	hbi_69_0_9cb2c0024f9919c5_bp;
wire	\PIN_HSI~input_o ;
//wire	hbi_7_0_14f6b4c97af9700f_bp;
wire	\PLL_CLKIN~input_o ;
wire	\PLL_ENABLE~clkctrl_outclk ;
//wire	hbi_71_0_14f6b4c97af9700f_bp;
wire	\PLL_ENABLE~combout ;
wire	\PLL_LOCK~combout ;
//wire	\SPI0_CSN~output_o ;
//wire	\SPI0_SCK~output_o ;
//wire	\SPI0_SI_IO0~output_o ;
wire	\SPI0_SI_IO0~input_o ;
//wire	\TEST_SINGLE~output_o ;
wire	\TEST_SINGLE~input_o ;
wire	\UART0_UARTRXD~input_o ;
//wire	\UART0_UARTTXD~output_o ;
//wire	\UART1_RX~output_o ;
wire	\UART1_RX~input_o ;
//wire	\UART1_TX~output_o ;
wire	\UART1_TX~input_o ;
//wire	hbo_13_a8f89aa4d95b80e7_bp;
//wire	\pll_inst|auto_generated|pll1~LOCKED ;
wire	\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ;
//wire	hbo_22_f9ff3d300b43c0f2_bp;
//wire	\gclksw_inst|clkout ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
//wire	devclrn;
tri1	devclrn;
//wire	devoe;
tri1	devoe;
//wire	devpor;
tri1	devpor;
wire	[7:0] gpio0_io_in;
//wire	gpio0_io_in[1];
//wire	gpio0_io_in[2];
//wire	gpio0_io_in[3];
//wire	gpio0_io_in[4];
//wire	gpio0_io_in[5];
//wire	gpio0_io_in[6];
//wire	gpio0_io_in[7];
wire	[7:0] gpio0_io_out_data;
//wire	gpio0_io_out_data[1];
//wire	gpio0_io_out_data[2];
//wire	gpio0_io_out_data[3];
//wire	gpio0_io_out_data[4];
//wire	gpio0_io_out_data[5];
//wire	gpio0_io_out_data[6];
//wire	gpio0_io_out_data[7];
wire	[7:0] gpio0_io_out_en;
//wire	gpio0_io_out_en[1];
//wire	gpio0_io_out_en[2];
//wire	gpio0_io_out_en[3];
//wire	gpio0_io_out_en[4];
//wire	gpio0_io_out_en[5];
//wire	gpio0_io_out_en[6];
//wire	gpio0_io_out_en[7];
wire	[7:0] gpio4_io_in;
//wire	gpio4_io_in[0];
//wire	gpio4_io_in[3];
//wire	gpio4_io_in[4];
//wire	gpio4_io_in[5];
//wire	gpio4_io_in[6];
//wire	gpio4_io_in[7];
wire	[7:0] gpio4_io_out_data;
//wire	gpio4_io_out_data[0];
//wire	gpio4_io_out_data[3];
//wire	gpio4_io_out_data[4];
//wire	gpio4_io_out_data[7];
wire	[7:0] gpio4_io_out_en;
//wire	gpio4_io_out_en[0];
//wire	gpio4_io_out_en[3];
//wire	gpio4_io_out_en[4];
//wire	gpio4_io_out_en[7];
wire	[7:0] gpio6_io_in;
//wire	gpio6_io_in[0];
//wire	gpio6_io_in[2];
//wire	gpio6_io_in[3];
//wire	gpio6_io_in[4];
//wire	gpio6_io_in[5];
//wire	gpio6_io_in[6];
//wire	gpio6_io_in[7];
wire	[7:0] gpio7_io_out_data;
//wire	gpio7_io_out_data[0];
//wire	gpio7_io_out_data[1];
//wire	gpio7_io_out_data[2];
//wire	gpio7_io_out_data[3];
//wire	gpio7_io_out_data[4];
//wire	gpio7_io_out_data[5];
//wire	gpio7_io_out_data[7];
wire	[7:0] gpio7_io_out_en;
//wire	gpio7_io_out_en[0];
//wire	gpio7_io_out_en[1];
//wire	gpio7_io_out_en[2];
//wire	gpio7_io_out_en[3];
//wire	gpio7_io_out_en[4];
//wire	gpio7_io_out_en[5];
//wire	gpio7_io_out_en[7];
wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
wire	\pll_inst|auto_generated|pll_lock_sync~q ;
wire	\rv32.dmactive ;
wire	\rv32.ext_dma_DMACCLR[0] ;
wire	\rv32.ext_dma_DMACCLR[1] ;
wire	\rv32.ext_dma_DMACCLR[2] ;
wire	\rv32.ext_dma_DMACCLR[3] ;
wire	\rv32.ext_dma_DMACTC[0] ;
wire	\rv32.ext_dma_DMACTC[1] ;
wire	\rv32.ext_dma_DMACTC[2] ;
wire	\rv32.ext_dma_DMACTC[3] ;
wire	\rv32.gpio0_io_out_data[0] ;
wire	\rv32.gpio0_io_out_data[1] ;
wire	\rv32.gpio0_io_out_data[2] ;
wire	\rv32.gpio0_io_out_data[3] ;
wire	\rv32.gpio0_io_out_data[4] ;
wire	\rv32.gpio0_io_out_data[5] ;
wire	\rv32.gpio0_io_out_data[6] ;
wire	\rv32.gpio0_io_out_data[7] ;
wire	\rv32.gpio0_io_out_en[0] ;
wire	\rv32.gpio0_io_out_en[1] ;
wire	\rv32.gpio0_io_out_en[2] ;
wire	\rv32.gpio0_io_out_en[3] ;
wire	\rv32.gpio0_io_out_en[4] ;
wire	\rv32.gpio0_io_out_en[5] ;
wire	\rv32.gpio0_io_out_en[6] ;
wire	\rv32.gpio0_io_out_en[7] ;
wire	\rv32.gpio1_io_out_data[0] ;
wire	\rv32.gpio1_io_out_data[1] ;
wire	\rv32.gpio1_io_out_data[2] ;
wire	\rv32.gpio1_io_out_data[3] ;
wire	\rv32.gpio1_io_out_data[4] ;
wire	\rv32.gpio1_io_out_data[5] ;
wire	\rv32.gpio1_io_out_data[6] ;
wire	\rv32.gpio1_io_out_data[7] ;
wire	\rv32.gpio1_io_out_en[0] ;
wire	\rv32.gpio1_io_out_en[1] ;
wire	\rv32.gpio1_io_out_en[2] ;
wire	\rv32.gpio1_io_out_en[3] ;
wire	\rv32.gpio1_io_out_en[4] ;
wire	\rv32.gpio1_io_out_en[5] ;
wire	\rv32.gpio1_io_out_en[6] ;
wire	\rv32.gpio1_io_out_en[7] ;
wire	\rv32.gpio2_io_out_data[0] ;
wire	\rv32.gpio2_io_out_data[1] ;
wire	\rv32.gpio2_io_out_data[2] ;
wire	\rv32.gpio2_io_out_data[3] ;
wire	\rv32.gpio2_io_out_data[4] ;
wire	\rv32.gpio2_io_out_data[5] ;
wire	\rv32.gpio2_io_out_data[6] ;
wire	\rv32.gpio2_io_out_data[7] ;
wire	\rv32.gpio2_io_out_en[0] ;
wire	\rv32.gpio2_io_out_en[1] ;
wire	\rv32.gpio2_io_out_en[2] ;
wire	\rv32.gpio2_io_out_en[3] ;
wire	\rv32.gpio2_io_out_en[4] ;
wire	\rv32.gpio2_io_out_en[5] ;
wire	\rv32.gpio2_io_out_en[6] ;
wire	\rv32.gpio2_io_out_en[7] ;
wire	\rv32.gpio3_io_out_data[0] ;
wire	\rv32.gpio3_io_out_data[1] ;
wire	\rv32.gpio3_io_out_data[2] ;
wire	\rv32.gpio3_io_out_data[3] ;
wire	\rv32.gpio3_io_out_data[4] ;
wire	\rv32.gpio3_io_out_data[5] ;
wire	\rv32.gpio3_io_out_data[6] ;
wire	\rv32.gpio3_io_out_data[7] ;
wire	\rv32.gpio3_io_out_en[0] ;
wire	\rv32.gpio3_io_out_en[1] ;
wire	\rv32.gpio3_io_out_en[2] ;
wire	\rv32.gpio3_io_out_en[3] ;
wire	\rv32.gpio3_io_out_en[4] ;
wire	\rv32.gpio3_io_out_en[5] ;
wire	\rv32.gpio3_io_out_en[6] ;
wire	\rv32.gpio3_io_out_en[7] ;
wire	\rv32.gpio4_io_out_data[0] ;
wire	\rv32.gpio4_io_out_data[1] ;
wire	\rv32.gpio4_io_out_data[2] ;
wire	\rv32.gpio4_io_out_data[3] ;
wire	\rv32.gpio4_io_out_data[4] ;
wire	\rv32.gpio4_io_out_data[5] ;
wire	\rv32.gpio4_io_out_data[6] ;
wire	\rv32.gpio4_io_out_data[7] ;
wire	\rv32.gpio4_io_out_en[0] ;
wire	\rv32.gpio4_io_out_en[1] ;
wire	\rv32.gpio4_io_out_en[2] ;
wire	\rv32.gpio4_io_out_en[3] ;
wire	\rv32.gpio4_io_out_en[4] ;
wire	\rv32.gpio4_io_out_en[5] ;
wire	\rv32.gpio4_io_out_en[6] ;
wire	\rv32.gpio4_io_out_en[7] ;
wire	\rv32.gpio5_io_out_data[0] ;
wire	\rv32.gpio5_io_out_data[1] ;
wire	\rv32.gpio5_io_out_data[2] ;
wire	\rv32.gpio5_io_out_data[3] ;
wire	\rv32.gpio5_io_out_data[4] ;
wire	\rv32.gpio5_io_out_data[5] ;
wire	\rv32.gpio5_io_out_data[6] ;
wire	\rv32.gpio5_io_out_data[7] ;
wire	\rv32.gpio5_io_out_en[0] ;
wire	\rv32.gpio5_io_out_en[1] ;
wire	\rv32.gpio5_io_out_en[2] ;
wire	\rv32.gpio5_io_out_en[3] ;
wire	\rv32.gpio5_io_out_en[4] ;
wire	\rv32.gpio5_io_out_en[5] ;
wire	\rv32.gpio5_io_out_en[6] ;
wire	\rv32.gpio5_io_out_en[7] ;
wire	\rv32.gpio6_io_out_data[0] ;
wire	\rv32.gpio6_io_out_data[1] ;
wire	\rv32.gpio6_io_out_data[2] ;
wire	\rv32.gpio6_io_out_data[3] ;
wire	\rv32.gpio6_io_out_data[4] ;
wire	\rv32.gpio6_io_out_data[5] ;
wire	\rv32.gpio6_io_out_data[6] ;
wire	\rv32.gpio6_io_out_data[7] ;
wire	\rv32.gpio6_io_out_en[0] ;
wire	\rv32.gpio6_io_out_en[1] ;
wire	\rv32.gpio6_io_out_en[2] ;
wire	\rv32.gpio6_io_out_en[3] ;
wire	\rv32.gpio6_io_out_en[4] ;
wire	\rv32.gpio6_io_out_en[5] ;
wire	\rv32.gpio6_io_out_en[6] ;
wire	\rv32.gpio6_io_out_en[7] ;
wire	\rv32.gpio7_io_out_data[0] ;
wire	\rv32.gpio7_io_out_data[1] ;
wire	\rv32.gpio7_io_out_data[2] ;
wire	\rv32.gpio7_io_out_data[3] ;
wire	\rv32.gpio7_io_out_data[4] ;
wire	\rv32.gpio7_io_out_data[5] ;
wire	\rv32.gpio7_io_out_data[6] ;
wire	\rv32.gpio7_io_out_data[7] ;
wire	\rv32.gpio7_io_out_en[0] ;
wire	\rv32.gpio7_io_out_en[1] ;
wire	\rv32.gpio7_io_out_en[2] ;
wire	\rv32.gpio7_io_out_en[3] ;
wire	\rv32.gpio7_io_out_en[4] ;
wire	\rv32.gpio7_io_out_en[5] ;
wire	\rv32.gpio7_io_out_en[6] ;
wire	\rv32.gpio7_io_out_en[7] ;
wire	\rv32.gpio8_io_out_data[0] ;
wire	\rv32.gpio8_io_out_data[1] ;
wire	\rv32.gpio8_io_out_data[2] ;
wire	\rv32.gpio8_io_out_data[3] ;
wire	\rv32.gpio8_io_out_data[4] ;
wire	\rv32.gpio8_io_out_data[5] ;
wire	\rv32.gpio8_io_out_data[6] ;
wire	\rv32.gpio8_io_out_data[7] ;
wire	\rv32.gpio8_io_out_en[0] ;
wire	\rv32.gpio8_io_out_en[1] ;
wire	\rv32.gpio8_io_out_en[2] ;
wire	\rv32.gpio8_io_out_en[3] ;
wire	\rv32.gpio8_io_out_en[4] ;
wire	\rv32.gpio8_io_out_en[5] ;
wire	\rv32.gpio8_io_out_en[6] ;
wire	\rv32.gpio8_io_out_en[7] ;
wire	\rv32.gpio9_io_out_data[0] ;
wire	\rv32.gpio9_io_out_data[1] ;
wire	\rv32.gpio9_io_out_data[2] ;
wire	\rv32.gpio9_io_out_data[3] ;
wire	\rv32.gpio9_io_out_data[4] ;
wire	\rv32.gpio9_io_out_data[5] ;
wire	\rv32.gpio9_io_out_data[6] ;
wire	\rv32.gpio9_io_out_data[7] ;
wire	\rv32.gpio9_io_out_en[0] ;
wire	\rv32.gpio9_io_out_en[1] ;
wire	\rv32.gpio9_io_out_en[2] ;
wire	\rv32.gpio9_io_out_en[3] ;
wire	\rv32.gpio9_io_out_en[4] ;
wire	\rv32.gpio9_io_out_en[5] ;
wire	\rv32.gpio9_io_out_en[6] ;
wire	\rv32.gpio9_io_out_en[7] ;
wire	\rv32.mem_ahb_haddr[0] ;
wire	\rv32.mem_ahb_haddr[10] ;
wire	\rv32.mem_ahb_haddr[11] ;
wire	\rv32.mem_ahb_haddr[12] ;
wire	\rv32.mem_ahb_haddr[13] ;
wire	\rv32.mem_ahb_haddr[14] ;
wire	\rv32.mem_ahb_haddr[15] ;
wire	\rv32.mem_ahb_haddr[16] ;
wire	\rv32.mem_ahb_haddr[17] ;
wire	\rv32.mem_ahb_haddr[18] ;
wire	\rv32.mem_ahb_haddr[19] ;
wire	\rv32.mem_ahb_haddr[1] ;
wire	\rv32.mem_ahb_haddr[20] ;
wire	\rv32.mem_ahb_haddr[21] ;
wire	\rv32.mem_ahb_haddr[22] ;
wire	\rv32.mem_ahb_haddr[23] ;
wire	\rv32.mem_ahb_haddr[24] ;
wire	\rv32.mem_ahb_haddr[25] ;
wire	\rv32.mem_ahb_haddr[26] ;
wire	\rv32.mem_ahb_haddr[27] ;
wire	\rv32.mem_ahb_haddr[28] ;
wire	\rv32.mem_ahb_haddr[29] ;
wire	\rv32.mem_ahb_haddr[2] ;
wire	\rv32.mem_ahb_haddr[30] ;
wire	\rv32.mem_ahb_haddr[31] ;
wire	\rv32.mem_ahb_haddr[3] ;
wire	\rv32.mem_ahb_haddr[4] ;
wire	\rv32.mem_ahb_haddr[5] ;
wire	\rv32.mem_ahb_haddr[6] ;
wire	\rv32.mem_ahb_haddr[7] ;
wire	\rv32.mem_ahb_haddr[8] ;
wire	\rv32.mem_ahb_haddr[9] ;
wire	\rv32.mem_ahb_hburst[0] ;
wire	\rv32.mem_ahb_hburst[1] ;
wire	\rv32.mem_ahb_hburst[2] ;
wire	\rv32.mem_ahb_hready ;
wire	\rv32.mem_ahb_hsize[0] ;
wire	\rv32.mem_ahb_hsize[1] ;
wire	\rv32.mem_ahb_hsize[2] ;
wire	\rv32.mem_ahb_htrans[0] ;
wire	\rv32.mem_ahb_htrans[1] ;
wire	\rv32.mem_ahb_hwdata[0] ;
wire	\rv32.mem_ahb_hwdata[10] ;
wire	\rv32.mem_ahb_hwdata[11] ;
wire	\rv32.mem_ahb_hwdata[12] ;
wire	\rv32.mem_ahb_hwdata[13] ;
wire	\rv32.mem_ahb_hwdata[14] ;
wire	\rv32.mem_ahb_hwdata[15] ;
wire	\rv32.mem_ahb_hwdata[16] ;
wire	\rv32.mem_ahb_hwdata[17] ;
wire	\rv32.mem_ahb_hwdata[18] ;
wire	\rv32.mem_ahb_hwdata[19] ;
wire	\rv32.mem_ahb_hwdata[1] ;
wire	\rv32.mem_ahb_hwdata[20] ;
wire	\rv32.mem_ahb_hwdata[21] ;
wire	\rv32.mem_ahb_hwdata[22] ;
wire	\rv32.mem_ahb_hwdata[23] ;
wire	\rv32.mem_ahb_hwdata[24] ;
wire	\rv32.mem_ahb_hwdata[25] ;
wire	\rv32.mem_ahb_hwdata[26] ;
wire	\rv32.mem_ahb_hwdata[27] ;
wire	\rv32.mem_ahb_hwdata[28] ;
wire	\rv32.mem_ahb_hwdata[29] ;
wire	\rv32.mem_ahb_hwdata[2] ;
wire	\rv32.mem_ahb_hwdata[30] ;
wire	\rv32.mem_ahb_hwdata[31] ;
wire	\rv32.mem_ahb_hwdata[3] ;
wire	\rv32.mem_ahb_hwdata[4] ;
wire	\rv32.mem_ahb_hwdata[5] ;
wire	\rv32.mem_ahb_hwdata[6] ;
wire	\rv32.mem_ahb_hwdata[7] ;
wire	\rv32.mem_ahb_hwdata[8] ;
wire	\rv32.mem_ahb_hwdata[9] ;
wire	\rv32.mem_ahb_hwrite ;
wire	\rv32.resetn_out ;
wire	\rv32.slave_ahb_hrdata[0] ;
wire	\rv32.slave_ahb_hrdata[10] ;
wire	\rv32.slave_ahb_hrdata[11] ;
wire	\rv32.slave_ahb_hrdata[12] ;
wire	\rv32.slave_ahb_hrdata[13] ;
wire	\rv32.slave_ahb_hrdata[14] ;
wire	\rv32.slave_ahb_hrdata[15] ;
wire	\rv32.slave_ahb_hrdata[16] ;
wire	\rv32.slave_ahb_hrdata[17] ;
wire	\rv32.slave_ahb_hrdata[18] ;
wire	\rv32.slave_ahb_hrdata[19] ;
wire	\rv32.slave_ahb_hrdata[1] ;
wire	\rv32.slave_ahb_hrdata[20] ;
wire	\rv32.slave_ahb_hrdata[21] ;
wire	\rv32.slave_ahb_hrdata[22] ;
wire	\rv32.slave_ahb_hrdata[23] ;
wire	\rv32.slave_ahb_hrdata[24] ;
wire	\rv32.slave_ahb_hrdata[25] ;
wire	\rv32.slave_ahb_hrdata[26] ;
wire	\rv32.slave_ahb_hrdata[27] ;
wire	\rv32.slave_ahb_hrdata[28] ;
wire	\rv32.slave_ahb_hrdata[29] ;
wire	\rv32.slave_ahb_hrdata[2] ;
wire	\rv32.slave_ahb_hrdata[30] ;
wire	\rv32.slave_ahb_hrdata[31] ;
wire	\rv32.slave_ahb_hrdata[3] ;
wire	\rv32.slave_ahb_hrdata[4] ;
wire	\rv32.slave_ahb_hrdata[5] ;
wire	\rv32.slave_ahb_hrdata[6] ;
wire	\rv32.slave_ahb_hrdata[7] ;
wire	\rv32.slave_ahb_hrdata[8] ;
wire	\rv32.slave_ahb_hrdata[9] ;
wire	\rv32.slave_ahb_hreadyout ;
wire	\rv32.slave_ahb_hresp ;
wire	\rv32.swj_JTAGIR[0] ;
wire	\rv32.swj_JTAGIR[1] ;
wire	\rv32.swj_JTAGIR[2] ;
wire	\rv32.swj_JTAGIR[3] ;
wire	\rv32.swj_JTAGNSW ;
wire	\rv32.swj_JTAGSTATE[0] ;
wire	\rv32.swj_JTAGSTATE[1] ;
wire	\rv32.swj_JTAGSTATE[2] ;
wire	\rv32.swj_JTAGSTATE[3] ;
wire	\rv32.sys_ctrl_clkSource[0] ;
wire	\rv32.sys_ctrl_clkSource[1] ;
wire	\rv32.sys_ctrl_hseBypass ;
wire	\rv32.sys_ctrl_hseEnable ;
wire	\rv32.sys_ctrl_pllEnable ;
wire	\rv32.sys_ctrl_sleep ;
wire	\rv32.sys_ctrl_standby ;
wire	\rv32.sys_ctrl_stop ;
//wire	\so_io1~output_o ;
wire	\so_io1~input_o ;
wire	\~GND~combout ;
wire	\~VCC~combout ;
wire	hbi_272_0_9cb2c0024f9919c5_bp;
wire	hbi_272_1_9cb2c0024f9919c5_bp;
wire	[4:0] \pll_inst|auto_generated|clk ;
//wire	\pll_inst|auto_generated|clk [0];
wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
//wire	\pll_inst|auto_generated|clk [1];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
//wire	\pll_inst|auto_generated|clk [2];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
//wire	\pll_inst|auto_generated|clk [3];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
//wire	\pll_inst|auto_generated|clk [4];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
wire	\pll_inst|auto_generated|pll1~FBOUT ;

wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;
wire unknown;
assign unknown = 1'bx;

// Location: IOIBUF_X16_Y62_N8
cycloneive_io_ibuf \BAUD_RATE~input (
	.i(BAUD_RATE),
	.ibar(gnd),
	.o(\BAUD_RATE~input_o ));
defparam \BAUD_RATE~input .bus_hold = "false";
defparam \BAUD_RATE~input .simulate_z_as = "z";

// Location: IOOBUF_X16_Y62_N9
cycloneive_io_obuf \BAUD_RATE~output (
	.i(gnd),
	.oe(gnd),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(BAUD_RATE),
	.obar());
defparam \BAUD_RATE~output .bus_hold = "false";
defparam \BAUD_RATE~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N1
cycloneive_io_ibuf \GPIO4_1~input (
	.i(GPIO4_1),
	.ibar(gnd),
	.o(\GPIO4_1~input_o ));
defparam \GPIO4_1~input .bus_hold = "false";
defparam \GPIO4_1~input .simulate_z_as = "z";

// Location: IOOBUF_X45_Y0_N2
cycloneive_io_obuf \GPIO4_1~output (
	.i(\rv32.gpio4_io_out_data[1] ),
	.oe(\rv32.gpio4_io_out_en[1] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(GPIO4_1),
	.obar());
defparam \GPIO4_1~output .bus_hold = "false";
defparam \GPIO4_1~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N15
cycloneive_io_ibuf \GPIO4_2~input (
	.i(GPIO4_2),
	.ibar(gnd),
	.o(\GPIO4_2~input_o ));
defparam \GPIO4_2~input .bus_hold = "false";
defparam \GPIO4_2~input .simulate_z_as = "z";

// Location: IOOBUF_X45_Y0_N16
cycloneive_io_obuf \GPIO4_2~output (
	.i(\rv32.gpio4_io_out_data[2] ),
	.oe(\rv32.gpio4_io_out_en[2] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(GPIO4_2),
	.obar());
defparam \GPIO4_2~output .bus_hold = "false";
defparam \GPIO4_2~output .open_drain_output = "false";

// Location: IOIBUF_X76_Y0_N1
cycloneive_io_ibuf \PIN_HSE~input (
	.i(PIN_HSE),
	.ibar(gnd),
	.o(\PIN_HSE~input_o ));
defparam \PIN_HSE~input .bus_hold = "false";
defparam \PIN_HSE~input .simulate_z_as = "z";

// Location: IOIBUF_X0_Y30_N15
cycloneive_io_ibuf \PIN_HSI~input (
	.i(PIN_HSI),
	.ibar(gnd),
	.o(\PIN_HSI~input_o ));
defparam \PIN_HSI~input .bus_hold = "false";
defparam \PIN_HSI~input .simulate_z_as = "z";

// Location: IOIBUF_X0_Y30_N8
cycloneive_io_ibuf \PLL_CLKIN~input (
	.i(PLL_CLKIN),
	.ibar(gnd),
	.o(\PLL_CLKIN~input_o ));
defparam \PLL_CLKIN~input .bus_hold = "false";
defparam \PLL_CLKIN~input .simulate_z_as = "z";

// Location: LCCOMB_X49_Y1_N28
cycloneive_lcell_comb PLL_ENABLE(
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(\rv32.sys_ctrl_pllEnable ),
	.cin(gnd),
	.combout(\PLL_ENABLE~combout ),
	.cout());
defparam PLL_ENABLE.lut_mask = 16'h00FF;
defparam PLL_ENABLE.sum_lutc_input = "datac";

// Location: CLKCTRL_G15
cycloneive_clkctrl \PLL_ENABLE~clkctrl (
	.inclk({vcc, vcc, vcc, \PLL_ENABLE~combout }),
	.clkselect({gnd, gnd}),
	.ena(vcc),
	.devpor(devpor),
	.devclrn(devclrn),
	.outclk(\PLL_ENABLE~clkctrl_outclk ));
defparam \PLL_ENABLE~clkctrl .clock_type = "global clock";
defparam \PLL_ENABLE~clkctrl .ena_register_mode = "none";

// Location: LCCOMB_X49_Y1_N20
cycloneive_lcell_comb PLL_LOCK(
	.dataa(gnd),
	.datab(gnd),
	.datac(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.datad(\pll_inst|auto_generated|pll_lock_sync~q ),
	.cin(gnd),
	.combout(\PLL_LOCK~combout ),
	.cout());
defparam PLL_LOCK.lut_mask = 16'hF000;
defparam PLL_LOCK.sum_lutc_input = "datac";

// Location: IOOBUF_X45_Y0_N9
cycloneive_io_obuf \SPI0_CSN~output (
	.i(\rv32.gpio4_io_out_data[6] ),
	.oe(\rv32.gpio4_io_out_en[6] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(SPI0_CSN),
	.obar());
defparam \SPI0_CSN~output .bus_hold = "false";
defparam \SPI0_CSN~output .open_drain_output = "false";

// Location: IOOBUF_X43_Y0_N9
cycloneive_io_obuf \SPI0_SCK~output (
	.i(\rv32.gpio4_io_out_data[5] ),
	.oe(\rv32.gpio4_io_out_en[5] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(SPI0_SCK),
	.obar());
defparam \SPI0_SCK~output .bus_hold = "false";
defparam \SPI0_SCK~output .open_drain_output = "false";

// Location: IOIBUF_X56_Y0_N15
cycloneive_io_ibuf \SPI0_SI_IO0~input (
	.i(SPI0_SI_IO0),
	.ibar(gnd),
	.o(\SPI0_SI_IO0~input_o ));
defparam \SPI0_SI_IO0~input .bus_hold = "false";
defparam \SPI0_SI_IO0~input .simulate_z_as = "z";

// Location: IOOBUF_X56_Y0_N16
cycloneive_io_obuf \SPI0_SI_IO0~output (
	.i(\rv32.gpio0_io_out_data[0] ),
	.oe(\rv32.gpio0_io_out_en[0] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(SPI0_SI_IO0),
	.obar());
defparam \SPI0_SI_IO0~output .bus_hold = "false";
defparam \SPI0_SI_IO0~output .open_drain_output = "false";

// Location: IOIBUF_X0_Y47_N8
cycloneive_io_ibuf \TEST_SINGLE~input (
	.i(TEST_SINGLE),
	.ibar(gnd),
	.o(\TEST_SINGLE~input_o ));
defparam \TEST_SINGLE~input .bus_hold = "false";
defparam \TEST_SINGLE~input .simulate_z_as = "z";

// Location: IOOBUF_X0_Y47_N9
cycloneive_io_obuf \TEST_SINGLE~output (
	.i(gnd),
	.oe(gnd),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(TEST_SINGLE),
	.obar());
defparam \TEST_SINGLE~output .bus_hold = "false";
defparam \TEST_SINGLE~output .open_drain_output = "false";

// Location: IOIBUF_X47_Y0_N8
cycloneive_io_ibuf \UART0_UARTRXD~input (
	.i(UART0_UARTRXD),
	.ibar(gnd),
	.o(\UART0_UARTRXD~input_o ));
defparam \UART0_UARTRXD~input .bus_hold = "false";
defparam \UART0_UARTRXD~input .simulate_z_as = "z";

// Location: IOOBUF_X51_Y0_N23
cycloneive_io_obuf \UART0_UARTTXD~output (
	.i(\rv32.gpio7_io_out_data[6] ),
	.oe(\rv32.gpio7_io_out_en[6] ),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(UART0_UARTTXD),
	.obar());
defparam \UART0_UARTTXD~output .bus_hold = "false";
defparam \UART0_UARTTXD~output .open_drain_output = "false";

// Location: IOIBUF_X92_Y0_N8
cycloneive_io_ibuf \UART1_RX~input (
	.i(UART1_RX),
	.ibar(gnd),
	.o(\UART1_RX~input_o ));
defparam \UART1_RX~input .bus_hold = "false";
defparam \UART1_RX~input .simulate_z_as = "z";

// Location: IOOBUF_X92_Y0_N9
cycloneive_io_obuf \UART1_RX~output (
	.i(gnd),
	.oe(gnd),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(UART1_RX),
	.obar());
defparam \UART1_RX~output .bus_hold = "false";
defparam \UART1_RX~output .open_drain_output = "false";

// Location: IOIBUF_X5_Y62_N1
cycloneive_io_ibuf \UART1_TX~input (
	.i(UART1_TX),
	.ibar(gnd),
	.o(\UART1_TX~input_o ));
defparam \UART1_TX~input .bus_hold = "false";
defparam \UART1_TX~input .simulate_z_as = "z";

// Location: IOOBUF_X5_Y62_N2
cycloneive_io_obuf \UART1_TX~output (
	.i(gnd),
	.oe(gnd),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(UART1_TX),
	.obar());
defparam \UART1_TX~output .bus_hold = "false";
defparam \UART1_TX~output .open_drain_output = "false";

// Location: LCCOMB_X56_Y5_N2
cycloneive_lcell_comb \gpio0_io_in[1] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[1]),
	.cout());
defparam \gpio0_io_in[1] .lut_mask = 16'h0000;
defparam \gpio0_io_in[1] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N4
cycloneive_lcell_comb \gpio0_io_in[2] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[2]),
	.cout());
defparam \gpio0_io_in[2] .lut_mask = 16'h0000;
defparam \gpio0_io_in[2] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N6
cycloneive_lcell_comb \gpio0_io_in[3] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[3]),
	.cout());
defparam \gpio0_io_in[3] .lut_mask = 16'h0000;
defparam \gpio0_io_in[3] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N8
cycloneive_lcell_comb \gpio0_io_in[4] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[4]),
	.cout());
defparam \gpio0_io_in[4] .lut_mask = 16'h0000;
defparam \gpio0_io_in[4] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N10
cycloneive_lcell_comb \gpio0_io_in[5] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[5]),
	.cout());
defparam \gpio0_io_in[5] .lut_mask = 16'h0000;
defparam \gpio0_io_in[5] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N12
cycloneive_lcell_comb \gpio0_io_in[6] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[6]),
	.cout());
defparam \gpio0_io_in[6] .lut_mask = 16'h0000;
defparam \gpio0_io_in[6] .sum_lutc_input = "datac";

// Location: LCCOMB_X56_Y5_N14
cycloneive_lcell_comb \gpio0_io_in[7] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio0_io_in[7]),
	.cout());
defparam \gpio0_io_in[7] .lut_mask = 16'h0000;
defparam \gpio0_io_in[7] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N0
cycloneive_lcell_comb \gpio4_io_in[0] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[0]),
	.cout());
defparam \gpio4_io_in[0] .lut_mask = 16'h0000;
defparam \gpio4_io_in[0] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N6
cycloneive_lcell_comb \gpio4_io_in[3] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[3]),
	.cout());
defparam \gpio4_io_in[3] .lut_mask = 16'h0000;
defparam \gpio4_io_in[3] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N8
cycloneive_lcell_comb \gpio4_io_in[4] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[4]),
	.cout());
defparam \gpio4_io_in[4] .lut_mask = 16'h0000;
defparam \gpio4_io_in[4] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N10
cycloneive_lcell_comb \gpio4_io_in[5] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[5]),
	.cout());
defparam \gpio4_io_in[5] .lut_mask = 16'h0000;
defparam \gpio4_io_in[5] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N12
cycloneive_lcell_comb \gpio4_io_in[6] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[6]),
	.cout());
defparam \gpio4_io_in[6] .lut_mask = 16'h0000;
defparam \gpio4_io_in[6] .sum_lutc_input = "datac";

// Location: LCCOMB_X45_Y4_N14
cycloneive_lcell_comb \gpio4_io_in[7] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio4_io_in[7]),
	.cout());
defparam \gpio4_io_in[7] .lut_mask = 16'h0000;
defparam \gpio4_io_in[7] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N0
cycloneive_lcell_comb \gpio6_io_in[0] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[0]),
	.cout());
defparam \gpio6_io_in[0] .lut_mask = 16'h0000;
defparam \gpio6_io_in[0] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N4
cycloneive_lcell_comb \gpio6_io_in[2] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[2]),
	.cout());
defparam \gpio6_io_in[2] .lut_mask = 16'h0000;
defparam \gpio6_io_in[2] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N6
cycloneive_lcell_comb \gpio6_io_in[3] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[3]),
	.cout());
defparam \gpio6_io_in[3] .lut_mask = 16'h0000;
defparam \gpio6_io_in[3] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N8
cycloneive_lcell_comb \gpio6_io_in[4] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[4]),
	.cout());
defparam \gpio6_io_in[4] .lut_mask = 16'h0000;
defparam \gpio6_io_in[4] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N10
cycloneive_lcell_comb \gpio6_io_in[5] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[5]),
	.cout());
defparam \gpio6_io_in[5] .lut_mask = 16'h0000;
defparam \gpio6_io_in[5] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N12
cycloneive_lcell_comb \gpio6_io_in[6] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[6]),
	.cout());
defparam \gpio6_io_in[6] .lut_mask = 16'h0000;
defparam \gpio6_io_in[6] .sum_lutc_input = "datac";

// Location: LCCOMB_X47_Y4_N14
cycloneive_lcell_comb \gpio6_io_in[7] (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(gpio6_io_in[7]),
	.cout());
defparam \gpio6_io_in[7] .lut_mask = 16'h0000;
defparam \gpio6_io_in[7] .sum_lutc_input = "datac";

// Location: FF_X49_Y1_N1
dffeas \pll_inst|auto_generated|pll_lock_sync (
	.clk(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.d(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.asdata(vcc),
	.clrn(!\PLL_ENABLE~clkctrl_outclk ),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.q(\pll_inst|auto_generated|pll_lock_sync~q ),
	.prn(vcc));
defparam \pll_inst|auto_generated|pll_lock_sync .is_wysiwyg = "true";
defparam \pll_inst|auto_generated|pll_lock_sync .power_up = "low";

// Location: LCCOMB_X49_Y1_N0
cycloneive_lcell_comb \pll_inst|auto_generated|pll_lock_sync~feeder (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.cout());
defparam \pll_inst|auto_generated|pll_lock_sync~feeder .lut_mask = 16'hFFFF;
defparam \pll_inst|auto_generated|pll_lock_sync~feeder .sum_lutc_input = "datac";

// Location: BBOX_X1_Y1_N0
alta_rv32 rv32(
	.sys_clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.mem_ahb_hready(\rv32.mem_ahb_hready ),
	.mem_ahb_hreadyout(\~VCC~combout ),
	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
	.mem_ahb_hresp(\~GND~combout ),
	.mem_ahb_hrdata({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hsel(\~GND~combout ),
	.slave_ahb_hready(\~VCC~combout ),
	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
	.slave_ahb_htrans({\~GND~combout , \~GND~combout }),
	.slave_ahb_hsize({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hburst({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwrite(\~GND~combout ),
	.slave_ahb_haddr({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwdata({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
	.gpio0_io_in({gpio0_io_in[7], gpio0_io_in[6], gpio0_io_in[5], gpio0_io_in[4], gpio0_io_in[3], gpio0_io_in[2], gpio0_io_in[1], \SPI0_SI_IO0~input_o }),
	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
	.gpio1_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
	.sys_ctrl_pllReady(\PLL_LOCK~combout ),
	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
	.gpio2_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
	.gpio3_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
	.gpio4_io_in({gpio4_io_in[7], gpio4_io_in[6], gpio4_io_in[5], gpio4_io_in[4], gpio4_io_in[3], \GPIO4_2~input_o , \GPIO4_1~input_o , gpio4_io_in[0]}),
	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
	.gpio5_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
	.gpio6_io_in({gpio6_io_in[7], gpio6_io_in[6], gpio6_io_in[5], gpio6_io_in[4], gpio6_io_in[3], gpio6_io_in[2], \UART0_UARTRXD~input_o , gpio6_io_in[0]}),
	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
	.gpio7_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
	.gpio8_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
	.gpio9_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
	.ext_resetn(\~VCC~combout ),
	.resetn_out(\rv32.resetn_out ),
	.dmactive(\rv32.dmactive ),
	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
	.ext_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACBREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACLBREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACLSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
	.local_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.test_mode({\~GND~combout , \~GND~combout }),
	.usb0_xcvr_clk(\~VCC~combout ),
	.usb0_id(\~VCC~combout ));

// Location: IOIBUF_X56_Y0_N22
cycloneive_io_ibuf \so_io1~input (
	.i(so_io1),
	.ibar(gnd),
	.o(\so_io1~input_o ));
defparam \so_io1~input .bus_hold = "false";
defparam \so_io1~input .simulate_z_as = "z";

// Location: IOOBUF_X56_Y0_N23
cycloneive_io_obuf \so_io1~output (
	.i(gnd),
	.oe(gnd),
	.seriesterminationcontrol({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.devoe(devoe),
	.o(so_io1),
	.obar());
defparam \so_io1~output .bus_hold = "false";
defparam \so_io1~output .open_drain_output = "false";

// Location: LCCOMB_X57_Y8_N0
cycloneive_lcell_comb \~GND (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\~GND~combout ),
	.cout());
defparam \~GND .lut_mask = 16'h0000;
defparam \~GND .sum_lutc_input = "datac";

// Location: LCCOMB_X57_Y5_N10
cycloneive_lcell_comb \~VCC (
	.dataa(gnd),
	.datab(gnd),
	.datac(gnd),
	.datad(gnd),
	.cin(gnd),
	.combout(\~VCC~combout ),
	.cout());
defparam \~VCC .lut_mask = 16'hFFFF;
defparam \~VCC .sum_lutc_input = "datac";

// Location: CLKCTRL_G3
cycloneive_clkctrl \gclksw_inst|gclk_switch (
	.inclk({vcc, \pll_inst|auto_generated|pll1_CLK_bus [0], vcc, \PIN_HSI~input_o }),
	.clkselect({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.ena(vcc),
	.devpor(devpor),
	.devclrn(devclrn),
	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
defparam \gclksw_inst|gclk_switch .clock_type = "global clock";
defparam \gclksw_inst|gclk_switch .ena_register_mode = "none";

// Location: PLL_1
cycloneive_pll \pll_inst|auto_generated|pll1 (
	.inclk({gnd, \PLL_CLKIN~input_o }),
	.fbin(\pll_inst|auto_generated|pll1~FBOUT ),
	.fbout(\pll_inst|auto_generated|pll1~FBOUT ),
	.clkswitch(gnd),
	.areset(\PLL_ENABLE~combout ),
	.pfdena(vcc),
	.scanclk(gnd),
	.scandata(gnd),
	.scanclkena(vcc),
	.configupdate(gnd),
	.clk(\pll_inst|auto_generated|pll1_CLK_bus ),
	.phasecounterselect({gnd, gnd, gnd}),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.clkbad(),
	.activeclock(),
	.locked(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.scandataout(),
	.scandone(),
	.phasedone(),
	.vcooverrange(),
	.vcounderrange());
defparam \pll_inst|auto_generated|pll1 .auto_settings = "false";
defparam \pll_inst|auto_generated|pll1 .bandwidth_type = "medium";
defparam \pll_inst|auto_generated|pll1 .c0_high = 2;
defparam \pll_inst|auto_generated|pll1 .c0_initial = 1;
defparam \pll_inst|auto_generated|pll1 .c0_low = 1;
defparam \pll_inst|auto_generated|pll1 .c0_mode = "odd";
defparam \pll_inst|auto_generated|pll1 .c0_ph = 0;
defparam \pll_inst|auto_generated|pll1 .c1_high = 0;
defparam \pll_inst|auto_generated|pll1 .c1_initial = 0;
defparam \pll_inst|auto_generated|pll1 .c1_low = 0;
defparam \pll_inst|auto_generated|pll1 .c1_mode = "bypass";
defparam \pll_inst|auto_generated|pll1 .c1_ph = 0;
defparam \pll_inst|auto_generated|pll1 .c1_use_casc_in = "off";
defparam \pll_inst|auto_generated|pll1 .c2_high = 0;
defparam \pll_inst|auto_generated|pll1 .c2_initial = 0;
defparam \pll_inst|auto_generated|pll1 .c2_low = 0;
defparam \pll_inst|auto_generated|pll1 .c2_mode = "bypass";
defparam \pll_inst|auto_generated|pll1 .c2_ph = 0;
defparam \pll_inst|auto_generated|pll1 .c2_use_casc_in = "off";
defparam \pll_inst|auto_generated|pll1 .c3_high = 0;
defparam \pll_inst|auto_generated|pll1 .c3_initial = 0;
defparam \pll_inst|auto_generated|pll1 .c3_low = 0;
defparam \pll_inst|auto_generated|pll1 .c3_mode = "bypass";
defparam \pll_inst|auto_generated|pll1 .c3_ph = 0;
defparam \pll_inst|auto_generated|pll1 .c3_use_casc_in = "off";
defparam \pll_inst|auto_generated|pll1 .c4_high = 0;
defparam \pll_inst|auto_generated|pll1 .c4_initial = 0;
defparam \pll_inst|auto_generated|pll1 .c4_low = 0;
defparam \pll_inst|auto_generated|pll1 .c4_mode = "bypass";
defparam \pll_inst|auto_generated|pll1 .c4_ph = 0;
defparam \pll_inst|auto_generated|pll1 .c4_use_casc_in = "off";
defparam \pll_inst|auto_generated|pll1 .charge_pump_current_bits = 1;
defparam \pll_inst|auto_generated|pll1 .clk0_counter = "c0";
defparam \pll_inst|auto_generated|pll1 .clk0_divide_by = 1;
defparam \pll_inst|auto_generated|pll1 .clk0_duty_cycle = 50;
defparam \pll_inst|auto_generated|pll1 .clk0_multiply_by = 13;
defparam \pll_inst|auto_generated|pll1 .clk0_phase_shift = 0;
defparam \pll_inst|auto_generated|pll1 .clk1_counter = "unused";
defparam \pll_inst|auto_generated|pll1 .clk1_divide_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk1_duty_cycle = 50;
defparam \pll_inst|auto_generated|pll1 .clk1_multiply_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk1_phase_shift = 0;
defparam \pll_inst|auto_generated|pll1 .clk2_counter = "unused";
defparam \pll_inst|auto_generated|pll1 .clk2_divide_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk2_duty_cycle = 50;
defparam \pll_inst|auto_generated|pll1 .clk2_multiply_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk2_phase_shift = 0;
defparam \pll_inst|auto_generated|pll1 .clk3_counter = "unused";
defparam \pll_inst|auto_generated|pll1 .clk3_divide_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk3_duty_cycle = 50;
defparam \pll_inst|auto_generated|pll1 .clk3_multiply_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk3_phase_shift = 0;
defparam \pll_inst|auto_generated|pll1 .clk4_counter = "unused";
defparam \pll_inst|auto_generated|pll1 .clk4_divide_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk4_duty_cycle = 50;
defparam \pll_inst|auto_generated|pll1 .clk4_multiply_by = 0;
defparam \pll_inst|auto_generated|pll1 .clk4_phase_shift = 0;
defparam \pll_inst|auto_generated|pll1 .compensate_clock = "clock0";
defparam \pll_inst|auto_generated|pll1 .inclk0_input_frequency = 125000;
defparam \pll_inst|auto_generated|pll1 .inclk1_input_frequency = 0;
defparam \pll_inst|auto_generated|pll1 .loop_filter_c_bits = 0;
defparam \pll_inst|auto_generated|pll1 .loop_filter_r_bits = 20;
defparam \pll_inst|auto_generated|pll1 .m = 39;
defparam \pll_inst|auto_generated|pll1 .m_initial = 1;
defparam \pll_inst|auto_generated|pll1 .m_ph = 0;
defparam \pll_inst|auto_generated|pll1 .n = 1;
defparam \pll_inst|auto_generated|pll1 .operation_mode = "normal";
defparam \pll_inst|auto_generated|pll1 .pfd_max = 200000;
defparam \pll_inst|auto_generated|pll1 .pfd_min = 3076;
defparam \pll_inst|auto_generated|pll1 .pll_compensation_delay = 7538;
defparam \pll_inst|auto_generated|pll1 .self_reset_on_loss_lock = "off";
defparam \pll_inst|auto_generated|pll1 .simulation_type = "timing";
defparam \pll_inst|auto_generated|pll1 .switch_over_type = "auto";
defparam \pll_inst|auto_generated|pll1 .vco_center = 1538;
defparam \pll_inst|auto_generated|pll1 .vco_divide_by = 0;
defparam \pll_inst|auto_generated|pll1 .vco_frequency_control = "auto";
defparam \pll_inst|auto_generated|pll1 .vco_max = 3333;
defparam \pll_inst|auto_generated|pll1 .vco_min = 1538;
defparam \pll_inst|auto_generated|pll1 .vco_multiply_by = 0;
defparam \pll_inst|auto_generated|pll1 .vco_phase_shift_step = 400;
defparam \pll_inst|auto_generated|pll1 .vco_post_scale = 2;

endmodule