9102_BOOT/logic/quartus_logs/fpga_boot.sta.rpt

TimeQuest Timing Analyzer report for fpga_boot
Sat May 09 16:12:21 2026
Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI'
 15. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE'
 16. Clock to Output Times
 17. Minimum Clock to Output Times
 18. Slow 1200mV 85C Model Metastability Report
 19. Slow 1200mV 0C Model Fmax Summary
 20. Slow 1200mV 0C Model Setup Summary
 21. Slow 1200mV 0C Model Hold Summary
 22. Slow 1200mV 0C Model Recovery Summary
 23. Slow 1200mV 0C Model Removal Summary
 24. Slow 1200mV 0C Model Minimum Pulse Width Summary
 25. Slow 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN'
 26. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
 27. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
 28. Clock to Output Times
 29. Minimum Clock to Output Times
 30. Slow 1200mV 0C Model Metastability Report
 31. Fast 1200mV 0C Model Setup Summary
 32. Fast 1200mV 0C Model Hold Summary
 33. Fast 1200mV 0C Model Recovery Summary
 34. Fast 1200mV 0C Model Removal Summary
 35. Fast 1200mV 0C Model Minimum Pulse Width Summary
 36. Fast 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN'
 37. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
 38. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
 39. Clock to Output Times
 40. Minimum Clock to Output Times
 41. Fast 1200mV 0C Model Metastability Report
 42. Multicorner Timing Analysis Summary
 43. Clock to Output Times
 44. Minimum Clock to Output Times
 45. Board Trace Model Assignments
 46. Input Transition Times
 47. Signal Integrity Metrics (Slow 1200mv 0c Model)
 48. Signal Integrity Metrics (Slow 1200mv 85c Model)
 49. Signal Integrity Metrics (Fast 1200mv 0c Model)
 50. Clock Transfers
 51. Report TCCS
 52. Report RSKM
 53. Unconstrained Paths
 54. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Full Version ;
; Revision Name      ; fpga_boot                                           ;
; Device Family      ; Cyclone IV E                                        ;
; Device Name        ; EP4CE75F29C8                                        ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ; < 0.1%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; fpga_boot.sdc ; OK     ; Sat May 09 16:12:20 2026 ;
+---------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                           ;
+-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+
; Clock Name                          ; Type      ; Period  ; Frequency ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master    ; Source                                ; Targets                                 ;
+-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+
; PIN_HSE                             ; Base      ; 125.000 ; 8.0 MHz   ; 0.000 ; 62.500 ;            ;           ;             ;       ;        ;           ;            ;          ;           ;                                       ; { PIN_HSE }                             ;
; PIN_HSI                             ; Base      ; 100.000 ; 10.0 MHz  ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;           ;                                       ; { PIN_HSI }                             ;
; PLL_CLKIN                           ; Base      ; 125.000 ; 8.0 MHz   ; 0.000 ; 62.500 ;            ;           ;             ;       ;        ;           ;            ;          ;           ;                                       ; { PLL_CLKIN }                           ;
; pll_inst|auto_generated|pll1|clk[0] ; Generated ; 9.615   ; 104.0 MHz ; 0.000 ; 4.807  ; 50.00      ; 1         ; 13          ;       ;        ;           ;            ; false    ; PLL_CLKIN ; pll_inst|auto_generated|pll1|inclk[0] ; { pll_inst|auto_generated|pll1|clk[0] } ;
+-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+


--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+-----------+---------+-----------------------------+
; Clock     ; Slack   ; End Point TNS               ;
+-----------+---------+-----------------------------+
; PLL_CLKIN ; 62.371  ; 0.000                       ;
; PIN_HSI   ; 96.000  ; 0.000                       ;
; PIN_HSE   ; 121.000 ; 0.000                       ;
+-----------+---------+-----------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN'                                                                              ;
+---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock     ; Clock Edge ; Target                                        ;
+---------+------