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|
- Fitter report for fpga_boot
- Sat May 09 16:12:18 2026
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. I/O Assignment Warnings
- 6. Ignored Assignments
- 7. Incremental Compilation Preservation Summary
- 8. Incremental Compilation Partition Settings
- 9. Incremental Compilation Placement Preservation
- 10. Incremental Compilation LogicLock Region Preservation
- 11. Pin-Out File
- 12. Fitter Resource Usage Summary
- 13. LogicLock Region Resource Usage
- 14. Fitter Partition Statistics
- 15. Input Pins
- 16. Output Pins
- 17. Bidir Pins
- 18. Dual Purpose and Dedicated Pins
- 19. I/O Bank Usage
- 20. All Package Pins
- 21. PLL Summary
- 22. PLL Usage
- 23. Fitter Resource Utilization by Entity
- 24. Delay Chain Summary
- 25. Pad To Core Delay Chain Fanout
- 26. Control Signals
- 27. Global & Other Fast Signals
- 28. Non-Global High Fan-Out Signals
- 29. Other Routing Usage Summary
- 30. LAB Logic Elements
- 31. LAB-wide Signals
- 32. LAB Signals Sourced
- 33. LAB Signals Sourced Out
- 34. LAB Distinct Inputs
- 35. I/O Rules Summary
- 36. I/O Rules Details
- 37. I/O Rules Matrix
- 38. Fitter Device Options
- 39. Operating Settings and Conditions
- 40. Fitter Messages
- 41. Fitter Suppressed Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +----------------------------------------------------------------------------------+
- ; Fitter Summary ;
- +------------------------------------+---------------------------------------------+
- ; Fitter Status ; Successful - Sat May 09 16:12:18 2026 ;
- ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
- ; Revision Name ; fpga_boot ;
- ; Top-level Entity Name ; fpga_boot ;
- ; Family ; Cyclone IV E ;
- ; Device ; EP4CE75F29C8 ;
- ; Timing Models ; Final ;
- ; Total logic elements ; 44 / 75,408 ( < 1 % ) ;
- ; Total combinational functions ; 44 / 75,408 ( < 1 % ) ;
- ; Dedicated logic registers ; 1 / 75,408 ( < 1 % ) ;
- ; Total registers ; 1 ;
- ; Total pins ; 15 / 427 ( 4 % ) ;
- ; Total virtual pins ; 1 ;
- ; Total memory bits ; 0 / 2,810,880 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 400 ( 0 % ) ;
- ; Total PLLs ; 1 / 4 ( 25 % ) ;
- +------------------------------------+---------------------------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Settings ;
- +----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- ; Option ; Setting ; Default Value ;
- +----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- ; Device ; EP4CE75F29C8 ; ;
- ; Maximum processors allowed for parallel compilation ; All ; ;
- ; Minimum Core Junction Temperature ; 0 ; ;
- ; Maximum Core Junction Temperature ; 85 ; ;
- ; Router Timing Optimization Level ; MAXIMUM ; Normal ;
- ; Placement Effort Multiplier ; 10 ; 1.0 ;
- ; Router Effort Multiplier ; 10 ; 1.0 ;
- ; Fit Attempts to Skip ; 0 ; 0.0 ;
- ; Device I/O Standard ; 3.3-V LVTTL ; ;
- ; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; All Paths ;
- ; Optimize Timing for ECOs ; On ; Off ;
- ; Final Placement Optimizations ; Always ; Automatically ;
- ; Fitter Aggressive Routability Optimizations ; Always ; Automatically ;
- ; Perform Physical Synthesis for Combinational Logic for Fitting ; On ; Off ;
- ; Perform Physical Synthesis for Combinational Logic for Performance ; On ; Off ;
- ; Fitter Effort ; Standard Fit ; Auto Fit ;
- ; Physical Synthesis Effort Level ; Extra ; Normal ;
- ; Maximum number of global clocks allowed ; 6 ; -1 (Unlimited) ;
- ; Use smart compilation ; Off ; Off ;
- ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
- ; Enable compact report table ; Off ; Off ;
- ; Auto Merge PLLs ; On ; On ;
- ; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
- ; Optimize Multi-Corner Timing ; On ; On ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; SSN Optimization ; Off ; Off ;
- ; Optimize Timing ; Normal compilation ; Normal compilation ;
- ; Regenerate full fit report during ECO compiles ; Off ; Off ;
- ; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
- ; Limit to One Fitting Attempt ; Off ; Off ;
- ; Fitter Initial Placement Seed ; 1 ; 1 ;
- ; PCI I/O ; Off ; Off ;
- ; Weak Pull-Up Resistor ; Off ; Off ;
- ; Enable Bus-Hold Circuitry ; Off ; Off ;
- ; Auto Packed Registers ; Auto ; Auto ;
- ; Auto Delay Chains ; On ; On ;
- ; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
- ; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
- ; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
- ; Perform Register Duplication for Performance ; Off ; Off ;
- ; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
- ; Perform Register Retiming for Performance ; Off ; Off ;
- ; Perform Asynchronous Signal Pipelining ; Off ; Off ;
- ; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
- ; Auto Register Duplication ; Auto ; Auto ;
- ; Auto Global Clock ; On ; On ;
- ; Auto Global Register Control Signals ; On ; On ;
- ; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
- ; Synchronizer Identification ; Off ; Off ;
- ; Enable Beneficial Skew Optimization ; On ; On ;
- ; Optimize Design for Metastability ; On ; On ;
- ; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
- ; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
- +----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
- +------------------------------------------+
- ; Parallel Compilation ;
- +----------------------------+-------------+
- ; Processors ; Number ;
- +----------------------------+-------------+
- ; Number detected on machine ; 8 ;
- ; Maximum allowed ; 4 ;
- ; ; ;
- ; Average used ; 2.41 ;
- ; Maximum used ; 4 ;
- ; ; ;
- ; Usage by Processor ; % Time Used ;
- ; Processor 1 ; 100.0% ;
- ; Processors 2-4 ; 47.1% ;
- ; Processors 5-8 ; 0.0% ;
- +----------------------------+-------------+
- +----------------------------------------+
- ; I/O Assignment Warnings ;
- +---------------+------------------------+
- ; Pin Name ; Reason ;
- +---------------+------------------------+
- ; SPI0_CSN ; Missing drive strength ;
- ; SPI0_SCK ; Missing drive strength ;
- ; UART0_UARTTXD ; Missing drive strength ;
- ; BAUD_RATE ; Missing drive strength ;
- ; GPIO4_1 ; Missing drive strength ;
- ; GPIO4_2 ; Missing drive strength ;
- ; SPI0_SI_IO0 ; Missing drive strength ;
- ; TEST_SINGLE ; Missing drive strength ;
- ; UART1_RX ; Missing drive strength ;
- ; UART1_TX ; Missing drive strength ;
- ; so_io1 ; Missing drive strength ;
- +---------------+------------------------+
- +------------------------------------------------------------------------------------------------------------+
- ; Ignored Assignments ;
- +---------------+----------------+--------------+----------------------+--------------------+----------------+
- ; Name ; Ignored Entity ; Ignored From ; Ignored To ; Ignored Value ; Ignored Source ;
- +---------------+----------------+--------------+----------------------+--------------------+----------------+
- ; Location ; ; ; dmactive ; LCCOMB_X53_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACBREQ[0] ; LCCOMB_X52_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACBREQ[1] ; LCCOMB_X52_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACBREQ[2] ; LCCOMB_X52_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACBREQ[3] ; LCCOMB_X52_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACCLR[0] ; LCCOMB_X54_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACCLR[1] ; LCCOMB_X54_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACCLR[2] ; LCCOMB_X54_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACCLR[3] ; LCCOMB_X54_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLBREQ[0] ; LCCOMB_X52_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLBREQ[1] ; LCCOMB_X52_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLBREQ[2] ; LCCOMB_X52_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLBREQ[3] ; LCCOMB_X52_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLSREQ[0] ; LCCOMB_X53_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLSREQ[1] ; LCCOMB_X53_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLSREQ[2] ; LCCOMB_X53_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACLSREQ[3] ; LCCOMB_X53_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACSREQ[0] ; LCCOMB_X53_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACSREQ[1] ; LCCOMB_X53_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACSREQ[2] ; LCCOMB_X53_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACSREQ[3] ; LCCOMB_X53_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACTC[0] ; LCCOMB_X54_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACTC[1] ; LCCOMB_X54_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACTC[2] ; LCCOMB_X54_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; ext_dma_DMACTC[3] ; LCCOMB_X54_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; ext_int[0] ; LCCOMB_X51_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; ext_int[1] ; LCCOMB_X51_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; ext_int[2] ; LCCOMB_X51_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; ext_int[3] ; LCCOMB_X51_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; ext_int[4] ; LCCOMB_X51_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; ext_int[5] ; LCCOMB_X51_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; ext_int[6] ; LCCOMB_X51_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; ext_int[7] ; LCCOMB_X51_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; ext_resetn ; LCCOMB_X51_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[1] ; LCCOMB_X57_Y7_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[2] ; LCCOMB_X57_Y7_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[3] ; LCCOMB_X57_Y7_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[4] ; LCCOMB_X57_Y7_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[5] ; LCCOMB_X57_Y7_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[6] ; LCCOMB_X57_Y7_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_data[7] ; LCCOMB_X57_Y7_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[1] ; LCCOMB_X57_Y7_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[2] ; LCCOMB_X58_Y7_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[3] ; LCCOMB_X58_Y7_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[4] ; LCCOMB_X57_Y6_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[5] ; LCCOMB_X57_Y6_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[6] ; LCCOMB_X57_Y6_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio0_io_out_en[7] ; LCCOMB_X57_Y6_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[0] ; LCCOMB_X56_Y5_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[1] ; LCCOMB_X56_Y5_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[2] ; LCCOMB_X56_Y5_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[3] ; LCCOMB_X56_Y5_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[4] ; LCCOMB_X56_Y5_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[5] ; LCCOMB_X56_Y5_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[6] ; LCCOMB_X56_Y5_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_in[7] ; LCCOMB_X56_Y5_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[0] ; LCCOMB_X57_Y6_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[1] ; LCCOMB_X57_Y6_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[2] ; LCCOMB_X57_Y6_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[3] ; LCCOMB_X57_Y6_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[4] ; LCCOMB_X57_Y6_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[5] ; LCCOMB_X57_Y6_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[6] ; LCCOMB_X57_Y6_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_data[7] ; LCCOMB_X57_Y6_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[0] ; LCCOMB_X57_Y6_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[1] ; LCCOMB_X57_Y6_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[2] ; LCCOMB_X57_Y6_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[3] ; LCCOMB_X57_Y6_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[4] ; LCCOMB_X58_Y6_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[5] ; LCCOMB_X58_Y6_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[6] ; LCCOMB_X58_Y6_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio1_io_out_en[7] ; LCCOMB_X58_Y6_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[0] ; LCCOMB_X43_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[1] ; LCCOMB_X43_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[2] ; LCCOMB_X43_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[3] ; LCCOMB_X43_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[4] ; LCCOMB_X43_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[5] ; LCCOMB_X43_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[6] ; LCCOMB_X43_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_in[7] ; LCCOMB_X43_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[0] ; LCCOMB_X57_Y5_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[1] ; LCCOMB_X57_Y5_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[2] ; LCCOMB_X57_Y5_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[3] ; LCCOMB_X57_Y5_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[4] ; LCCOMB_X57_Y5_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[5] ; LCCOMB_X57_Y5_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[6] ; LCCOMB_X57_Y5_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_data[7] ; LCCOMB_X57_Y5_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[0] ; LCCOMB_X58_Y5_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[1] ; LCCOMB_X58_Y5_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[2] ; LCCOMB_X58_Y5_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[3] ; LCCOMB_X43_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[4] ; LCCOMB_X43_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[5] ; LCCOMB_X43_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[6] ; LCCOMB_X43_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio2_io_out_en[7] ; LCCOMB_X43_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[0] ; LCCOMB_X44_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[1] ; LCCOMB_X44_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[2] ; LCCOMB_X44_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[3] ; LCCOMB_X44_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[4] ; LCCOMB_X44_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[5] ; LCCOMB_X44_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[6] ; LCCOMB_X44_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_in[7] ; LCCOMB_X44_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[0] ; LCCOMB_X43_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[1] ; LCCOMB_X43_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[2] ; LCCOMB_X43_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[3] ; LCCOMB_X43_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[4] ; LCCOMB_X43_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[5] ; LCCOMB_X43_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[6] ; LCCOMB_X43_Y3_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_data[7] ; LCCOMB_X44_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[0] ; LCCOMB_X44_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[1] ; LCCOMB_X44_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[2] ; LCCOMB_X44_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[3] ; LCCOMB_X44_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[4] ; LCCOMB_X44_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[5] ; LCCOMB_X44_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[6] ; LCCOMB_X44_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio3_io_out_en[7] ; LCCOMB_X44_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_data[0] ; LCCOMB_X44_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_data[3] ; LCCOMB_X45_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_data[4] ; LCCOMB_X45_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_data[7] ; LCCOMB_X45_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_en[0] ; LCCOMB_X45_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_en[3] ; LCCOMB_X45_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_en[4] ; LCCOMB_X45_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio4_io_out_en[7] ; LCCOMB_X46_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[0] ; LCCOMB_X46_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[1] ; LCCOMB_X46_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[2] ; LCCOMB_X46_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[3] ; LCCOMB_X46_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[4] ; LCCOMB_X46_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[5] ; LCCOMB_X46_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[6] ; LCCOMB_X46_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_in[7] ; LCCOMB_X46_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[0] ; LCCOMB_X46_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[1] ; LCCOMB_X46_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[2] ; LCCOMB_X46_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[3] ; LCCOMB_X46_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[4] ; LCCOMB_X46_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[5] ; LCCOMB_X46_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[6] ; LCCOMB_X46_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_data[7] ; LCCOMB_X46_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[0] ; LCCOMB_X46_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[1] ; LCCOMB_X46_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[2] ; LCCOMB_X46_Y3_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[3] ; LCCOMB_X47_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[4] ; LCCOMB_X47_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[5] ; LCCOMB_X47_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[6] ; LCCOMB_X47_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio5_io_out_en[7] ; LCCOMB_X47_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[0] ; LCCOMB_X47_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[1] ; LCCOMB_X47_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[2] ; LCCOMB_X47_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[3] ; LCCOMB_X47_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[4] ; LCCOMB_X47_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[5] ; LCCOMB_X47_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[6] ; LCCOMB_X48_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_data[7] ; LCCOMB_X48_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[0] ; LCCOMB_X48_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[1] ; LCCOMB_X48_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[2] ; LCCOMB_X48_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[3] ; LCCOMB_X48_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[4] ; LCCOMB_X48_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[5] ; LCCOMB_X48_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[6] ; LCCOMB_X48_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio6_io_out_en[7] ; LCCOMB_X48_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[0] ; LCCOMB_X48_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[1] ; LCCOMB_X48_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[2] ; LCCOMB_X48_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[3] ; LCCOMB_X48_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[4] ; LCCOMB_X48_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[5] ; LCCOMB_X48_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[6] ; LCCOMB_X48_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_in[7] ; LCCOMB_X48_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[0] ; LCCOMB_X48_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[1] ; LCCOMB_X49_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[2] ; LCCOMB_X49_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[3] ; LCCOMB_X49_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[4] ; LCCOMB_X49_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[5] ; LCCOMB_X49_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_data[7] ; LCCOMB_X49_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[0] ; LCCOMB_X49_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[1] ; LCCOMB_X49_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[2] ; LCCOMB_X49_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[3] ; LCCOMB_X49_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[4] ; LCCOMB_X50_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[5] ; LCCOMB_X50_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio7_io_out_en[7] ; LCCOMB_X50_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[0] ; LCCOMB_X49_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[1] ; LCCOMB_X49_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[2] ; LCCOMB_X49_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[3] ; LCCOMB_X49_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[4] ; LCCOMB_X49_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[5] ; LCCOMB_X49_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[6] ; LCCOMB_X49_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_in[7] ; LCCOMB_X49_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[0] ; LCCOMB_X50_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[1] ; LCCOMB_X50_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[2] ; LCCOMB_X50_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[3] ; LCCOMB_X50_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[4] ; LCCOMB_X50_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[5] ; LCCOMB_X50_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[6] ; LCCOMB_X50_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_data[7] ; LCCOMB_X50_Y3_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[0] ; LCCOMB_X51_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[1] ; LCCOMB_X51_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[2] ; LCCOMB_X51_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[3] ; LCCOMB_X51_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[4] ; LCCOMB_X51_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[5] ; LCCOMB_X51_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[6] ; LCCOMB_X51_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio8_io_out_en[7] ; LCCOMB_X51_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[0] ; LCCOMB_X50_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[1] ; LCCOMB_X50_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[2] ; LCCOMB_X50_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[3] ; LCCOMB_X50_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[4] ; LCCOMB_X50_Y4_N8 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[5] ; LCCOMB_X50_Y4_N10 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[6] ; LCCOMB_X50_Y4_N12 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_in[7] ; LCCOMB_X50_Y4_N14 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[0] ; LCCOMB_X51_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[1] ; LCCOMB_X51_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[2] ; LCCOMB_X51_Y3_N6 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[3] ; LCCOMB_X52_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[4] ; LCCOMB_X52_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[5] ; LCCOMB_X52_Y4_N20 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[6] ; LCCOMB_X52_Y4_N22 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_data[7] ; LCCOMB_X52_Y4_N24 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[0] ; LCCOMB_X52_Y4_N26 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[1] ; LCCOMB_X52_Y4_N28 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[2] ; LCCOMB_X52_Y4_N30 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[3] ; LCCOMB_X52_Y3_N0 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[4] ; LCCOMB_X52_Y3_N2 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[5] ; LCCOMB_X52_Y3_N4 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[6] ; LCCOMB_X53_Y4_N16 ; QSF Assignment ;
- ; Location ; ; ; gpio9_io_out_en[7] ; LCCOMB_X53_Y4_N18 ; QSF Assignment ;
- ; Location ; ; ; local_int[0] ; LCCOMB_X54_Y4_N0 ; QSF Assignment ;
- ; Location ; ; ; local_int[1] ; LCCOMB_X54_Y4_N2 ; QSF Assignment ;
- ; Location ; ; ; local_int[2] ; LCCOMB_X54_Y4_N4 ; QSF Assignment ;
- ; Location ; ; ; local_int[3] ; LCCOMB_X54_Y4_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[0] ; LCCOMB_X57_Y12_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[10] ; LCCOMB_X57_Y11_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[11] ; LCCOMB_X57_Y11_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[12] ; LCCOMB_X57_Y11_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[13] ; LCCOMB_X57_Y11_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[14] ; LCCOMB_X57_Y11_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[15] ; LCCOMB_X57_Y11_N16 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[16] ; LCCOMB_X57_Y11_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[17] ; LCCOMB_X57_Y11_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[18] ; LCCOMB_X57_Y11_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[19] ; LCCOMB_X57_Y11_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[1] ; LCCOMB_X57_Y12_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[20] ; LCCOMB_X57_Y11_N26 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[21] ; LCCOMB_X57_Y11_N28 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[22] ; LCCOMB_X57_Y11_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[23] ; LCCOMB_X58_Y11_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[24] ; LCCOMB_X58_Y11_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[25] ; LCCOMB_X58_Y11_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[26] ; LCCOMB_X58_Y11_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[27] ; LCCOMB_X58_Y11_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[28] ; LCCOMB_X58_Y11_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[29] ; LCCOMB_X58_Y11_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[2] ; LCCOMB_X57_Y12_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[30] ; LCCOMB_X56_Y10_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[31] ; LCCOMB_X57_Y10_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[3] ; LCCOMB_X57_Y12_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[4] ; LCCOMB_X57_Y12_N26 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[5] ; LCCOMB_X57_Y12_N28 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[6] ; LCCOMB_X57_Y12_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[7] ; LCCOMB_X58_Y12_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[8] ; LCCOMB_X58_Y12_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_haddr[9] ; LCCOMB_X58_Y12_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hburst[0] ; LCCOMB_X57_Y12_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hburst[1] ; LCCOMB_X57_Y12_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hburst[2] ; LCCOMB_X57_Y12_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[0] ; LCCOMB_X56_Y12_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[10] ; LCCOMB_X56_Y12_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[11] ; LCCOMB_X56_Y12_N26 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[12] ; LCCOMB_X56_Y12_N28 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[13] ; LCCOMB_X56_Y11_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[14] ; LCCOMB_X56_Y11_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[15] ; LCCOMB_X56_Y11_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[16] ; LCCOMB_X56_Y11_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[17] ; LCCOMB_X56_Y11_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[18] ; LCCOMB_X56_Y11_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[19] ; LCCOMB_X56_Y11_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[1] ; LCCOMB_X56_Y12_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[20] ; LCCOMB_X56_Y11_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[21] ; LCCOMB_X56_Y11_N16 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[22] ; LCCOMB_X56_Y11_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[23] ; LCCOMB_X56_Y11_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[24] ; LCCOMB_X56_Y11_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[25] ; LCCOMB_X56_Y11_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[26] ; LCCOMB_X56_Y11_N26 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[27] ; LCCOMB_X56_Y11_N28 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[28] ; LCCOMB_X56_Y11_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[29] ; LCCOMB_X57_Y11_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[2] ; LCCOMB_X56_Y12_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[30] ; LCCOMB_X57_Y11_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[31] ; LCCOMB_X57_Y11_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[3] ; LCCOMB_X56_Y12_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[4] ; LCCOMB_X56_Y12_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[5] ; LCCOMB_X56_Y12_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[6] ; LCCOMB_X56_Y12_N16 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[7] ; LCCOMB_X56_Y12_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[8] ; LCCOMB_X56_Y12_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hrdata[9] ; LCCOMB_X56_Y12_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hready ; LCCOMB_X56_Y12_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hreadyout ; LCCOMB_X56_Y12_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hresp ; LCCOMB_X56_Y12_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hsize[0] ; LCCOMB_X57_Y12_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hsize[1] ; LCCOMB_X57_Y12_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hsize[2] ; LCCOMB_X57_Y12_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_htrans[0] ; LCCOMB_X57_Y12_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_htrans[1] ; LCCOMB_X57_Y12_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[0] ; LCCOMB_X57_Y10_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[10] ; LCCOMB_X57_Y10_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[11] ; LCCOMB_X57_Y10_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[12] ; LCCOMB_X57_Y10_N26 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[13] ; LCCOMB_X57_Y10_N28 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[14] ; LCCOMB_X57_Y10_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[15] ; LCCOMB_X58_Y10_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[16] ; LCCOMB_X58_Y10_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[17] ; LCCOMB_X58_Y10_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[18] ; LCCOMB_X56_Y9_N30 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[19] ; LCCOMB_X57_Y9_N0 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[1] ; LCCOMB_X57_Y10_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[20] ; LCCOMB_X57_Y9_N2 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[21] ; LCCOMB_X57_Y9_N4 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[22] ; LCCOMB_X57_Y9_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[23] ; LCCOMB_X57_Y9_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[24] ; LCCOMB_X57_Y9_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[25] ; LCCOMB_X57_Y9_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[26] ; LCCOMB_X57_Y9_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[27] ; LCCOMB_X57_Y9_N16 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[28] ; LCCOMB_X57_Y9_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[29] ; LCCOMB_X57_Y9_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[2] ; LCCOMB_X57_Y10_N6 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[30] ; LCCOMB_X57_Y9_N22 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[31] ; LCCOMB_X57_Y9_N24 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[3] ; LCCOMB_X57_Y10_N8 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[4] ; LCCOMB_X57_Y10_N10 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[5] ; LCCOMB_X57_Y10_N12 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[6] ; LCCOMB_X57_Y10_N14 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[7] ; LCCOMB_X57_Y10_N16 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[8] ; LCCOMB_X57_Y10_N18 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwdata[9] ; LCCOMB_X57_Y10_N20 ; QSF Assignment ;
- ; Location ; ; ; mem_ahb_hwrite ; LCCOMB_X57_Y12_N16 ; QSF Assignment ;
- ; Location ; ; ; resetn_out ; LCCOMB_X58_Y5_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[0] ; LCCOMB_X56_Y10_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[10] ; LCCOMB_X56_Y9_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[11] ; LCCOMB_X56_Y9_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[12] ; LCCOMB_X56_Y9_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[13] ; LCCOMB_X56_Y9_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[14] ; LCCOMB_X56_Y9_N20 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[15] ; LCCOMB_X56_Y9_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[16] ; LCCOMB_X56_Y9_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[17] ; LCCOMB_X56_Y9_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[18] ; LCCOMB_X56_Y9_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[19] ; LCCOMB_X56_Y8_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[1] ; LCCOMB_X56_Y10_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[20] ; LCCOMB_X56_Y8_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[21] ; LCCOMB_X56_Y8_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[22] ; LCCOMB_X56_Y8_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[23] ; LCCOMB_X56_Y8_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[24] ; LCCOMB_X56_Y8_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[25] ; LCCOMB_X56_Y8_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[26] ; LCCOMB_X56_Y8_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[27] ; LCCOMB_X56_Y8_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[28] ; LCCOMB_X56_Y8_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[29] ; LCCOMB_X56_Y8_N20 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[2] ; LCCOMB_X56_Y10_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[30] ; LCCOMB_X56_Y8_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[31] ; LCCOMB_X56_Y8_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[3] ; LCCOMB_X56_Y10_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[4] ; LCCOMB_X56_Y9_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[5] ; LCCOMB_X56_Y9_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[6] ; LCCOMB_X56_Y9_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[7] ; LCCOMB_X56_Y9_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[8] ; LCCOMB_X56_Y9_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_haddr[9] ; LCCOMB_X56_Y9_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hburst[0] ; LCCOMB_X56_Y10_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hburst[1] ; LCCOMB_X56_Y10_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hburst[2] ; LCCOMB_X56_Y10_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[0] ; LCCOMB_X57_Y9_N30 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[10] ; LCCOMB_X57_Y8_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[11] ; LCCOMB_X57_Y8_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[12] ; LCCOMB_X57_Y8_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[13] ; LCCOMB_X57_Y8_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[14] ; LCCOMB_X57_Y8_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[15] ; LCCOMB_X57_Y8_N20 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[16] ; LCCOMB_X57_Y8_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[17] ; LCCOMB_X57_Y8_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[18] ; LCCOMB_X57_Y8_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[19] ; LCCOMB_X57_Y8_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[1] ; LCCOMB_X58_Y9_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[20] ; LCCOMB_X57_Y8_N30 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[21] ; LCCOMB_X58_Y8_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[22] ; LCCOMB_X58_Y8_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[23] ; LCCOMB_X58_Y8_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[24] ; LCCOMB_X56_Y7_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[25] ; LCCOMB_X56_Y7_N30 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[26] ; LCCOMB_X57_Y7_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[27] ; LCCOMB_X57_Y7_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[28] ; LCCOMB_X57_Y7_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[29] ; LCCOMB_X57_Y7_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[2] ; LCCOMB_X58_Y9_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[30] ; LCCOMB_X57_Y7_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[31] ; LCCOMB_X57_Y7_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[3] ; LCCOMB_X58_Y9_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[4] ; LCCOMB_X56_Y8_N30 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[5] ; LCCOMB_X57_Y8_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[6] ; LCCOMB_X57_Y8_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[7] ; LCCOMB_X57_Y8_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[8] ; LCCOMB_X57_Y8_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hrdata[9] ; LCCOMB_X57_Y8_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hready ; LCCOMB_X56_Y10_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hreadyout ; LCCOMB_X57_Y9_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hresp ; LCCOMB_X57_Y9_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hsel ; LCCOMB_X56_Y10_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hsize[0] ; LCCOMB_X56_Y10_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hsize[1] ; LCCOMB_X56_Y10_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hsize[2] ; LCCOMB_X56_Y10_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_htrans[0] ; LCCOMB_X56_Y10_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_htrans[1] ; LCCOMB_X56_Y10_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[0] ; LCCOMB_X56_Y8_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[10] ; LCCOMB_X56_Y7_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[11] ; LCCOMB_X56_Y7_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[12] ; LCCOMB_X56_Y7_N20 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[13] ; LCCOMB_X56_Y7_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[14] ; LCCOMB_X56_Y7_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[15] ; LCCOMB_X56_Y7_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[16] ; LCCOMB_X56_Y6_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[17] ; LCCOMB_X56_Y6_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[18] ; LCCOMB_X56_Y6_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[19] ; LCCOMB_X56_Y6_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[1] ; LCCOMB_X56_Y8_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[20] ; LCCOMB_X56_Y6_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[21] ; LCCOMB_X56_Y6_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[22] ; LCCOMB_X56_Y6_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[23] ; LCCOMB_X56_Y6_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[24] ; LCCOMB_X56_Y6_N16 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[25] ; LCCOMB_X56_Y6_N18 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[26] ; LCCOMB_X56_Y6_N20 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[27] ; LCCOMB_X56_Y6_N22 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[28] ; LCCOMB_X56_Y6_N24 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[29] ; LCCOMB_X56_Y6_N26 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[2] ; LCCOMB_X56_Y7_N0 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[30] ; LCCOMB_X56_Y6_N28 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[31] ; LCCOMB_X56_Y6_N30 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[3] ; LCCOMB_X56_Y7_N2 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[4] ; LCCOMB_X56_Y7_N4 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[5] ; LCCOMB_X56_Y7_N6 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[6] ; LCCOMB_X56_Y7_N8 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[7] ; LCCOMB_X56_Y7_N10 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[8] ; LCCOMB_X56_Y7_N12 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwdata[9] ; LCCOMB_X56_Y7_N14 ; QSF Assignment ;
- ; Location ; ; ; slave_ahb_hwrite ; LCCOMB_X56_Y10_N20 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_hseBypass ; LCCOMB_X57_Y5_N6 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_hseEnable ; LCCOMB_X57_Y5_N4 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_pllEnable ; LCCOMB_X57_Y5_N8 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_sleep ; LCCOMB_X57_Y5_N10 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_standby ; LCCOMB_X57_Y5_N14 ; QSF Assignment ;
- ; Location ; ; ; sys_ctrl_stop ; LCCOMB_X57_Y5_N12 ; QSF Assignment ;
- ; Location ; ; ; usb0_id ; LCCOMB_X54_Y4_N10 ; QSF Assignment ;
- ; Global Signal ; fpga_boot ; ; sys_resetn ; GLOBAL_CLOCK ; QSF Assignment ;
- +---------------+----------------+--------------+----------------------+--------------------+----------------+
- +----------------------------------------------+
- ; Incremental Compilation Preservation Summary ;
- +---------------------+------------------------+
- ; Type ; Value ;
- +---------------------+------------------------+
- ; Placement (by node) ; ;
- ; -- Requested ; 0 / 97 ( 0.00 % ) ;
- ; -- Achieved ; 0 / 97 ( 0.00 % ) ;
- ; ; ;
- ; Routing (by net) ; ;
- ; -- Requested ; 0 / 0 ( 0.00 % ) ;
- ; -- Achieved ; 0 / 0 ( 0.00 % ) ;
- +---------------------+------------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Incremental Compilation Partition Settings ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- ; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- ; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
- ; rv32 ; User-created ; Source File ; N/A ; Source File ; N/A ; alta_rv32:rv32 ;
- ; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
- +--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
- +------------------------------------------------------------------------------------------------------------+
- ; Incremental Compilation Placement Preservation ;
- +--------------------------------+---------+-------------------+-------------------------+-------------------+
- ; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
- +--------------------------------+---------+-------------------+-------------------------+-------------------+
- ; Top ; 83 ; 0 ; N/A ; Source File ;
- ; rv32 ; 2 ; 0 ; N/A ; Source File ;
- ; hard_block:auto_generated_inst ; 12 ; 0 ; N/A ; Source File ;
- +--------------------------------+---------+-------------------+-------------------------+-------------------+
- +----------------------------------------------------------------------------------------------------------------------------------------------+
- ; Incremental Compilation LogicLock Region Preservation ;
- +-----------------+------------+------------------+-----------------+------------------+------------------+-----------------+------------------+
- ; Region Name ; Partitions ; Requested Origin ; Requested Width ; Requested Height ; Effective Origin ; Effective Width ; Effective Height ;
- +-----------------+------------+------------------+-----------------+------------------+------------------+-----------------+------------------+
- ; LOGIC_RESERVE_0 ; ; X43_Y5 ; 13 ; 8 ; X43_Y5 ; 13 ; 8 ;
- ; core_logic ; Top, rv32 ; X43_Y1 ; 20 ; 12 ; X43_Y1 ; 20 ; 12 ;
- +-----------------+------------+------------------+-----------------+------------------+------------------+-----------------+------------------+
- Note: The effective origin and size are the region properties taking into account any post-fit logic assigned to the LogicLock region.
- +--------------+
- ; Pin-Out File ;
- +--------------+
- The pin-out file can be found in D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/quartus_logs/fpga_boot.pin.
- +---------------------------------------------------------------------+
- ; Fitter Resource Usage Summary ;
- +---------------------------------------------+-----------------------+
- ; Resource ; Usage ;
- +---------------------------------------------+-----------------------+
- ; Total logic elements ; 44 / 75,408 ( < 1 % ) ;
- ; -- Combinational with no register ; 43 ;
- ; -- Register only ; 0 ;
- ; -- Combinational with a register ; 1 ;
- ; ; ;
- ; Logic element usage by number of LUT inputs ; ;
- ; -- 4 input functions ; 0 ;
- ; -- 3 input functions ; 0 ;
- ; -- <=2 input functions ; 44 ;
- ; -- Register only ; 0 ;
- ; ; ;
- ; Logic elements by mode ; ;
- ; -- normal mode ; 44 ;
- ; -- arithmetic mode ; 0 ;
- ; ; ;
- ; Total registers* ; 1 / 77,471 ( < 1 % ) ;
- ; -- Dedicated logic registers ; 1 / 75,408 ( < 1 % ) ;
- ; -- I/O registers ; 0 / 2,063 ( 0 % ) ;
- ; ; ;
- ; Total LABs: partially or completely used ; 12 / 4,713 ( < 1 % ) ;
- ; Virtual pins ; 1 ;
- ; I/O pins ; 15 / 427 ( 4 % ) ;
- ; -- Clock pins ; 2 / 7 ( 29 % ) ;
- ; -- Dedicated input pins ; 0 / 9 ( 0 % ) ;
- ; ; ;
- ; Global signals ; 2 ;
- ; M9Ks ; 0 / 305 ( 0 % ) ;
- ; Total block memory bits ; 0 / 2,810,880 ( 0 % ) ;
- ; Total block memory implementation bits ; 0 / 2,810,880 ( 0 % ) ;
- ; Embedded Multiplier 9-bit elements ; 0 / 400 ( 0 % ) ;
- ; PLLs ; 1 / 4 ( 25 % ) ;
- ; Global clocks ; 2 / 20 ( 10 % ) ;
- ; JTAGs ; 0 / 1 ( 0 % ) ;
- ; CRC blocks ; 0 / 1 ( 0 % ) ;
- ; ASMI blocks ; 0 / 1 ( 0 % ) ;
- ; Impedance control blocks ; 0 / 4 ( 0 % ) ;
- ; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ;
- ; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ;
- ; Maximum fan-out ; 12 ;
- ; Highest non-global fan-out ; 12 ;
- ; Total fan-out ; 73 ;
- ; Average fan-out ; 0.75 ;
- +---------------------------------------------+-----------------------+
- * Register count does not include registers inside RAM blocks or DSP blocks.
- +---------------------------------------------------------------------------------------------------------+
- ; LogicLock Region Resource Usage ;
- +---------------------------------------------+-------------------+------------------+--------------------+
- ; Statistic ; Root Region ; LOGIC_RESERVE_0 ; core_logic ;
- +---------------------------------------------+-------------------+------------------+--------------------+
- ; Difficulty Clustering Region ; Low ; Low ; Low ;
- ; ; ; ; ;
- ; Total logic elements ; 0 / 75408 ( 0 % ) ; 0 / 1536 ( 0 % ) ; 44 / 3648 ( 1 % ) ;
- ; -- Combinational with no register ; 0 ; 0 ; 43 ;
- ; -- Register only ; 0 ; 0 ; 0 ;
- ; -- Combinational with a register ; 0 ; 0 ; 1 ;
- ; ; ; ; ;
- ; Logic element usage by number of LUT inputs ; ; ; ;
- ; -- 4 input functions ; 0 ; 0 ; 0 ;
- ; -- 3 input functions ; 0 ; 0 ; 0 ;
- ; -- <=2 input functions ; 0 ; 0 ; 44 ;
- ; -- Register only ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Logic elements by mode ; ; ; ;
- ; -- normal mode ; 0 ; 0 ; 44 ;
- ; -- arithmetic mode ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Total registers ; 0 ; 0 ; 1 ;
- ; -- Dedicated logic registers ; 0 / 75408 ( 0 % ) ; 0 / 1536 ( 0 % ) ; 1 / 3648 ( < 1 % ) ;
- ; ; ; ; ;
- ; Total LABs: partially or completely used ; 0 / 4713 ( 0 % ) ; 0 / 96 ( 0 % ) ; 11 / 228 ( 5 % ) ;
- ; ; ; ; ;
- ; Virtual pins ; 0 ; 0 ; 1 ;
- ; I/O pins ; 15 ; 0 ; 0 ;
- ; Embedded Multiplier 9-bit elements ; 0 / 400 ( 0 % ) ; 0 ; 0 ;
- ; Total memory bits ; 0 ; 0 ; 0 ;
- ; Total RAM block bits ; 0 ; 0 ; 0 ;
- ; PLL ; 1 / 4 ( 25 % ) ; 0 ; 0 ;
- ; Clock control block ; 2 / 24 ( 8 % ) ; 0 ; 0 ;
- ; ; ; ; ;
- ; Connections ; ; ; ;
- ; -- Input Connections ; 15 ; 0 ; 8 ;
- ; -- Registered Input Connections ; 0 ; 0 ; 2 ;
- ; -- Output Connections ; 8 ; 0 ; 15 ;
- ; -- Registered Output Connections ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Internal Connections ; ; ; ;
- ; -- Total Connections ; 56 ; 0 ; 40 ;
- ; -- Registered Connections ; 0 ; 0 ; 3 ;
- ; ; ; ; ;
- ; External Connections ; ; ; ;
- ; -- Root Region ; 0 ; 0 ; 23 ;
- ; -- LOGIC_RESERVE_0 ; 0 ; 0 ; 0 ;
- ; -- core_logic ; 23 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Region Placement ; ; ; ;
- ; -- Origin ; -- ; X43_Y5 ; X43_Y1 ;
- ; -- Width ; -- ; 13 ; 20 ;
- ; -- Height ; -- ; 8 ; 12 ;
- +---------------------------------------------+-------------------+------------------+--------------------+
- +---------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Partition Statistics ;
- +---------------------------------------------+----------------------+---------------------+--------------------------------+
- ; Statistic ; Top ; rv32 ; hard_block:auto_generated_inst ;
- +---------------------------------------------+----------------------+---------------------+--------------------------------+
- ; Difficulty Clustering Region ; Low ; Low ; Low ;
- ; ; ; ; ;
- ; Total logic elements ; 43 / 75408 ( < 1 % ) ; 1 / 75408 ( < 1 % ) ; 0 / 75408 ( 0 % ) ;
- ; -- Combinational with no register ; 42 ; 1 ; 0 ;
- ; -- Register only ; 0 ; 0 ; 0 ;
- ; -- Combinational with a register ; 1 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Logic element usage by number of LUT inputs ; ; ; ;
- ; -- 4 input functions ; 0 ; 0 ; 0 ;
- ; -- 3 input functions ; 0 ; 0 ; 0 ;
- ; -- <=2 input functions ; 43 ; 1 ; 0 ;
- ; -- Register only ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Logic elements by mode ; ; ; ;
- ; -- normal mode ; 43 ; 1 ; 0 ;
- ; -- arithmetic mode ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Total registers ; 1 ; 0 ; 0 ;
- ; -- Dedicated logic registers ; 1 / 75408 ( < 1 % ) ; 0 / 75408 ( 0 % ) ; 0 / 75408 ( 0 % ) ;
- ; ; ; ; ;
- ; Total LABs: partially or completely used ; 11 / 4713 ( < 1 % ) ; 1 / 4713 ( < 1 % ) ; 0 / 4713 ( 0 % ) ;
- ; ; ; ; ;
- ; Virtual pins ; 0 ; 1 ; 0 ;
- ; I/O pins ; 15 ; 0 ; 0 ;
- ; Embedded Multiplier 9-bit elements ; 0 / 400 ( 0 % ) ; 0 / 400 ( 0 % ) ; 0 / 400 ( 0 % ) ;
- ; Total memory bits ; 0 ; 0 ; 0 ;
- ; Total RAM block bits ; 0 ; 0 ; 0 ;
- ; PLL ; 0 / 4 ( 0 % ) ; 0 / 4 ( 0 % ) ; 1 / 4 ( 25 % ) ;
- ; Clock control block ; 1 / 24 ( 4 % ) ; 0 / 24 ( 0 % ) ; 1 / 24 ( 4 % ) ;
- ; ; ; ; ;
- ; Connections ; ; ; ;
- ; -- Input Connections ; 25 ; 1 ; 5 ;
- ; -- Registered Input Connections ; 1 ; 0 ; 0 ;
- ; -- Output Connections ; 16 ; 12 ; 3 ;
- ; -- Registered Output Connections ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Internal Connections ; ; ; ;
- ; -- Total Connections ; 65 ; 13 ; 15 ;
- ; -- Registered Connections ; 2 ; 0 ; 0 ;
- ; ; ; ; ;
- ; External Connections ; ; ; ;
- ; -- Top ; 22 ; 12 ; 7 ;
- ; -- rv32 ; 12 ; 0 ; 1 ;
- ; -- hard_block:auto_generated_inst ; 7 ; 1 ; 0 ;
- ; ; ; ; ;
- ; Partition Interface ; ; ; ;
- ; -- Input Ports ; 4 ; 224 ; 5 ;
- ; -- Output Ports ; 3 ; 295 ; 2 ;
- ; -- Bidir Ports ; 8 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Registered Ports ; ; ; ;
- ; -- Registered Input Ports ; 0 ; 0 ; 0 ;
- ; -- Registered Output Ports ; 0 ; 0 ; 0 ;
- ; ; ; ; ;
- ; Port Connectivity ; ; ; ;
- ; -- Input Ports driven by GND ; 0 ; 213 ; 0 ;
- ; -- Output Ports driven by GND ; 0 ; 170 ; 0 ;
- ; -- Input Ports driven by VCC ; 0 ; 5 ; 0 ;
- ; -- Output Ports driven by VCC ; 0 ; 0 ; 0 ;
- ; -- Input Ports with no Source ; 0 ; 0 ; 0 ;
- ; -- Output Ports with no Source ; 0 ; 0 ; 0 ;
- ; -- Input Ports with no Fanout ; 0 ; 150 ; 0 ;
- ; -- Output Ports with no Fanout ; 0 ; 280 ; 0 ;
- +---------------------------------------------+----------------------+---------------------+--------------------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Input Pins ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
- ; PIN_HSE ; AB17 ; 4 ; 76 ; 0 ; 0 ; 0 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; Fitter ;
- ; PIN_HSI ; Y2 ; 2 ; 0 ; 30 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; Fitter ;
- ; PLL_CLKIN ; J1 ; 1 ; 0 ; 30 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; Fitter ;
- ; UART0_UARTRXD ; AG12 ; 3 ; 47 ; 0 ; 7 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 3.3-V LVTTL ; -- ; Fitter ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+
- +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Output Pins ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- ; SPI0_CSN ; AD12 ; 3 ; 45 ; 0 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
- ; SPI0_SCK ; AE13 ; 3 ; 43 ; 0 ; 7 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
- ; UART0_UARTTXD ; AC15 ; 4 ; 51 ; 0 ; 21 ; no ; no ; no ; 2 ; yes ; no ; yes ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; no ; no ; Fitter ; - ; - ;
- +---------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Bidir Pins ;
- +-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-------------------------------+---------------------+
- ; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Output Termination ; Termination Control Block ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
- +-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-------------------------------+---------------------+
- ; BAUD_RATE ; F10 ; 8 ; 16 ; 62 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; - ; - ;
- ; GPIO4_1 ; AE14 ; 3 ; 45 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; gpio4_io_out_en[1] (inverted) ; - ;
- ; GPIO4_2 ; AB13 ; 3 ; 45 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; gpio4_io_out_en[2] (inverted) ; - ;
- ; SPI0_SI_IO0 ; AA15 ; 4 ; 56 ; 0 ; 14 ; 1 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; gpio0_io_out_en[0] (inverted) ; - ;
- ; TEST_SINGLE ; H5 ; 1 ; 0 ; 47 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; - ; - ;
- ; UART1_RX ; AG26 ; 4 ; 92 ; 0 ; 7 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; - ; - ;
- ; UART1_TX ; B3 ; 8 ; 5 ; 62 ; 0 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; - ; - ;
- ; so_io1 ; AB16 ; 4 ; 56 ; 0 ; 21 ; 0 ; 0 ; no ; no ; no ; no ; no ; 2 ; yes ; no ; no ; Off ; 3.3-V LVTTL ; 8mA ; Off ; -- ; Fitter ; 0 pF ; - ; - ;
- +-------------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+------------------------+---------------+-----------+-----------------+------------+----------+--------------+--------------+------------------+--------------------+---------------------------+----------------------+------+-------------------------------+---------------------+
- +-------------------------------------------------------------------------------------------------------------------------+
- ; Dual Purpose and Dedicated Pins ;
- +----------+-----------------------------+--------------------------+-------------------------+---------------------------+
- ; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
- +----------+-----------------------------+--------------------------+-------------------------+---------------------------+
- ; F4 ; DIFFIO_L5n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
- ; E2 ; DIFFIO_L8p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
- ; M6 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
- ; P3 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
- ; N7 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
- ; P4 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
- ; R8 ; nCE ; - ; - ; Dedicated Programming Pin ;
- ; P24 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
- ; N22 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
- ; P23 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
- ; M22 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
- ; P22 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
- ; P28 ; DIFFIO_R19n, nCEO ; Use as programming pin ; ~ALTERA_nCEO~ ; Dual Purpose Pin ;
- +----------+-----------------------------+--------------------------+-------------------------+---------------------------+
- +-----------------------------------------------------------+
- ; I/O Bank Usage ;
- +----------+-----------------+---------------+--------------+
- ; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
- +----------+-----------------+---------------+--------------+
- ; 1 ; 6 / 45 ( 13 % ) ; 3.3V ; -- ;
- ; 2 ; 1 / 49 ( 2 % ) ; 3.3V ; -- ;
- ; 3 ; 5 / 59 ( 8 % ) ; 3.3V ; -- ;
- ; 4 ; 5 / 58 ( 9 % ) ; 3.3V ; -- ;
- ; 5 ; 0 / 52 ( 0 % ) ; 3.3V ; -- ;
- ; 6 ; 1 / 48 ( 2 % ) ; 3.3V ; -- ;
- ; 7 ; 0 / 59 ( 0 % ) ; 3.3V ; -- ;
- ; 8 ; 2 / 57 ( 4 % ) ; 3.3V ; -- ;
- +----------+-----------------+---------------+--------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; All Package Pins ;
- +----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
- +----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- ; A2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A3 ; 435 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A4 ; 432 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A5 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A6 ; 412 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A7 ; 409 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A8 ; 418 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A10 ; 399 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A11 ; 397 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A12 ; 392 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A14 ; 384 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; A15 ; 382 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; A16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A17 ; 377 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A18 ; 365 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A19 ; 363 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A20 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A21 ; 350 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A22 ; 348 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A23 ; 337 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A24 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; A25 ; 330 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A26 ; 329 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; A27 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AA1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AA3 ; 90 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AA4 ; 89 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AA5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA8 ; 129 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AA9 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AA10 ; 130 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AA11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AA12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA15 ; 173 ; 4 ; SPI0_SI_IO0 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AA16 ; 171 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AA17 ; 201 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AA18 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AA19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA20 ; ; ; GNDA4 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AA21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA22 ; 223 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AA23 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AA24 ; 226 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; AA25 ; 240 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AA26 ; 239 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AA27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AA28 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AB1 ; 74 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB2 ; 73 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB3 ; 87 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB4 ; 96 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; AB5 ; 102 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB6 ; 101 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB7 ; 127 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AB8 ; 123 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AB9 ; 122 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AB10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB11 ; 139 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AB12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB13 ; 154 ; 3 ; GPIO4_2 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AB14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB16 ; 172 ; 4 ; so_io1 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AB17 ; 202 ; 4 ; PIN_HSE ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AB18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB20 ; 211 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AB21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AB23 ; 224 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB24 ; 222 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB25 ; 238 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB26 ; 237 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB27 ; 242 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AB28 ; 241 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC1 ; 82 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC2 ; 81 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC3 ; 83 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC4 ; 100 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC5 ; 99 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC7 ; 119 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AC8 ; 128 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AC9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AC11 ; 148 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AC12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AC13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AC15 ; 164 ; 4 ; UART0_UARTTXD ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC17 ; 181 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AC18 ; 200 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AC19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AC20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC21 ; 212 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AC22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AC23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AC24 ; 221 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC25 ; 220 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC26 ; 228 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC27 ; 236 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AC28 ; 235 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD1 ; 86 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD2 ; 85 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD3 ; 84 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD4 ; 105 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD5 ; 103 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD7 ; 109 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD8 ; 118 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD10 ; 124 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD11 ; 149 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD12 ; 155 ; 3 ; SPI0_CSN ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AD13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AD15 ; 165 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD17 ; 182 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD18 ; 197 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AD20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD21 ; 213 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AD23 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AD24 ; 217 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD25 ; 209 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AD26 ; 227 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD27 ; 232 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AD28 ; 231 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AE1 ; 94 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AE2 ; 93 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AE3 ; 97 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AE4 ; 107 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE5 ; 110 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE6 ; 104 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE7 ; 133 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE8 ; 136 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE9 ; 138 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE10 ; 140 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE11 ; 146 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE12 ; 144 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE13 ; 152 ; 3 ; SPI0_SCK ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AE14 ; 156 ; 3 ; GPIO4_1 ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AE15 ; 166 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE16 ; 174 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE17 ; 175 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE18 ; 185 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE19 ; 191 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE20 ; 195 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE21 ; 198 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE22 ; 207 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE23 ; 215 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE24 ; 210 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE25 ; 203 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AE26 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; AE27 ; 230 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AE28 ; 229 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AF2 ; 98 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AF3 ; 113 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF4 ; 106 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF5 ; 111 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF6 ; 114 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF7 ; 134 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF8 ; 137 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF9 ; 135 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF10 ; 141 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF11 ; 147 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF12 ; 145 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF13 ; 153 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF14 ; 157 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF15 ; 167 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF16 ; 170 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF17 ; 176 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF18 ; 186 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF19 ; 192 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF20 ; 196 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF21 ; 199 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF22 ; 208 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF23 ; 216 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF24 ; 193 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF25 ; 194 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF26 ; 204 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AF27 ; 225 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; AF28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AG2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG3 ; 108 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG4 ; 116 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG6 ; 120 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG7 ; 125 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG8 ; 131 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG10 ; 142 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG11 ; 150 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG12 ; 158 ; 3 ; UART0_UARTRXD ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AG13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG14 ; 160 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AG15 ; 162 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AG16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG17 ; 168 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG18 ; 177 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG19 ; 179 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG21 ; 183 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG22 ; 187 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG23 ; 189 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG25 ; 205 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AG26 ; 218 ; 4 ; UART1_RX ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; AG27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; AG28 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH3 ; 112 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH4 ; 117 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH5 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH6 ; 121 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH7 ; 126 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH8 ; 132 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH10 ; 143 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH11 ; 151 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH12 ; 159 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH13 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH14 ; 161 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AH15 ; 163 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; AH16 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH17 ; 169 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH18 ; 178 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH19 ; 180 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH20 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH21 ; 184 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH22 ; 188 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH23 ; 190 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH24 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; AH25 ; 206 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH26 ; 219 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; AH27 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; B1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B3 ; 434 ; 8 ; UART1_TX ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; B4 ; 433 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B6 ; 413 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B7 ; 410 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B8 ; 419 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B10 ; 400 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B11 ; 398 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B14 ; 385 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; B15 ; 383 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ;
- ; B16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B17 ; 378 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B18 ; 366 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B19 ; 364 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B21 ; 351 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B22 ; 349 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B23 ; 338 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B25 ; 331 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B26 ; 326 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; B27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; B28 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; C2 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; C3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; C4 ; 439 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C5 ; 437 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C6 ; 436 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C7 ; 422 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C8 ; 420 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C9 ; 416 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C10 ; 403 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C11 ; 414 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C12 ; 390 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C13 ; 386 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C14 ; 388 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C15 ; 380 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C16 ; 375 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C17 ; 361 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C18 ; 354 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C19 ; 358 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C20 ; 356 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C21 ; 347 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C22 ; 343 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C23 ; 339 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C24 ; 341 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C25 ; 336 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C26 ; 325 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; C27 ; 316 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; C28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; D1 ; 3 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; D2 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; D4 ; 440 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D5 ; 438 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D6 ; 424 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D7 ; 423 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D8 ; 421 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D9 ; 417 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D10 ; 404 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D11 ; 415 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D12 ; 391 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D13 ; 387 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D14 ; 389 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D15 ; 381 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D16 ; 376 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D17 ; 362 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D18 ; 355 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D19 ; 359 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D20 ; 357 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D21 ; 344 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D22 ; 327 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D23 ; 340 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D24 ; 342 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D25 ; 335 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; D26 ; 317 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; D27 ; 315 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; D28 ; 314 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; E1 ; 17 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; E2 ; 16 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
- ; E3 ; 7 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; E4 ; 441 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E5 ; 430 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E7 ; 431 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E8 ; 428 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E10 ; 426 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E11 ; 407 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E12 ; 405 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E13 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E14 ; 396 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E15 ; 379 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E16 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E17 ; 373 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E18 ; 352 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E19 ; 346 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E20 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E21 ; 332 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E22 ; 328 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E23 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; E24 ; 370 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E25 ; 369 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; E26 ; 313 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; E27 ; 309 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; E28 ; 308 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F1 ; 19 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F2 ; 18 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F3 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F4 ; 10 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
- ; F5 ; 9 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; F8 ; 429 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F10 ; 427 ; 8 ; BAUD_RATE ; bidir ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ;
- ; F11 ; 408 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F12 ; 406 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F14 ; 395 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F15 ; 367 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F17 ; 371 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F18 ; 353 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F19 ; 345 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F21 ; 333 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; F22 ; 334 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; F23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; F24 ; 324 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F25 ; 323 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F26 ; 311 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F27 ; 307 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; F28 ; 306 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G1 ; 26 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G2 ; 25 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G3 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G4 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G5 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G6 ; 5 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G9 ; 425 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; G10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G11 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G12 ; 411 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; G13 ; 401 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; G14 ; 394 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; G15 ; 374 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; G16 ; 368 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; G17 ; 360 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; G18 ; 372 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; G19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G23 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G24 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; G25 ; 321 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G26 ; 320 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G27 ; 301 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; G28 ; 300 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H3 ; 15 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H4 ; 14 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H5 ; 20 ; 1 ; TEST_SINGLE ; bidir ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; H6 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H7 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; H8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H9 ; ; ; GNDA3 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; H12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H13 ; 402 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; H14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H18 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; H19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H20 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; H23 ; 319 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H24 ; 318 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H25 ; 312 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H26 ; 310 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; H27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; H28 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; J1 ; 53 ; 1 ; PLL_CLKIN ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J3 ; 23 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; J4 ; 22 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J8 ; ; -- ; VCCA3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; J9 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; J10 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; J19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J20 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; J21 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; J22 ; 322 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; J23 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J24 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; J25 ; 299 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; J26 ; 298 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; J27 ; 273 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; J28 ; 272 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; K1 ; 28 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K2 ; 27 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K3 ; 30 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K4 ; 29 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; K6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; K22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; K23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; K24 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; K25 ; 305 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K26 ; 304 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K27 ; 296 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; K28 ; 295 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L1 ; 38 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L2 ; 37 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L3 ; 32 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L4 ; 31 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L5 ; 21 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; L6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; L8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; L9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; L20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; L21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; L22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; L23 ; 294 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L24 ; 293 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L25 ; 303 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L26 ; 297 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L27 ; 292 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; L28 ; 291 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M1 ; 40 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M2 ; 39 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M3 ; 34 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M4 ; 33 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M5 ; 36 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; M6 ; 24 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
- ; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; M21 ; 302 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; M22 ; 277 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
- ; M23 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; M24 ; 281 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M25 ; 290 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M26 ; 289 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M27 ; 288 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; M28 ; 287 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; N1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N3 ; 43 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; N4 ; 35 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; N5 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N7 ; 45 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
- ; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; N21 ; 282 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; N22 ; 275 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
- ; N23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N24 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; N25 ; 286 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; N26 ; 285 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; N27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; N28 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; P1 ; 42 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; P2 ; 41 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; P3 ; 44 ; 1 ; ~ALTERA_DCLK~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ;
- ; P4 ; 46 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
- ; P5 ; 48 ; 1 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
- ; P6 ; 50 ; 1 ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
- ; P7 ; 47 ; 1 ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
- ; P8 ; 49 ; 1 ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
- ; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; P22 ; 278 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
- ; P23 ; 276 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
- ; P24 ; 274 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
- ; P25 ; 280 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; P26 ; 279 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; P27 ; 284 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; P28 ; 283 ; 6 ; ~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; R1 ; 57 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R2 ; 56 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R3 ; 61 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R4 ; 62 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R5 ; 65 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R6 ; 58 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; R8 ; 51 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
- ; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; R20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; R21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; R22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; R23 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; R24 ; 269 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R25 ; 266 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R26 ; 265 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R27 ; 268 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; R28 ; 267 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T3 ; 64 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T4 ; 63 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; T6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T7 ; 66 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; T8 ; 88 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; T9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T21 ; 264 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T22 ; 263 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T24 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; T25 ; 262 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T26 ; 257 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; T28 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; U1 ; 68 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U2 ; 67 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U3 ; 59 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U4 ; 60 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U5 ; 78 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U6 ; 77 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U7 ; 91 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U8 ; 92 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; U20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; U21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; U22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; U23 ; 251 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; U24 ; 260 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
- ; U25 ; 259 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U26 ; 258 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U27 ; 256 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; U28 ; 261 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V1 ; 72 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V2 ; 71 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V3 ; 70 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V4 ; 69 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V15 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V17 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V19 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; V20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; V21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; V23 ; 255 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V24 ; 254 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V25 ; 253 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V26 ; 252 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V27 ; 250 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; V28 ; 249 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W1 ; 76 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W2 ; 75 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W3 ; 95 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; W5 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; W8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W16 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W18 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W20 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; W21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; W22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; W23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; W24 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
- ; W25 ; 246 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W26 ; 245 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W27 ; 247 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; W28 ; 248 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y1 ; 55 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; Y2 ; 54 ; 2 ; PIN_HSI ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ;
- ; Y3 ; 80 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y4 ; 79 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y8 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; Y9 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; Y10 ; 115 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
- ; Y11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; Y12 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y13 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
- ; Y19 ; 214 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
- ; Y20 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
- ; Y21 ; ; -- ; VCCA4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
- ; Y22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ;
- ; Y23 ; 234 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y24 ; 233 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y25 ; 244 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y26 ; 243 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
- ; Y27 ; 271 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- ; Y28 ; 270 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
- +----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
- Note: Pin directions (input, output or bidir) are based on device operating in user mode.
- +---------------------------------------------------------------------------------+
- ; PLL Summary ;
- +-------------------------------+-------------------------------------------------+
- ; Name ; altpll:pll_inst|altpll_6o32:auto_generated|pll1 ;
- +-------------------------------+-------------------------------------------------+
- ; SDC pin name ; pll_inst|auto_generated|pll1 ;
- ; PLL mode ; Normal ;
- ; Compensate clock ; clock0 ;
- ; Compensated input/output pins ; -- ;
- ; Switchover type ; -- ;
- ; Input frequency 0 ; 8.0 MHz ;
- ; Input frequency 1 ; -- ;
- ; Nominal PFD frequency ; 8.0 MHz ;
- ; Nominal VCO frequency ; 312.0 MHz ;
- ; VCO post scale K counter ; 2 ;
- ; VCO frequency control ; Auto ;
- ; VCO phase shift step ; 400 ps ;
- ; VCO multiply ; -- ;
- ; VCO divide ; -- ;
- ; Freq min lock ; 7.69 MHz ;
- ; Freq max lock ; 16.67 MHz ;
- ; M VCO Tap ; 0 ;
- ; M Initial ; 1 ;
- ; M value ; 39 ;
- ; N value ; 1 ;
- ; Charge pump current ; setting 1 ;
- ; Loop filter resistance ; setting 20 ;
- ; Loop filter capacitance ; setting 0 ;
- ; Bandwidth ; 450 kHz to 590 kHz ;
- ; Bandwidth type ; Medium ;
- ; Real time reconfigurable ; Off ;
- ; Scan chain MIF file ; -- ;
- ; Preserve PLL counter order ; Off ;
- ; PLL location ; PLL_1 ;
- ; Inclk0 signal ; PLL_CLKIN ;
- ; Inclk1 signal ; -- ;
- ; Inclk0 signal type ; Dedicated Pin ;
- ; Inclk1 signal type ; -- ;
- +-------------------------------+-------------------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; PLL Usage ;
- +---------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------+
- ; Name ; Output Clock ; Mult ; Div ; Output Frequency ; Phase Shift ; Phase Shift Step ; Duty Cycle ; Counter ; Counter Value ; High / Low ; Cascade Input ; Initial ; VCO Tap ; SDC Pin Name ;
- +---------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------+
- ; altpll:pll_inst|altpll_6o32:auto_generated|clk[0] ; clock0 ; 13 ; 1 ; 104.0 MHz ; 0 (0 ps) ; 15.00 (400 ps) ; 50/50 ; C0 ; 3 ; 2/1 Odd ; -- ; 1 ; 0 ; pll_inst|auto_generated|pll1|clk[0] ;
- +---------------------------------------------------+--------------+------+-----+------------------+-------------+------------------+------------+---------+---------------+------------+---------------+---------+---------+-------------------------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Fitter Resource Utilization by Entity ;
- +------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
- ; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ;
- +------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
- ; |fpga_boot ; 44 (42) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 1 ; 43 (42) ; 0 (0) ; 1 (0) ; |fpga_boot ; ;
- ; |alta_gclksw:gclksw_inst| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |fpga_boot|alta_gclksw:gclksw_inst ; ;
- ; |alta_rv32:rv32| ; 1 (1) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 ; 1 (1) ; 0 (0) ; 0 (0) ; |fpga_boot|alta_rv32:rv32 ; ;
- ; |altpll:pll_inst| ; 1 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (0) ; |fpga_boot|altpll:pll_inst ; ;
- ; |altpll_6o32:auto_generated| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |fpga_boot|altpll:pll_inst|altpll_6o32:auto_generated ; ;
- +------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-------------------------------------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-----------------------------------------------------------------------------------------------+
- ; Delay Chain Summary ;
- +---------------+----------+---------------+---------------+-----------------------+-----+------+
- ; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
- +---------------+----------+---------------+---------------+-----------------------+-----+------+
- ; PIN_HSE ; Input ; -- ; -- ; -- ; -- ; -- ;
- ; SPI0_CSN ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; SPI0_SCK ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; UART0_UARTTXD ; Output ; -- ; -- ; -- ; -- ; -- ;
- ; BAUD_RATE ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; GPIO4_1 ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
- ; GPIO4_2 ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
- ; SPI0_SI_IO0 ; Bidir ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
- ; TEST_SINGLE ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; UART1_RX ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; UART1_TX ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; so_io1 ; Bidir ; -- ; -- ; -- ; -- ; -- ;
- ; UART0_UARTRXD ; Input ; (6) 1314 ps ; -- ; -- ; -- ; -- ;
- ; PIN_HSI ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
- ; PLL_CLKIN ; Input ; -- ; -- ; -- ; -- ; -- ;
- +---------------+----------+---------------+---------------+-----------------------+-----+------+
- +-----------------------------------------------------+
- ; Pad To Core Delay Chain Fanout ;
- +-----------------------+-------------------+---------+
- ; Source Pin / Fanout ; Pad To Core Index ; Setting ;
- +-----------------------+-------------------+---------+
- ; PIN_HSE ; ; ;
- ; BAUD_RATE ; ; ;
- ; GPIO4_1 ; ; ;
- ; - gpio4_io_in[1] ; 0 ; 6 ;
- ; GPIO4_2 ; ; ;
- ; - gpio4_io_in[2] ; 0 ; 6 ;
- ; SPI0_SI_IO0 ; ; ;
- ; - gpio0_io_in[0] ; 0 ; 6 ;
- ; TEST_SINGLE ; ; ;
- ; UART1_RX ; ; ;
- ; UART1_TX ; ; ;
- ; so_io1 ; ; ;
- ; UART0_UARTRXD ; ; ;
- ; - gpio6_io_in[1] ; 0 ; 6 ;
- ; PIN_HSI ; ; ;
- ; PLL_CLKIN ; ; ;
- +-----------------------+-------------------+---------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Control Signals ;
- +--------------------------------------------------------+-------------------+---------+---------------+--------+----------------------+------------------+---------------------------+---------------+---------------+---------------+---------------+----------------+----------------+
- ; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; Input Clock 0 ; Input Clock 1 ; Input Clock 2 ; Input Clock 3 ; Clock Select 0 ; Clock Select 1 ;
- +--------------------------------------------------------+-------------------+---------+---------------+--------+----------------------+------------------+---------------------------+---------------+---------------+---------------+---------------+----------------+----------------+
- ; PIN_HSI ; PIN_Y2 ; 1 ; Clock ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; PLL_CLKIN ; PIN_J1 ; 1 ; Clock ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; PLL_ENABLE ; LCCOMB_X49_Y1_N28 ; 2 ; Async. clear ; yes ; Global Clock ; GCLK15 ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|clk[0] ; PLL_1 ; 1 ; Clock ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|pll1~LOCKED ; PLL_1 ; 2 ; Clock ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio0_io_out_en[0] ; LCCOMB_X57_Y7_N28 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio4_io_out_en[1] ; LCCOMB_X45_Y4_N28 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio4_io_out_en[2] ; LCCOMB_X45_Y4_N30 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio4_io_out_en[5] ; LCCOMB_X45_Y3_N4 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio4_io_out_en[6] ; LCCOMB_X45_Y3_N6 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; gpio7_io_out_en[6] ; LCCOMB_X50_Y4_N20 ; 1 ; Output enable ; no ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- +--------------------------------------------------------+-------------------+---------+---------------+--------+----------------------+------------------+---------------------------+---------------+---------------+---------------+---------------+----------------+----------------+
- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Global & Other Fast Signals ;
- +--------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+---------------+---------------+---------------------------------------------------+---------------+-----------------------+-----------------------+
- ; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; Input Clock 0 ; Input Clock 1 ; Input Clock 2 ; Input Clock 3 ; Clock Select 0 ; Clock Select 1 ;
- +--------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+---------------+---------------+---------------------------------------------------+---------------+-----------------------+-----------------------+
- ; PLL_ENABLE ; LCCOMB_X49_Y1_N28 ; 2 ; 0 ; Global Clock ; GCLK15 ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
- ; alta_gclksw:gclksw_inst|clkout ; CLKCTRL_G3 ; 1 ; 0 ; Global Clock ; GCLK3 ; VCC ; PIN_HSI ; -- ; altpll:pll_inst|altpll_6o32:auto_generated|clk[0] ; -- ; sys_ctrl_clkSource[0] ; sys_ctrl_clkSource[1] ;
- +--------------------------------+-------------------+---------+--------------------------------------+----------------------+------------------+---------------------------+---------------+---------------+---------------------------------------------------+---------------+-----------------------+-----------------------+
- +---------------------------------------------------------------------------+
- ; Non-Global High Fan-Out Signals ;
- +-----------------------------------------------------------------+---------+
- ; Name ; Fan-Out ;
- +-----------------------------------------------------------------+---------+
- ; alta_rv32:rv32|~GND ; 12 ;
- ; PLL_LOCK ; 2 ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|pll1~LOCKED ; 2 ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|pll_lock_sync~feeder ; 1 ;
- ; PLL_CLKIN~input ; 1 ;
- ; PIN_HSI~input ; 1 ;
- ; UART0_UARTRXD~input ; 1 ;
- ; SPI0_SI_IO0~input ; 1 ;
- ; GPIO4_2~input ; 1 ;
- ; GPIO4_1~input ; 1 ;
- ; ~VCC ; 1 ;
- ; gpio0_io_out_en[0] ; 1 ;
- ; gpio0_io_out_data[0] ; 1 ;
- ; gpio4_io_out_en[2] ; 1 ;
- ; gpio4_io_out_data[2] ; 1 ;
- ; gpio4_io_out_en[1] ; 1 ;
- ; gpio4_io_out_data[1] ; 1 ;
- ; sys_ctrl_clkSource[1] ; 1 ;
- ; sys_ctrl_clkSource[0] ; 1 ;
- ; gpio7_io_out_en[6] ; 1 ;
- ; gpio7_io_out_data[6] ; 1 ;
- ; gpio4_io_out_en[5] ; 1 ;
- ; gpio4_io_out_data[5] ; 1 ;
- ; gpio4_io_out_en[6] ; 1 ;
- ; gpio4_io_out_data[6] ; 1 ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|pll_lock_sync ; 1 ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|clk[0] ; 1 ;
- ; altpll:pll_inst|altpll_6o32:auto_generated|pll1~FBOUT ; 1 ;
- +-----------------------------------------------------------------+---------+
- +------------------------------------------------------+
- ; Other Routing Usage Summary ;
- +-----------------------------+------------------------+
- ; Other Routing Resource Type ; Usage ;
- +-----------------------------+------------------------+
- ; Block interconnects ; 28 / 238,469 ( < 1 % ) ;
- ; C16 interconnects ; 2 / 7,238 ( < 1 % ) ;
- ; C4 interconnects ; 38 / 146,424 ( < 1 % ) ;
- ; Global clocks ; 2 / 20 ( 10 % ) ;
- ; Local interconnects ; 4 / 81,264 ( < 1 % ) ;
- ; R24 interconnects ; 6 / 7,153 ( < 1 % ) ;
- ; R4 interconnects ; 23 / 201,722 ( < 1 % ) ;
- +-----------------------------+------------------------+
- +---------------------------------------------------------------------------+
- ; LAB Logic Elements ;
- +--------------------------------------------+------------------------------+
- ; Number of Logic Elements (Average = 3.75) ; Number of LABs (Total = 12) ;
- +--------------------------------------------+------------------------------+
- ; 1 ; 4 ;
- ; 2 ; 2 ;
- ; 3 ; 3 ;
- ; 4 ; 0 ;
- ; 5 ; 0 ;
- ; 6 ; 0 ;
- ; 7 ; 0 ;
- ; 8 ; 2 ;
- ; 9 ; 0 ;
- ; 10 ; 0 ;
- ; 11 ; 0 ;
- ; 12 ; 1 ;
- ; 13 ; 0 ;
- ; 14 ; 0 ;
- ; 15 ; 0 ;
- ; 16 ; 0 ;
- +--------------------------------------------+------------------------------+
- +-------------------------------------------------------------------+
- ; LAB-wide Signals ;
- +------------------------------------+------------------------------+
- ; LAB-wide Signals (Average = 0.08) ; Number of LABs (Total = 12) ;
- +------------------------------------+------------------------------+
- ; 1 Async. clear ; 1 ;
- +------------------------------------+------------------------------+
- +----------------------------------------------------------------------------+
- ; LAB Signals Sourced ;
- +---------------------------------------------+------------------------------+
- ; Number of Signals Sourced (Average = 1.67) ; Number of LABs (Total = 12) ;
- +---------------------------------------------+------------------------------+
- ; 0 ; 4 ;
- ; 1 ; 2 ;
- ; 2 ; 2 ;
- ; 3 ; 2 ;
- ; 4 ; 2 ;
- +---------------------------------------------+------------------------------+
- +--------------------------------------------------------------------------------+
- ; LAB Signals Sourced Out ;
- +-------------------------------------------------+------------------------------+
- ; Number of Signals Sourced Out (Average = 1.42) ; Number of LABs (Total = 12) ;
- +-------------------------------------------------+------------------------------+
- ; 0 ; 4 ;
- ; 1 ; 2 ;
- ; 2 ; 4 ;
- ; 3 ; 1 ;
- ; 4 ; 1 ;
- +-------------------------------------------------+------------------------------+
- +----------------------------------------------------------------------------+
- ; LAB Distinct Inputs ;
- +---------------------------------------------+------------------------------+
- ; Number of Distinct Inputs (Average = 1.08) ; Number of LABs (Total = 12) ;
- +---------------------------------------------+------------------------------+
- ; 0 ; 0 ;
- ; 1 ; 8 ;
- ; 2 ; 1 ;
- ; 3 ; 1 ;
- +---------------------------------------------+------------------------------+
- +------------------------------------------+
- ; I/O Rules Summary ;
- +----------------------------------+-------+
- ; I/O Rules Statistic ; Total ;
- +----------------------------------+-------+
- ; Total I/O Rules ; 30 ;
- ; Number of I/O Rules Passed ; 7 ;
- ; Number of I/O Rules Failed ; 0 ;
- ; Number of I/O Rules Unchecked ; 0 ;
- ; Number of I/O Rules Inapplicable ; 23 ;
- +----------------------------------+-------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; I/O Rules Details ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
- ; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
- ; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
- ; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
- ; Pass ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
- ; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
- ; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
- ; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
- ; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
- ; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
- +--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+
- +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; I/O Rules Matrix ;
- +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+-----------+-----------+-----------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- ; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
- +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+-----------+-----------+-----------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- ; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 15 ; 15 ; 15 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ;
- ; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; Total Inapplicable ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 15 ; 0 ; 0 ; 0 ; 15 ; 15 ; 15 ; 15 ; 0 ; 15 ; 15 ; 0 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 15 ; 0 ; 15 ; 15 ;
- ; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
- ; PIN_HSE ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; SPI0_CSN ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; SPI0_SCK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; UART0_UARTTXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; BAUD_RATE ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; GPIO4_1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; GPIO4_2 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; SPI0_SI_IO0 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; TEST_SINGLE ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; UART1_RX ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; UART1_TX ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; so_io1 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; UART0_UARTRXD ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; PIN_HSI ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- ; PLL_CLKIN ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
- +--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+-----------+-----------+-----------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
- +---------------------------------------------------------------------------------------------+
- ; Fitter Device Options ;
- +------------------------------------------------------------------+--------------------------+
- ; Option ; Setting ;
- +------------------------------------------------------------------+--------------------------+
- ; Enable user-supplied start-up clock (CLKUSR) ; Off ;
- ; Enable device-wide reset (DEV_CLRn) ; Off ;
- ; Enable device-wide output enable (DEV_OE) ; Off ;
- ; Enable INIT_DONE output ; Off ;
- ; Configuration scheme ; Active Serial ;
- ; Error detection CRC ; Off ;
- ; Enable open drain on CRC_ERROR pin ; Off ;
- ; Enable input tri-state on active configuration pins in user mode ; Off ;
- ; Configuration Voltage Level ; Auto ;
- ; Force Configuration Voltage Level ; Off ;
- ; nCEO ; As output driving ground ;
- ; Data[0] ; As input tri-stated ;
- ; Data[1]/ASDO ; As input tri-stated ;
- ; Data[7..2] ; Unreserved ;
- ; FLASH_nCE/nCSO ; As input tri-stated ;
- ; Other Active Parallel pins ; Unreserved ;
- ; DCLK ; As output driving ground ;
- ; Base pin-out file on sameframe device ; Off ;
- +------------------------------------------------------------------+--------------------------+
- +------------------------------------+
- ; Operating Settings and Conditions ;
- +---------------------------+--------+
- ; Setting ; Value ;
- +---------------------------+--------+
- ; Nominal Core Voltage ; 1.20 V ;
- ; Low Junction Temperature ; 0 °C ;
- ; High Junction Temperature ; 85 °C ;
- +---------------------------+--------+
- +-----------------+
- ; Fitter Messages ;
- +-----------------+
- Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
- Info (119006): Selected device EP4CE75F29C8 for design "fpga_boot"
- Info (21077): Low junction temperature is 0 degrees C
- Info (21077): High junction temperature is 85 degrees C
- Info (15535): Implemented PLL "altpll:pll_inst|altpll_6o32:auto_generated|pll1" as Cyclone IV E PLL type
- Info (15099): Implementing clock multiplication of 13, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:pll_inst|altpll_6o32:auto_generated|clk[0] port
- Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
- Warning (171002): Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals
- Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
- Info (176445): Device EP4CE40F29C8 is compatible
- Info (176445): Device EP4CE30F29C8 is compatible
- Info (176445): Device EP4CE55F29C8 is compatible
- Info (176445): Device EP4CE115F29C8 is compatible
- Info (169124): Fitter converted 5 user pins into dedicated programming pins
- Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4
- Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2
- Info (169125): Pin ~ALTERA_DCLK~ is reserved at location P3
- Info (169125): Pin ~ALTERA_DATA0~ is reserved at location N7
- Info (169125): Pin ~ALTERA_nCEO~ is reserved at location P28
- Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
- Critical Warning (169085): No exact pin location assignment(s) for 15 pins of 15 total pins
- Info (169086): Pin PIN_HSE not assigned to an exact location on the device
- Info (169086): Pin SPI0_CSN not assigned to an exact location on the device
- Info (169086): Pin SPI0_SCK not assigned to an exact location on the device
- Info (169086): Pin UART0_UARTTXD not assigned to an exact location on the device
- Info (169086): Pin BAUD_RATE not assigned to an exact location on the device
- Info (169086): Pin GPIO4_1 not assigned to an exact location on the device
- Info (169086): Pin GPIO4_2 not assigned to an exact location on the device
- Info (169086): Pin SPI0_SI_IO0 not assigned to an exact location on the device
- Info (169086): Pin TEST_SINGLE not assigned to an exact location on the device
- Info (169086): Pin UART1_RX not assigned to an exact location on the device
- Info (169086): Pin UART1_TX not assigned to an exact location on the device
- Info (169086): Pin so_io1 not assigned to an exact location on the device
- Info (169086): Pin UART0_UARTRXD not assigned to an exact location on the device
- Info (169086): Pin PIN_HSI not assigned to an exact location on the device
- Info (169086): Pin PLL_CLKIN not assigned to an exact location on the device
- Info (332104): Reading SDC File: 'fpga_boot.sdc'
- Info (332110): Deriving PLL clocks
- Info (332110): create_clock -period 125.000 -waveform {0.000 62.500} -name PLL_CLKIN PLL_CLKIN
- Info (332110): create_generated_clock -source {pll_inst|auto_generated|pll1|inclk[0]} -multiply_by 13 -duty_cycle 50.00 -name {pll_inst|auto_generated|pll1|clk[0]} {pll_inst|auto_generated|pll1|clk[0]}
- Warning (332174): Ignored filter at fpga_boot.sdc(13): rv32|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition
- Warning (332049): Ignored set_false_path at fpga_boot.sdc(13): Argument <from> is not an object ID
- Info (332050): set_false_path -from rv32|resetn_out
- Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
- Info (332111): Found 4 clocks
- Info (332111): Period Clock Name
- Info (332111): ======== ============
- Info (332111): 125.000 PIN_HSE
- Info (332111): 100.000 PIN_HSI
- Info (332111): 125.000 PLL_CLKIN
- Info (332111): 9.615 pll_inst|auto_generated|pll1|clk[0]
- Info (176352): Promoted node altpll:pll_inst|altpll_6o32:auto_generated|clk[0] (placed in counter C0 of PLL_1)
- Info (176355): Automatically promoted alta_gclksw:gclksw_inst|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3
- Info (176352): Promoted node PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))
- Info (176355): Automatically promoted alta_gclksw:gclksw_inst|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3
- Info (176353): Automatically promoted node PLL_ENABLE
- Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
- Info (176233): Starting register packing
- Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
- Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
- Info (176211): Number of I/O pins in group: 13 (unused VREF, 3.3V VCCIO, 2 input, 3 output, 8 bidirectional)
- Info (176212): I/O standards used: 3.3-V LVTTL.
- Info (176215): I/O bank details before I/O pin placement
- Info (176214): Statistics of I/O banks
- Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 40 pins available
- Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 48 pins available
- Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available
- Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 58 pins available
- Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 52 pins available
- Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 47 pins available
- Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 59 pins available
- Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available
- Info (128000): Starting physical synthesis optimizations for speed
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
- Warning (15705): Ignored locations or region assignments to the following nodes
- Warning (15706): Node "dmactive" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACBREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACBREQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACBREQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACBREQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACCLR[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACCLR[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACCLR[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACCLR[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLBREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLBREQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLBREQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLBREQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLSREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLSREQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLSREQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACLSREQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACSREQ[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACSREQ[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACSREQ[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACSREQ[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACTC[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACTC[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACTC[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_dma_DMACTC[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_int[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "ext_resetn" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio0_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio1_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio2_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio3_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio4_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio5_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio6_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio7_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio8_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_in[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_data[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "gpio9_io_out_en[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "local_int[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "local_int[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "local_int[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "local_int[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_haddr[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hburst[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hburst[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hburst[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hrdata[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hready" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hreadyout" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hresp" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hsize[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hsize[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hsize[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_htrans[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_htrans[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwdata[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "mem_ahb_hwrite" is assigned to location or region, but does not exist in design
- Warning (15706): Node "resetn_out" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_haddr[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hburst[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hburst[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hburst[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hrdata[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hready" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hreadyout" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hresp" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hsel" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hsize[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hsize[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hsize[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_htrans[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_htrans[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[0]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[10]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[11]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[12]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[13]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[14]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[15]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[16]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[17]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[18]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[19]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[1]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[20]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[21]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[22]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[23]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[24]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[25]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[26]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[27]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[28]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[29]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[2]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[30]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[31]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[3]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[4]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[5]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[6]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[7]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[8]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwdata[9]" is assigned to location or region, but does not exist in design
- Warning (15706): Node "slave_ahb_hwrite" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_hseBypass" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_hseEnable" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_pllEnable" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_sleep" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_standby" is assigned to location or region, but does not exist in design
- Warning (15706): Node "sys_ctrl_stop" is assigned to location or region, but does not exist in design
- Warning (15706): Node "usb0_id" is assigned to location or region, but does not exist in design
- Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
- Info (170189): Fitter placement preparation operations beginning
- Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
- Info (170191): Fitter placement operations beginning
- Info (170137): Fitter placement was successful
- Info (170192): Fitter placement operations ending: elapsed time is 00:00:06
- Info (128000): Starting physical synthesis optimizations for speed
- Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
- Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
- Info (128002): Starting physical synthesis algorithm logic replication
- Info (128003): Physical synthesis algorithm logic replication complete: estimated slack improvement of 0 ps
- Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:00
- Info (170193): Fitter routing operations beginning
- Info (170195): Router estimated average interconnect usage is 0% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X47_Y0 to location X58_Y11
- Info (170194): Fitter routing operations ending: elapsed time is 00:00:03
- Info (11888): Total time spent on timing analysis during the Fitter is 0.73 seconds.
- Info (334003): Started post-fitting delay annotation
- Info (334004): Delay annotation completed successfully
- Info (334003): Started post-fitting delay annotation
- Info (334004): Delay annotation completed successfully
- Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:01
- Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
- Warning (169177): 15 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
- Info (169178): Pin PIN_HSE uses I/O standard 3.3-V LVTTL at AB17
- Info (169178): Pin SPI0_CSN uses I/O standard 3.3-V LVTTL at AD12
- Info (169178): Pin SPI0_SCK uses I/O standard 3.3-V LVTTL at AE13
- Info (169178): Pin UART0_UARTTXD uses I/O standard 3.3-V LVTTL at AC15
- Info (169178): Pin BAUD_RATE uses I/O standard 3.3-V LVTTL at F10
- Info (169178): Pin GPIO4_1 uses I/O standard 3.3-V LVTTL at AE14
- Info (169178): Pin GPIO4_2 uses I/O standard 3.3-V LVTTL at AB13
- Info (169178): Pin SPI0_SI_IO0 uses I/O standard 3.3-V LVTTL at AA15
- Info (169178): Pin TEST_SINGLE uses I/O standard 3.3-V LVTTL at H5
- Info (169178): Pin UART1_RX uses I/O standard 3.3-V LVTTL at AG26
- Info (169178): Pin UART1_TX uses I/O standard 3.3-V LVTTL at B3
- Info (169178): Pin so_io1 uses I/O standard 3.3-V LVTTL at AB16
- Info (169178): Pin UART0_UARTRXD uses I/O standard 3.3-V LVTTL at AG12
- Info (169178): Pin PIN_HSI uses I/O standard 3.3-V LVTTL at Y2
- Info (169178): Pin PLL_CLKIN uses I/O standard 3.3-V LVTTL at J1
- Warning (169064): Following 5 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
- Info (169065): Pin BAUD_RATE has a permanently disabled output enable
- Info (169065): Pin TEST_SINGLE has a permanently disabled output enable
- Info (169065): Pin UART1_RX has a permanently disabled output enable
- Info (169065): Pin UART1_TX has a permanently disabled output enable
- Info (169065): Pin so_io1 has a permanently disabled output enable
- Info (144001): Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/quartus_logs/fpga_boot.fit.smsg
- Info: Quartus II 64-Bit Fitter was successful. 0 errors, 476 warnings
- Info: Peak virtual memory: 5437 megabytes
- Info: Processing ended: Sat May 09 16:12:18 2026
- Info: Elapsed time: 00:00:18
- Info: Total CPU time (on all processors): 00:00:23
- +----------------------------+
- ; Fitter Suppressed Messages ;
- +----------------------------+
- The suppressed messages can be found in D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/quartus_logs/fpga_boot.fit.smsg.
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