9102_BOOT/logic/db/fpga_boot.hier_info

|fpga_boot
BAUD_RATE <> boot_ip:macro_inst.BAUD_RATE
GPIO4_1 <> GPIO4_1
GPIO4_2 <> GPIO4_2
PIN_HSE => PIN_HSE_in.IN1
PIN_HSI => PIN_HSI_in.IN1
PLL_CLKIN => PIN_OSC_in.IN1
SPI0_CSN <= SPI0_CSN.DB_MAX_OUTPUT_PORT_TYPE
SPI0_SCK <= SPI0_SCK.DB_MAX_OUTPUT_PORT_TYPE
SPI0_SI_IO0 <> SPI0_SI_IO0
TEST_SINGLE <> boot_ip:macro_inst.TEST_SINGLE
UART0_UARTRXD => gpio6_io_in[1].DATAIN
UART0_UARTTXD <= UART0_UARTTXD.DB_MAX_OUTPUT_PORT_TYPE
UART1_RX <> boot_ip:macro_inst.UART1_RX
UART1_TX <> boot_ip:macro_inst.UART1_TX
so_io1 <> boot_ip:macro_inst.so_io1


|fpga_boot|altpll:pll_inst
inclk[0] => altpll_6o32:auto_generated.inclk[0]
inclk[1] => altpll_6o32:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => altpll_6o32:auto_generated.areset
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= altpll_6o32:auto_generated.locked
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|fpga_boot|altpll:pll_inst|altpll_6o32:auto_generated
areset => pll_lock_sync.IN0
areset => pll1.ARESET
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
locked <= locked.DB_MAX_OUTPUT_PORT_TYPE


|fpga_boot|alta_gclksw:gclksw_inst
resetn => ~NO_FANOUT~
ena => gclk_switch.ENA
clkin0 => gclk_switch.INCLK
clkin1 => ~NO_FANOUT~
clkin2 => gclk_switch.INCLK2
clkin3 => gclk_switch.INCLK3
select[0] => gclk_switch.CLKSELECT
select[1] => gclk_switch.CLKSELECT1
clkout <= gclk_switch.CLK


|fpga_boot|boot_ip:macro_inst
BAUD_RATE <> <UNC>
TEST_SINGLE <> <UNC>
UART1_RX <> <UNC>
UART1_TX <> <UNC>
so_io1 <> <UNC>
csn_out_data => ~NO_FANOUT~
csn_out_en => ~NO_FANOUT~
rxd1_ip_in <= <GND>
sck_out_data => ~NO_FANOUT~
sck_out_en => ~NO_FANOUT~
so_io1_in <= <GND>
so_io1_out_data => ~NO_FANOUT~
so_io1_out_en => ~NO_FANOUT~
txd1_ip_out_data => ~NO_FANOUT~
txd1_ip_out_en => ~NO_FANOUT~
sys_clock => ~NO_FANOUT~
bus_clock => ~NO_FANOUT~
resetn => ~NO_FANOUT~
stop => ~NO_FANOUT~
mem_ahb_htrans[0] => ~NO_FANOUT~
mem_ahb_htrans[1] => ~NO_FANOUT~
mem_ahb_hready => ~NO_FANOUT~
mem_ahb_hwrite => ~NO_FANOUT~
mem_ahb_haddr[0] => ~NO_FANOUT~
mem_ahb_haddr[1] => ~NO_FANOUT~
mem_ahb_haddr[2] => ~NO_FANOUT~
mem_ahb_haddr[3] => ~NO_FANOUT~
mem_ahb_haddr[4] => ~NO_FANOUT~
mem_ahb_haddr[5] => ~NO_FANOUT~
mem_ahb_haddr[6] => ~NO_FANOUT~
mem_ahb_haddr[7] => ~NO_FANOUT~
mem_ahb_haddr[8] => ~NO_FANOUT~
mem_ahb_haddr[9] => ~NO_FANOUT~
mem_ahb_haddr[10] => ~NO_FANOUT~
mem_ahb_haddr[11] => ~NO_FANOUT~
mem_ahb_haddr[12] => ~NO_FANOUT~
mem_ahb_haddr[13] => ~NO_FANOUT~
mem_ahb_haddr[14] => ~NO_FANOUT~
mem_ahb_haddr[15] => ~NO_FANOUT~
mem_ahb_haddr[16] => ~NO_FANOUT~
mem_ahb_haddr[17] => ~NO_FANOUT~
mem_ahb_haddr[18] => ~NO_FANOUT~
mem_ahb_haddr[19] => ~NO_FANOUT~
mem_ahb_haddr[20] => ~NO_FANOUT~
mem_ahb_haddr[21] => ~NO_FANOUT~
mem_ahb_haddr[22] => ~NO_FANOUT~