9102_BOOT/logic/db/fpga_boot.fit.qmsg

{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1778314321426 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "fpga_boot EP4CE75F29C8 " "Selected device EP4CE75F29C8 for design \"fpga_boot\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1778314321441 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778314321485 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778314321485 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] 13 1 0 0 " "Implementing clock multiplication of 13, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] port" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 443 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1778314321555 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 443 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1778314321555 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1778314321576 ""}
{ "Warning" "WFITCC_FITCC_WARNING_DANGEROUS_HOLD_TIMING_SCENARIO" "" "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" {  } {  } 0 171002 "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" 0 0 "Fitter" 0 -1 1778314321577 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C8 " "Device EP4CE40F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778314321956 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C8 " "Device EP4CE30F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778314321956 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C8 " "Device EP4CE55F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778314321956 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29C8 " "Device EP4CE115F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778314321956 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1778314321956 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 1220 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778314321958 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 1222 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778314321958 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 1224 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778314321958 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 1226 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778314321958 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 1228 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778314321958 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1778314321958 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1778314321958 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "15 15 " "No exact pin location assignment(s) for 15 pins of 15 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSE " "Pin PIN_HSE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSE } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 25 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 208 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_CSN " "Pin SPI0_CSN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_CSN } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 28 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_CSN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 202 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SCK " "Pin SPI0_SCK not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SCK } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 29 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 205 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTTXD " "Pin UART0_UARTTXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTTXD } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 33 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTTXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 204 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BAUD_RATE " "Pin BAUD_RATE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 207 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_1 " "Pin GPIO4_1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_1 } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 23 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 203 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_2 " "Pin GPIO4_2 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_2 } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 24 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 206 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SI_IO0 " "Pin SPI0_SI_IO0 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SI_IO0 } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 30 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SI_IO0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 201 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TEST_SINGLE " "Pin TEST_SINGLE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 211 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_RX " "Pin UART1_RX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_TX " "Pin UART1_TX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_TX } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 35 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_TX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "so_io1 " "Pin so_io1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTRXD " "Pin UART0_UARTRXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTRXD } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 32 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTRXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSI " "Pin PIN_HSI not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSI } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 209 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PLL_CLKIN " "Pin PLL_CLKIN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PLL_CLKIN } } } { "fpga_boot.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v" 27 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_CLKIN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 210 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778314322965 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1778314322965 ""}
{ "Info" "ISTA_SDC_FOUND" "fpga_boot.sdc " "Reading SDC File: 'fpga_boot.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1778314323185 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN " "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323187 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323187 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1778314323187 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "fpga_boot.sdc 13 rv32\|resetn_out clock or keeper or register or port or pin or cell or partition " "Ignored filter at fpga_boot.sdc(13): rv32\|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" 13 -1 0 } }  } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1778314323187 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_false_path fpga_boot.sdc 13 Argument <from> is not an object ID " "Ignored set_false_path at fpga_boot.sdc(13): Argument <from> is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_false_path -from rv32\|resetn_out " "set_false_path -from rv32\|resetn_out" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" 13 -1 0 } }  } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323187 ""}  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc" 13 -1 0 } }  } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1778314323187 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1778314323188 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000      PIN_HSE " " 125.000      PIN_HSE" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778314323188 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1778314323188 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1) " "Promoted node altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "alta_gclksw:gclksw_inst\|gclk_switch Global Clock CLKCTRL_G3 " "Automatically promoted alta_gclksw:gclksw_inst\|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { alta_gclksw:gclksw_inst|clkout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 440 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778314323194 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/db/altpll_6o32.tdf" 36 2 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altpll:pll_inst|altpll_6o32:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/" { { 0 { 0 ""} 0 443 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778314323194 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Promoted node PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p