// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE75F29C8 Package FBGA780
// 

//
// This file contains Slow Corner delays for the design using part EP4CE75F29C8,
// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
//

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "fpga_boot")
  (DATE "05/09/2026 16:12:23")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pll_inst\|auto_generated\|pll_lock_sync)
    (DELAY
      (ABSOLUTE
        (PORT clk (4296:4296:4296) (4885:4885:4885))
        (PORT d (99:99:99) (115:115:115))
        (PORT clrn (2251:2251:2251) (2207:2207:2207))
        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (212:212:212))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE PLL_LOCK)
    (DELAY
      (ABSOLUTE
        (PORT datac (3578:3578:3578) (4154:4154:4154))
        (PORT datad (294:294:294) (363:363:363))
        (IOPATH datac combout (324:324:324) (316:316:316))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (240:240:240) (258:258:258))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1518:1518:1518) (1367:1367:1367))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE PLL_ENABLE)
    (DELAY
      (ABSOLUTE
        (PORT datad (263:263:263) (281:281:281))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO4_1\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (728:728:728) (837:837:837))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO4_2\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (718:718:718) (827:827:827))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE SPI0_SI_IO0\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (698:698:698) (807:807:807))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE UART0_UARTRXD\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (778:778:778) (887:887:887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSI\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (799:799:799) (908:908:908))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PLL_CLKIN\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (809:809:809) (918:918:918))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE PLL_ENABLE\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (909:909:909) (845:845:845))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE SPI0_CSN\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (781:781:781) (720:720:720))
        (PORT oe (733:733:733) (660:660:660))
        (IOPATH i o (3042:3042:3042) (2922:2922:2922))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE SPI0_SCK\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (783:783:783) (714:714:714))
        (PORT oe (1021:1021:1021) (904:904:904))
        (IOPATH i o (3052:3052:3052) (2932:2932:2932))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE UART0_UARTTXD\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1112:1112:1112) (978:978:978))
        (PORT oe (809:809:809) (739:739:739))
        (IOPATH i o (3032:3032:3032) (2912:2912:2912))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO4_1\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1026:1026:1026) (902:902:902))
        (PORT oe (783:783:783) (715:715:715))
        (IOPATH i o (3042:3042:3042) (2922:2922:2922))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO4_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (761:761:761) (681:681:681))
        (PORT oe (758:758:758) (693:693:693))
        (IOPATH i o (5259:5259:5259) (4789:4789:4789))
        (IOPATH oe o (5368:5368:5368) (4829:4829:4829))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE SPI0_SI_IO0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (1135:1135:1135) (1038:1038:1038))
        (PORT oe (1078:1078:1078) (975:975:975))
        (IOPATH i o (5239:5239:5239) (4769:4769:4769))
        (IOPATH oe o (5368:5368:5368) (4829:4829:4829))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_data\[6\])
    (DELAY
      (ABSOLUTE
        (PORT datad (2292:2292:2292) (2117:2117:2117))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_en\[6\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1883:1883:1883) (1744:1744:1744))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_data\[5\])
    (DELAY
      (ABSOLUTE
        (PORT datad (2293:2293:2293) (2117:2117:2117))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_en\[5\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1883:1883:1883) (1744:1744:1744))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio7_io_out_data\[6\])
    (DELAY
      (ABSOLUTE
        (PORT datac (1914:1914:1914) (1768:1768:1768))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio7_io_out_en\[6\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1903:1903:1903) (1750:1750:1750))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_data\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1890:1890:1890) (1752:1752:1752))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_en\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (2292:2292:2292) (2116:2116:2116))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1890:1890:1890) (1752:1752:1752))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (2291:2291:2291) (2116:2116:2116))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio0_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datac (276:276:276) (306:306:306))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio0_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datac (272:272:272) (302:302:302))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio0_io_in\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (3743:3743:3743) (3920:3920:3920))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_in\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (3316:3316:3316) (3544:3544:3544))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio4_io_in\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (3292:3292:3292) (3520:3520:3520))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_in\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (3299:3299:3299) (3532:3532:3532))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rv32.sys_clk\~QIC_DANGLING_PORT)
    (DELAY
      (ABSOLUTE
        (PORT datad (2025:2025:2025) (1990:1990:1990))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE auto_generated_inst.gclksw_inst\|gclk_switch)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (207:207:207) (194:194:194))
        (PORT inclk[2] (2420:2420:2420) (2384:2384:2384))
        (PORT clkselect[0] (4526:4526:4526) (4244:4244:4244))
        (PORT clkselect[1] (5620:5620:5620) (5469:5469:5469))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE auto_generated_inst.pll_inst\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT areset (1884:1884:1884) (1884:1884:1884))
        (PORT inclk[0] (2422:2422:2422) (2422:2422:2422))
      )
    )
  )
)