vendor_name = ModelSim
source_file = 1, D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.v
source_file = 1, D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/boot_ip.v
source_file = 1, C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v
source_file = 1, D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/fpga_boot.sdc
source_file = 1, D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/db/fpga_boot.cbx.xml
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc
source_file = 1, c:/altera/13.0/quartus/libraries/megafunctions/cbx.lst
source_file = 1, D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/9102_BOOT/logic/db/altpll_6o32.tdf
design_name = fpga_boot
instance = comp, \pll_inst|auto_generated|pll_lock_sync , pll_inst|auto_generated|pll_lock_sync, fpga_boot, 1
instance = comp, \sys_ctrl_clkSource[0] , sys_ctrl_clkSource[0], fpga_boot, 1
instance = comp, \sys_ctrl_clkSource[1] , sys_ctrl_clkSource[1], fpga_boot, 1
instance = comp, \~VCC , ~VCC, fpga_boot, 1
instance = comp, \GPIO4_1~input , GPIO4_1~input, fpga_boot, 1
instance = comp, \GPIO4_2~input , GPIO4_2~input, fpga_boot, 1
instance = comp, \SPI0_SI_IO0~input , SPI0_SI_IO0~input, fpga_boot, 1
instance = comp, \UART0_UARTRXD~input , UART0_UARTRXD~input, fpga_boot, 1
instance = comp, \PIN_HSI~input , PIN_HSI~input, fpga_boot, 1
instance = comp, \PLL_CLKIN~input , PLL_CLKIN~input, fpga_boot, 1
instance = comp, \PLL_ENABLE~clkctrl , PLL_ENABLE~clkctrl, fpga_boot, 1
instance = comp, \pll_inst|auto_generated|pll_lock_sync~feeder , pll_inst|auto_generated|pll_lock_sync~feeder, fpga_boot, 1
instance = comp, \SPI0_CSN~output , SPI0_CSN~output, fpga_boot, 1
instance = comp, \SPI0_SCK~output , SPI0_SCK~output, fpga_boot, 1
instance = comp, \UART0_UARTTXD~output , UART0_UARTTXD~output, fpga_boot, 1
instance = comp, \BAUD_RATE~output , BAUD_RATE~output, fpga_boot, 1
instance = comp, \GPIO4_1~output , GPIO4_1~output, fpga_boot, 1
instance = comp, \GPIO4_2~output , GPIO4_2~output, fpga_boot, 1
instance = comp, \SPI0_SI_IO0~output , SPI0_SI_IO0~output, fpga_boot, 1
instance = comp, \TEST_SINGLE~output , TEST_SINGLE~output, fpga_boot, 1
instance = comp, \UART1_RX~output , UART1_RX~output, fpga_boot, 1
instance = comp, \UART1_TX~output , UART1_TX~output, fpga_boot, 1
instance = comp, \so_io1~output , so_io1~output, fpga_boot, 1
instance = comp, \gpio4_io_out_data[6] , gpio4_io_out_data[6], fpga_boot, 1
instance = comp, \gpio4_io_out_en[6] , gpio4_io_out_en[6], fpga_boot, 1
instance = comp, \gpio4_io_out_data[5] , gpio4_io_out_data[5], fpga_boot, 1
instance = comp, \gpio4_io_out_en[5] , gpio4_io_out_en[5], fpga_boot, 1
instance = comp, \gpio7_io_out_data[6] , gpio7_io_out_data[6], fpga_boot, 1
instance = comp, \gpio7_io_out_en[6] , gpio7_io_out_en[6], fpga_boot, 1
instance = comp, \gpio4_io_out_data[1] , gpio4_io_out_data[1], fpga_boot, 1
instance = comp, \gpio4_io_out_en[1] , gpio4_io_out_en[1], fpga_boot, 1
instance = comp, \gpio4_io_out_data[2] , gpio4_io_out_data[2], fpga_boot, 1
instance = comp, \gpio4_io_out_en[2] , gpio4_io_out_en[2], fpga_boot, 1
instance = comp, \gpio0_io_out_data[0] , gpio0_io_out_data[0], fpga_boot, 1
instance = comp, \gpio0_io_out_en[0] , gpio0_io_out_en[0], fpga_boot, 1
instance = comp, \gpio0_io_in[0] , gpio0_io_in[0], fpga_boot, 1
instance = comp, \gpio0_io_in[1] , gpio0_io_in[1], fpga_boot, 1
instance = comp, \gpio0_io_in[2] , gpio0_io_in[2], fpga_boot, 1
instance = comp, \gpio0_io_in[3] , gpio0_io_in[3], fpga_boot, 1
instance = comp, \gpio0_io_in[4] , gpio0_io_in[4], fpga_boot, 1
instance = comp, \gpio0_io_in[5] , gpio0_io_in[5], fpga_boot, 1
instance = comp, \gpio0_io_in[6] , gpio0_io_in[6], fpga_boot, 1
instance = comp, \gpio0_io_in[7] , gpio0_io_in[7], fpga_boot, 1
instance = comp, \gpio4_io_in[0] , gpio4_io_in[0], fpga_boot, 1
instance = comp, \gpio4_io_in[1] , gpio4_io_in[1], fpga_boot, 1
instance = comp, \gpio4_io_in[2] , gpio4_io_in[2], fpga_boot, 1
instance = comp, \gpio4_io_in[3] , gpio4_io_in[3], fpga_boot, 1
instance = comp, \gpio4_io_in[4] , gpio4_io_in[4], fpga_boot, 1
instance = comp, \gpio4_io_in[5] , gpio4_io_in[5], fpga_boot, 1
instance = comp, \gpio4_io_in[6] , gpio4_io_in[6], fpga_boot, 1
instance = comp, \gpio4_io_in[7] , gpio4_io_in[7], fpga_boot, 1
instance = comp, \gpio6_io_in[0] , gpio6_io_in[0], fpga_boot, 1
instance = comp, \gpio6_io_in[1] , gpio6_io_in[1], fpga_boot, 1
instance = comp, \gpio6_io_in[2] , gpio6_io_in[2], fpga_boot, 1
instance = comp, \gpio6_io_in[3] , gpio6_io_in[3], fpga_boot, 1
instance = comp, \gpio6_io_in[4] , gpio6_io_in[4], fpga_boot, 1
instance = comp, \gpio6_io_in[5] , gpio6_io_in[5], fpga_boot, 1
instance = comp, \gpio6_io_in[6] , gpio6_io_in[6], fpga_boot, 1
instance = comp, \gpio6_io_in[7] , gpio6_io_in[7], fpga_boot, 1
instance = comp, \~GND , ~GND, fpga_boot, 1
instance = comp, \PIN_HSE~input , PIN_HSE~input, fpga_boot, 1
instance = comp, \BAUD_RATE~input , BAUD_RATE~input, fpga_boot, 1
instance = comp, \TEST_SINGLE~input , TEST_SINGLE~input, fpga_boot, 1
instance = comp, \UART1_RX~input , UART1_RX~input, fpga_boot, 1
instance = comp, \UART1_TX~input , UART1_TX~input, fpga_boot, 1
instance = comp, \so_io1~input , so_io1~input, fpga_boot, 1
design_name = alta_rv32
instance = comp, \~GND , ~GND, alta_rv32, 1
instance = comp, \sys_clk~QIC_DANGLING_PORT , sys_clk~QIC_DANGLING_PORT, alta_rv32, 1
design_name = hard_block
instance = comp, \gclksw_inst|gclk_switch , gclksw_inst|gclk_switch, hard_block, 1
instance = comp, \pll_inst|auto_generated|pll1 , pll_inst|auto_generated|pll1, hard_block, 1