> set sh_continue_on_error false
> set sh_echo_on_source  true
> set sh_quiet_on_source true
> set cc_critical_as_fatal true
> 
> set_seed_rand 10
> if { ! [info exists LOGIC_DEVICE] } {
  set LOGIC_DEVICE AGRV2KL100
}
> if { ! [info exists LOGIC_DESIGN] } {
  set LOGIC_DESIGN top
}
> if { ! [info exists LOGIC_MODULE] } {
  set LOGIC_MODULE "$LOGIC_DESIGN"
}
> if { ! [info exists LOGIC_FORCE] } {
  set LOGIC_FORCE false
}
> if { ! [info exists IP_INSTALL_DIR] } {
  set IP_INSTALL_DIR ""
}
> if { ! [info exists LOGIC_TOPPIN] } {
  set LOGIC_TOPPIN false
}
> if { ! [info exists LOGIC_DIR] } {
  set LOGIC_DIR .
}
> if { ! [info exists LOGIC_VV] } {
  set LOGIC_VV "${LOGIC_DESIGN}.v"
}
> if { ! [info exists IP_VV] } {
  set IP_VV ""
}
> if { ! [info exists LIB_DIRS] } {
  set LIB_DIRS {.}
}
> if { ! [info exists LOGIC_ASF] } {
  set LOGIC_ASF ""
}
> if { ! [info exists LOGIC_PRE] } {
  set LOGIC_PRE ""
}
> if { ! [info exists LOGIC_POST] } {
  set LOGIC_POST ""
}
> if { ! [info exists DESIGN_ASF] } {
  set DESIGN_ASF ""
}
> if { ! [info exists DESIGN_PRE] } {
  set DESIGN_PRE ""
}
> if { ! [info exists DESIGN_POST] } {
  set DESIGN_POST ""
}
> if { ! [info exists SDC_FILE] } {
  set SDC_FILE ""
}
> if { ! [info exists VE_FILE] } {
  set VE_FILE ""
}
> if { ! [info exists VEX_FILE] } {
  set VEX_FILE ""
}
> if { ! [info exists AGF_FILE] } {
  set AGF_FILE ""
}
> if { ! [info exists LOGIC_COMPRESS] } {
  set LOGIC_COMPRESS false
}
> 
> cd $LOGIC_DIR
> 
> alta::set_verbose_cmd false
> set logic_ip false
> if { $IP_INSTALL_DIR != "" } {
  set logic_ip true
}
> 
> set ETC_DIR [file join [alta::prog_home] "etc"]
> set IP_FILES ""
> set VERILOG_FILES $LOGIC_VV
> if { $IP_VV != "" } {
  set VERILOG_FILES "$VERILOG_FILES $IP_VV"
}
> set VQM_FILES ""
> set VHDL_FILES ""
> set AF_QUARTUS_TEMPL [file join $ETC_DIR "af_quartus.tcl"]
> set AF_QUARTUS "af_quartus.tcl"
> set AF_IP_TEMPL [file join $ETC_DIR "af_ip.tcl"]
> set AF_IP "af_ip.tcl"
> set AF_MAP_TEMPL [file join $ETC_DIR "af_map.tcl"]
> set AF_MAP "af_map.tcl"
> set AF_RUN_TEMPL [file join $ETC_DIR "af_run.tcl"]
> set AF_RUN "af_run.tcl"
> set AF_BATCH_TEMPL [file join $ETC_DIR "af_batch.tcl"]
> set AF_BATCH "af_batch.tcl"
> 
> if { ! [info exists ORIGINAL_DIR] } {
  set ORIGINAL_DIR ""
}
> if { ! [info exists ORIGINAL_OUTPUT] } {
  set ORIGINAL_OUTPUT ""
}
> if { ! [info exists ORIGINAL_QSF] } {
  set ORIGINAL_QSF ""
}
> if { ! [info exists ORIGINAL_PIN] } {
  set ORIGINAL_PIN ""
}
> 
> set GCLK_CNT -1; # Allow an extra gclk for GCLKSW
> set USE_DESIGN_TEMPL true
> 
> proc print_fdata { fp data } {
  if { [string index $data end] == "\n" } {
    puts -nonewline $fp $data
  } else {
    puts $fp $data
  }
}
> 
> proc backup_files { fnames } {
  foreach fname $fnames {
    if { $fname != "" } {
      set new_fname ".__${fname}__"
      if { [file exists $fname] } {
        catch "file delete -force $new_fname"
        catch "file rename -force $fname $new_fname"
      }
    }
  }
}
> 
> proc restore_files { fnames } {
  foreach fname $fnames {
    if { $fname != "" } {
      set new_fname ".__${fname}__"
      if { [file exists $new_fname] } {
        catch "file delete -force $fname"
        catch "file rename -force $new_fname $fname"
      }
    }
  }
}
> 
> proc read_file { fname } {
  set lines {}
  if { ! [file exists $fname] } {
    return $lines
  }
  set fp [open $fname]
  set is_pio false
  set skip_empty false
  while { [gets $fp line] >= 0 } {
    if { [string first "pio_begin" $line] >= 0 } {
      set is_pio true
    } elseif { [string first "pio_end" $line] >= 0 } {
      set is_pio false
      set skip_empty true
    } elseif { ! $is_pio } {
      if { ! ($skip_empty && [regexp -expanded {^[ #]*$} $line]) } {
        lappend lines $line
        set skip_empty false
      }
    }
  }
  close $fp
  return $lines
}
> 
> set logic_hx ${LOGIC_DESIGN}.hx
> set hx_fp [open $logic_hx r]
> set hsi_freq 0
> set hse_freq 0
> set sys_freq 0
> set bus_freq 0
> while { [gets $hx_fp line] >= 0 } {
  set words [split $line]
  if { [lindex $words 0] == "#define" } {
    if { [lindex $words 1] == "BOARD_HSI_FREQUENCY" } {
      set hsi_freq [lindex $words 2]
    } elseif { [lindex $words 1] == "BOARD_HSE_FREQUENCY" } {
      set hse_freq [lindex $words 2]
    } elseif { [lindex $words 1] == "BOARD_PLL_FREQUENCY" } {
      set sys_freq [lindex $words 2]
    } elseif { [lindex $words 1] == "BOARD_BUS_FREQUENCY" } {
      set bus_freq [lindex $words 2]
    }
    if { [lindex $words 1] == "BOARD_PLL_CLKIN" } {
      set BOARD_PLL_CLKIN [lindex $words 2]
    }
    if { [lindex $words 1] == "USB0_MODE" } {
      set USB0_MODE [lindex $words 2]
    }
  }
}
> close $hx_fp
> 
> if { ! $logic_ip } {
  set sdc_file ${LOGIC_DESIGN}.sdc
  set sdc_ip ""
} else {
  set sdc_file ${LOGIC_DESIGN}_.sdc
  set sdc_ip ${LOGIC_DESIGN}.sdc
}
> 
> set logic_qsf ${LOGIC_DESIGN}.qsf
> set logic_qpf ${LOGIC_DESIGN}.qpf
> set supra_proj ${LOGIC_DESIGN}.proj
> set keep_files [list $sdc_file $sdc_ip]
> set skip_setup 0
> if { [file exists $logic_qsf] || [file exists $logic_qpf] } {
  if { $LOGIC_FORCE } {
    alta::tcl_info "Overwrite existing LOGIC preparation files in $LOGIC_DIR"
    set skip_setup 1
  } else {
    alta::tcl_warn "Files for LOGIC preparation already exist in $LOGIC_DIR"
    set skip_setup 2
    alta::lconcat keep_files [list $logic_qsf $logic_qpf $supra_proj]
  }
}
> 
> if { $skip_setup < 3 } {
  backup_files $keep_files
  load_architect -no_work -no_route -type $LOGIC_DEVICE
  if { ${SDC_FILE} == "" && ${AGF_FILE} == "" && ${VEX_FILE} == "" } {
    alta::setupRun ${LOGIC_DESIGN} ${LOGIC_MODULE} \
                   "${IP_FILES}" \
                   "${VERILOG_FILES}" \
                   "${VQM_FILES}" \
                   "${VHDL_FILES}" \
                   "${LIB_DIRS}" \
                   "${AF_QUARTUS_TEMPL}" "${AF_QUARTUS}" \
                   "${AF_IP_TEMPL}" "${AF_IP}" \
                   "${AF_MAP_TEMPL}" "${AF_MAP}" \
                   "${AF_RUN_TEMPL}" "${AF_RUN}" \
                   "${AF_BATCH_TEMPL}" "${AF_BATCH}" \
                   "${VE_FILE}" \
                   "." "${ORIGINAL_DIR}" "${ORIGINAL_OUTPUT}"\
                   "${ORIGINAL_QSF}" "${ORIGINAL_PIN}" \
                   "${GCLK_CNT}" "${USE_DESIGN_TEMPL}"
  } else {
    alta::setupRun ${LOGIC_DESIGN} ${LOGIC_MODULE} \
                   "${IP_FILES}" \
                   "${VERILOG_FILES}" \
                   "${VQM_FILES}" \
                   "${VHDL_FILES}" \
                   "${LIB_DIRS}" \
                   "${AF_QUARTUS_TEMPL}" "${AF_QUARTUS}" \
                   "${AF_IP_TEMPL}" "${AF_IP}" \
                   "${AF_MAP_TEMPL}" "${AF_MAP}" \
                   "${AF_RUN_TEMPL}" "${AF_RUN}" \
                   "${AF_BATCH_TEMPL}" "${AF_BATCH}" \
                   "${VE_FILE}" \
                   "." "${ORIGINAL_DIR}" "${ORIGINAL_OUTPUT}"\
                   "${ORIGINAL_QSF}" "${ORIGINAL_PIN}" \
                   "${GCLK_CNT}" "${USE_DESIGN_TEMPL}" \
                   "${SDC_FILE}" "${AGF_FILE}" "${VEX_FILE}"
  }
  if { true } {
    set proj_fp [open $supra_proj w]
    puts $proj_fp {[GuiMigrateSetupPage]}
    puts $proj_fp "design=$LOGIC_DESIGN"
    puts $proj_fp "device=$LOGIC_DEVICE"
    puts $proj_fp "flowInline=true"
    puts $proj_fp ""
    puts $proj_fp {[GuiMigrateRunPage]}
    puts $proj_fp "fitting=1"
    puts $proj_fp "fitter=5"
    puts $proj_fp "effort=2"
    puts $proj_fp "skew=2"
    if { $logic_ip } {
      puts $proj_fp "flow=0"
    }
    close $proj_fp
  }
  restore_files $keep_files

  if { true } {
    set proj_lines [read_file $supra_proj]
    set proj_fp [open $supra_proj w]
    set flow_inline false
    foreach line $proj_lines {
      if { [string first "flowInline" $line] >= 0 } {
        puts $proj_fp "flowInline=force"
        set flow_inline true
      } else {
        puts $proj_fp $line
      }
    }
    if { ! $flow_inline } {
      puts $proj_fp "\n\[GuiMigrateSetupPage\]"
      puts $proj_fp "flowInline=force"
    }
    close $proj_fp
  }

  if { $sdc_file != "" } {
    set sdc_lines [read_file $sdc_file]
    set sdc_fp [open $sdc_file w]
    puts $sdc_fp "# pio_begin"
    if { $hsi_freq != 0 } {
      set hsi_period [expr 1000000000.0/$hsi_freq]
      puts $sdc_fp "if { ! \[info exists ::HSI_PERIOD\] } {"
      puts $sdc_fp "  set ::HSI_PERIOD $hsi_period"
      puts $sdc_fp "}"
      puts $sdc_fp "create_clock -name PIN_HSI -period \$::HSI_PERIOD \[get_ports PIN_HSI\]"
      puts $sdc_fp "set_clock_groups -asynchronous -group PIN_HSI"
    }
    if { $hse_freq != 0 } {
      set hse_period [expr 1000000000.0/$hse_freq]
      puts $sdc_fp "if { ! \[info exists ::HSE_PERIOD\] } {"
      puts $sdc_fp "  set ::HSE_PERIOD $hse_period"
      puts $sdc_fp "}"
      puts $sdc_fp "create_clock -name PIN_HSE -period \$::HSE_PERIOD \[get_ports PIN_HSE\]"
      puts $sdc_fp "set_clock_groups -asynchronous -group PIN_HSE"
    }
    puts $sdc_fp "derive_pll_clocks -create_base_clocks"
    puts $sdc_fp "set_false_path -from rv32|resetn_out"
    puts $sdc_fp "# pio_end"
    puts $sdc_fp "##\n"
    foreach line $sdc_lines {
      puts $sdc_fp $line
    }
    close $sdc_fp
  }

  if { $sdc_ip != "" } {
    set sdc_lines [read_file $sdc_ip]
    set sdc_fp [open $sdc_ip w]
    puts $sdc_fp "# pio_begin"
    if { $sys_freq != 0 } {
      set sys_period [expr 1000000000.0/$sys_freq]
      puts $sdc_fp "create_clock -name sys_clock -period $sys_period \[get_ports sys_clock\]"
    }
    if { $bus_freq != 0 } {
      set bus_period [expr 1000000000.0/$bus_freq]
      puts $sdc_fp "create_clock -name bus_clock -period $bus_period \[get_ports bus_clock\]"
    }
    puts $sdc_fp "set_false_path -from resetn"
    puts $sdc_fp "# pio_end"
    puts $sdc_fp "##\n"
    foreach line $sdc_lines {
      puts $sdc_fp $line
    }
    close $sdc_fp
  }

  if { $logic_ip } {
    set qsf_lines [read_file $logic_qsf]
    set qsf_fp [open $logic_qsf w]
    puts $qsf_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    puts $qsf_fp "set_instance_assignment -name VIRTUAL_PIN ON -to *"
    puts $qsf_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $qsf_fp "##\n"
    foreach line $qsf_lines {
      puts $qsf_fp $line
    }
    close $qsf_fp

    set run_lines [read_file $AF_RUN]
    set run_fp [open $AF_RUN w]
    puts $run_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    puts $run_fp "if { [info exists MODE] && (\$MODE == \"SYNPLICITY\" || \$MODE == \"NATIVE\") } {"
    puts $run_fp "  set FLOW SKIP"
    puts $run_fp "} else {"
    puts $run_fp "  set FLOW PACK"
    puts $run_fp "}"
    puts $run_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $run_fp "##\n"
    foreach line $run_lines {
      puts $run_fp $line
    }
    close $run_fp

    set map_lines [read_file $AF_MAP]
    set map_fp [open $AF_MAP w]
    puts $map_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    if { $logic_ip } {
      puts $map_fp "set IOPAD false"
    } else {
      puts $map_fp "set IOPAD true"
    }
    puts $map_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $map_fp "##\n"
    foreach line $map_lines {
      puts $map_fp $line
    }
    close $map_fp
  }

  if { true } {
    set pre_asf ${LOGIC_DESIGN}.pre.asf
    set pre_lines [read_file $pre_asf]
    set pre_fp [open $pre_asf w]
    puts $pre_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    if { "$LOGIC_PRE" != "" } {
      set logic_fp [open $LOGIC_PRE r]; set logic_data [read $logic_fp]; close $logic_fp
      print_fdata $pre_fp $logic_data
    }
    if { !$logic_ip } {
      if { [info exists BOARD_PLL_CLKIN] } {
        puts $pre_fp "set BOARD_PLL_CLKIN $BOARD_PLL_CLKIN"
      }
      if { [info exists USB0_MODE] } {
        puts $pre_fp "set USB0_MODE $USB0_MODE"
      }
      puts $pre_fp "set db_io_name_priority $LOGIC_TOPPIN"
      puts $pre_fp "set ip_pll_vco_lowpower true"
      if { $LOGIC_COMPRESS } {
        puts $pre_fp "set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION \"ON\""
      } else {
        puts $pre_fp "set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION \"OFF\""
      }
    }
    if { "$DESIGN_PRE" != "" } {
      set design_fp [open $DESIGN_PRE r]; set design_data [read $design_fp]; close $design_fp
      print_fdata $pre_fp $design_data
    }
    puts $pre_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $pre_fp "##\n"
    foreach line $pre_lines {
      puts $pre_fp $line
    }
    close $pre_fp
  }
 
  if { true } {
    set asf_asf ${LOGIC_DESIGN}.asf
    set asf_lines [read_file $asf_asf]
    set asf_fp [open $asf_asf w]
    puts $asf_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    if { "$LOGIC_ASF" != "" } {
      set logic_fp [open $LOGIC_ASF r]; set logic_data [read $logic_fp]; close $logic_fp
      print_fdata $asf_fp $logic_data
    }
    if { "$DESIGN_ASF" != "" } {
      set design_fp [open $DESIGN_ASF r]; set design_data [read $design_fp]; close $design_fp
      print_fdata $asf_fp $design_data
    }
    puts $asf_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $asf_fp "##\n"
    foreach line $asf_lines {
      puts $asf_fp $line
    }
    close $asf_fp
  }

  if { true } {
    set post_asf ${LOGIC_DESIGN}.post.asf
    set post_lines [read_file $post_asf]
    set post_fp [open $post_asf w]
    puts $post_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    if { "$LOGIC_POST" != "" } {
      set logic_fp [open $LOGIC_POST r]; set logic_data [read $logic_fp]; close $logic_fp
      print_fdata $post_fp $logic_data
    }
    if { $logic_ip } {
      puts $post_fp "file mkdir $IP_INSTALL_DIR"
      puts $post_fp "if { ! \[file exists ${IP_INSTALL_DIR}/${LOGIC_DESIGN}.sdc\] } {"
      puts $post_fp "  file copy -force ./${LOGIC_DESIGN}_.sdc ${IP_INSTALL_DIR}/${LOGIC_DESIGN}.sdc"
      puts $post_fp "}"
      puts $post_fp "file copy -force ./${LOGIC_DESIGN}_.ve ${IP_INSTALL_DIR}/${LOGIC_DESIGN}.ve"
      puts $post_fp "if { \$MODE == \"SYNPLICITY\" || \$MODE == \"NATIVE\" } {"
      puts $post_fp "  file copy -force ${LOGIC_DESIGN}.vqm ${IP_INSTALL_DIR}/${LOGIC_DESIGN}.vq"
      puts $post_fp "} else {"
      puts $post_fp "  file copy -force ./alta_db/packed.vx ${IP_INSTALL_DIR}/${LOGIC_DESIGN}.vx"
      puts $post_fp "}"
    }
    if { "$DESIGN_POST" != "" } {
      set design_fp [open $DESIGN_POST r]; set design_data [read $design_fp]; close $design_fp
      print_fdata $post_fp $design_data
    }
    puts $post_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $post_fp "##\n"
    foreach line $post_lines {
      puts $post_fp $line
    }
    close $post_fp
  }

  if { true } {
    set pre_asf ${LOGIC_DESIGN}.pre_map.asf
    set pre_lines [read_file $pre_asf]
    set pre_fp [open $pre_asf w]
    puts $pre_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    puts $pre_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $pre_fp "##\n"
    foreach line $pre_lines {
      puts $pre_fp $line
    }
    close $pre_fp
  }
 
  if { true } {
    set post_asf ${LOGIC_DESIGN}.post_map.asf
    set post_lines [read_file $post_asf]
    set post_fp [open $post_asf w]
    puts $post_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
    puts $post_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
    puts $post_fp "##\n"
    foreach line $post_lines {
      puts $post_fp $line
    }
    close $post_fp
  }
 
}
Total IO  : 150
Total Pin : 128/17
Top array is built.
Loading architect libraries...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 52MB (52MB)
Warn: Can not find SDC file .\\fpga_boot.sdc, create a empty one.
Info: Using device QSF template file C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/AGRV2K_templ.qsf.
Info: Can not find ASF file ./fpga_boot.asf, create a empty one.
Info: Can not find pre-ASF file ./fpga_boot.pre.asf, create a empty one.
Info: Can not find post-ASF file ./fpga_boot.post.asf, create a empty one.
Info: Can not find pre_map-ASF file ./fpga_boot.pre_map.asf, create a empty one.
Info: Can not find post_map-ASF file ./fpga_boot.post_map.asf, create a empty one.
> 
> exit

Total 0 fatals, 0 errors, 1 warnings, 6 infos.
