`timescale 1 ps/ 1 ps

module fpga_boot(
	BAUD_RATE,
	GPIO4_1,
	GPIO4_2,
	PIN_HSE,
	PIN_HSI,
	PLL_CLKIN,
	SPI0_CSN,
	SPI0_SCK,
	SPI0_SI_IO0,
	TEST_SINGLE,
	UART0_UARTRXD,
	UART0_UARTTXD,
	UART1_RX,
	UART1_TX,
	so_io1);
inout	BAUD_RATE;
inout	GPIO4_1;
inout	GPIO4_2;
input	PIN_HSE;
input	PIN_HSI;
input	PLL_CLKIN;
output	SPI0_CSN;
output	SPI0_SCK;
inout	SPI0_SI_IO0;
inout	TEST_SINGLE;
input	UART0_UARTRXD;
output	UART0_UARTTXD;
inout	UART1_RX;
inout	UART1_TX;
inout	so_io1;

//wire	gnd;
//wire	vcc;
//wire	unknown;
wire	\BAUD_RATE~input_o ;
wire	\GPIO4_1~input_o ;
wire	\GPIO4_2~input_o ;
wire	\PIN_HSE~input_o ;
wire	\PIN_HSI~input_o ;
wire	\PLL_CLKIN~input_o ;
wire	\PLL_ENABLE~clkctrl_outclk ;
wire	\PLL_ENABLE~clkctrl_outclk__AsyncReset_X49_Y1_SIG ;
wire	\PLL_ENABLE~combout ;
wire	\PLL_LOCK~combout ;
wire	\SPI0_SI_IO0~input_o ;
wire	\TEST_SINGLE~input_o ;
wire	\UART0_UARTRXD~input_o ;
wire	\UART1_RX~input_o ;
wire	\UART1_TX~input_o ;
wire	\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ;
wire	\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp_X49_Y1_SIG_VCC ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
tri1	devclrn;
tri1	devoe;
tri1	devpor;
wire	\gclksw_inst|gclk_switch__alta_gclksw__clkout ;
wire	[7:0] gpio0_io_in;
//wire	gpio0_io_in[0];
//wire	gpio0_io_in[1];
//wire	gpio0_io_in[2];
//wire	gpio0_io_in[3];
//wire	gpio0_io_in[4];
//wire	gpio0_io_in[5];
//wire	gpio0_io_in[6];
//wire	gpio0_io_in[7];
wire	[7:0] gpio0_io_out_data;
//wire	gpio0_io_out_data[0];
//wire	gpio0_io_out_data[1];
//wire	gpio0_io_out_data[2];
//wire	gpio0_io_out_data[3];
//wire	gpio0_io_out_data[4];
//wire	gpio0_io_out_data[5];
//wire	gpio0_io_out_data[6];
//wire	gpio0_io_out_data[7];
wire	[7:0] gpio0_io_out_en;
//wire	gpio0_io_out_en[0];
//wire	gpio0_io_out_en[1];
//wire	gpio0_io_out_en[2];
//wire	gpio0_io_out_en[3];
//wire	gpio0_io_out_en[4];
//wire	gpio0_io_out_en[5];
//wire	gpio0_io_out_en[6];
//wire	gpio0_io_out_en[7];
wire	[7:0] gpio4_io_in;
//wire	gpio4_io_in[0];
//wire	gpio4_io_in[1];
//wire	gpio4_io_in[2];
//wire	gpio4_io_in[3];
//wire	gpio4_io_in[4];
//wire	gpio4_io_in[5];
//wire	gpio4_io_in[6];
//wire	gpio4_io_in[7];
wire	[7:0] gpio4_io_out_data;
//wire	gpio4_io_out_data[0];
//wire	gpio4_io_out_data[1];
//wire	gpio4_io_out_data[2];
//wire	gpio4_io_out_data[3];
//wire	gpio4_io_out_data[4];
//wire	gpio4_io_out_data[5];
//wire	gpio4_io_out_data[6];
//wire	gpio4_io_out_data[7];
wire	[7:0] gpio4_io_out_en;
//wire	gpio4_io_out_en[0];
//wire	gpio4_io_out_en[1];
//wire	gpio4_io_out_en[2];
//wire	gpio4_io_out_en[3];
//wire	gpio4_io_out_en[4];
//wire	gpio4_io_out_en[5];
//wire	gpio4_io_out_en[6];
//wire	gpio4_io_out_en[7];
wire	[7:0] gpio6_io_in;
//wire	gpio6_io_in[0];
//wire	gpio6_io_in[1];
//wire	gpio6_io_in[2];
//wire	gpio6_io_in[3];
//wire	gpio6_io_in[4];
//wire	gpio6_io_in[5];
//wire	gpio6_io_in[6];
//wire	gpio6_io_in[7];
wire	[7:0] gpio7_io_out_data;
//wire	gpio7_io_out_data[0];
//wire	gpio7_io_out_data[1];
//wire	gpio7_io_out_data[2];
//wire	gpio7_io_out_data[3];
//wire	gpio7_io_out_data[4];
//wire	gpio7_io_out_data[5];
//wire	gpio7_io_out_data[6];
//wire	gpio7_io_out_data[7];
wire	[7:0] gpio7_io_out_en;
//wire	gpio7_io_out_en[0];
//wire	gpio7_io_out_en[1];
//wire	gpio7_io_out_en[2];
//wire	gpio7_io_out_en[3];
//wire	gpio7_io_out_en[4];
//wire	gpio7_io_out_en[5];
//wire	gpio7_io_out_en[6];
//wire	gpio7_io_out_en[7];
wire	hbi_272_0_9cb2c0024f9919c5_bp;
wire	hbi_272_1_9cb2c0024f9919c5_bp;
wire	[4:0] \pll_inst|auto_generated|clk ;
//wire	\pll_inst|auto_generated|clk [0];
//wire	\pll_inst|auto_generated|clk [1];
//wire	\pll_inst|auto_generated|clk [2];
//wire	\pll_inst|auto_generated|clk [3];
//wire	\pll_inst|auto_generated|clk [4];
wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
wire	\pll_inst|auto_generated|pll1~FBOUT ;
wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
wire	\pll_inst|auto_generated|pll_lock_sync~q ;
wire	\rv32.dmactive ;
wire	\rv32.ext_dma_DMACCLR[0] ;
wire	\rv32.ext_dma_DMACCLR[1] ;
wire	\rv32.ext_dma_DMACCLR[2] ;
wire	\rv32.ext_dma_DMACCLR[3] ;
wire	\rv32.ext_dma_DMACTC[0] ;
wire	\rv32.ext_dma_DMACTC[1] ;
wire	\rv32.ext_dma_DMACTC[2] ;
wire	\rv32.ext_dma_DMACTC[3] ;
wire	\rv32.gpio0_io_out_data[0] ;
wire	\rv32.gpio0_io_out_data[1] ;
wire	\rv32.gpio0_io_out_data[2] ;
wire	\rv32.gpio0_io_out_data[3] ;
wire	\rv32.gpio0_io_out_data[4] ;
wire	\rv32.gpio0_io_out_data[5] ;
wire	\rv32.gpio0_io_out_data[6] ;
wire	\rv32.gpio0_io_out_data[7] ;
wire	\rv32.gpio0_io_out_en[0] ;
wire	\rv32.gpio0_io_out_en[1] ;
wire	\rv32.gpio0_io_out_en[2] ;
wire	\rv32.gpio0_io_out_en[3] ;
wire	\rv32.gpio0_io_out_en[4] ;
wire	\rv32.gpio0_io_out_en[5] ;
wire	\rv32.gpio0_io_out_en[6] ;
wire	\rv32.gpio0_io_out_en[7] ;
wire	\rv32.gpio1_io_out_data[0] ;
wire	\rv32.gpio1_io_out_data[1] ;
wire	\rv32.gpio1_io_out_data[2] ;
wire	\rv32.gpio1_io_out_data[3] ;
wire	\rv32.gpio1_io_out_data[4] ;
wire	\rv32.gpio1_io_out_data[5] ;
wire	\rv32.gpio1_io_out_data[6] ;
wire	\rv32.gpio1_io_out_data[7] ;
wire	\rv32.gpio1_io_out_en[0] ;
wire	\rv32.gpio1_io_out_en[1] ;
wire	\rv32.gpio1_io_out_en[2] ;
wire	\rv32.gpio1_io_out_en[3] ;
wire	\rv32.gpio1_io_out_en[4] ;
wire	\rv32.gpio1_io_out_en[5] ;
wire	\rv32.gpio1_io_out_en[6] ;
wire	\rv32.gpio1_io_out_en[7] ;
wire	\rv32.gpio2_io_out_data[0] ;
wire	\rv32.gpio2_io_out_data[1] ;
wire	\rv32.gpio2_io_out_data[2] ;
wire	\rv32.gpio2_io_out_data[3] ;
wire	\rv32.gpio2_io_out_data[4] ;
wire	\rv32.gpio2_io_out_data[5] ;
wire	\rv32.gpio2_io_out_data[6] ;
wire	\rv32.gpio2_io_out_data[7] ;
wire	\rv32.gpio2_io_out_en[0] ;
wire	\rv32.gpio2_io_out_en[1] ;
wire	\rv32.gpio2_io_out_en[2] ;
wire	\rv32.gpio2_io_out_en[3] ;
wire	\rv32.gpio2_io_out_en[4] ;
wire	\rv32.gpio2_io_out_en[5] ;
wire	\rv32.gpio2_io_out_en[6] ;
wire	\rv32.gpio2_io_out_en[7] ;
wire	\rv32.gpio3_io_out_data[0] ;
wire	\rv32.gpio3_io_out_data[1] ;
wire	\rv32.gpio3_io_out_data[2] ;
wire	\rv32.gpio3_io_out_data[3] ;
wire	\rv32.gpio3_io_out_data[4] ;
wire	\rv32.gpio3_io_out_data[5] ;
wire	\rv32.gpio3_io_out_data[6] ;
wire	\rv32.gpio3_io_out_data[7] ;
wire	\rv32.gpio3_io_out_en[0] ;
wire	\rv32.gpio3_io_out_en[1] ;
wire	\rv32.gpio3_io_out_en[2] ;
wire	\rv32.gpio3_io_out_en[3] ;
wire	\rv32.gpio3_io_out_en[4] ;
wire	\rv32.gpio3_io_out_en[5] ;
wire	\rv32.gpio3_io_out_en[6] ;
wire	\rv32.gpio3_io_out_en[7] ;
wire	\rv32.gpio4_io_out_data[0] ;
wire	\rv32.gpio4_io_out_data[1] ;
wire	\rv32.gpio4_io_out_data[2] ;
wire	\rv32.gpio4_io_out_data[3] ;
wire	\rv32.gpio4_io_out_data[4] ;
wire	\rv32.gpio4_io_out_data[5] ;
wire	\rv32.gpio4_io_out_data[6] ;
wire	\rv32.gpio4_io_out_data[7] ;
wire	\rv32.gpio4_io_out_en[0] ;
wire	\rv32.gpio4_io_out_en[1] ;
wire	\rv32.gpio4_io_out_en[2] ;
wire	\rv32.gpio4_io_out_en[3] ;
wire	\rv32.gpio4_io_out_en[4] ;
wire	\rv32.gpio4_io_out_en[5] ;
wire	\rv32.gpio4_io_out_en[6] ;
wire	\rv32.gpio4_io_out_en[7] ;
wire	\rv32.gpio5_io_out_data[0] ;
wire	\rv32.gpio5_io_out_data[1] ;
wire	\rv32.gpio5_io_out_data[2] ;
wire	\rv32.gpio5_io_out_data[3] ;
wire	\rv32.gpio5_io_out_data[4] ;
wire	\rv32.gpio5_io_out_data[5] ;
wire	\rv32.gpio5_io_out_data[6] ;
wire	\rv32.gpio5_io_out_data[7] ;
wire	\rv32.gpio5_io_out_en[0] ;
wire	\rv32.gpio5_io_out_en[1] ;
wire	\rv32.gpio5_io_out_en[2] ;
wire	\rv32.gpio5_io_out_en[3] ;
wire	\rv32.gpio5_io_out_en[4] ;
wire	\rv32.gpio5_io_out_en[5] ;
wire	\rv32.gpio5_io_out_en[6] ;
wire	\rv32.gpio5_io_out_en[7] ;
wire	\rv32.gpio6_io_out_data[0] ;
wire	\rv32.gpio6_io_out_data[1] ;
wire	\rv32.gpio6_io_out_data[2] ;
wire	\rv32.gpio6_io_out_data[3] ;
wire	\rv32.gpio6_io_out_data[4] ;
wire	\rv32.gpio6_io_out_data[5] ;
wire	\rv32.gpio6_io_out_data[6] ;
wire	\rv32.gpio6_io_out_data[7] ;
wire	\rv32.gpio6_io_out_en[0] ;
wire	\rv32.gpio6_io_out_en[1] ;
wire	\rv32.gpio6_io_out_en[2] ;
wire	\rv32.gpio6_io_out_en[3] ;
wire	\rv32.gpio6_io_out_en[4] ;
wire	\rv32.gpio6_io_out_en[5] ;
wire	\rv32.gpio6_io_out_en[6] ;
wire	\rv32.gpio6_io_out_en[7] ;
wire	\rv32.gpio7_io_out_data[0] ;
wire	\rv32.gpio7_io_out_data[1] ;
wire	\rv32.gpio7_io_out_data[2] ;
wire	\rv32.gpio7_io_out_data[3] ;
wire	\rv32.gpio7_io_out_data[4] ;
wire	\rv32.gpio7_io_out_data[5] ;
wire	\rv32.gpio7_io_out_data[6] ;
wire	\rv32.gpio7_io_out_data[7] ;
wire	\rv32.gpio7_io_out_en[0] ;
wire	\rv32.gpio7_io_out_en[1] ;
wire	\rv32.gpio7_io_out_en[2] ;
wire	\rv32.gpio7_io_out_en[3] ;
wire	\rv32.gpio7_io_out_en[4] ;
wire	\rv32.gpio7_io_out_en[5] ;
wire	\rv32.gpio7_io_out_en[6] ;
wire	\rv32.gpio7_io_out_en[7] ;
wire	\rv32.gpio8_io_out_data[0] ;
wire	\rv32.gpio8_io_out_data[1] ;
wire	\rv32.gpio8_io_out_data[2] ;
wire	\rv32.gpio8_io_out_data[3] ;
wire	\rv32.gpio8_io_out_data[4] ;
wire	\rv32.gpio8_io_out_data[5] ;
wire	\rv32.gpio8_io_out_data[6] ;
wire	\rv32.gpio8_io_out_data[7] ;
wire	\rv32.gpio8_io_out_en[0] ;
wire	\rv32.gpio8_io_out_en[1] ;
wire	\rv32.gpio8_io_out_en[2] ;
wire	\rv32.gpio8_io_out_en[3] ;
wire	\rv32.gpio8_io_out_en[4] ;
wire	\rv32.gpio8_io_out_en[5] ;
wire	\rv32.gpio8_io_out_en[6] ;
wire	\rv32.gpio8_io_out_en[7] ;
wire	\rv32.gpio9_io_out_data[0] ;
wire	\rv32.gpio9_io_out_data[1] ;
wire	\rv32.gpio9_io_out_data[2] ;
wire	\rv32.gpio9_io_out_data[3] ;
wire	\rv32.gpio9_io_out_data[4] ;
wire	\rv32.gpio9_io_out_data[5] ;
wire	\rv32.gpio9_io_out_data[6] ;
wire	\rv32.gpio9_io_out_data[7] ;
wire	\rv32.gpio9_io_out_en[0] ;
wire	\rv32.gpio9_io_out_en[1] ;
wire	\rv32.gpio9_io_out_en[2] ;
wire	\rv32.gpio9_io_out_en[3] ;
wire	\rv32.gpio9_io_out_en[4] ;
wire	\rv32.gpio9_io_out_en[5] ;
wire	\rv32.gpio9_io_out_en[6] ;
wire	\rv32.gpio9_io_out_en[7] ;
wire	\rv32.mem_ahb_haddr[0] ;
wire	\rv32.mem_ahb_haddr[10] ;
wire	\rv32.mem_ahb_haddr[11] ;
wire	\rv32.mem_ahb_haddr[12] ;
wire	\rv32.mem_ahb_haddr[13] ;
wire	\rv32.mem_ahb_haddr[14] ;
wire	\rv32.mem_ahb_haddr[15] ;
wire	\rv32.mem_ahb_haddr[16] ;
wire	\rv32.mem_ahb_haddr[17] ;
wire	\rv32.mem_ahb_haddr[18] ;
wire	\rv32.mem_ahb_haddr[19] ;
wire	\rv32.mem_ahb_haddr[1] ;
wire	\rv32.mem_ahb_haddr[20] ;
wire	\rv32.mem_ahb_haddr[21] ;
wire	\rv32.mem_ahb_haddr[22] ;
wire	\rv32.mem_ahb_haddr[23] ;
wire	\rv32.mem_ahb_haddr[24] ;
wire	\rv32.mem_ahb_haddr[25] ;
wire	\rv32.mem_ahb_haddr[26] ;
wire	\rv32.mem_ahb_haddr[27] ;
wire	\rv32.mem_ahb_haddr[28] ;
wire	\rv32.mem_ahb_haddr[29] ;
wire	\rv32.mem_ahb_haddr[2] ;
wire	\rv32.mem_ahb_haddr[30] ;
wire	\rv32.mem_ahb_haddr[31] ;
wire	\rv32.mem_ahb_haddr[3] ;
wire	\rv32.mem_ahb_haddr[4] ;
wire	\rv32.mem_ahb_haddr[5] ;
wire	\rv32.mem_ahb_haddr[6] ;
wire	\rv32.mem_ahb_haddr[7] ;
wire	\rv32.mem_ahb_haddr[8] ;
wire	\rv32.mem_ahb_haddr[9] ;
wire	\rv32.mem_ahb_hburst[0] ;
wire	\rv32.mem_ahb_hburst[1] ;
wire	\rv32.mem_ahb_hburst[2] ;
wire	\rv32.mem_ahb_hready ;
wire	\rv32.mem_ahb_hsize[0] ;
wire	\rv32.mem_ahb_hsize[1] ;
wire	\rv32.mem_ahb_hsize[2] ;
wire	\rv32.mem_ahb_htrans[0] ;
wire	\rv32.mem_ahb_htrans[1] ;
wire	\rv32.mem_ahb_hwdata[0] ;
wire	\rv32.mem_ahb_hwdata[10] ;
wire	\rv32.mem_ahb_hwdata[11] ;
wire	\rv32.mem_ahb_hwdata[12] ;
wire	\rv32.mem_ahb_hwdata[13] ;
wire	\rv32.mem_ahb_hwdata[14] ;
wire	\rv32.mem_ahb_hwdata[15] ;
wire	\rv32.mem_ahb_hwdata[16] ;
wire	\rv32.mem_ahb_hwdata[17] ;
wire	\rv32.mem_ahb_hwdata[18] ;
wire	\rv32.mem_ahb_hwdata[19] ;
wire	\rv32.mem_ahb_hwdata[1] ;
wire	\rv32.mem_ahb_hwdata[20] ;
wire	\rv32.mem_ahb_hwdata[21] ;
wire	\rv32.mem_ahb_hwdata[22] ;
wire	\rv32.mem_ahb_hwdata[23] ;
wire	\rv32.mem_ahb_hwdata[24] ;
wire	\rv32.mem_ahb_hwdata[25] ;
wire	\rv32.mem_ahb_hwdata[26] ;
wire	\rv32.mem_ahb_hwdata[27] ;
wire	\rv32.mem_ahb_hwdata[28] ;
wire	\rv32.mem_ahb_hwdata[29] ;
wire	\rv32.mem_ahb_hwdata[2] ;
wire	\rv32.mem_ahb_hwdata[30] ;
wire	\rv32.mem_ahb_hwdata[31] ;
wire	\rv32.mem_ahb_hwdata[3] ;
wire	\rv32.mem_ahb_hwdata[4] ;
wire	\rv32.mem_ahb_hwdata[5] ;
wire	\rv32.mem_ahb_hwdata[6] ;
wire	\rv32.mem_ahb_hwdata[7] ;
wire	\rv32.mem_ahb_hwdata[8] ;
wire	\rv32.mem_ahb_hwdata[9] ;
wire	\rv32.mem_ahb_hwrite ;
wire	\rv32.resetn_out ;
wire	\rv32.slave_ahb_hrdata[0] ;
wire	\rv32.slave_ahb_hrdata[10] ;
wire	\rv32.slave_ahb_hrdata[11] ;
wire	\rv32.slave_ahb_hrdata[12] ;
wire	\rv32.slave_ahb_hrdata[13] ;
wire	\rv32.slave_ahb_hrdata[14] ;
wire	\rv32.slave_ahb_hrdata[15] ;
wire	\rv32.slave_ahb_hrdata[16] ;
wire	\rv32.slave_ahb_hrdata[17] ;
wire	\rv32.slave_ahb_hrdata[18] ;
wire	\rv32.slave_ahb_hrdata[19] ;
wire	\rv32.slave_ahb_hrdata[1] ;
wire	\rv32.slave_ahb_hrdata[20] ;
wire	\rv32.slave_ahb_hrdata[21] ;
wire	\rv32.slave_ahb_hrdata[22] ;
wire	\rv32.slave_ahb_hrdata[23] ;
wire	\rv32.slave_ahb_hrdata[24] ;
wire	\rv32.slave_ahb_hrdata[25] ;
wire	\rv32.slave_ahb_hrdata[26] ;
wire	\rv32.slave_ahb_hrdata[27] ;
wire	\rv32.slave_ahb_hrdata[28] ;
wire	\rv32.slave_ahb_hrdata[29] ;
wire	\rv32.slave_ahb_hrdata[2] ;
wire	\rv32.slave_ahb_hrdata[30] ;
wire	\rv32.slave_ahb_hrdata[31] ;
wire	\rv32.slave_ahb_hrdata[3] ;
wire	\rv32.slave_ahb_hrdata[4] ;
wire	\rv32.slave_ahb_hrdata[5] ;
wire	\rv32.slave_ahb_hrdata[6] ;
wire	\rv32.slave_ahb_hrdata[7] ;
wire	\rv32.slave_ahb_hrdata[8] ;
wire	\rv32.slave_ahb_hrdata[9] ;
wire	\rv32.slave_ahb_hreadyout ;
wire	\rv32.slave_ahb_hresp ;
wire	\rv32.swj_JTAGIR[0] ;
wire	\rv32.swj_JTAGIR[1] ;
wire	\rv32.swj_JTAGIR[2] ;
wire	\rv32.swj_JTAGIR[3] ;
wire	\rv32.swj_JTAGNSW ;
wire	\rv32.swj_JTAGSTATE[0] ;
wire	\rv32.swj_JTAGSTATE[1] ;
wire	\rv32.swj_JTAGSTATE[2] ;
wire	\rv32.swj_JTAGSTATE[3] ;
wire	\rv32.sys_ctrl_clkSource[0] ;
wire	\rv32.sys_ctrl_clkSource[1] ;
wire	\rv32.sys_ctrl_hseBypass ;
wire	\rv32.sys_ctrl_hseEnable ;
wire	\rv32.sys_ctrl_pllEnable ;
wire	\rv32.sys_ctrl_sleep ;
wire	\rv32.sys_ctrl_standby ;
wire	\rv32.sys_ctrl_stop ;
wire	\so_io1~input_o ;
wire	\~GND~combout ;
wire	\~VCC~combout ;

wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;
wire unknown;
assign unknown = 1'bx;

alta_rio \BAUD_RATE~output (
	.padio(BAUD_RATE),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\BAUD_RATE~input_o ),
	.regout());
defparam \BAUD_RATE~output .coord_x = 0;
defparam \BAUD_RATE~output .coord_y = 4;
defparam \BAUD_RATE~output .coord_z = 2;
defparam \BAUD_RATE~output .IN_ASYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .IN_SYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .IN_POWERUP = 1'b0;
defparam \BAUD_RATE~output .OUT_REG_MODE = 1'b0;
defparam \BAUD_RATE~output .OUT_ASYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .OUT_SYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .OUT_POWERUP = 1'b0;
defparam \BAUD_RATE~output .OE_REG_MODE = 1'b0;
defparam \BAUD_RATE~output .OE_ASYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .OE_SYNC_MODE = 1'b0;
defparam \BAUD_RATE~output .OE_POWERUP = 1'b0;
defparam \BAUD_RATE~output .CFG_TRI_INPUT = 1'b0;
defparam \BAUD_RATE~output .CFG_INPUT_EN = 1'b0;
defparam \BAUD_RATE~output .CFG_PULL_UP = 1'b0;
defparam \BAUD_RATE~output .CFG_SLR = 1'b0;
defparam \BAUD_RATE~output .CFG_OPEN_DRAIN = 1'b0;
defparam \BAUD_RATE~output .CFG_PDRCTRL = 4'b0100;
defparam \BAUD_RATE~output .CFG_KEEP = 2'b00;
defparam \BAUD_RATE~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \BAUD_RATE~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \BAUD_RATE~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \BAUD_RATE~output .CFG_LVDS_IN_EN = 1'b0;
defparam \BAUD_RATE~output .DPCLK_DELAY = 4'b0000;
defparam \BAUD_RATE~output .OUT_DELAY = 1'b0;
defparam \BAUD_RATE~output .IN_DATA_DELAY = 3'b000;
defparam \BAUD_RATE~output .IN_REG_DELAY = 3'b000;

alta_rio \GPIO4_1~output (
	.padio(GPIO4_1),
	.datain(\rv32.gpio4_io_out_data[1] ),
	.oe(\rv32.gpio4_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO4_1~input_o ),
	.regout());
defparam \GPIO4_1~output .coord_x = 17;
defparam \GPIO4_1~output .coord_y = 0;
defparam \GPIO4_1~output .coord_z = 2;
defparam \GPIO4_1~output .IN_ASYNC_MODE = 1'b0;
defparam \GPIO4_1~output .IN_SYNC_MODE = 1'b0;
defparam \GPIO4_1~output .IN_POWERUP = 1'b0;
defparam \GPIO4_1~output .OUT_REG_MODE = 1'b0;
defparam \GPIO4_1~output .OUT_ASYNC_MODE = 1'b0;
defparam \GPIO4_1~output .OUT_SYNC_MODE = 1'b0;
defparam \GPIO4_1~output .OUT_POWERUP = 1'b0;
defparam \GPIO4_1~output .OE_REG_MODE = 1'b0;
defparam \GPIO4_1~output .OE_ASYNC_MODE = 1'b0;
defparam \GPIO4_1~output .OE_SYNC_MODE = 1'b0;
defparam \GPIO4_1~output .OE_POWERUP = 1'b0;
defparam \GPIO4_1~output .CFG_TRI_INPUT = 1'b0;
defparam \GPIO4_1~output .CFG_INPUT_EN = 1'b1;
defparam \GPIO4_1~output .CFG_PULL_UP = 1'b0;
defparam \GPIO4_1~output .CFG_SLR = 1'b0;
defparam \GPIO4_1~output .CFG_OPEN_DRAIN = 1'b0;
defparam \GPIO4_1~output .CFG_PDRCTRL = 4'b0100;
defparam \GPIO4_1~output .CFG_KEEP = 2'b00;
defparam \GPIO4_1~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \GPIO4_1~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \GPIO4_1~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \GPIO4_1~output .CFG_LVDS_IN_EN = 1'b0;
defparam \GPIO4_1~output .DPCLK_DELAY = 4'b0000;
defparam \GPIO4_1~output .OUT_DELAY = 1'b0;
defparam \GPIO4_1~output .IN_DATA_DELAY = 3'b000;
defparam \GPIO4_1~output .IN_REG_DELAY = 3'b000;

alta_rio \GPIO4_2~output (
	.padio(GPIO4_2),
	.datain(\rv32.gpio4_io_out_data[2] ),
	.oe(\rv32.gpio4_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO4_2~input_o ),
	.regout());
defparam \GPIO4_2~output .coord_x = 19;
defparam \GPIO4_2~output .coord_y = 13;
defparam \GPIO4_2~output .coord_z = 3;
defparam \GPIO4_2~output .IN_ASYNC_MODE = 1'b0;
defparam \GPIO4_2~output .IN_SYNC_MODE = 1'b0;
defparam \GPIO4_2~output .IN_POWERUP = 1'b0;
defparam \GPIO4_2~output .OUT_REG_MODE = 1'b0;
defparam \GPIO4_2~output .OUT_ASYNC_MODE = 1'b0;
defparam \GPIO4_2~output .OUT_SYNC_MODE = 1'b0;
defparam \GPIO4_2~output .OUT_POWERUP = 1'b0;
defparam \GPIO4_2~output .OE_REG_MODE = 1'b0;
defparam \GPIO4_2~output .OE_ASYNC_MODE = 1'b0;
defparam \GPIO4_2~output .OE_SYNC_MODE = 1'b0;
defparam \GPIO4_2~output .OE_POWERUP = 1'b0;
defparam \GPIO4_2~output .CFG_TRI_INPUT = 1'b0;
defparam \GPIO4_2~output .CFG_INPUT_EN = 1'b1;
defparam \GPIO4_2~output .CFG_PULL_UP = 1'b0;
defparam \GPIO4_2~output .CFG_SLR = 1'b0;
defparam \GPIO4_2~output .CFG_OPEN_DRAIN = 1'b0;
defparam \GPIO4_2~output .CFG_PDRCTRL = 4'b0100;
defparam \GPIO4_2~output .CFG_KEEP = 2'b00;
defparam \GPIO4_2~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \GPIO4_2~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \GPIO4_2~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \GPIO4_2~output .CFG_LVDS_IN_EN = 1'b0;
defparam \GPIO4_2~output .DPCLK_DELAY = 4'b0000;
defparam \GPIO4_2~output .OUT_DELAY = 1'b0;
defparam \GPIO4_2~output .IN_DATA_DELAY = 3'b000;
defparam \GPIO4_2~output .IN_REG_DELAY = 3'b000;

alta_rio \PIN_HSE~input (
	.padio(PIN_HSE),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSE~input_o ),
	.regout());
defparam \PIN_HSE~input .coord_x = 22;
defparam \PIN_HSE~input .coord_y = 4;
defparam \PIN_HSE~input .coord_z = 1;
defparam \PIN_HSE~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .IN_POWERUP = 1'b0;
defparam \PIN_HSE~input .OUT_REG_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OUT_POWERUP = 1'b0;
defparam \PIN_HSE~input .OE_REG_MODE = 1'b0;
defparam \PIN_HSE~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_HSE~input .OE_POWERUP = 1'b0;
defparam \PIN_HSE~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_HSE~input .CFG_PULL_UP = 1'b0;
defparam \PIN_HSE~input .CFG_SLR = 1'b0;
defparam \PIN_HSE~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_HSE~input .CFG_PDRCTRL = 4'b0010;
defparam \PIN_HSE~input .CFG_KEEP = 2'b00;
defparam \PIN_HSE~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_HSE~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_HSE~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_HSE~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_HSE~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_HSE~input .OUT_DELAY = 1'b0;
defparam \PIN_HSE~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_HSE~input .IN_REG_DELAY = 3'b000;

alta_rio \PIN_HSI~input (
	.padio(PIN_HSI),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSI~input_o ),
	.regout());
defparam \PIN_HSI~input .coord_x = 22;
defparam \PIN_HSI~input .coord_y = 4;
defparam \PIN_HSI~input .coord_z = 0;
defparam \PIN_HSI~input .IN_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .IN_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .IN_POWERUP = 1'b0;
defparam \PIN_HSI~input .OUT_REG_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OUT_POWERUP = 1'b0;
defparam \PIN_HSI~input .OE_REG_MODE = 1'b0;
defparam \PIN_HSI~input .OE_ASYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OE_SYNC_MODE = 1'b0;
defparam \PIN_HSI~input .OE_POWERUP = 1'b0;
defparam \PIN_HSI~input .CFG_TRI_INPUT = 1'b0;
defparam \PIN_HSI~input .CFG_PULL_UP = 1'b0;
defparam \PIN_HSI~input .CFG_SLR = 1'b0;
defparam \PIN_HSI~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PIN_HSI~input .CFG_PDRCTRL = 4'b0010;
defparam \PIN_HSI~input .CFG_KEEP = 2'b00;
defparam \PIN_HSI~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PIN_HSI~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PIN_HSI~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PIN_HSI~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PIN_HSI~input .DPCLK_DELAY = 4'b0000;
defparam \PIN_HSI~input .OUT_DELAY = 1'b0;
defparam \PIN_HSI~input .IN_DATA_DELAY = 3'b000;
defparam \PIN_HSI~input .IN_REG_DELAY = 3'b000;

alta_rio \PLL_CLKIN~input (
	.padio(PLL_CLKIN),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PLL_CLKIN~input_o ),
	.regout());
defparam \PLL_CLKIN~input .coord_x = 22;
defparam \PLL_CLKIN~input .coord_y = 4;
defparam \PLL_CLKIN~input .coord_z = 2;
defparam \PLL_CLKIN~input .IN_ASYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .IN_SYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .IN_POWERUP = 1'b0;
defparam \PLL_CLKIN~input .OUT_REG_MODE = 1'b0;
defparam \PLL_CLKIN~input .OUT_ASYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .OUT_SYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .OUT_POWERUP = 1'b0;
defparam \PLL_CLKIN~input .OE_REG_MODE = 1'b0;
defparam \PLL_CLKIN~input .OE_ASYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .OE_SYNC_MODE = 1'b0;
defparam \PLL_CLKIN~input .OE_POWERUP = 1'b0;
defparam \PLL_CLKIN~input .CFG_TRI_INPUT = 1'b0;
defparam \PLL_CLKIN~input .CFG_PULL_UP = 1'b0;
defparam \PLL_CLKIN~input .CFG_SLR = 1'b0;
defparam \PLL_CLKIN~input .CFG_OPEN_DRAIN = 1'b0;
defparam \PLL_CLKIN~input .CFG_PDRCTRL = 4'b0010;
defparam \PLL_CLKIN~input .CFG_KEEP = 2'b00;
defparam \PLL_CLKIN~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \PLL_CLKIN~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \PLL_CLKIN~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \PLL_CLKIN~input .CFG_LVDS_IN_EN = 1'b0;
defparam \PLL_CLKIN~input .DPCLK_DELAY = 4'b0000;
defparam \PLL_CLKIN~input .OUT_DELAY = 1'b0;
defparam \PLL_CLKIN~input .IN_DATA_DELAY = 3'b000;
defparam \PLL_CLKIN~input .IN_REG_DELAY = 3'b000;

alta_slice PLL_ENABLE(
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.sys_ctrl_pllEnable ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_ENABLE~combout ),
	.Cout(),
	.Q());
defparam PLL_ENABLE.coord_x = 20;
defparam PLL_ENABLE.coord_y = 5;
defparam PLL_ENABLE.coord_z = 14;
defparam PLL_ENABLE.mask = 16'h00FF;
defparam PLL_ENABLE.modeMux = 1'b0;
defparam PLL_ENABLE.FeedbackMux = 1'b0;
defparam PLL_ENABLE.ShiftMux = 1'b0;
defparam PLL_ENABLE.BypassEn = 1'b0;
defparam PLL_ENABLE.CarryEnb = 1'b1;

alta_io_gclk \PLL_ENABLE~clkctrl (
	.inclk(\PLL_ENABLE~combout ),
	.outclk(\PLL_ENABLE~clkctrl_outclk ));
defparam \PLL_ENABLE~clkctrl .coord_x = 22;
defparam \PLL_ENABLE~clkctrl .coord_y = 4;
defparam \PLL_ENABLE~clkctrl .coord_z = 4;

alta_slice PLL_LOCK(
	.A(vcc),
	.B(vcc),
	.C(\pll_inst|auto_generated|pll_lock_sync~q ),
	.D(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_LOCK~combout ),
	.Cout(),
	.Q());
defparam PLL_LOCK.coord_x = 20;
defparam PLL_LOCK.coord_y = 5;
defparam PLL_LOCK.coord_z = 1;
defparam PLL_LOCK.mask = 16'hF000;
defparam PLL_LOCK.modeMux = 1'b0;
defparam PLL_LOCK.FeedbackMux = 1'b0;
defparam PLL_LOCK.ShiftMux = 1'b0;
defparam PLL_LOCK.BypassEn = 1'b0;
defparam PLL_LOCK.CarryEnb = 1'b1;

alta_rio \SPI0_CSN~output (
	.padio(SPI0_CSN),
	.datain(\rv32.gpio4_io_out_data[6] ),
	.oe(\rv32.gpio4_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \SPI0_CSN~output .coord_x = 22;
defparam \SPI0_CSN~output .coord_y = 3;
defparam \SPI0_CSN~output .coord_z = 3;
defparam \SPI0_CSN~output .IN_ASYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .IN_SYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .IN_POWERUP = 1'b0;
defparam \SPI0_CSN~output .OUT_REG_MODE = 1'b0;
defparam \SPI0_CSN~output .OUT_ASYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .OUT_SYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .OUT_POWERUP = 1'b0;
defparam \SPI0_CSN~output .OE_REG_MODE = 1'b0;
defparam \SPI0_CSN~output .OE_ASYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .OE_SYNC_MODE = 1'b0;
defparam \SPI0_CSN~output .OE_POWERUP = 1'b0;
defparam \SPI0_CSN~output .CFG_TRI_INPUT = 1'b0;
defparam \SPI0_CSN~output .CFG_INPUT_EN = 1'b0;
defparam \SPI0_CSN~output .CFG_PULL_UP = 1'b0;
defparam \SPI0_CSN~output .CFG_SLR = 1'b0;
defparam \SPI0_CSN~output .CFG_OPEN_DRAIN = 1'b0;
defparam \SPI0_CSN~output .CFG_PDRCTRL = 4'b0100;
defparam \SPI0_CSN~output .CFG_KEEP = 2'b00;
defparam \SPI0_CSN~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \SPI0_CSN~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \SPI0_CSN~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \SPI0_CSN~output .CFG_LVDS_IN_EN = 1'b0;
defparam \SPI0_CSN~output .DPCLK_DELAY = 4'b0000;
defparam \SPI0_CSN~output .OUT_DELAY = 1'b0;
defparam \SPI0_CSN~output .IN_DATA_DELAY = 3'b000;
defparam \SPI0_CSN~output .IN_REG_DELAY = 3'b000;

alta_rio \SPI0_SCK~output (
	.padio(SPI0_SCK),
	.datain(\rv32.gpio4_io_out_data[5] ),
	.oe(\rv32.gpio4_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \SPI0_SCK~output .coord_x = 22;
defparam \SPI0_SCK~output .coord_y = 3;
defparam \SPI0_SCK~output .coord_z = 0;
defparam \SPI0_SCK~output .IN_ASYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .IN_SYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .IN_POWERUP = 1'b0;
defparam \SPI0_SCK~output .OUT_REG_MODE = 1'b0;
defparam \SPI0_SCK~output .OUT_ASYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .OUT_SYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .OUT_POWERUP = 1'b0;
defparam \SPI0_SCK~output .OE_REG_MODE = 1'b0;
defparam \SPI0_SCK~output .OE_ASYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .OE_SYNC_MODE = 1'b0;
defparam \SPI0_SCK~output .OE_POWERUP = 1'b0;
defparam \SPI0_SCK~output .CFG_TRI_INPUT = 1'b0;
defparam \SPI0_SCK~output .CFG_INPUT_EN = 1'b0;
defparam \SPI0_SCK~output .CFG_PULL_UP = 1'b0;
defparam \SPI0_SCK~output .CFG_SLR = 1'b0;
defparam \SPI0_SCK~output .CFG_OPEN_DRAIN = 1'b0;
defparam \SPI0_SCK~output .CFG_PDRCTRL = 4'b0100;
defparam \SPI0_SCK~output .CFG_KEEP = 2'b00;
defparam \SPI0_SCK~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \SPI0_SCK~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \SPI0_SCK~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \SPI0_SCK~output .CFG_LVDS_IN_EN = 1'b0;
defparam \SPI0_SCK~output .DPCLK_DELAY = 4'b0000;
defparam \SPI0_SCK~output .OUT_DELAY = 1'b0;
defparam \SPI0_SCK~output .IN_DATA_DELAY = 3'b000;
defparam \SPI0_SCK~output .IN_REG_DELAY = 3'b000;

alta_rio \SPI0_SI_IO0~output (
	.padio(SPI0_SI_IO0),
	.datain(\rv32.gpio0_io_out_data[0] ),
	.oe(\rv32.gpio0_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SPI0_SI_IO0~input_o ),
	.regout());
defparam \SPI0_SI_IO0~output .coord_x = 19;
defparam \SPI0_SI_IO0~output .coord_y = 0;
defparam \SPI0_SI_IO0~output .coord_z = 3;
defparam \SPI0_SI_IO0~output .IN_ASYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .IN_SYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .IN_POWERUP = 1'b0;
defparam \SPI0_SI_IO0~output .OUT_REG_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OUT_ASYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OUT_SYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OUT_POWERUP = 1'b0;
defparam \SPI0_SI_IO0~output .OE_REG_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OE_ASYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OE_SYNC_MODE = 1'b0;
defparam \SPI0_SI_IO0~output .OE_POWERUP = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_TRI_INPUT = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_INPUT_EN = 1'b1;
defparam \SPI0_SI_IO0~output .CFG_PULL_UP = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_SLR = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_OPEN_DRAIN = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_PDRCTRL = 4'b0100;
defparam \SPI0_SI_IO0~output .CFG_KEEP = 2'b00;
defparam \SPI0_SI_IO0~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \SPI0_SI_IO0~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \SPI0_SI_IO0~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \SPI0_SI_IO0~output .CFG_LVDS_IN_EN = 1'b0;
defparam \SPI0_SI_IO0~output .DPCLK_DELAY = 4'b0000;
defparam \SPI0_SI_IO0~output .OUT_DELAY = 1'b0;
defparam \SPI0_SI_IO0~output .IN_DATA_DELAY = 3'b000;
defparam \SPI0_SI_IO0~output .IN_REG_DELAY = 3'b000;

alta_rio \TEST_SINGLE~output (
	.padio(TEST_SINGLE),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\TEST_SINGLE~input_o ),
	.regout());
defparam \TEST_SINGLE~output .coord_x = 19;
defparam \TEST_SINGLE~output .coord_y = 13;
defparam \TEST_SINGLE~output .coord_z = 0;
defparam \TEST_SINGLE~output .IN_ASYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .IN_SYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .IN_POWERUP = 1'b0;
defparam \TEST_SINGLE~output .OUT_REG_MODE = 1'b0;
defparam \TEST_SINGLE~output .OUT_ASYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .OUT_SYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .OUT_POWERUP = 1'b0;
defparam \TEST_SINGLE~output .OE_REG_MODE = 1'b0;
defparam \TEST_SINGLE~output .OE_ASYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .OE_SYNC_MODE = 1'b0;
defparam \TEST_SINGLE~output .OE_POWERUP = 1'b0;
defparam \TEST_SINGLE~output .CFG_TRI_INPUT = 1'b0;
defparam \TEST_SINGLE~output .CFG_INPUT_EN = 1'b0;
defparam \TEST_SINGLE~output .CFG_PULL_UP = 1'b0;
defparam \TEST_SINGLE~output .CFG_SLR = 1'b0;
defparam \TEST_SINGLE~output .CFG_OPEN_DRAIN = 1'b0;
defparam \TEST_SINGLE~output .CFG_PDRCTRL = 4'b0100;
defparam \TEST_SINGLE~output .CFG_KEEP = 2'b00;
defparam \TEST_SINGLE~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \TEST_SINGLE~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \TEST_SINGLE~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \TEST_SINGLE~output .CFG_LVDS_IN_EN = 1'b0;
defparam \TEST_SINGLE~output .DPCLK_DELAY = 4'b0000;
defparam \TEST_SINGLE~output .OUT_DELAY = 1'b0;
defparam \TEST_SINGLE~output .IN_DATA_DELAY = 3'b000;
defparam \TEST_SINGLE~output .IN_REG_DELAY = 3'b000;

alta_rio \UART0_UARTRXD~input (
	.padio(UART0_UARTRXD),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART0_UARTRXD~input_o ),
	.regout());
defparam \UART0_UARTRXD~input .coord_x = 0;
defparam \UART0_UARTRXD~input .coord_y = 1;
defparam \UART0_UARTRXD~input .coord_z = 0;
defparam \UART0_UARTRXD~input .IN_ASYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .IN_SYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .IN_POWERUP = 1'b0;
defparam \UART0_UARTRXD~input .OUT_REG_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OUT_ASYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OUT_SYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OUT_POWERUP = 1'b0;
defparam \UART0_UARTRXD~input .OE_REG_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OE_ASYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OE_SYNC_MODE = 1'b0;
defparam \UART0_UARTRXD~input .OE_POWERUP = 1'b0;
defparam \UART0_UARTRXD~input .CFG_TRI_INPUT = 1'b0;
defparam \UART0_UARTRXD~input .CFG_INPUT_EN = 1'b1;
defparam \UART0_UARTRXD~input .CFG_PULL_UP = 1'b0;
defparam \UART0_UARTRXD~input .CFG_SLR = 1'b0;
defparam \UART0_UARTRXD~input .CFG_OPEN_DRAIN = 1'b0;
defparam \UART0_UARTRXD~input .CFG_PDRCTRL = 4'b0100;
defparam \UART0_UARTRXD~input .CFG_KEEP = 2'b00;
defparam \UART0_UARTRXD~input .CFG_LVDS_OUT_EN = 1'b0;
defparam \UART0_UARTRXD~input .CFG_LVDS_SEL_CUA = 2'b00;
defparam \UART0_UARTRXD~input .CFG_LVDS_IREF = 10'b0110000000;
defparam \UART0_UARTRXD~input .CFG_LVDS_IN_EN = 1'b0;
defparam \UART0_UARTRXD~input .DPCLK_DELAY = 4'b0000;
defparam \UART0_UARTRXD~input .OUT_DELAY = 1'b0;
defparam \UART0_UARTRXD~input .IN_DATA_DELAY = 3'b000;
defparam \UART0_UARTRXD~input .IN_REG_DELAY = 3'b000;

alta_rio \UART0_UARTTXD~output (
	.padio(UART0_UARTTXD),
	.datain(\rv32.gpio7_io_out_data[6] ),
	.oe(\rv32.gpio7_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout());
defparam \UART0_UARTTXD~output .coord_x = 0;
defparam \UART0_UARTTXD~output .coord_y = 2;
defparam \UART0_UARTTXD~output .coord_z = 5;
defparam \UART0_UARTTXD~output .IN_ASYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .IN_SYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .IN_POWERUP = 1'b0;
defparam \UART0_UARTTXD~output .OUT_REG_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OUT_ASYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OUT_SYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OUT_POWERUP = 1'b0;
defparam \UART0_UARTTXD~output .OE_REG_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OE_ASYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OE_SYNC_MODE = 1'b0;
defparam \UART0_UARTTXD~output .OE_POWERUP = 1'b0;
defparam \UART0_UARTTXD~output .CFG_TRI_INPUT = 1'b0;
defparam \UART0_UARTTXD~output .CFG_INPUT_EN = 1'b0;
defparam \UART0_UARTTXD~output .CFG_PULL_UP = 1'b0;
defparam \UART0_UARTTXD~output .CFG_SLR = 1'b0;
defparam \UART0_UARTTXD~output .CFG_OPEN_DRAIN = 1'b0;
defparam \UART0_UARTTXD~output .CFG_PDRCTRL = 4'b0100;
defparam \UART0_UARTTXD~output .CFG_KEEP = 2'b00;
defparam \UART0_UARTTXD~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \UART0_UARTTXD~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \UART0_UARTTXD~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \UART0_UARTTXD~output .CFG_LVDS_IN_EN = 1'b0;
defparam \UART0_UARTTXD~output .DPCLK_DELAY = 4'b0000;
defparam \UART0_UARTTXD~output .OUT_DELAY = 1'b0;
defparam \UART0_UARTTXD~output .IN_DATA_DELAY = 3'b000;
defparam \UART0_UARTTXD~output .IN_REG_DELAY = 3'b000;

alta_rio \UART1_RX~output (
	.padio(UART1_RX),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART1_RX~input_o ),
	.regout());
defparam \UART1_RX~output .coord_x = 20;
defparam \UART1_RX~output .coord_y = 13;
defparam \UART1_RX~output .coord_z = 3;
defparam \UART1_RX~output .IN_ASYNC_MODE = 1'b0;
defparam \UART1_RX~output .IN_SYNC_MODE = 1'b0;
defparam \UART1_RX~output .IN_POWERUP = 1'b0;
defparam \UART1_RX~output .OUT_REG_MODE = 1'b0;
defparam \UART1_RX~output .OUT_ASYNC_MODE = 1'b0;
defparam \UART1_RX~output .OUT_SYNC_MODE = 1'b0;
defparam \UART1_RX~output .OUT_POWERUP = 1'b0;
defparam \UART1_RX~output .OE_REG_MODE = 1'b0;
defparam \UART1_RX~output .OE_ASYNC_MODE = 1'b0;
defparam \UART1_RX~output .OE_SYNC_MODE = 1'b0;
defparam \UART1_RX~output .OE_POWERUP = 1'b0;
defparam \UART1_RX~output .CFG_TRI_INPUT = 1'b0;
defparam \UART1_RX~output .CFG_INPUT_EN = 1'b0;
defparam \UART1_RX~output .CFG_PULL_UP = 1'b0;
defparam \UART1_RX~output .CFG_SLR = 1'b0;
defparam \UART1_RX~output .CFG_OPEN_DRAIN = 1'b0;
defparam \UART1_RX~output .CFG_PDRCTRL = 4'b0100;
defparam \UART1_RX~output .CFG_KEEP = 2'b00;
defparam \UART1_RX~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \UART1_RX~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \UART1_RX~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \UART1_RX~output .CFG_LVDS_IN_EN = 1'b0;
defparam \UART1_RX~output .DPCLK_DELAY = 4'b0000;
defparam \UART1_RX~output .OUT_DELAY = 1'b0;
defparam \UART1_RX~output .IN_DATA_DELAY = 3'b000;
defparam \UART1_RX~output .IN_REG_DELAY = 3'b000;

alta_rio \UART1_TX~output (
	.padio(UART1_TX),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART1_TX~input_o ),
	.regout());
defparam \UART1_TX~output .coord_x = 20;
defparam \UART1_TX~output .coord_y = 13;
defparam \UART1_TX~output .coord_z = 2;
defparam \UART1_TX~output .IN_ASYNC_MODE = 1'b0;
defparam \UART1_TX~output .IN_SYNC_MODE = 1'b0;
defparam \UART1_TX~output .IN_POWERUP = 1'b0;
defparam \UART1_TX~output .OUT_REG_MODE = 1'b0;
defparam \UART1_TX~output .OUT_ASYNC_MODE = 1'b0;
defparam \UART1_TX~output .OUT_SYNC_MODE = 1'b0;
defparam \UART1_TX~output .OUT_POWERUP = 1'b0;
defparam \UART1_TX~output .OE_REG_MODE = 1'b0;
defparam \UART1_TX~output .OE_ASYNC_MODE = 1'b0;
defparam \UART1_TX~output .OE_SYNC_MODE = 1'b0;
defparam \UART1_TX~output .OE_POWERUP = 1'b0;
defparam \UART1_TX~output .CFG_TRI_INPUT = 1'b0;
defparam \UART1_TX~output .CFG_INPUT_EN = 1'b0;
defparam \UART1_TX~output .CFG_PULL_UP = 1'b0;
defparam \UART1_TX~output .CFG_SLR = 1'b0;
defparam \UART1_TX~output .CFG_OPEN_DRAIN = 1'b0;
defparam \UART1_TX~output .CFG_PDRCTRL = 4'b0100;
defparam \UART1_TX~output .CFG_KEEP = 2'b00;
defparam \UART1_TX~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \UART1_TX~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \UART1_TX~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \UART1_TX~output .CFG_LVDS_IN_EN = 1'b0;
defparam \UART1_TX~output .DPCLK_DELAY = 4'b0000;
defparam \UART1_TX~output .OUT_DELAY = 1'b0;
defparam \UART1_TX~output .IN_DATA_DELAY = 3'b000;
defparam \UART1_TX~output .IN_REG_DELAY = 3'b000;

alta_asyncctrl asyncreset_ctrl_X49_Y1_N0(
	.Din(\PLL_ENABLE~clkctrl_outclk ),
	.Dout(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X49_Y1_SIG ));
defparam asyncreset_ctrl_X49_Y1_N0.coord_x = 20;
defparam asyncreset_ctrl_X49_Y1_N0.coord_y = 5;
defparam asyncreset_ctrl_X49_Y1_N0.coord_z = 0;
defparam asyncreset_ctrl_X49_Y1_N0.AsyncCtrlMux = 2'b10;

alta_clkenctrl clken_ctrl_X49_Y1_N0(
	.ClkIn(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.ClkEn(),
	.ClkOut(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp_X49_Y1_SIG_VCC ));
defparam clken_ctrl_X49_Y1_N0.coord_x = 20;
defparam clken_ctrl_X49_Y1_N0.coord_y = 5;
defparam clken_ctrl_X49_Y1_N0.coord_z = 0;
defparam clken_ctrl_X49_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y1_N0.ClkEnMux = 2'b01;

alta_io_gclk \gclksw_inst|gclk_switch (
	.inclk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
defparam \gclksw_inst|gclk_switch .coord_x = 22;
defparam \gclksw_inst|gclk_switch .coord_y = 4;
defparam \gclksw_inst|gclk_switch .coord_z = 5;

alta_gclksw \gclksw_inst|gclk_switch__alta_gclksw (
	.resetn(\rv32.resetn_out ),
	.clkin0(\PIN_HSI~input_o ),
	.clkin1(\PIN_HSE~input_o ),
	.clkin2(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkin3(1'bx),
	.select({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.clkout(\gclksw_inst|gclk_switch__alta_gclksw__clkout ));
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_x = 22;
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_y = 4;
defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_z = 0;

alta_pllve \pll_inst|auto_generated|pll1 (
	.clkin(\PLL_CLKIN~input_o ),
	.clkfb(\pll_inst|auto_generated|pll1~FBOUT ),
	.pfden(vcc),
	.resetn(!\PLL_ENABLE~combout ),
	.phasecounterselect({gnd, gnd, gnd}),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.scandata(gnd),
	.configupdate(gnd),
	.scandataout(),
	.scandone(),
	.phasedone(),
	.clkout0(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkout1(\pll_inst|auto_generated|pll1_CLK_bus [1]),
	.clkout2(\pll_inst|auto_generated|pll1_CLK_bus [2]),
	.clkout3(\pll_inst|auto_generated|pll1_CLK_bus [3]),
	.clkout4(\pll_inst|auto_generated|pll1_CLK_bus [4]),
	.clkfbout(\pll_inst|auto_generated|pll1~FBOUT ),
	.lock(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ));
defparam \pll_inst|auto_generated|pll1 .coord_x = 22;
defparam \pll_inst|auto_generated|pll1 .coord_y = 5;
defparam \pll_inst|auto_generated|pll1 .coord_z = 0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKIN_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKIN_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_BYPASS = 1'b1;
defparam \pll_inst|auto_generated|pll1 .CLKFB_HIGH = 8'b00011001;
defparam \pll_inst|auto_generated|pll1 .CLKFB_LOW = 8'b00011001;
defparam \pll_inst|auto_generated|pll1 .CLKFB_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV0_EN = 1'b1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV1_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV2_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV3_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV4_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_HIGH = 8'b00000001;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_LOW = 8'b00000001;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_HIGH = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_LOW = 8'b11111111;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_TRIM = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_BYPASS = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .CLKFB_DEL = 8'b00000000;
defparam \pll_inst|auto_generated|pll1 .CLKFB_PHASE = 3'b000;
defparam \pll_inst|auto_generated|pll1 .FEEDBACK_MODE = 3'b100;
defparam \pll_inst|auto_generated|pll1 .FBDELAY_VAL = 3'b100;
defparam \pll_inst|auto_generated|pll1 .PLLOUTP_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .PLLOUTN_EN = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_CASCADE = 1'b0;
defparam \pll_inst|auto_generated|pll1 .VCO_POST_DIV = 1'b1;
defparam \pll_inst|auto_generated|pll1 .REG_CTRL = 2'b00;
defparam \pll_inst|auto_generated|pll1 .CP = 3'b100;
defparam \pll_inst|auto_generated|pll1 .RREF = 2'b01;
defparam \pll_inst|auto_generated|pll1 .RVI = 2'b01;
defparam \pll_inst|auto_generated|pll1 .IVCO = 3'b010;
defparam \pll_inst|auto_generated|pll1 .PLL_EN_FLAG = 1'b1;

alta_slice \pll_inst|auto_generated|pll_lock_sync (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\pll_inst|auto_generated|pll_lock_sync~q ),
	.Clk(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp_X49_Y1_SIG_VCC ),
	.AsyncReset(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X49_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.Cout(),
	.Q(\pll_inst|auto_generated|pll_lock_sync~q ));
defparam \pll_inst|auto_generated|pll_lock_sync .coord_x = 20;
defparam \pll_inst|auto_generated|pll_lock_sync .coord_y = 5;
defparam \pll_inst|auto_generated|pll_lock_sync .coord_z = 0;
defparam \pll_inst|auto_generated|pll_lock_sync .mask = 16'hFFFF;
defparam \pll_inst|auto_generated|pll_lock_sync .modeMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .FeedbackMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .ShiftMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .BypassEn = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .CarryEnb = 1'b1;

alta_rv32 rv32(
	.sys_clk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.mem_ahb_hready(\rv32.mem_ahb_hready ),
	.mem_ahb_hreadyout(vcc),
	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
	.mem_ahb_hresp(gnd),
	.mem_ahb_hrdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.slave_ahb_hsel(gnd),
	.slave_ahb_hready(vcc),
	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
	.slave_ahb_htrans({gnd, gnd}),
	.slave_ahb_hsize({gnd, gnd, gnd}),
	.slave_ahb_hburst({gnd, gnd, gnd}),
	.slave_ahb_hwrite(gnd),
	.slave_ahb_haddr({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.slave_ahb_hwdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
	.gpio0_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, \SPI0_SI_IO0~input_o }),
	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
	.gpio1_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
	.sys_ctrl_pllReady(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
	.gpio2_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
	.gpio3_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
	.gpio4_io_in({gnd, gnd, gnd, gnd, gnd, \GPIO4_2~input_o , \GPIO4_1~input_o , gnd}),
	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
	.gpio5_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
	.gpio6_io_in({gnd, gnd, gnd, gnd, gnd, gnd, \UART0_UARTRXD~input_o , gnd}),
	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
	.gpio7_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
	.gpio8_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
	.gpio9_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
	.ext_resetn(vcc),
	.resetn_out(\rv32.resetn_out ),
	.dmactive(\rv32.dmactive ),
	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
	.ext_int({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
	.ext_dma_DMACBREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACLBREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACSREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACLSREQ({gnd, gnd, gnd, gnd}),
	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
	.local_int({gnd, gnd, gnd, gnd}),
	.test_mode({gnd, gnd}),
	.usb0_xcvr_clk(vcc),
	.usb0_id(vcc));
defparam rv32.coord_x = 0;
defparam rv32.coord_y = 5;
defparam rv32.coord_z = 0;

alta_rio \so_io1~output (
	.padio(so_io1),
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\so_io1~input_o ),
	.regout());
defparam \so_io1~output .coord_x = 22;
defparam \so_io1~output .coord_y = 2;
defparam \so_io1~output .coord_z = 3;
defparam \so_io1~output .IN_ASYNC_MODE = 1'b0;
defparam \so_io1~output .IN_SYNC_MODE = 1'b0;
defparam \so_io1~output .IN_POWERUP = 1'b0;
defparam \so_io1~output .OUT_REG_MODE = 1'b0;
defparam \so_io1~output .OUT_ASYNC_MODE = 1'b0;
defparam \so_io1~output .OUT_SYNC_MODE = 1'b0;
defparam \so_io1~output .OUT_POWERUP = 1'b0;
defparam \so_io1~output .OE_REG_MODE = 1'b0;
defparam \so_io1~output .OE_ASYNC_MODE = 1'b0;
defparam \so_io1~output .OE_SYNC_MODE = 1'b0;
defparam \so_io1~output .OE_POWERUP = 1'b0;
defparam \so_io1~output .CFG_TRI_INPUT = 1'b0;
defparam \so_io1~output .CFG_INPUT_EN = 1'b0;
defparam \so_io1~output .CFG_PULL_UP = 1'b0;
defparam \so_io1~output .CFG_SLR = 1'b0;
defparam \so_io1~output .CFG_OPEN_DRAIN = 1'b0;
defparam \so_io1~output .CFG_PDRCTRL = 4'b0100;
defparam \so_io1~output .CFG_KEEP = 2'b00;
defparam \so_io1~output .CFG_LVDS_OUT_EN = 1'b0;
defparam \so_io1~output .CFG_LVDS_SEL_CUA = 2'b00;
defparam \so_io1~output .CFG_LVDS_IREF = 10'b0110000000;
defparam \so_io1~output .CFG_LVDS_IN_EN = 1'b0;
defparam \so_io1~output .DPCLK_DELAY = 4'b0000;
defparam \so_io1~output .OUT_DELAY = 1'b0;
defparam \so_io1~output .IN_DATA_DELAY = 3'b000;
defparam \so_io1~output .IN_REG_DELAY = 3'b000;

endmodule
