9102_APP/logic/db/sign_div_unsign_vlh.tdf

--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=7 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=18 SKIP_BITS=0 denominator numerator quotient remainder
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_abs 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_divide 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ  VERSION_END


-- Copyright (C) 1991-2013 Altera Corporation
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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
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--  applicable agreement for further details.


FUNCTION alt_u_div_i7f (denominator[6..0], numerator[17..0])
RETURNS ( quotient[17..0], remainder[6..0]);

--synthesis_resources = lut 129 
SUBDESIGN sign_div_unsign_vlh
( 
	denominator[6..0]	:	input;
	numerator[17..0]	:	input;
	quotient[17..0]	:	output;
	remainder[6..0]	:	output;
) 
VARIABLE 
	divider : alt_u_div_i7f;
	norm_num[17..0]	: WIRE;
	protect_quotient[17..0]	: WIRE;
	protect_remainder[6..0]	: WIRE;

BEGIN 
	divider.denominator[] = denominator[];
	divider.numerator[] = norm_num[];
	norm_num[] = numerator[];
	protect_quotient[] = divider.quotient[];
	protect_remainder[] = divider.remainder[];
	quotient[] = protect_quotient[];
	remainder[] = protect_remainder[];
END;
--VALID FILE