9102_APP/logic/db/mult_9dt.tdf

--lpm_mult CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone IV E" DSP_BLOCK_BALANCING="Auto" INPUT_A_IS_CONSTANT="NO" INPUT_B_IS_CONSTANT="NO" LPM_REPRESENTATION="UNSIGNED" LPM_WIDTHA=19 LPM_WIDTHB=10 LPM_WIDTHP=29 LPM_WIDTHS=1 MAXIMIZE_SPEED=5 dataa datab result CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_mult 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_padd 2013:04:24:18:08:47:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION cycloneive_mac_mult (aclr, clk, dataa[dataa_width-1..0], datab[datab_width-1..0], ena, signa, signb)
WITH ( dataa_clock, dataa_width, datab_clock, datab_width, signa_clock, signb_clock)
RETURNS ( dataout[dataa_width+datab_width-1..0]);
FUNCTION cycloneive_mac_out (aclr, clk, dataa[dataa_width-1..0], ena)
WITH ( dataa_width = 0, output_clock)
RETURNS ( dataout[dataa_width-1..0]);
FUNCTION soft (in)
RETURNS ( out);

--synthesis_resources = dsp_9bit 4 lut 12 
SUBDESIGN mult_9dt
( 
	dataa[18..0]	:	input;
	datab[9..0]	:	input;
	result[28..0]	:	output;
) 
VARIABLE
	add5_result[11..0]	:	WIRE;
	mac_mult1 : cycloneive_mac_mult
		WITH (
			dataa_clock = "none",
			dataa_width = 18,
			datab_clock = "none",
			datab_width = 10,
			signa_clock = "none",
			signb_clock = "none"
		);
	mac_mult3 : cycloneive_mac_mult
		WITH (
			dataa_clock = "none",
			dataa_width = 1,
			datab_clock = "none",
			datab_width = 10,
			signa_clock = "none",
			signb_clock = "none"
		);
	mac_out2 : cycloneive_mac_out
		WITH (
			dataa_width = 28,
			output_clock = "none"
		);
	mac_out4 : cycloneive_mac_out
		WITH (
			dataa_width = 11,
			output_clock = "none"
		);
	sft6a[11..0] : soft;
	sft7a[11..0] : soft;
	sft8a[11..0] : soft;
	w140w[29..0]	: WIRE;
	w85w	: WIRE;

BEGIN 
	add5_result[] = sft6a[].out + sft7a[].out;
	mac_mult1.dataa[] = ( dataa[17..0]);
	mac_mult1.datab[] = ( datab[9..0]);
	mac_mult1.signa = B"0";
	mac_mult1.signb = B"0";
	mac_mult3.dataa[] = ( dataa[18..18]);
	mac_mult3.datab[] = ( datab[9..0]);
	mac_mult3.signa = B"0";
	mac_mult3.signb = B"0";
	mac_out2.dataa[] = mac_mult1.dataout[];
	mac_out4.dataa[] = mac_mult3.dataout[];
	sft6a[].in = ( w85w, ( mac_out4.dataout[10..10], ( mac_out2.dataout[27..27], ( mac_out2.dataout[26..26], ( mac_out2.dataout[25..25], ( mac_out2.dataout[24..24], ( mac_out2.dataout[23..23], ( mac_out2.dataout[22..22], ( mac_out2.dataout[21..21], ( mac_out2.dataout[20..20], ( mac_out2.dataout[19..18])))))))))));
	sft7a[].in = ( w85w, ( w85w, ( mac_out4.dataout[9..9], ( mac_out4.dataout[8..8], ( mac_out4.dataout[7..7], ( mac_out4.dataout[6..6], ( mac_out4.dataout[5..5], ( mac_out4.dataout[4..4], ( mac_out4.dataout[3..3], ( mac_out4.dataout[2..2], ( mac_out4.dataout[1..0])))))))))));
	sft8a[].in = add5_result[];
	result[28..0] = w140w[28..0];
	w140w[] = ( sft8a[11..10].out, sft8a[9..8].out, sft8a[7..6].out, sft8a[5..4].out, sft8a[3..2].out, sft8a[1..0].out, mac_out2.dataout[17..17], mac_out2.dataout[16..16], mac_out2.dataout[15..15], mac_out2.dataout[14..14], mac_out2.dataout[13..13], mac_out2.dataout[12..12], mac_out2.dataout[11..11], mac_out2.dataout[10..10], mac_out2.dataout[9..9], mac_out2.dataout[8..8], mac_out2.dataout[7..7], mac_out2.dataout[6..6], mac_out2.dataout[5..5], mac_out2.dataout[4..4], mac_out2.dataout[3..3], mac_out2.dataout[2..2], mac_out2.dataout[1..1], mac_out2.dataout[0..0]);
	w85w = B"0";
END;
--VALID FILE