9102_APP/logic/db/mac_out_mr82.tdf

--alt_mac_out ADDNSUB0_CLEAR="NONE" ADDNSUB0_CLOCK="NONE" ADDNSUB0_PIPELINE_CLEAR="NONE" ADDNSUB0_PIPELINE_CLOCK="NONE" ADDNSUB1_CLEAR="NONE" ADDNSUB1_CLOCK="NONE" ADDNSUB1_PIPELINE_CLEAR="NONE" ADDNSUB1_PIPELINE_CLOCK="NONE" DATAA_WIDTH=21 DATAB_WIDTH=0 DATAC_WIDTH=0 DATAD_WIDTH=0 FIRST_ADDER0_CLEAR="NONE" FIRST_ADDER0_CLOCK="NONE" OPERATION_MODE="OUTPUT_ONLY" OUTPUT_CLEAR="NONE" OUTPUT_CLOCK="NONE" OUTPUT_WIDTH=21 SIGNA_CLEAR="NONE" SIGNA_CLOCK="NONE" SIGNA_PIPELINE_CLEAR="NONE" SIGNA_PIPELINE_CLOCK="NONE" SIGNB_CLEAR="NONE" SIGNB_CLOCK="NONE" SIGNB_PIPELINE_CLEAR="NONE" SIGNB_PIPELINE_CLOCK="NONE" ZEROACC_CLEAR="NONE" ZEROACC_CLOCK="NONE" ZEROACC_PIPELINE_CLEAR="NONE" ZEROACC_PIPELINE_CLOCK="NONE" dataa dataout CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E"
--VERSION_BEGIN 13.0 cbx_alt_mac_out 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ  VERSION_END


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--synthesis_resources = 
SUBDESIGN mac_out_mr82
( 
	dataa[20..0]	:	input;
	dataout[20..0]	:	output;
) 
VARIABLE 
	first_adder0_out[20..0]	: WIRE;
	signa	: NODE;
	signb	: NODE;

BEGIN 
	dataout[] = (first_adder0_out[] & (((signa # (! signa)) # signb) # (! signb)));
	first_adder0_out[20..0] = dataa[20..0];
	signa = VCC;
	signb = VCC;
END;
--VALID FILE