9102_APP/logic/cfg_reg_test.v

// 无用接口硬接 0
assign dma_req = 1'b0;

// APB 兼容（保留但不使用，防止报错）
parameter ADDR_CTRL = 'h00;
parameter ADDR_DATA = 'h04;
wire apb_data_phase = apb_psel && apb_penable;
reg [9:0] dummy_din;

always @(posedge apb_clock or negedge apb_resetn) begin
  if (!apb_resetn)
    dummy_din <= 10'd0;
  else if (apb_data_phase && apb_pwrite && apb_paddr == ADDR_DATA)
    dummy_din <= apb_pwdata[9:0];
end

always @(*) begin
  apb_prdata = 32'd0;
end

// ------------------------------
// DDS 相位累加器（仅加法，无除法）
// ------------------------------
reg [31:0] phase;
always @(posedge apb_clock or negedge apb_resetn) begin
  if (!apb_resetn || !dac_run || !dac_en)
    phase <= 32'd0;
  else
    phase <= phase + frequency;
end

wire [9:0] phase_10bit = phase[31:22];

// ------------------------------
// 4 种波形生成（无 RAM、无除法）
// ------------------------------
wire [9:0] square_wave = (phase_10bit < (duty_cycle * 1024 / 100)) ? max_vol : min_vol;

wire [9:0] tri_wave = phase_10bit[9] ? 
    (max_vol - ((phase_10bit[8:0]) * (max_vol - min_vol) / 512)) :
    (min_vol + ((phase_10bit[8:0]) * (max_vol - min_vol) / 512));

wire [9:0] saw_wave = min_vol + ((max_vol - min_vol) * phase_10bit) / 1024;

wire [9:0] sine_wave = (phase_10bit < 512) ? 
    min_vol + ((max_vol - min_vol) * phase_10bit) / 512 :
    max_vol - ((max_vol - min_vol) * (phase_10bit - 512)) / 512;

reg [9:0] dac_data;
always @(*) begin
  case (wave_type)
    2'b00: dac_data = square_wave;
    2'b01: dac_data = sine_wave;
    2'b10: dac_data = tri_wave;
    2'b11: dac_data = saw_wave;
  endcase
end

// ------------------------------
// DAC 硬核例化
// 严格按你要求：
// dac_en   → enb
// dac_run  → stop
// bufen    → 0
// ------------------------------
alta_dac dac_inst(
  .enb      (~dac_en),        // 你要的匹配
  .bufenb   (1'b0),           // 写死 0
  .din      (dac_data),
  .stop     (~dac_run),       // 你要的匹配
  .dout     ()
);