9102_APP/logic/apb2ram.v

module apb2ram #(parameter ADDR_BITS = 32) (
  input                  resetn,
  input                  apb_clock,
  input                  apb_psel,
  input                  apb_penable,
  input                  apb_pwrite,
  input  [ADDR_BITS-1:0] apb_paddr,
  input  [31:0]          apb_pwdata,
  input  [3:0]           apb_pstrb,
  input  [2:0]           apb_pprot,
  output                 apb_pready,
  output                 apb_pslverr,
  output [31:0]          apb_prdata,
  output [9:0]           ram_addr,
  output [1:0]           ram_byteena,
  output [15:0]          ram_data,
  output                 ram_wren,
  output                 ram_rden,
  input  [15:0]          ram_q
);

assign apb_pready = 1'b1;
assign apb_pslverr = 1'b0;
assign apb_prdata = apb_paddr[1] ? {ram_q, 16'd0} : {16'd0, ram_q};

assign ram_addr = apb_paddr[ADDR_BITS-1:1];
assign ram_byteena = apb_pstrb[1:0];
assign ram_data = apb_pwdata[15:0];
assign ram_wren = apb_psel && apb_penable && apb_pwrite;
assign ram_rden = apb_psel && apb_penable && !apb_pwrite;

endmodule