9102_APP/logic/alta_db/packed.vx

`timescale 1 ps/ 1 ps

module example_board(
	BAUD_RATE,
	TEST_SINGLE,
	UART1_RX,
	so_io1,
	GPIO4_1,
	GPIO4_2,
	PIN_HSE,
	PIN_HSI,
	PLL_CLKIN,
	SPI0_CSN,
	SPI0_SCK,
	SPI0_SI_IO0,
	UART0_UARTRXD,
	UART0_UARTTXD,
	UART1_TX);
inout	BAUD_RATE;
inout	TEST_SINGLE;
inout	UART1_RX;
inout	so_io1;
inout	GPIO4_1;
inout	GPIO4_2;
input	PIN_HSE;
input	PIN_HSI;
input	PLL_CLKIN;
output	SPI0_CSN;
output	SPI0_SCK;
inout	SPI0_SI_IO0;
input	UART0_UARTRXD;
output	UART0_UARTTXD;
inout	UART1_TX;

// module alta_adc
// Design Ports Information

// module alta_dac
// Design Ports Information

// module alta_rv32
// Design Ports Information

// module example_board
// Design Ports Information
// PIN_HSE	=>  Location: PIN_C23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// SPI0_CSN	=>  Location: PIN_AF13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SPI0_SCK	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART0_UARTTXD	=>  Location: PIN_AD15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// BAUD_RATE	=>  Location: PIN_AB17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO4_1	=>  Location: PIN_AE14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO4_2	=>  Location: PIN_AB13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SPI0_SI_IO0	=>  Location: PIN_AB16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// TEST_SINGLE	=>  Location: PIN_AG25,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART1_RX	=>  Location: PIN_AG12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART1_TX	=>  Location: PIN_AC15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// so_io1	=>  Location: PIN_V27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART0_UARTRXD	=>  Location: PIN_AH12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PIN_HSI	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PLL_CLKIN	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default

// module hard_block
// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA

//wire	gnd;
//wire	gnd;
//wire	vcc;
//wire	vcc;
//wire	unknown;
//wire	unknown;
//wire	\BAUD_RATE~output_o ;
wire	\BAUD_RATE~input_o ;
//wire	\GPIO4_1~output_o ;
wire	\GPIO4_1~input_o ;
//wire	\GPIO4_2~output_o ;
wire	\GPIO4_2~input_o ;
wire	\PIN_HSE~input_o ;
//wire	hbi_69_0_9cb2c0024f9919c5_bp;
wire	\PIN_HSI~input_o ;
//wire	hbi_7_0_14f6b4c97af9700f_bp;
wire	\PLL_CLKIN~input_o ;
wire	\PLL_ENABLE~clkctrl_outclk ;
//wire	hbi_71_0_14f6b4c97af9700f_bp;
wire	\PLL_ENABLE~combout ;
wire	\PLL_LOCK~combout ;
//wire	\SPI0_CSN~output_o ;
//wire	\SPI0_SCK~output_o ;
//wire	\SPI0_SI_IO0~output_o ;
wire	\SPI0_SI_IO0~input_o ;
//wire	\TEST_SINGLE~output_o ;
wire	\TEST_SINGLE~input_o ;
wire	\UART0_UARTRXD~input_o ;
//wire	\UART0_UARTTXD~output_o ;
//wire	\UART1_RX~output_o ;
wire	\UART1_RX~input_o ;
//wire	\UART1_TX~output_o ;
wire	\UART1_TX~input_o ;
//wire	hbo_13_a8f89aa4d95b80e7_bp;
//wire	\pll_inst|auto_generated|pll1~LOCKED ;
wire	\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ;
//wire	hbo_22_f9ff3d300b43c0f2_bp;
//wire	\gclksw_inst|clkout ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
//wire	devclrn;
tri1	devclrn;
//wire	devoe;
tri1	devoe;
//wire	devpor;
tri1	devpor;
wire	[7:0] gpio0_io_in;
//wire	gpio0_io_in[1];
//wire	gpio0_io_in[2];
//wire	gpio0_io_in[3];
//wire	gpio0_io_in[4];
//wire	gpio0_io_in[5];
//wire	gpio0_io_in[6];
//wire	gpio0_io_in[7];
wire	[7:0] gpio0_io_out_data;
//wire	gpio0_io_out_data[1];
//wire	gpio0_io_out_data[2];
//wire	gpio0_io_out_data[3];
//wire	gpio0_io_out_data[4];
//wire	gpio0_io_out_data[5];
//wire	gpio0_io_out_data[6];
//wire	gpio0_io_out_data[7];
wire	[7:0] gpio0_io_out_en;
//wire	gpio0_io_out_en[1];
//wire	gpio0_io_out_en[2];
//wire	gpio0_io_out_en[3];
//wire	gpio0_io_out_en[4];
//wire	gpio0_io_out_en[5];
//wire	gpio0_io_out_en[6];
//wire	gpio0_io_out_en[7];
wire	[7:0] gpio4_io_in;
//wire	gpio4_io_in[0];
//wire	gpio4_io_in[3];
//wire	gpio4_io_in[4];
//wire	gpio4_io_in[5];
//wire	gpio4_io_in[6];
//wire	gpio4_io_in[7];
wire	[7:0] gpio4_io_out_data;
//wire	gpio4_io_out_data[0];
//wire	gpio4_io_out_data[3];
//wire	gpio4_io_out_data[4];
//wire	gpio4_io_out_data[7];
wire	[7:0] gpio4_io_out_en;
//wire	gpio4_io_out_en[0];
//wire	gpio4_io_out_en[3];
//wire	gpio4_io_out_en[4];
//wire	gpio4_io_out_en[7];
wire	[7:0] gpio6_io_in;
//wire	gpio6_io_in[0];
//wire	gpio6_io_in[2];
//wire	gpio6_io_in[4];
//wire	gpio6_io_in[5];
//wire	gpio6_io_in[6];
//wire	gpio6_io_in[7];
wire	[7:0] gpio7_io_out_data;
//wire	gpio7_io_out_data[0];
//wire	gpio7_io_out_data[1];
//wire	gpio7_io_out_data[2];
//wire	gpio7_io_out_data[3];
//wire	gpio7_io_out_data[4];
//wire	gpio7_io_out_data[5];
//wire	gpio7_io_out_data[7];
wire	[7:0] gpio7_io_out_en;
//wire	gpio7_io_out_en[0];
//wire	gpio7_io_out_en[1];
//wire	gpio7_io_out_en[2];
//wire	gpio7_io_out_en[3];
//wire	gpio7_io_out_en[4];
//wire	gpio7_io_out_en[5];
//wire	gpio7_io_out_en[7];
wire	[7:0] gpio8_io_out_data;
//wire	gpio8_io_out_data[1];
//wire	gpio8_io_out_data[2];
//wire	gpio8_io_out_data[3];
//wire	gpio8_io_out_data[4];
//wire	gpio8_io_out_data[5];
//wire	gpio8_io_out_data[6];
//wire	gpio8_io_out_data[7];
wire	[7:0] gpio8_io_out_en;
//wire	gpio8_io_out_en[1];
//wire	gpio8_io_out_en[2];
//wire	gpio8_io_out_en[3];
//wire	gpio8_io_out_en[4];
//wire	gpio8_io_out_en[5];
//wire	gpio8_io_out_en[6];
//wire	gpio8_io_out_en[7];
wire	\macro_inst|ShiftLeft0~0_combout ;
wire	\macro_inst|ShiftLeft0~1_combout ;
wire	\macro_inst|ShiftLeft0~2_combout ;
wire	\macro_inst|ShiftLeft0~3_combout ;
wire	\macro_inst|ahb2apb_inst|Selector0~0_combout ;
wire	\macro_inst|ahb2apb_inst|Selector25~0_combout ;
wire	\macro_inst|ahb2apb_inst|always0~0_combout ;
wire	\macro_inst|ahb2apb_inst|always2~0_combout ;
wire	\macro_inst|ahb2apb_inst|apbState.apbIdle~q ;
wire	\macro_inst|ahb2apb_inst|apbState.apbSetup~q ;
wire	\macro_inst|ahb2apb_inst|comb~0_combout ;
wire	[15:0] \macro_inst|ahb2apb_inst|haddr ;
//wire	\macro_inst|ahb2apb_inst|haddr [0];
//wire	\macro_inst|ahb2apb_inst|haddr [10];
//wire	\macro_inst|ahb2apb_inst|haddr [11];
//wire	\macro_inst|ahb2apb_inst|haddr [12];
//wire	\macro_inst|ahb2apb_inst|haddr [13];
//wire	\macro_inst|ahb2apb_inst|haddr [14];
//wire	\macro_inst|ahb2apb_inst|haddr [15];
//wire	\macro_inst|ahb2apb_inst|haddr [1];
//wire	\macro_inst|ahb2apb_inst|haddr [2];
//wire	\macro_inst|ahb2apb_inst|haddr [3];
//wire	\macro_inst|ahb2apb_inst|haddr [4];
//wire	\macro_inst|ahb2apb_inst|haddr [5];
//wire	\macro_inst|ahb2apb_inst|haddr [6];
//wire	\macro_inst|ahb2apb_inst|haddr [7];
//wire	\macro_inst|ahb2apb_inst|haddr [8];
//wire	\macro_inst|ahb2apb_inst|haddr [9];
wire	\macro_inst|ahb2apb_inst|hdone~0_combout ;
wire	\macro_inst|ahb2apb_inst|hdone~q ;
wire	\macro_inst|ahb2apb_inst|hreadyout~0_combout ;
wire	\macro_inst|ahb2apb_inst|hreadyout~q ;
wire	\macro_inst|ahb2apb_inst|hwrite~q ;
wire	[15:0] \macro_inst|ahb2apb_inst|paddr ;
//wire	\macro_inst|ahb2apb_inst|paddr [0];
//wire	\macro_inst|ahb2apb_inst|paddr [10];
//wire	\macro_inst|ahb2apb_inst|paddr [11];
//wire	\macro_inst|ahb2apb_inst|paddr [12];
wire	\macro_inst|ahb2apb_inst|paddr[12]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [13];
//wire	\macro_inst|ahb2apb_inst|paddr [14];
wire	\macro_inst|ahb2apb_inst|paddr[14]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [15];
wire	\macro_inst|ahb2apb_inst|paddr[15]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [1];
wire	\macro_inst|ahb2apb_inst|paddr[1]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [2];
wire	\macro_inst|ahb2apb_inst|paddr[2]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [3];
//wire	\macro_inst|ahb2apb_inst|paddr [4];
//wire	\macro_inst|ahb2apb_inst|paddr [5];
//wire	\macro_inst|ahb2apb_inst|paddr [6];
wire	\macro_inst|ahb2apb_inst|paddr[6]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [7];
wire	\macro_inst|ahb2apb_inst|paddr[7]~0_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [8];
wire	\macro_inst|ahb2apb_inst|paddr[8]~feeder_combout ;
//wire	\macro_inst|ahb2apb_inst|paddr [9];
wire	\macro_inst|ahb2apb_inst|pdone~0_combout ;
wire	\macro_inst|ahb2apb_inst|pdone~q ;
wire	\macro_inst|ahb2apb_inst|penable~q ;
wire	[31:0] \macro_inst|ahb2apb_inst|prdata ;
//wire	\macro_inst|ahb2apb_inst|prdata [0];
wire	\macro_inst|ahb2apb_inst|prdata[0]~0_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [10];
//wire	\macro_inst|ahb2apb_inst|prdata [11];
//wire	\macro_inst|ahb2apb_inst|prdata [12];
//wire	\macro_inst|ahb2apb_inst|prdata [13];
//wire	\macro_inst|ahb2apb_inst|prdata [14];
wire	\macro_inst|ahb2apb_inst|prdata[14]~12_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [15];
//wire	\macro_inst|ahb2apb_inst|prdata [16];
//wire	\macro_inst|ahb2apb_inst|prdata [17];
//wire	\macro_inst|ahb2apb_inst|prdata [18];
//wire	\macro_inst|ahb2apb_inst|prdata [19];
//wire	\macro_inst|ahb2apb_inst|prdata [1];
wire	\macro_inst|ahb2apb_inst|prdata[1]~1_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [20];
//wire	\macro_inst|ahb2apb_inst|prdata [21];
//wire	\macro_inst|ahb2apb_inst|prdata [22];
//wire	\macro_inst|ahb2apb_inst|prdata [23];
//wire	\macro_inst|ahb2apb_inst|prdata [24];
//wire	\macro_inst|ahb2apb_inst|prdata [25];
//wire	\macro_inst|ahb2apb_inst|prdata [26];
//wire	\macro_inst|ahb2apb_inst|prdata [27];
//wire	\macro_inst|ahb2apb_inst|prdata [28];
//wire	\macro_inst|ahb2apb_inst|prdata [29];
wire	\macro_inst|ahb2apb_inst|prdata[29]~13_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [2];
wire	\macro_inst|ahb2apb_inst|prdata[2]~2_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [30];
//wire	\macro_inst|ahb2apb_inst|prdata [31];
//wire	\macro_inst|ahb2apb_inst|prdata [3];
wire	\macro_inst|ahb2apb_inst|prdata[3]~3_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [4];
wire	\macro_inst|ahb2apb_inst|prdata[4]~4_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [5];
wire	\macro_inst|ahb2apb_inst|prdata[5]~5_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [6];
wire	\macro_inst|ahb2apb_inst|prdata[6]~6_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [7];
wire	\macro_inst|ahb2apb_inst|prdata[7]~7_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [8];
wire	\macro_inst|ahb2apb_inst|prdata[8]~8_combout ;
//wire	\macro_inst|ahb2apb_inst|prdata [9];
wire	\macro_inst|ahb2apb_inst|prdata[9]~10_combout ;
wire	\macro_inst|ahb2apb_inst|prdata[9]~11_combout ;
wire	\macro_inst|ahb2apb_inst|prdata[9]~9_combout ;
wire	\macro_inst|ahb2apb_inst|psel~0_combout ;
wire	\macro_inst|ahb2apb_inst|psel~q ;
wire	\macro_inst|ahb2apb_inst|pvalid~q ;
wire	\macro_inst|ahb2apb_inst|pwrite~q ;
wire	\macro_inst|always0~0_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~0_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~1_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~2_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~3_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~4_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~5_combout ;
wire	\macro_inst|apb_adc0_inst|Equal0~6_combout ;
wire	\macro_inst|apb_adc0_inst|adc_eoc_out~combout ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[0] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[10] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[11] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[1] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[2] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[3] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[4] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[5] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[6] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[7] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[8] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.db[9] ;
wire	\macro_inst|apb_adc0_inst|adc_inst.eoc ;
wire	\macro_inst|apb_adc0_inst|always1~0_combout ;
wire	[11:0] \macro_inst|apb_adc0_inst|apb_db ;
//wire	\macro_inst|apb_adc0_inst|apb_db [0];
//wire	\macro_inst|apb_adc0_inst|apb_db [10];
//wire	\macro_inst|apb_adc0_inst|apb_db [11];
//wire	\macro_inst|apb_adc0_inst|apb_db [1];
//wire	\macro_inst|apb_adc0_inst|apb_db [2];
//wire	\macro_inst|apb_adc0_inst|apb_db [3];
//wire	\macro_inst|apb_adc0_inst|apb_db [4];
//wire	\macro_inst|apb_adc0_inst|apb_db [5];
//wire	\macro_inst|apb_adc0_inst|apb_db [6];
//wire	\macro_inst|apb_adc0_inst|apb_db [7];
//wire	\macro_inst|apb_adc0_inst|apb_db [8];
//wire	\macro_inst|apb_adc0_inst|apb_db [9];
wire	\macro_inst|apb_adc0_inst|apb_eoc~q ;
wire	[15:0] \macro_inst|apb_adc0_inst|sclk_counter ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [0];
wire	\macro_inst|apb_adc0_inst|sclk_counter[0]~16_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[0]~17 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [10];
wire	\macro_inst|apb_adc0_inst|sclk_counter[10]~37_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[10]~38 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [11];
wire	\macro_inst|apb_adc0_inst|sclk_counter[11]~39_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[11]~40 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [12];
wire	\macro_inst|apb_adc0_inst|sclk_counter[12]~41_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[12]~42 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [13];
wire	\macro_inst|apb_adc0_inst|sclk_counter[13]~43_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[13]~44 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [14];
wire	\macro_inst|apb_adc0_inst|sclk_counter[14]~45_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[14]~46 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [15];
wire	\macro_inst|apb_adc0_inst|sclk_counter[15]~47_combout ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [1];
wire	\macro_inst|apb_adc0_inst|sclk_counter[1]~19_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[1]~20 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [2];
wire	\macro_inst|apb_adc0_inst|sclk_counter[2]~21_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[2]~22 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [3];
wire	\macro_inst|apb_adc0_inst|sclk_counter[3]~23_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[3]~24 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [4];
wire	\macro_inst|apb_adc0_inst|sclk_counter[4]~25_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[4]~26 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [5];
wire	\macro_inst|apb_adc0_inst|sclk_counter[5]~27_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[5]~28 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [6];
wire	\macro_inst|apb_adc0_inst|sclk_counter[6]~29_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[6]~30 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [7];
wire	\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[7]~31_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[7]~32 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [8];
wire	\macro_inst|apb_adc0_inst|sclk_counter[8]~33_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[8]~34 ;
//wire	\macro_inst|apb_adc0_inst|sclk_counter [9];
wire	\macro_inst|apb_adc0_inst|sclk_counter[9]~35_combout ;
wire	\macro_inst|apb_adc0_inst|sclk_counter[9]~36 ;
wire	\macro_inst|apb_adc0_inst|sclk~0_combout ;
wire	\macro_inst|apb_adc0_inst|sclk~q ;
wire	\macro_inst|apb_dac0_inst|Add2~20_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~21_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~22 ;
wire	\macro_inst|apb_dac0_inst|Add2~23_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~24_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~25 ;
wire	\macro_inst|apb_dac0_inst|Add2~26_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~27_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~28 ;
wire	\macro_inst|apb_dac0_inst|Add2~29_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~30_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~31 ;
wire	\macro_inst|apb_dac0_inst|Add2~32_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~33_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~34 ;
wire	\macro_inst|apb_dac0_inst|Add2~35_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~36_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~37 ;
wire	\macro_inst|apb_dac0_inst|Add2~38_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~39_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~40 ;
wire	\macro_inst|apb_dac0_inst|Add2~41_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~42_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~43 ;
wire	\macro_inst|apb_dac0_inst|Add2~44_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~45_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~46 ;
wire	\macro_inst|apb_dac0_inst|Add2~47_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~48_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~50_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~51_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~52_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~53_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~54_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~55_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~56_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~57_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~58_combout ;
wire	\macro_inst|apb_dac0_inst|Add2~59_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~0_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~1 ;
wire	\macro_inst|apb_dac0_inst|Add3~10_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~11 ;
wire	\macro_inst|apb_dac0_inst|Add3~12_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~13 ;
wire	\macro_inst|apb_dac0_inst|Add3~14_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~15 ;
wire	\macro_inst|apb_dac0_inst|Add3~16_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~17 ;
wire	\macro_inst|apb_dac0_inst|Add3~18_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~2_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~3 ;
wire	\macro_inst|apb_dac0_inst|Add3~4_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~5 ;
wire	\macro_inst|apb_dac0_inst|Add3~6_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~7 ;
wire	\macro_inst|apb_dac0_inst|Add3~8_combout ;
wire	\macro_inst|apb_dac0_inst|Add3~9 ;
wire	\macro_inst|apb_dac0_inst|Add4~0_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~1 ;
wire	\macro_inst|apb_dac0_inst|Add4~10_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~11 ;
wire	\macro_inst|apb_dac0_inst|Add4~12_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~13 ;
wire	\macro_inst|apb_dac0_inst|Add4~14_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~15 ;
wire	\macro_inst|apb_dac0_inst|Add4~16_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~17 ;
wire	\macro_inst|apb_dac0_inst|Add4~18_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~2_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~3 ;
wire	\macro_inst|apb_dac0_inst|Add4~4_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~5 ;
wire	\macro_inst|apb_dac0_inst|Add4~6_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~7 ;
wire	\macro_inst|apb_dac0_inst|Add4~8_combout ;
wire	\macro_inst|apb_dac0_inst|Add4~9 ;
wire	\macro_inst|apb_dac0_inst|Add5~0_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~1 ;
wire	\macro_inst|apb_dac0_inst|Add5~10_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~11 ;
wire	\macro_inst|apb_dac0_inst|Add5~12_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~13 ;
wire	\macro_inst|apb_dac0_inst|Add5~14_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~15 ;
wire	\macro_inst|apb_dac0_inst|Add5~16_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~17 ;
wire	\macro_inst|apb_dac0_inst|Add5~18_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~2_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~3 ;
wire	\macro_inst|apb_dac0_inst|Add5~4_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~5 ;
wire	\macro_inst|apb_dac0_inst|Add5~6_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~7 ;
wire	\macro_inst|apb_dac0_inst|Add5~8_combout ;
wire	\macro_inst|apb_dac0_inst|Add5~9 ;
wire	\macro_inst|apb_dac0_inst|LessThan0~11_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~13_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~15_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~17_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~18_combout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~1_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~3_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~5_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~7_cout ;
wire	\macro_inst|apb_dac0_inst|LessThan0~9_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ;
wire	[11:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [11];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [9];
wire	[10:0] \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a ;
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [0];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [10];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [1];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [2];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [3];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [4];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [5];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [6];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [7];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [8];
//wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [9];
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ;
wire	\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~21 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~23 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~25 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~13 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~15 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~17 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~19 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~13 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~15 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~17 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ;
wire	[11:0] \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a ;
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [0];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [10];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [11];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [1];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [2];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [3];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [4];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [5];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [6];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [7];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [8];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a ;
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [0];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [10];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [1];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [2];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [3];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [4];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [5];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [6];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [7];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [8];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a ;
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [0];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [10];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [1];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [2];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [3];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [4];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [5];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [6];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [7];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [8];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a ;
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [0];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [10];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [1];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [2];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [3];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [4];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [5];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [6];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [7];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [8];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [9];
wire	[10:0] \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a ;
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [0];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [10];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [1];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [2];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [3];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [4];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [5];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [6];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [7];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [8];
//wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [9];
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~19 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~21 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~23 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~25 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~27 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~29 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~31 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~33 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~35 ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36_combout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7_cout ;
wire	\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ;
wire	[11:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [11];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [11];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [11];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [11];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [9];
wire	[11:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [11];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [9];
wire	[10:0] \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a ;
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [0];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [10];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [1];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [2];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [3];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [4];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [5];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [6];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [7];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [8];
//wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [9];
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ;
wire	\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ;
wire	\macro_inst|apb_dac0_inst|Mux0~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux0~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux1~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux1~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux2~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux2~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux3~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux3~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux4~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux4~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux5~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux5~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux6~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux6~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~2_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~3_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~4_combout ;
wire	\macro_inst|apb_dac0_inst|Mux7~5_combout ;
wire	\macro_inst|apb_dac0_inst|Mux8~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux8~1_combout ;
wire	\macro_inst|apb_dac0_inst|Mux9~0_combout ;
wire	\macro_inst|apb_dac0_inst|Mux9~1_combout ;
wire	\macro_inst|apb_dac0_inst|always0~0_combout ;
wire	\macro_inst|apb_dac0_inst|dac_inst.dout ;
wire	\macro_inst|apb_dac0_inst|diff[0]~0_combout ;
wire	\macro_inst|apb_dac0_inst|diff[0]~1 ;
wire	\macro_inst|apb_dac0_inst|diff[1]~2_combout ;
wire	\macro_inst|apb_dac0_inst|diff[1]~3 ;
wire	\macro_inst|apb_dac0_inst|diff[2]~4_combout ;
wire	\macro_inst|apb_dac0_inst|diff[2]~5 ;
wire	\macro_inst|apb_dac0_inst|diff[3]~6_combout ;
wire	\macro_inst|apb_dac0_inst|diff[3]~7 ;
wire	\macro_inst|apb_dac0_inst|diff[4]~8_combout ;
wire	\macro_inst|apb_dac0_inst|diff[4]~9 ;
wire	\macro_inst|apb_dac0_inst|diff[5]~10_combout ;
wire	\macro_inst|apb_dac0_inst|diff[5]~11 ;
wire	\macro_inst|apb_dac0_inst|diff[6]~12_combout ;
wire	\macro_inst|apb_dac0_inst|diff[6]~13 ;
wire	\macro_inst|apb_dac0_inst|diff[7]~14_combout ;
wire	\macro_inst|apb_dac0_inst|diff[7]~15 ;
wire	\macro_inst|apb_dac0_inst|diff[8]~16_combout ;
wire	\macro_inst|apb_dac0_inst|diff[8]~17 ;
wire	\macro_inst|apb_dac0_inst|diff[9]~18_combout ;
wire	[9:0] \macro_inst|apb_dac0_inst|max_vol_r ;
//wire	\macro_inst|apb_dac0_inst|max_vol_r [0];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [1];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [2];
wire	\macro_inst|apb_dac0_inst|max_vol_r[2]~3_combout ;
//wire	\macro_inst|apb_dac0_inst|max_vol_r [3];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [4];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [5];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [6];
//wire	\macro_inst|apb_dac0_inst|max_vol_r [7];
wire	\macro_inst|apb_dac0_inst|max_vol_r[7]~2_combout ;
//wire	\macro_inst|apb_dac0_inst|max_vol_r [8];
wire	\macro_inst|apb_dac0_inst|max_vol_r[8]~1_combout ;
//wire	\macro_inst|apb_dac0_inst|max_vol_r [9];
wire	\macro_inst|apb_dac0_inst|max_vol_r[9]~0_combout ;
wire	[9:0] \macro_inst|apb_dac0_inst|min_vol_r ;
//wire	\macro_inst|apb_dac0_inst|min_vol_r [0];
wire	\macro_inst|apb_dac0_inst|min_vol_r[0]~feeder_combout ;
//wire	\macro_inst|apb_dac0_inst|min_vol_r [1];
//wire	\macro_inst|apb_dac0_inst|min_vol_r [2];
wire	\macro_inst|apb_dac0_inst|min_vol_r[2]~0_combout ;
//wire	\macro_inst|apb_dac0_inst|min_vol_r [3];
//wire	\macro_inst|apb_dac0_inst|min_vol_r [4];
//wire	\macro_inst|apb_dac0_inst|min_vol_r [5];
wire	\macro_inst|apb_dac0_inst|min_vol_r[5]~1_combout ;
//wire	\macro_inst|apb_dac0_inst|min_vol_r [6];
wire	\macro_inst|apb_dac0_inst|min_vol_r[6]~2_combout ;
//wire	\macro_inst|apb_dac0_inst|min_vol_r [7];
//wire	\macro_inst|apb_dac0_inst|min_vol_r [8];
//wire	\macro_inst|apb_dac0_inst|min_vol_r [9];
wire	[31:0] \macro_inst|apb_dac0_inst|phase_acc ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [0];
wire	\macro_inst|apb_dac0_inst|phase_acc[0]~32_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[0]~33 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [10];
wire	\macro_inst|apb_dac0_inst|phase_acc[10]~52_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[10]~53 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [11];
wire	\macro_inst|apb_dac0_inst|phase_acc[11]~54_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[11]~55 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [12];
wire	\macro_inst|apb_dac0_inst|phase_acc[12]~56_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[12]~57 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [13];
wire	\macro_inst|apb_dac0_inst|phase_acc[13]~58_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[13]~59 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [14];
wire	\macro_inst|apb_dac0_inst|phase_acc[14]~60_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[14]~61 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [15];
wire	\macro_inst|apb_dac0_inst|phase_acc[15]~62_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[15]~63 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [16];
wire	\macro_inst|apb_dac0_inst|phase_acc[16]~64_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[16]~65 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [17];
wire	\macro_inst|apb_dac0_inst|phase_acc[17]~66_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[17]~67 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [18];
wire	\macro_inst|apb_dac0_inst|phase_acc[18]~68_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[18]~69 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [19];
wire	\macro_inst|apb_dac0_inst|phase_acc[19]~70_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[19]~71 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [1];
wire	\macro_inst|apb_dac0_inst|phase_acc[1]~34_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[1]~35 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [20];
wire	\macro_inst|apb_dac0_inst|phase_acc[20]~72_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[20]~73 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [21];
wire	\macro_inst|apb_dac0_inst|phase_acc[21]~74_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[21]~75 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [22];
wire	\macro_inst|apb_dac0_inst|phase_acc[22]~76_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[22]~77 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [23];
wire	\macro_inst|apb_dac0_inst|phase_acc[23]~78_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[23]~79 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [24];
wire	\macro_inst|apb_dac0_inst|phase_acc[24]~80_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[24]~81 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [25];
wire	\macro_inst|apb_dac0_inst|phase_acc[25]~82_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[25]~83 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [26];
wire	\macro_inst|apb_dac0_inst|phase_acc[26]~84_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[26]~85 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [27];
wire	\macro_inst|apb_dac0_inst|phase_acc[27]~86_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[27]~87 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [28];
wire	\macro_inst|apb_dac0_inst|phase_acc[28]~88_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[28]~89 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [29];
wire	\macro_inst|apb_dac0_inst|phase_acc[29]~90_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[29]~91 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [2];
wire	\macro_inst|apb_dac0_inst|phase_acc[2]~36_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[2]~37 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [30];
wire	\macro_inst|apb_dac0_inst|phase_acc[30]~92_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[30]~93 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [31];
wire	\macro_inst|apb_dac0_inst|phase_acc[31]~94_combout ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [3];
wire	\macro_inst|apb_dac0_inst|phase_acc[3]~38_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[3]~39 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [4];
wire	\macro_inst|apb_dac0_inst|phase_acc[4]~40_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[4]~41 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [5];
wire	\macro_inst|apb_dac0_inst|phase_acc[5]~42_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[5]~43 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [6];
wire	\macro_inst|apb_dac0_inst|phase_acc[6]~44_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[6]~45 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [7];
wire	\macro_inst|apb_dac0_inst|phase_acc[7]~46_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[7]~47 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [8];
wire	\macro_inst|apb_dac0_inst|phase_acc[8]~48_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[8]~49 ;
//wire	\macro_inst|apb_dac0_inst|phase_acc [9];
wire	\macro_inst|apb_dac0_inst|phase_acc[9]~50_combout ;
wire	\macro_inst|apb_dac0_inst|phase_acc[9]~51 ;
wire	[9:0] \macro_inst|apb_dac0_inst|phase_r ;
//wire	\macro_inst|apb_dac0_inst|phase_r [0];
//wire	\macro_inst|apb_dac0_inst|phase_r [1];
//wire	\macro_inst|apb_dac0_inst|phase_r [2];
wire	\macro_inst|apb_dac0_inst|phase_r[2]~feeder_combout ;
//wire	\macro_inst|apb_dac0_inst|phase_r [3];
wire	\macro_inst|apb_dac0_inst|phase_r[3]~feeder_combout ;
//wire	\macro_inst|apb_dac0_inst|phase_r [4];
//wire	\macro_inst|apb_dac0_inst|phase_r [5];
//wire	\macro_inst|apb_dac0_inst|phase_r [6];
//wire	\macro_inst|apb_dac0_inst|phase_r [7];
//wire	\macro_inst|apb_dac0_inst|phase_r [8];
//wire	\macro_inst|apb_dac0_inst|phase_r [9];
wire	\macro_inst|apb_dac0_inst|sine_rom~100_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~101_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~102_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~103_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~104_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~105_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~106_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~107_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~108_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~109_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~10_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~110_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~111_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~112_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~113_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~114_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~115_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~116_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~117_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~118_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~119_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~11_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~120_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~121_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~122_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~123_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~124_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~125_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~126_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~127_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~128_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~129_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~12_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~130_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~131_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~132_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~133_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~134_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~135_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~136_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~137_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~138_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~139_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~13_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~140_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~141_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~142_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~143_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~144_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~145_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~146_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~147_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~148_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~149_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~14_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~150_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~151_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~152_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~153_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~154_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~155_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~156_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~157_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~158_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~159_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~15_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~160_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~161_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~162_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~163_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~164_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~165_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~166_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~167_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~168_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~169_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~16_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~170_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~171_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~172_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~173_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~174_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~175_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~176_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~177_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~178_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~17_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~180_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~181_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~182_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~183_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~184_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~185_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~186_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~187_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~188_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~189_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~18_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~190_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~191_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~192_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~193_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~194_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~195_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~196_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~197_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~198_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~199_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~19_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~200_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~201_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~202_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~203_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~204_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~205_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~206_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~207_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~208_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~209_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~20_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~210_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~211_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~212_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~213_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~214_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~215_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~216_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~217_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~218_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~219_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~21_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~220_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~221_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~222_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~223_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~224_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~225_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~226_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~227_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~228_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~229_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~22_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~230_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~231_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~232_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~233_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~234_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~235_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~236_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~237_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~238_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~239_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~23_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~240_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~241_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~242_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~243_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~244_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~245_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~246_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~247_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~248_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~249_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~24_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~250_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~251_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~252_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~253_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~254_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~255_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~256_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~257_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~258_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~259_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~25_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~260_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~261_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~262_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~263_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~264_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~265_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~266_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~267_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~268_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~269_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~26_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~270_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~271_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~272_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~273_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~274_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~275_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~276_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~277_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~278_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~279_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~27_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~280_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~281_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~282_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~283_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~284_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~285_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~286_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~287_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~288_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~289_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~28_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~290_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~291_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~292_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~293_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~294_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~295_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~296_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~297_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~298_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~299_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~29_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~2_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~300_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~301_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~302_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~303_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~304_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~305_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~306_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~307_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~308_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~309_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~30_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~310_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~311_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~312_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~313_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~314_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~315_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~316_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~317_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~318_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~319_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~31_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~320_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~321_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~322_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~323_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~324_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~325_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~326_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~327_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~328_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~329_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~32_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~330_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~331_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~332_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~333_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~334_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~335_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~336_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~337_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~338_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~339_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~33_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~340_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~341_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~342_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~343_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~344_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~345_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~346_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~34_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~35_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~36_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~37_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~38_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~39_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~3_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~40_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~41_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~42_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~43_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~44_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~45_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~46_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~47_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~48_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~49_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~4_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~50_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~51_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~52_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~53_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~54_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~55_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~56_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~57_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~58_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~59_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~5_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~60_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~61_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~62_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~63_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~64_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~65_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~66_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~67_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~68_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~69_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~6_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~70_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~71_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~72_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~73_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~74_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~75_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~76_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~77_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~78_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~79_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~7_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~80_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~81_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~82_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~83_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~84_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~85_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~86_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~87_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~88_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~89_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~8_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~90_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~91_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~92_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~93_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~94_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~95_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~96_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~97_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~98_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~99_combout ;
wire	\macro_inst|apb_dac0_inst|sine_rom~9_combout ;
wire	\macro_inst|apb_prdata[10]~0_combout ;
wire	\macro_inst|apb_prdata[10]~1_combout ;
wire	\macro_inst|apb_prdata[11]~2_combout ;
wire	\macro_inst|apb_prdata[12]~3_combout ;
wire	\macro_inst|apb_prdata[13]~4_combout ;
wire	\macro_inst|apb_prdata[14]~5_combout ;
wire	\macro_inst|apb_prdata[15]~6_combout ;
wire	\macro_inst|apb_prdata[16]~7_combout ;
wire	\macro_inst|apb_prdata[17]~8_combout ;
wire	\macro_inst|apb_prdata[18]~9_combout ;
wire	\macro_inst|apb_prdata[19]~10_combout ;
wire	\macro_inst|apb_prdata[20]~11_combout ;
wire	\macro_inst|apb_prdata[21]~12_combout ;
wire	\macro_inst|apb_prdata[22]~13_combout ;
wire	\macro_inst|apb_prdata[23]~14_combout ;
wire	\macro_inst|apb_prdata[24]~15_combout ;
wire	\macro_inst|apb_prdata[25]~16_combout ;
wire	\macro_inst|apb_prdata[26]~17_combout ;
wire	\macro_inst|apb_prdata[27]~18_combout ;
wire	\macro_inst|apb_prdata[28]~19_combout ;
wire	\macro_inst|apb_prdata[29]~20_combout ;
wire	\macro_inst|apb_prdata[30]~21_combout ;
wire	\macro_inst|apb_prdata[31]~22_combout ;
wire	\macro_inst|cfg_reg_inst|Equal0~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal0~1_combout ;
wire	\macro_inst|cfg_reg_inst|Equal0~2_combout ;
wire	\macro_inst|cfg_reg_inst|Equal0~3_combout ;
wire	\macro_inst|cfg_reg_inst|Equal10~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal10~1_combout ;
wire	\macro_inst|cfg_reg_inst|Equal10~2_combout ;
wire	\macro_inst|cfg_reg_inst|Equal11~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal1~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal1~1_combout ;
wire	\macro_inst|cfg_reg_inst|Equal2~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal2~1_combout ;
wire	\macro_inst|cfg_reg_inst|Equal3~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal4~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal4~1_combout ;
wire	\macro_inst|cfg_reg_inst|Equal4~2_combout ;
wire	\macro_inst|cfg_reg_inst|Equal5~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal8~0_combout ;
wire	\macro_inst|cfg_reg_inst|Equal9~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector0~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector10~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector10~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector11~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector11~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector12~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector12~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector13~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector13~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector13~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector14~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector14~combout ;
wire	\macro_inst|cfg_reg_inst|Selector15~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector15~combout ;
wire	\macro_inst|cfg_reg_inst|Selector16~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector16~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector16~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector17~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector17~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector17~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector17~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector18~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector18~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector18~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector18~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector18~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector19~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector19~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector19~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector19~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector19~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector1~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector20~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector21~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector22~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector23~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~6_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~7_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~8_combout ;
wire	\macro_inst|cfg_reg_inst|Selector24~9_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~1_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~2_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~3_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~4_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~5_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~6_combout ;
wire	\macro_inst|cfg_reg_inst|Selector25~7_combout ;
wire	\macro_inst|cfg_reg_inst|Selector2~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector3~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector4~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector5~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector6~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector7~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector8~0_combout ;
wire	\macro_inst|cfg_reg_inst|Selector9~0_combout ;
wire	[3:0] \macro_inst|cfg_reg_inst|adc_chnl_sel ;
//wire	\macro_inst|cfg_reg_inst|adc_chnl_sel [0];
wire	\macro_inst|cfg_reg_inst|adc_chnl_sel[0]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|adc_chnl_sel [1];
//wire	\macro_inst|cfg_reg_inst|adc_chnl_sel [2];
wire	\macro_inst|cfg_reg_inst|adc_chnl_sel[2]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|adc_chnl_sel [3];
wire	\macro_inst|cfg_reg_inst|adc_chnl_sel[3]~2_combout ;
wire	[7:0] \macro_inst|cfg_reg_inst|adc_clk_div ;
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [0];
wire	\macro_inst|cfg_reg_inst|adc_clk_div[0]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [1];
wire	\macro_inst|cfg_reg_inst|adc_clk_div[1]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [2];
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [3];
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [4];
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [5];
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [6];
//wire	\macro_inst|cfg_reg_inst|adc_clk_div [7];
wire	\macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout ;
wire	\macro_inst|cfg_reg_inst|adc_en~0_combout ;
wire	\macro_inst|cfg_reg_inst|adc_en~q ;
wire	\macro_inst|cfg_reg_inst|adc_restart~q ;
wire	\macro_inst|cfg_reg_inst|adc_run~0_combout ;
wire	\macro_inst|cfg_reg_inst|adc_run~q ;
wire	\macro_inst|cfg_reg_inst|always0~0_combout ;
wire	\macro_inst|cfg_reg_inst|always1~2_combout ;
wire	\macro_inst|cfg_reg_inst|dac_en~2_combout ;
wire	\macro_inst|cfg_reg_inst|dac_en~_wirecell_combout ;
wire	\macro_inst|cfg_reg_inst|dac_en~q ;
wire	\macro_inst|cfg_reg_inst|dac_run~q ;
wire	[7:0] \macro_inst|cfg_reg_inst|duty_cycle ;
//wire	\macro_inst|cfg_reg_inst|duty_cycle [0];
wire	\macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|duty_cycle [1];
wire	\macro_inst|cfg_reg_inst|duty_cycle[1]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|duty_cycle [2];
//wire	\macro_inst|cfg_reg_inst|duty_cycle [3];
//wire	\macro_inst|cfg_reg_inst|duty_cycle [4];
wire	\macro_inst|cfg_reg_inst|duty_cycle[4]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|duty_cycle [5];
wire	\macro_inst|cfg_reg_inst|duty_cycle[5]~3_combout ;
//wire	\macro_inst|cfg_reg_inst|duty_cycle [6];
//wire	\macro_inst|cfg_reg_inst|duty_cycle [7];
wire	[31:0] \macro_inst|cfg_reg_inst|frequency ;
//wire	\macro_inst|cfg_reg_inst|frequency [0];
//wire	\macro_inst|cfg_reg_inst|frequency [10];
//wire	\macro_inst|cfg_reg_inst|frequency [11];
//wire	\macro_inst|cfg_reg_inst|frequency [12];
//wire	\macro_inst|cfg_reg_inst|frequency [13];
//wire	\macro_inst|cfg_reg_inst|frequency [14];
//wire	\macro_inst|cfg_reg_inst|frequency [15];
//wire	\macro_inst|cfg_reg_inst|frequency [16];
//wire	\macro_inst|cfg_reg_inst|frequency [17];
//wire	\macro_inst|cfg_reg_inst|frequency [18];
//wire	\macro_inst|cfg_reg_inst|frequency [19];
//wire	\macro_inst|cfg_reg_inst|frequency [1];
//wire	\macro_inst|cfg_reg_inst|frequency [20];
//wire	\macro_inst|cfg_reg_inst|frequency [21];
//wire	\macro_inst|cfg_reg_inst|frequency [22];
//wire	\macro_inst|cfg_reg_inst|frequency [23];
//wire	\macro_inst|cfg_reg_inst|frequency [24];
//wire	\macro_inst|cfg_reg_inst|frequency [25];
//wire	\macro_inst|cfg_reg_inst|frequency [26];
//wire	\macro_inst|cfg_reg_inst|frequency [27];
//wire	\macro_inst|cfg_reg_inst|frequency [28];
//wire	\macro_inst|cfg_reg_inst|frequency [29];
//wire	\macro_inst|cfg_reg_inst|frequency [2];
//wire	\macro_inst|cfg_reg_inst|frequency [30];
//wire	\macro_inst|cfg_reg_inst|frequency [31];
wire	\macro_inst|cfg_reg_inst|frequency[31]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [3];
wire	\macro_inst|cfg_reg_inst|frequency[3]~6_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [4];
//wire	\macro_inst|cfg_reg_inst|frequency [5];
wire	\macro_inst|cfg_reg_inst|frequency[5]~5_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [6];
wire	\macro_inst|cfg_reg_inst|frequency[6]~4_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [7];
wire	\macro_inst|cfg_reg_inst|frequency[7]~3_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [8];
wire	\macro_inst|cfg_reg_inst|frequency[8]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|frequency [9];
wire	\macro_inst|cfg_reg_inst|frequency[9]~1_combout ;
wire	[9:0] \macro_inst|cfg_reg_inst|max_vol ;
//wire	\macro_inst|cfg_reg_inst|max_vol [0];
//wire	\macro_inst|cfg_reg_inst|max_vol [1];
//wire	\macro_inst|cfg_reg_inst|max_vol [2];
wire	\macro_inst|cfg_reg_inst|max_vol[2]~3_combout ;
//wire	\macro_inst|cfg_reg_inst|max_vol [3];
//wire	\macro_inst|cfg_reg_inst|max_vol [4];
//wire	\macro_inst|cfg_reg_inst|max_vol [5];
//wire	\macro_inst|cfg_reg_inst|max_vol [6];
//wire	\macro_inst|cfg_reg_inst|max_vol [7];
wire	\macro_inst|cfg_reg_inst|max_vol[7]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|max_vol [8];
wire	\macro_inst|cfg_reg_inst|max_vol[8]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|max_vol [9];
wire	\macro_inst|cfg_reg_inst|max_vol[9]~0_combout ;
wire	[9:0] \macro_inst|cfg_reg_inst|min_vol ;
//wire	\macro_inst|cfg_reg_inst|min_vol [0];
wire	\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|min_vol [1];
//wire	\macro_inst|cfg_reg_inst|min_vol [2];
wire	\macro_inst|cfg_reg_inst|min_vol[2]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|min_vol [3];
//wire	\macro_inst|cfg_reg_inst|min_vol [4];
//wire	\macro_inst|cfg_reg_inst|min_vol [5];
wire	\macro_inst|cfg_reg_inst|min_vol[5]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|min_vol [6];
wire	\macro_inst|cfg_reg_inst|min_vol[6]~3_combout ;
//wire	\macro_inst|cfg_reg_inst|min_vol [7];
//wire	\macro_inst|cfg_reg_inst|min_vol [8];
//wire	\macro_inst|cfg_reg_inst|min_vol [9];
wire	[31:0] \macro_inst|cfg_reg_inst|prdata ;
//wire	\macro_inst|cfg_reg_inst|prdata [0];
//wire	\macro_inst|cfg_reg_inst|prdata [10];
wire	\macro_inst|cfg_reg_inst|prdata[10]~0_combout ;
wire	\macro_inst|cfg_reg_inst|prdata[10]~1_combout ;
wire	\macro_inst|cfg_reg_inst|prdata[10]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|prdata [11];
//wire	\macro_inst|cfg_reg_inst|prdata [12];
//wire	\macro_inst|cfg_reg_inst|prdata [13];
//wire	\macro_inst|cfg_reg_inst|prdata [14];
//wire	\macro_inst|cfg_reg_inst|prdata [15];
//wire	\macro_inst|cfg_reg_inst|prdata [16];
//wire	\macro_inst|cfg_reg_inst|prdata [17];
//wire	\macro_inst|cfg_reg_inst|prdata [18];
//wire	\macro_inst|cfg_reg_inst|prdata [19];
//wire	\macro_inst|cfg_reg_inst|prdata [1];
//wire	\macro_inst|cfg_reg_inst|prdata [20];
//wire	\macro_inst|cfg_reg_inst|prdata [21];
//wire	\macro_inst|cfg_reg_inst|prdata [22];
//wire	\macro_inst|cfg_reg_inst|prdata [23];
//wire	\macro_inst|cfg_reg_inst|prdata [24];
//wire	\macro_inst|cfg_reg_inst|prdata [25];
//wire	\macro_inst|cfg_reg_inst|prdata [26];
//wire	\macro_inst|cfg_reg_inst|prdata [27];
//wire	\macro_inst|cfg_reg_inst|prdata [28];
//wire	\macro_inst|cfg_reg_inst|prdata [29];
//wire	\macro_inst|cfg_reg_inst|prdata [2];
//wire	\macro_inst|cfg_reg_inst|prdata [30];
//wire	\macro_inst|cfg_reg_inst|prdata [31];
//wire	\macro_inst|cfg_reg_inst|prdata [3];
//wire	\macro_inst|cfg_reg_inst|prdata [4];
//wire	\macro_inst|cfg_reg_inst|prdata [5];
//wire	\macro_inst|cfg_reg_inst|prdata [6];
//wire	\macro_inst|cfg_reg_inst|prdata [7];
//wire	\macro_inst|cfg_reg_inst|prdata [8];
//wire	\macro_inst|cfg_reg_inst|prdata [9];
wire	\macro_inst|cfg_reg_inst|prdata~3_combout ;
wire	\macro_inst|cfg_reg_inst|prdata~4_combout ;
wire	\macro_inst|cfg_reg_inst|prdata~5_combout ;
wire	\macro_inst|cfg_reg_inst|prdata~6_combout ;
wire	\macro_inst|cfg_reg_inst|prdata~7_combout ;
wire	\macro_inst|cfg_reg_inst|prdata~8_combout ;
wire	[15:0] \macro_inst|cfg_reg_inst|trig_auto_timeout ;
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [0];
wire	\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [10];
wire	\macro_inst|cfg_reg_inst|trig_auto_timeout[10]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [11];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [12];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [13];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [14];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [15];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [1];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [2];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [3];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [4];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [5];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [6];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [7];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [8];
//wire	\macro_inst|cfg_reg_inst|trig_auto_timeout [9];
wire	[1:0] \macro_inst|cfg_reg_inst|trig_edge ;
//wire	\macro_inst|cfg_reg_inst|trig_edge [0];
//wire	\macro_inst|cfg_reg_inst|trig_edge [1];
wire	[1:0] \macro_inst|cfg_reg_inst|trig_mode ;
//wire	\macro_inst|cfg_reg_inst|trig_mode [0];
//wire	\macro_inst|cfg_reg_inst|trig_mode [1];
wire	\macro_inst|cfg_reg_inst|trig_mode[1]~0_combout ;
wire	[15:0] \macro_inst|cfg_reg_inst|trig_pulse_width ;
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [0];
wire	\macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [10];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [11];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [12];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [13];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [14];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [15];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [1];
wire	\macro_inst|cfg_reg_inst|trig_pulse_width[1]~3_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [2];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [3];
wire	\macro_inst|cfg_reg_inst|trig_pulse_width[3]~4_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [4];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [5];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [6];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [7];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [8];
//wire	\macro_inst|cfg_reg_inst|trig_pulse_width [9];
wire	[11:0] \macro_inst|cfg_reg_inst|trig_threshold ;
//wire	\macro_inst|cfg_reg_inst|trig_threshold [0];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [10];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [11];
wire	\macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout ;
wire	\macro_inst|cfg_reg_inst|trig_threshold[11]~1_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_threshold [1];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [2];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [3];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [4];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [5];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [6];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [7];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [8];
//wire	\macro_inst|cfg_reg_inst|trig_threshold [9];
wire	[4:0] \macro_inst|cfg_reg_inst|trig_time_slot ;
//wire	\macro_inst|cfg_reg_inst|trig_time_slot [0];
wire	\macro_inst|cfg_reg_inst|trig_time_slot[0]~0_combout ;
//wire	\macro_inst|cfg_reg_inst|trig_time_slot [1];
//wire	\macro_inst|cfg_reg_inst|trig_time_slot [2];
//wire	\macro_inst|cfg_reg_inst|trig_time_slot [3];
//wire	\macro_inst|cfg_reg_inst|trig_time_slot [4];
wire	[1:0] \macro_inst|cfg_reg_inst|wave_type ;
//wire	\macro_inst|cfg_reg_inst|wave_type [0];
//wire	\macro_inst|cfg_reg_inst|wave_type [1];
wire	\macro_inst|cfg_reg_inst|wave_type[1]~0_combout ;
wire	\macro_inst|mem_apb_psel~0_combout ;
wire	\macro_inst|mem_apb_psel~combout ;
wire	[3:0] \macro_inst|pr_select ;
//wire	\macro_inst|pr_select [0];
//wire	\macro_inst|pr_select [1];
//wire	\macro_inst|pr_select [2];
//wire	\macro_inst|pr_select [3];
wire	\macro_inst|trig_ctrl_inst|Add0~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~1 ;
wire	\macro_inst|trig_ctrl_inst|Add0~10_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~11 ;
wire	\macro_inst|trig_ctrl_inst|Add0~12_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~13 ;
wire	\macro_inst|trig_ctrl_inst|Add0~14_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~15 ;
wire	\macro_inst|trig_ctrl_inst|Add0~16_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~17 ;
wire	\macro_inst|trig_ctrl_inst|Add0~18_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~19 ;
wire	\macro_inst|trig_ctrl_inst|Add0~20_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~21 ;
wire	\macro_inst|trig_ctrl_inst|Add0~22_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~23 ;
wire	\macro_inst|trig_ctrl_inst|Add0~24_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~25 ;
wire	\macro_inst|trig_ctrl_inst|Add0~26_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~27 ;
wire	\macro_inst|trig_ctrl_inst|Add0~28_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~29 ;
wire	\macro_inst|trig_ctrl_inst|Add0~2_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~3 ;
wire	\macro_inst|trig_ctrl_inst|Add0~30_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~31 ;
wire	\macro_inst|trig_ctrl_inst|Add0~32_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~4_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~5 ;
wire	\macro_inst|trig_ctrl_inst|Add0~6_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~7 ;
wire	\macro_inst|trig_ctrl_inst|Add0~8_combout ;
wire	\macro_inst|trig_ctrl_inst|Add0~9 ;
wire	\macro_inst|trig_ctrl_inst|Add3~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~1 ;
wire	\macro_inst|trig_ctrl_inst|Add3~10_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~11 ;
wire	\macro_inst|trig_ctrl_inst|Add3~12_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~13 ;
wire	\macro_inst|trig_ctrl_inst|Add3~14_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~15 ;
wire	\macro_inst|trig_ctrl_inst|Add3~16_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~17 ;
wire	\macro_inst|trig_ctrl_inst|Add3~18_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~19 ;
wire	\macro_inst|trig_ctrl_inst|Add3~20_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~21 ;
wire	\macro_inst|trig_ctrl_inst|Add3~22_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~23 ;
wire	\macro_inst|trig_ctrl_inst|Add3~24_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~25 ;
wire	\macro_inst|trig_ctrl_inst|Add3~26_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~27 ;
wire	\macro_inst|trig_ctrl_inst|Add3~28_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~29 ;
wire	\macro_inst|trig_ctrl_inst|Add3~2_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~3 ;
wire	\macro_inst|trig_ctrl_inst|Add3~30_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~31 ;
wire	\macro_inst|trig_ctrl_inst|Add3~32_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~4_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~5 ;
wire	\macro_inst|trig_ctrl_inst|Add3~6_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~7 ;
wire	\macro_inst|trig_ctrl_inst|Add3~8_combout ;
wire	\macro_inst|trig_ctrl_inst|Add3~9 ;
wire	\macro_inst|trig_ctrl_inst|Decoder0~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Decoder0~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Decoder0~2_combout ;
wire	\macro_inst|trig_ctrl_inst|Decoder1~0_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~23_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~25_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~27_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~29_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~30_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan0~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan1~0_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan1~1_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan1~2_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~22_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan2~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~22_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan3~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~22_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan4~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~22_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan5~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~11_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~13_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~15_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~17_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~19_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~1_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~21_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~23_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~25_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~27_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~29_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~30_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~3_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~5_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~7_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan6~9_cout ;
wire	\macro_inst|trig_ctrl_inst|LessThan7~0_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan7~1_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan7~2_combout ;
wire	\macro_inst|trig_ctrl_inst|LessThan7~3_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~10_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~2_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~3_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~4_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~5_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~6_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~7_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~8_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector0~9_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector1~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector1~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector2~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector2~2_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector3~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector3~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector4~0_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector4~1_combout ;
wire	\macro_inst|trig_ctrl_inst|Selector5~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr0~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr0~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr1~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr1~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr2~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr2~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr3~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr3~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr4~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr4~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr5~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr5~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr6~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr6~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr7~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr7~1_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr8~0_combout ;
wire	\macro_inst|trig_ctrl_inst|WideOr8~1_combout ;
wire	[11:0] \macro_inst|trig_ctrl_inst|adc_data_prev ;
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [0];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [10];
wire	\macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout ;
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [11];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [1];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [2];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [3];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [4];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [5];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [6];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [7];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [8];
//wire	\macro_inst|trig_ctrl_inst|adc_data_prev [9];
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~0_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~10_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~11_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~12_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~2_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~3_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~4_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~5_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~6_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~7_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~8_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_data_prev~9_combout ;
wire	\macro_inst|trig_ctrl_inst|adc_eoc_sync1~q ;
wire	\macro_inst|trig_ctrl_inst|adc_eoc_sync2~q ;
wire	\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ;
wire	\macro_inst|trig_ctrl_inst|adc_rst_sync1~q ;
wire	\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ;
wire	\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~1 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~3 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~5 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~7 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~9 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~11 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~13 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~15 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16_combout ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~17 ;
wire	\macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|always11~2_combout ;
wire	\macro_inst|trig_ctrl_inst|always1~1_combout ;
wire	\macro_inst|trig_ctrl_inst|always1~2_combout ;
wire	\macro_inst|trig_ctrl_inst|always4~0_combout ;
wire	\macro_inst|trig_ctrl_inst|always4~1_combout ;
wire	\macro_inst|trig_ctrl_inst|always4~2_combout ;
wire	\macro_inst|trig_ctrl_inst|always5~0_combout ;
wire	\macro_inst|trig_ctrl_inst|always5~1_combout ;
wire	\macro_inst|trig_ctrl_inst|always5~2_combout ;
wire	\macro_inst|trig_ctrl_inst|always5~3_combout ;
wire	\macro_inst|trig_ctrl_inst|always9~0_combout ;
wire	[9:0] \macro_inst|trig_ctrl_inst|auto_wait_cnt ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [0];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~12_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~13 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [1];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~14_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~15 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [2];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~16_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~17 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [3];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~19 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [4];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~20_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~21 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [5];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~22_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~23 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [6];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~24_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~25 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [7];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~26_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~27 ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [8];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~28_combout ;
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~29 ;
//wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt [9];
wire	\macro_inst|trig_ctrl_inst|auto_wait_cnt[9]~30_combout ;
wire	\macro_inst|trig_ctrl_inst|curr_state.DONE~q ;
wire	\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ;
wire	\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ;
wire	\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ;
wire	\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ;
wire	[15:0] \macro_inst|trig_ctrl_inst|decim_factor ;
//wire	\macro_inst|trig_ctrl_inst|decim_factor [0];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [10];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [11];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [12];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [13];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [14];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [15];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [1];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [2];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [3];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [4];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [5];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [6];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [7];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [8];
//wire	\macro_inst|trig_ctrl_inst|decim_factor [9];
wire	\macro_inst|trig_ctrl_inst|decim_factor~0_combout ;
wire	\macro_inst|trig_ctrl_inst|decim_factor~1_combout ;
wire	\macro_inst|trig_ctrl_inst|decim_factor~2_combout ;
wire	\macro_inst|trig_ctrl_inst|edge_trigger~0_combout ;
wire	\macro_inst|trig_ctrl_inst|edge_trigger~1_combout ;
wire	\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ;
wire	\macro_inst|trig_ctrl_inst|edge_trigger~3_combout ;
wire	\macro_inst|trig_ctrl_inst|edge_trigger~4_combout ;
wire	[15:0] \macro_inst|trig_ctrl_inst|eoc_cnt ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [0];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[0]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[0]~19 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [10];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[10]~38_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[10]~39 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [11];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[11]~40_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[11]~41 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [12];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[12]~42_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[12]~43 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [13];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[13]~44_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[13]~45 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [14];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[14]~46_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[14]~47 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [15];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[15]~48_combout ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [1];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[1]~20_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[1]~21 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [2];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[2]~22_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[2]~23 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [3];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[3]~24_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[3]~25 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [4];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[4]~26_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[4]~27 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [5];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[5]~28_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[5]~29 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [6];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[6]~30_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[6]~31 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [7];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[7]~32_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[7]~33 ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [8];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[8]~34_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[8]~35 ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout ;
//wire	\macro_inst|trig_ctrl_inst|eoc_cnt [9];
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[9]~36_combout ;
wire	\macro_inst|trig_ctrl_inst|eoc_cnt[9]~37 ;
wire	[10:0] \macro_inst|trig_ctrl_inst|gap_cnt_auto ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [0];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~11_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~12 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [10];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[10]~36_combout ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [1];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~19 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [2];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~20_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~21 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [3];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~22_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~23 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [4];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~24_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~25 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [5];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~26_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~27 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [6];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~28_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~29 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [7];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~30_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~31 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [8];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~32_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~33 ;
//wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto [9];
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~34_combout ;
wire	\macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~35 ;
wire	[9:0] \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge ;
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [0];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [1];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [2];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [3];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [4];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [5];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [6];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [7];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [8];
//wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [9];
wire	\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge~0_combout ;
wire	[8:0] \macro_inst|trig_ctrl_inst|post_trig_cnt ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [0];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[0]~10 ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[0]~9_combout ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [1];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[1]~12_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[1]~13 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [2];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[2]~14_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[2]~15 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [3];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[3]~16_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[3]~17 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [4];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[4]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[4]~19 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [5];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[5]~20_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[5]~21 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [6];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[6]~22_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[6]~23 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [7];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[7]~24_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[7]~25 ;
//wire	\macro_inst|trig_ctrl_inst|post_trig_cnt [8];
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout ;
wire	\macro_inst|trig_ctrl_inst|post_trig_cnt[8]~26_combout ;
wire	[31:0] \macro_inst|trig_ctrl_inst|prdata ;
//wire	\macro_inst|trig_ctrl_inst|prdata [0];
//wire	\macro_inst|trig_ctrl_inst|prdata [10];
//wire	\macro_inst|trig_ctrl_inst|prdata [11];
//wire	\macro_inst|trig_ctrl_inst|prdata [12];
//wire	\macro_inst|trig_ctrl_inst|prdata [13];
//wire	\macro_inst|trig_ctrl_inst|prdata [14];
//wire	\macro_inst|trig_ctrl_inst|prdata [15];
//wire	\macro_inst|trig_ctrl_inst|prdata [16];
//wire	\macro_inst|trig_ctrl_inst|prdata [17];
//wire	\macro_inst|trig_ctrl_inst|prdata [18];
//wire	\macro_inst|trig_ctrl_inst|prdata [19];
//wire	\macro_inst|trig_ctrl_inst|prdata [1];
//wire	\macro_inst|trig_ctrl_inst|prdata [20];
//wire	\macro_inst|trig_ctrl_inst|prdata [21];
//wire	\macro_inst|trig_ctrl_inst|prdata [22];
//wire	\macro_inst|trig_ctrl_inst|prdata [23];
//wire	\macro_inst|trig_ctrl_inst|prdata [24];
//wire	\macro_inst|trig_ctrl_inst|prdata [25];
//wire	\macro_inst|trig_ctrl_inst|prdata [26];
//wire	\macro_inst|trig_ctrl_inst|prdata [27];
//wire	\macro_inst|trig_ctrl_inst|prdata [28];
//wire	\macro_inst|trig_ctrl_inst|prdata [29];
//wire	\macro_inst|trig_ctrl_inst|prdata [2];
//wire	\macro_inst|trig_ctrl_inst|prdata [30];
//wire	\macro_inst|trig_ctrl_inst|prdata [31];
//wire	\macro_inst|trig_ctrl_inst|prdata [3];
//wire	\macro_inst|trig_ctrl_inst|prdata [4];
//wire	\macro_inst|trig_ctrl_inst|prdata [5];
//wire	\macro_inst|trig_ctrl_inst|prdata [6];
//wire	\macro_inst|trig_ctrl_inst|prdata [7];
//wire	\macro_inst|trig_ctrl_inst|prdata [8];
//wire	\macro_inst|trig_ctrl_inst|prdata [9];
wire	\macro_inst|trig_ctrl_inst|prdata~0_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~1_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~2_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~3_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~4_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~5_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~6_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~7_combout ;
wire	\macro_inst|trig_ctrl_inst|prdata~8_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_active~0_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_active~1_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_active~2_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_active~3_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_active~q ;
wire	[15:0] \macro_inst|trig_ctrl_inst|pulse_cnt ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [0];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[0]~19_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[0]~20 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [10];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[10]~39_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[10]~40 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [11];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[11]~41_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[11]~42 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [12];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~18_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~43_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~44 ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~52_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~53_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[12]~55_combout ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [13];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[13]~45_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[13]~46 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [14];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[14]~47_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[14]~48 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [15];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[15]~49_combout ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [1];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[1]~21_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[1]~22 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [2];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[2]~23_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[2]~24 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [3];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[3]~25_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[3]~26 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [4];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[4]~27_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[4]~28 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [5];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[5]~29_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[5]~30 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [6];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[6]~31_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[6]~32 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [7];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[7]~33_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[7]~34 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [8];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[8]~35_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[8]~36 ;
//wire	\macro_inst|trig_ctrl_inst|pulse_cnt [9];
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[9]~37_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_cnt[9]~38 ;
wire	\macro_inst|trig_ctrl_inst|pulse_level~2_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_level~3_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_level~4_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_level~q ;
wire	\macro_inst|trig_ctrl_inst|pulse_trigger~0_combout ;
wire	\macro_inst|trig_ctrl_inst|pulse_trigger~q ;
wire	[9:0] \macro_inst|trig_ctrl_inst|ram_wr_addr ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [0];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[0]~10_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[0]~11 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [1];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[1]~13_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[1]~14 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [2];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[2]~15_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[2]~16 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [3];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[3]~17_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[3]~18 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [4];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[4]~19_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[4]~20 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [5];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[5]~21_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[5]~22 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [6];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~23_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~24 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [7];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[7]~25_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[7]~26 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [8];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[8]~27_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[8]~28 ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_addr [9];
wire	\macro_inst|trig_ctrl_inst|ram_wr_addr[9]~29_combout ;
wire	[15:0] \macro_inst|trig_ctrl_inst|ram_wr_data_b ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [0];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[0]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [10];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[10]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [11];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[11]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [12];
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [13];
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [14];
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [15];
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [1];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[1]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [2];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[2]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [3];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[3]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [4];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[4]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [5];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[5]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [6];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[6]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [7];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[7]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [8];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[8]~feeder_combout ;
//wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b [9];
wire	\macro_inst|trig_ctrl_inst|ram_wr_data_b[9]~feeder_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wren_b~0_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wren_b~feeder_combout ;
wire	\macro_inst|trig_ctrl_inst|ram_wren_b~q ;
wire	\macro_inst|trig_ctrl_inst|sample_valid~combout ;
wire	\macro_inst|trig_ctrl_inst|single_shot_lock~2_combout ;
wire	\macro_inst|trig_ctrl_inst|single_shot_lock~3_combout ;
wire	\macro_inst|trig_ctrl_inst|single_shot_lock~q ;
wire	\macro_inst|trig_ctrl_inst|trig_done~0_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_done~q ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~0_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~1_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~2_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~4_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_comb~6_combout ;
wire	\macro_inst|trig_ctrl_inst|trig_hit_reg~q ;
wire	[9:0] \macro_inst|trig_ctrl_inst|trigger_ptr ;
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [0];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [1];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [2];
wire	\macro_inst|trig_ctrl_inst|trigger_ptr[2]~1_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout ;
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [3];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [4];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [5];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [6];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [7];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [8];
//wire	\macro_inst|trig_ctrl_inst|trigger_ptr [9];
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~0_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~10_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~11_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~3_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~4_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~5_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~6_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~7_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~8_combout ;
wire	\macro_inst|trig_ctrl_inst|trigger_ptr~9_combout ;
wire	\macro_inst|trig_ctrl_inst|write_strobe~0_combout ;
wire	\macro_inst|trig_ctrl_inst|write_strobe~q ;
wire	\macro_inst|u_apb2ram|ram_rden~0_combout ;
wire	\macro_inst|u_apb2ram|ram_wren~0_combout ;
wire	[15:0] \macro_inst|u_dual_port_ram|auto_generated|q_a ;
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [0];
wire	[8:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus ;
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [0];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [10];
wire	[8:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus ;
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [1];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [11];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [2];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [12];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [3];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [13];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [4];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [14];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [5];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [15];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [6];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [1];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [1];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [2];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [2];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [3];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [3];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [4];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [4];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [5];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [5];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [6];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [6];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [7];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [7];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [8];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [8];
//wire	\macro_inst|u_dual_port_ram|auto_generated|q_a [9];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [0];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [7];
//wire	\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [8];
wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
wire	\pll_inst|auto_generated|pll_lock_sync~q ;
wire	\rv32.dmactive ;
wire	\rv32.ext_dma_DMACCLR[0] ;
wire	\rv32.ext_dma_DMACCLR[1] ;
wire	\rv32.ext_dma_DMACCLR[2] ;
wire	\rv32.ext_dma_DMACCLR[3] ;
wire	\rv32.ext_dma_DMACTC[0] ;
wire	\rv32.ext_dma_DMACTC[1] ;
wire	\rv32.ext_dma_DMACTC[2] ;
wire	\rv32.ext_dma_DMACTC[3] ;
wire	\rv32.gpio0_io_out_data[0] ;
wire	\rv32.gpio0_io_out_data[1] ;
wire	\rv32.gpio0_io_out_data[2] ;
wire	\rv32.gpio0_io_out_data[3] ;
wire	\rv32.gpio0_io_out_data[4] ;
wire	\rv32.gpio0_io_out_data[5] ;
wire	\rv32.gpio0_io_out_data[6] ;
wire	\rv32.gpio0_io_out_data[7] ;
wire	\rv32.gpio0_io_out_en[0] ;
wire	\rv32.gpio0_io_out_en[1] ;
wire	\rv32.gpio0_io_out_en[2] ;
wire	\rv32.gpio0_io_out_en[3] ;
wire	\rv32.gpio0_io_out_en[4] ;
wire	\rv32.gpio0_io_out_en[5] ;
wire	\rv32.gpio0_io_out_en[6] ;
wire	\rv32.gpio0_io_out_en[7] ;
wire	\rv32.gpio1_io_out_data[0] ;
wire	\rv32.gpio1_io_out_data[1] ;
wire	\rv32.gpio1_io_out_data[2] ;
wire	\rv32.gpio1_io_out_data[3] ;
wire	\rv32.gpio1_io_out_data[4] ;
wire	\rv32.gpio1_io_out_data[5] ;
wire	\rv32.gpio1_io_out_data[6] ;
wire	\rv32.gpio1_io_out_data[7] ;
wire	\rv32.gpio1_io_out_en[0] ;
wire	\rv32.gpio1_io_out_en[1] ;
wire	\rv32.gpio1_io_out_en[2] ;
wire	\rv32.gpio1_io_out_en[3] ;
wire	\rv32.gpio1_io_out_en[4] ;
wire	\rv32.gpio1_io_out_en[5] ;
wire	\rv32.gpio1_io_out_en[6] ;
wire	\rv32.gpio1_io_out_en[7] ;
wire	\rv32.gpio2_io_out_data[0] ;
wire	\rv32.gpio2_io_out_data[1] ;
wire	\rv32.gpio2_io_out_data[2] ;
wire	\rv32.gpio2_io_out_data[3] ;
wire	\rv32.gpio2_io_out_data[4] ;
wire	\rv32.gpio2_io_out_data[5] ;
wire	\rv32.gpio2_io_out_data[6] ;
wire	\rv32.gpio2_io_out_data[7] ;
wire	\rv32.gpio2_io_out_en[0] ;
wire	\rv32.gpio2_io_out_en[1] ;
wire	\rv32.gpio2_io_out_en[2] ;
wire	\rv32.gpio2_io_out_en[3] ;
wire	\rv32.gpio2_io_out_en[4] ;
wire	\rv32.gpio2_io_out_en[5] ;
wire	\rv32.gpio2_io_out_en[6] ;
wire	\rv32.gpio2_io_out_en[7] ;
wire	\rv32.gpio3_io_out_data[0] ;
wire	\rv32.gpio3_io_out_data[1] ;
wire	\rv32.gpio3_io_out_data[2] ;
wire	\rv32.gpio3_io_out_data[3] ;
wire	\rv32.gpio3_io_out_data[4] ;
wire	\rv32.gpio3_io_out_data[5] ;
wire	\rv32.gpio3_io_out_data[6] ;
wire	\rv32.gpio3_io_out_data[7] ;
wire	\rv32.gpio3_io_out_en[0] ;
wire	\rv32.gpio3_io_out_en[1] ;
wire	\rv32.gpio3_io_out_en[2] ;
wire	\rv32.gpio3_io_out_en[3] ;
wire	\rv32.gpio3_io_out_en[4] ;
wire	\rv32.gpio3_io_out_en[5] ;
wire	\rv32.gpio3_io_out_en[6] ;
wire	\rv32.gpio3_io_out_en[7] ;
wire	\rv32.gpio4_io_out_data[0] ;
wire	\rv32.gpio4_io_out_data[1] ;
wire	\rv32.gpio4_io_out_data[2] ;
wire	\rv32.gpio4_io_out_data[3] ;
wire	\rv32.gpio4_io_out_data[4] ;
wire	\rv32.gpio4_io_out_data[5] ;
wire	\rv32.gpio4_io_out_data[6] ;
wire	\rv32.gpio4_io_out_data[7] ;
wire	\rv32.gpio4_io_out_en[0] ;
wire	\rv32.gpio4_io_out_en[1] ;
wire	\rv32.gpio4_io_out_en[2] ;
wire	\rv32.gpio4_io_out_en[3] ;
wire	\rv32.gpio4_io_out_en[4] ;
wire	\rv32.gpio4_io_out_en[5] ;
wire	\rv32.gpio4_io_out_en[6] ;
wire	\rv32.gpio4_io_out_en[7] ;
wire	\rv32.gpio5_io_out_data[0] ;
wire	\rv32.gpio5_io_out_data[1] ;
wire	\rv32.gpio5_io_out_data[2] ;
wire	\rv32.gpio5_io_out_data[3] ;
wire	\rv32.gpio5_io_out_data[4] ;
wire	\rv32.gpio5_io_out_data[5] ;
wire	\rv32.gpio5_io_out_data[6] ;
wire	\rv32.gpio5_io_out_data[7] ;
wire	\rv32.gpio5_io_out_en[0] ;
wire	\rv32.gpio5_io_out_en[1] ;
wire	\rv32.gpio5_io_out_en[2] ;
wire	\rv32.gpio5_io_out_en[3] ;
wire	\rv32.gpio5_io_out_en[4] ;
wire	\rv32.gpio5_io_out_en[5] ;
wire	\rv32.gpio5_io_out_en[6] ;
wire	\rv32.gpio5_io_out_en[7] ;
wire	\rv32.gpio6_io_out_data[0] ;
wire	\rv32.gpio6_io_out_data[1] ;
wire	\rv32.gpio6_io_out_data[2] ;
wire	\rv32.gpio6_io_out_data[3] ;
wire	\rv32.gpio6_io_out_data[4] ;
wire	\rv32.gpio6_io_out_data[5] ;
wire	\rv32.gpio6_io_out_data[6] ;
wire	\rv32.gpio6_io_out_data[7] ;
wire	\rv32.gpio6_io_out_en[0] ;
wire	\rv32.gpio6_io_out_en[1] ;
wire	\rv32.gpio6_io_out_en[2] ;
wire	\rv32.gpio6_io_out_en[3] ;
wire	\rv32.gpio6_io_out_en[4] ;
wire	\rv32.gpio6_io_out_en[5] ;
wire	\rv32.gpio6_io_out_en[6] ;
wire	\rv32.gpio6_io_out_en[7] ;
wire	\rv32.gpio7_io_out_data[0] ;
wire	\rv32.gpio7_io_out_data[1] ;
wire	\rv32.gpio7_io_out_data[2] ;
wire	\rv32.gpio7_io_out_data[3] ;
wire	\rv32.gpio7_io_out_data[4] ;
wire	\rv32.gpio7_io_out_data[5] ;
wire	\rv32.gpio7_io_out_data[6] ;
wire	\rv32.gpio7_io_out_data[7] ;
wire	\rv32.gpio7_io_out_en[0] ;
wire	\rv32.gpio7_io_out_en[1] ;
wire	\rv32.gpio7_io_out_en[2] ;
wire	\rv32.gpio7_io_out_en[3] ;
wire	\rv32.gpio7_io_out_en[4] ;
wire	\rv32.gpio7_io_out_en[5] ;
wire	\rv32.gpio7_io_out_en[6] ;
wire	\rv32.gpio7_io_out_en[7] ;
wire	\rv32.gpio8_io_out_data[0] ;
wire	\rv32.gpio8_io_out_data[1] ;
wire	\rv32.gpio8_io_out_data[2] ;
wire	\rv32.gpio8_io_out_data[3] ;
wire	\rv32.gpio8_io_out_data[4] ;
wire	\rv32.gpio8_io_out_data[5] ;
wire	\rv32.gpio8_io_out_data[6] ;
wire	\rv32.gpio8_io_out_data[7] ;
wire	\rv32.gpio8_io_out_en[0] ;
wire	\rv32.gpio8_io_out_en[1] ;
wire	\rv32.gpio8_io_out_en[2] ;
wire	\rv32.gpio8_io_out_en[3] ;
wire	\rv32.gpio8_io_out_en[4] ;
wire	\rv32.gpio8_io_out_en[5] ;
wire	\rv32.gpio8_io_out_en[6] ;
wire	\rv32.gpio8_io_out_en[7] ;
wire	\rv32.gpio9_io_out_data[0] ;
wire	\rv32.gpio9_io_out_data[1] ;
wire	\rv32.gpio9_io_out_data[2] ;
wire	\rv32.gpio9_io_out_data[3] ;
wire	\rv32.gpio9_io_out_data[4] ;
wire	\rv32.gpio9_io_out_data[5] ;
wire	\rv32.gpio9_io_out_data[6] ;
wire	\rv32.gpio9_io_out_data[7] ;
wire	\rv32.gpio9_io_out_en[0] ;
wire	\rv32.gpio9_io_out_en[1] ;
wire	\rv32.gpio9_io_out_en[2] ;
wire	\rv32.gpio9_io_out_en[3] ;
wire	\rv32.gpio9_io_out_en[4] ;
wire	\rv32.gpio9_io_out_en[5] ;
wire	\rv32.gpio9_io_out_en[6] ;
wire	\rv32.gpio9_io_out_en[7] ;
wire	\rv32.mem_ahb_haddr[0] ;
wire	\rv32.mem_ahb_haddr[10] ;
wire	\rv32.mem_ahb_haddr[11] ;
wire	\rv32.mem_ahb_haddr[12] ;
wire	\rv32.mem_ahb_haddr[13] ;
wire	\rv32.mem_ahb_haddr[14] ;
wire	\rv32.mem_ahb_haddr[15] ;
wire	\rv32.mem_ahb_haddr[16] ;
wire	\rv32.mem_ahb_haddr[17] ;
wire	\rv32.mem_ahb_haddr[18] ;
wire	\rv32.mem_ahb_haddr[19] ;
wire	\rv32.mem_ahb_haddr[1] ;
wire	\rv32.mem_ahb_haddr[20] ;
wire	\rv32.mem_ahb_haddr[21] ;
wire	\rv32.mem_ahb_haddr[22] ;
wire	\rv32.mem_ahb_haddr[23] ;
wire	\rv32.mem_ahb_haddr[24] ;
wire	\rv32.mem_ahb_haddr[25] ;
wire	\rv32.mem_ahb_haddr[26] ;
wire	\rv32.mem_ahb_haddr[27] ;
wire	\rv32.mem_ahb_haddr[28] ;
wire	\rv32.mem_ahb_haddr[29] ;
wire	\rv32.mem_ahb_haddr[2] ;
wire	\rv32.mem_ahb_haddr[30] ;
wire	\rv32.mem_ahb_haddr[31] ;
wire	\rv32.mem_ahb_haddr[3] ;
wire	\rv32.mem_ahb_haddr[4] ;
wire	\rv32.mem_ahb_haddr[5] ;
wire	\rv32.mem_ahb_haddr[6] ;
wire	\rv32.mem_ahb_haddr[7] ;
wire	\rv32.mem_ahb_haddr[8] ;
wire	\rv32.mem_ahb_haddr[9] ;
wire	\rv32.mem_ahb_hburst[0] ;
wire	\rv32.mem_ahb_hburst[1] ;
wire	\rv32.mem_ahb_hburst[2] ;
wire	\rv32.mem_ahb_hready ;
wire	\rv32.mem_ahb_hsize[0] ;
wire	\rv32.mem_ahb_hsize[1] ;
wire	\rv32.mem_ahb_hsize[2] ;
wire	\rv32.mem_ahb_htrans[0] ;
wire	\rv32.mem_ahb_htrans[1] ;
wire	\rv32.mem_ahb_hwdata[0] ;
wire	\rv32.mem_ahb_hwdata[10] ;
wire	\rv32.mem_ahb_hwdata[11] ;
wire	\rv32.mem_ahb_hwdata[12] ;
wire	\rv32.mem_ahb_hwdata[13] ;
wire	\rv32.mem_ahb_hwdata[14] ;
wire	\rv32.mem_ahb_hwdata[15] ;
wire	\rv32.mem_ahb_hwdata[16] ;
wire	\rv32.mem_ahb_hwdata[17] ;
wire	\rv32.mem_ahb_hwdata[18] ;
wire	\rv32.mem_ahb_hwdata[19] ;
wire	\rv32.mem_ahb_hwdata[1] ;
wire	\rv32.mem_ahb_hwdata[20] ;
wire	\rv32.mem_ahb_hwdata[21] ;
wire	\rv32.mem_ahb_hwdata[22] ;
wire	\rv32.mem_ahb_hwdata[23] ;
wire	\rv32.mem_ahb_hwdata[24] ;
wire	\rv32.mem_ahb_hwdata[25] ;
wire	\rv32.mem_ahb_hwdata[26] ;
wire	\rv32.mem_ahb_hwdata[27] ;
wire	\rv32.mem_ahb_hwdata[28] ;
wire	\rv32.mem_ahb_hwdata[29] ;
wire	\rv32.mem_ahb_hwdata[2] ;
wire	\rv32.mem_ahb_hwdata[30] ;
wire	\rv32.mem_ahb_hwdata[31] ;
wire	\rv32.mem_ahb_hwdata[3] ;
wire	\rv32.mem_ahb_hwdata[4] ;
wire	\rv32.mem_ahb_hwdata[5] ;
wire	\rv32.mem_ahb_hwdata[6] ;
wire	\rv32.mem_ahb_hwdata[7] ;
wire	\rv32.mem_ahb_hwdata[8] ;
wire	\rv32.mem_ahb_hwdata[9] ;
wire	\rv32.mem_ahb_hwrite ;
wire	\rv32.resetn_out ;
wire	\rv32.slave_ahb_hrdata[0] ;
wire	\rv32.slave_ahb_hrdata[10] ;
wire	\rv32.slave_ahb_hrdata[11] ;
wire	\rv32.slave_ahb_hrdata[12] ;
wire	\rv32.slave_ahb_hrdata[13] ;
wire	\rv32.slave_ahb_hrdata[14] ;
wire	\rv32.slave_ahb_hrdata[15] ;
wire	\rv32.slave_ahb_hrdata[16] ;
wire	\rv32.slave_ahb_hrdata[17] ;
wire	\rv32.slave_ahb_hrdata[18] ;
wire	\rv32.slave_ahb_hrdata[19] ;
wire	\rv32.slave_ahb_hrdata[1] ;
wire	\rv32.slave_ahb_hrdata[20] ;
wire	\rv32.slave_ahb_hrdata[21] ;
wire	\rv32.slave_ahb_hrdata[22] ;
wire	\rv32.slave_ahb_hrdata[23] ;
wire	\rv32.slave_ahb_hrdata[24] ;
wire	\rv32.slave_ahb_hrdata[25] ;
wire	\rv32.slave_ahb_hrdata[26] ;
wire	\rv32.slave_ahb_hrdata[27] ;
wire	\rv32.slave_ahb_hrdata[28] ;
wire	\rv32.slave_ahb_hrdata[29] ;
wire	\rv32.slave_ahb_hrdata[2] ;
wire	\rv32.slave_ahb_hrdata[30] ;
wire	\rv32.slave_ahb_hrdata[31] ;
wire	\rv32.slave_ahb_hrdata[3] ;
wire	\rv32.slave_ahb_hrdata[4] ;
wire	\rv32.slave_ahb_hrdata[5] ;
wire	\rv32.slave_ahb_hrdata[6] ;
wire	\rv32.slave_ahb_hrdata[7] ;
wire	\rv32.slave_ahb_hrdata[8] ;
wire	\rv32.slave_ahb_hrdata[9] ;
wire	\rv32.slave_ahb_hreadyout ;
wire	\rv32.slave_ahb_hresp ;
wire	\rv32.swj_JTAGIR[0] ;
wire	\rv32.swj_JTAGIR[1] ;
wire	\rv32.swj_JTAGIR[2] ;
wire	\rv32.swj_JTAGIR[3] ;
wire	\rv32.swj_JTAGNSW ;
wire	\rv32.swj_JTAGSTATE[0] ;
wire	\rv32.swj_JTAGSTATE[1] ;
wire	\rv32.swj_JTAGSTATE[2] ;
wire	\rv32.swj_JTAGSTATE[3] ;
wire	\rv32.sys_ctrl_clkSource[0] ;
wire	\rv32.sys_ctrl_clkSource[1] ;
wire	\rv32.sys_ctrl_hseBypass ;
wire	\rv32.sys_ctrl_hseEnable ;
wire	\rv32.sys_ctrl_pllEnable ;
wire	\rv32.sys_ctrl_sleep ;
wire	\rv32.sys_ctrl_standby ;
wire	\rv32.sys_ctrl_stop ;
//wire	\so_io1~output_o ;
wire	\so_io1~input_o ;
wire	\sys_resetn~clkctrl_outclk ;
wire	\sys_resetn~combout ;
wire	\~GND~combout ;
wire	\~VCC~combout ;
wire	hbi_272_0_9cb2c0024f9919c5_bp;
wire	hbi_272_1_9cb2c0024f9919c5_bp;
wire	[4:0] \pll_inst|auto_generated|clk ;
//wire	\pll_inst|auto_generated|clk [0];
wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
//wire	\pll_inst|auto_generated|clk [1];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
//wire	\pll_inst|auto_generated|clk [2];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
//wire	\pll_inst|auto_generated|clk [3];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
//wire	\pll_inst|auto_generated|clk [4];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
wire	\pll_inst|auto_generated|pll1~FBOUT ;

wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;
wire unknown;
assign unknown = 1'bx;

// Location: BBOX_X1_Y1_N0
alta_adc \macro_inst|apb_adc0_inst|adc_inst (
	.enb(!\macro_inst|cfg_reg_inst|adc_en~q ),
	.sclk(\macro_inst|apb_adc0_inst|sclk~q ),
	.insel({\~GND~combout , !\macro_inst|cfg_reg_inst|adc_chnl_sel [3], !\macro_inst|cfg_reg_inst|adc_chnl_sel [2], \macro_inst|cfg_reg_inst|adc_chnl_sel [1], !\macro_inst|cfg_reg_inst|adc_chnl_sel [0]}),
	.stop(\rv32.sys_ctrl_stop ),
	.db({\macro_inst|apb_adc0_inst|adc_inst.db[11] , \macro_inst|apb_adc0_inst|adc_inst.db[10] , \macro_inst|apb_adc0_inst|adc_inst.db[9] , \macro_inst|apb_adc0_inst|adc_inst.db[8] , \macro_inst|apb_adc0_inst|adc_inst.db[7] , \macro_inst|apb_adc0_inst|adc_inst.db[6] , \macro_inst|apb_adc0_inst|adc_inst.db[5] , \macro_inst|apb_adc0_inst|adc_inst.db[4] , \macro_inst|apb_adc0_inst|adc_inst.db[3] , \macro_inst|apb_adc0_inst|adc_inst.db[2] , \macro_inst|apb_adc0_inst|adc_inst.db[1] , \macro_inst|apb_adc0_inst|adc_inst.db[0] }),
	.eoc(\macro_inst|apb_adc0_inst|adc_inst.eoc ));

// Location: BBOX_X2_Y2_N0
alta_dac \macro_inst|apb_dac0_inst|dac_inst (
	.enb(\macro_inst|cfg_reg_inst|dac_en~_wirecell_combout ),
	.bufenb(\macro_inst|cfg_reg_inst|dac_en~_wirecell_combout ),
	.din({\macro_inst|apb_dac0_inst|Add2~59_combout , \macro_inst|apb_dac0_inst|Add2~58_combout , \macro_inst|apb_dac0_inst|Add2~57_combout , \macro_inst|apb_dac0_inst|Add2~56_combout , \macro_inst|apb_dac0_inst|Add2~55_combout , \macro_inst|apb_dac0_inst|Add2~54_combout , \macro_inst|apb_dac0_inst|Add2~53_combout , \macro_inst|apb_dac0_inst|Add2~52_combout , \macro_inst|apb_dac0_inst|Add2~51_combout , \macro_inst|apb_dac0_inst|Add2~50_combout }),
	.stop(\rv32.sys_ctrl_stop ));

// Location: BBOX_X3_Y3_N0
alta_rv32 rv32(
	.sys_clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.mem_ahb_hready(\rv32.mem_ahb_hready ),
	.mem_ahb_hreadyout(!\macro_inst|ahb2apb_inst|hreadyout~q ),
	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
	.mem_ahb_hresp(\~GND~combout ),
	.mem_ahb_hrdata(\macro_inst|ahb2apb_inst|prdata ),
	.slave_ahb_hsel(\~GND~combout ),
	.slave_ahb_hready(\~VCC~combout ),
	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
	.slave_ahb_htrans({\~GND~combout , \~GND~combout }),
	.slave_ahb_hsize({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hburst({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwrite(\~GND~combout ),
	.slave_ahb_haddr({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwdata({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
	.gpio0_io_in({gpio0_io_in[7], gpio0_io_in[6], gpio0_io_in[5], gpio0_io_in[4], gpio0_io_in[3], gpio0_io_in[2], gpio0_io_in[1], \SPI0_SI_IO0~input_o }),
	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
	.gpio1_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
	.sys_ctrl_pllReady(\PLL_LOCK~combout ),
	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
	.gpio2_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
	.gpio3_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
	.gpio4_io_in({gpio4_io_in[7], gpio4_io_in[6], gpio4_io_in[5], gpio4_io_in[4], gpio4_io_in[3], \GPIO4_2~input_o , \GPIO4_1~input_o , gpio4_io_in[0]}),
	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
	.gpio5_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
	.gpio6_io_in({gpio6_io_in[7], gpio6_io_in[6], gpio6_io_in[5], gpio6_io_in[4], \UART1_RX~input_o , gpio6_io_in[2], \UART0_UARTRXD~input_o , gpio6_io_in[0]}),
	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
	.gpio7_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
	.gpio8_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
	.gpio9_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
	.ext_resetn(\~VCC~combout ),
	.resetn_out(\rv32.resetn_out ),
	.dmactive(\rv32.dmactive ),
	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
	.ext_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACBREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACLBREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACLSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
	.local_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.test_mode({\~GND~combout , \~GND~combout }),
	.usb0_xcvr_clk(\~VCC~combout ),
	.usb0_id(\~VCC~combout ));

// Location: IOIBUF_X0_Y30_N1
// alta_io_ibuf \PLL_CLKIN~input (
alta_rio \PLL_CLKIN~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PLL_CLKIN~input_o ),
	.regout(),
	.padio(PLL_CLKIN));
defparam \PLL_CLKIN~input .CFG_KEEP = 2'b00;
// defparam \PLL_CLKIN~input .simulate_z_as = "z";

// Location: IOIBUF_X0_Y30_N2
// alta_io_ibuf \PIN_HSI~input (
alta_rio \PIN_HSI~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSI~input_o ),
	.regout(),
	.padio(PIN_HSI));
defparam \PIN_HSI~input .CFG_KEEP = 2'b00;
// defparam \PIN_HSI~input .simulate_z_as = "z";

// Location: IOOBUF_X43_Y0_N0
// alta_io_obuf \SPI0_CSN~output (
alta_rio \SPI0_CSN~output (
	.datain(\rv32.gpio4_io_out_data[6] ),
	.oe(\rv32.gpio4_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(SPI0_CSN));
defparam \SPI0_CSN~output .CFG_KEEP = 2'b00;
// defparam \SPI0_CSN~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N0
// alta_io_ibuf \GPIO4_1~input (
// Location: IOOBUF_X45_Y0_N0
// alta_io_obuf \GPIO4_1~output (
alta_rio \GPIO4_1~output (
	.datain(\rv32.gpio4_io_out_data[1] ),
	.oe(\rv32.gpio4_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO4_1~input_o ),
	.regout(),
	.padio(GPIO4_1));
defparam \GPIO4_1~output .CFG_KEEP = 2'b00;
// defparam \GPIO4_1~input .simulate_z_as = "z";
// defparam \GPIO4_1~output .open_drain_output = "false";

// Location: IOOBUF_X45_Y0_N1
// alta_io_obuf \SPI0_SCK~output (
alta_rio \SPI0_SCK~output (
	.datain(\rv32.gpio4_io_out_data[5] ),
	.oe(\rv32.gpio4_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(SPI0_SCK));
defparam \SPI0_SCK~output .CFG_KEEP = 2'b00;
// defparam \SPI0_SCK~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N2
// alta_io_ibuf \GPIO4_2~input (
// Location: IOOBUF_X45_Y0_N2
// alta_io_obuf \GPIO4_2~output (
alta_rio \GPIO4_2~output (
	.datain(\rv32.gpio4_io_out_data[2] ),
	.oe(\rv32.gpio4_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO4_2~input_o ),
	.regout(),
	.padio(GPIO4_2));
defparam \GPIO4_2~output .CFG_KEEP = 2'b00;
// defparam \GPIO4_2~input .simulate_z_as = "z";
// defparam \GPIO4_2~output .open_drain_output = "false";

// Location: IOIBUF_X47_Y0_N0
// alta_io_ibuf \UART0_UARTRXD~input (
alta_rio \UART0_UARTRXD~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART0_UARTRXD~input_o ),
	.regout(),
	.padio(UART0_UARTRXD));
defparam \UART0_UARTRXD~input .CFG_KEEP = 2'b00;
// defparam \UART0_UARTRXD~input .simulate_z_as = "z";

// Location: IOIBUF_X47_Y0_N1
// alta_io_ibuf \UART1_RX~input (
// Location: IOOBUF_X47_Y0_N1
// alta_io_obuf \UART1_RX~output (
alta_rio \UART1_RX~output (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART1_RX~input_o ),
	.regout(),
	.padio(UART1_RX));
defparam \UART1_RX~output .CFG_KEEP = 2'b00;
// defparam \UART1_RX~input .simulate_z_as = "z";
// defparam \UART1_RX~output .open_drain_output = "false";

// Location: IOOBUF_X51_Y0_N2
// alta_io_obuf \UART0_UARTTXD~output (
alta_rio \UART0_UARTTXD~output (
	.datain(\rv32.gpio7_io_out_data[6] ),
	.oe(\rv32.gpio7_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(UART0_UARTTXD));
defparam \UART0_UARTTXD~output .CFG_KEEP = 2'b00;
// defparam \UART0_UARTTXD~output .open_drain_output = "false";

// Location: IOIBUF_X51_Y0_N3
// alta_io_ibuf \UART1_TX~input (
// Location: IOOBUF_X51_Y0_N3
// alta_io_obuf \UART1_TX~output (
alta_rio \UART1_TX~output (
	.datain(\rv32.gpio8_io_out_data[0] ),
	.oe(\rv32.gpio8_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART1_TX~input_o ),
	.regout(),
	.padio(UART1_TX));
defparam \UART1_TX~output .CFG_KEEP = 2'b00;
// defparam \UART1_TX~input .simulate_z_as = "z";
// defparam \UART1_TX~output .open_drain_output = "false";

// Location: IOIBUF_X56_Y0_N3
// alta_io_ibuf \SPI0_SI_IO0~input (
// Location: IOOBUF_X56_Y0_N3
// alta_io_obuf \SPI0_SI_IO0~output (
alta_rio \SPI0_SI_IO0~output (
	.datain(\rv32.gpio0_io_out_data[0] ),
	.oe(\rv32.gpio0_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SPI0_SI_IO0~input_o ),
	.regout(),
	.padio(SPI0_SI_IO0));
defparam \SPI0_SI_IO0~output .CFG_KEEP = 2'b00;
// defparam \SPI0_SI_IO0~input .simulate_z_as = "z";
// defparam \SPI0_SI_IO0~output .open_drain_output = "false";

// Location: IOIBUF_X76_Y0_N0
// alta_io_ibuf \BAUD_RATE~input (
// Location: IOOBUF_X76_Y0_N0
// alta_io_obuf \BAUD_RATE~output (
alta_rio \BAUD_RATE~output (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\BAUD_RATE~input_o ),
	.regout(),
	.padio(BAUD_RATE));
defparam \BAUD_RATE~output .CFG_KEEP = 2'b00;
// defparam \BAUD_RATE~input .simulate_z_as = "z";
// defparam \BAUD_RATE~output .open_drain_output = "false";

// Location: IOIBUF_X80_Y0_N1
// alta_io_ibuf \TEST_SINGLE~input (
// Location: IOOBUF_X80_Y0_N1
// alta_io_obuf \TEST_SINGLE~output (
alta_rio \TEST_SINGLE~output (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\TEST_SINGLE~input_o ),
	.regout(),
	.padio(TEST_SINGLE));
defparam \TEST_SINGLE~output .CFG_KEEP = 2'b00;
// defparam \TEST_SINGLE~input .simulate_z_as = "z";
// defparam \TEST_SINGLE~output .open_drain_output = "false";

// Location: IOIBUF_X83_Y62_N0
// alta_io_ibuf \PIN_HSE~input (
alta_rio \PIN_HSE~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSE~input_o ),
	.regout(),
	.padio(PIN_HSE));
defparam \PIN_HSE~input .CFG_KEEP = 2'b00;
// defparam \PIN_HSE~input .simulate_z_as = "z";

// Location: IOIBUF_X94_Y21_N2
// alta_io_ibuf \so_io1~input (
// Location: IOOBUF_X94_Y21_N2
// alta_io_obuf \so_io1~output (
alta_rio \so_io1~output (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\so_io1~input_o ),
	.regout(),
	.padio(so_io1));
defparam \so_io1~output .CFG_KEEP = 2'b00;
// defparam \so_io1~input .simulate_z_as = "z";
// defparam \so_io1~output .open_drain_output = "false";

// Location: M9K_X55_Y3_N0
wire [17:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA ;
wire [17:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutB ;
alta_bram9k \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 (
	.DataInA({vcc,vcc,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,vcc,vcc,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }),
	.DataInB({vcc,vcc,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\macro_inst|trig_ctrl_inst|ram_wr_data_b [11],\macro_inst|trig_ctrl_inst|ram_wr_data_b [10],\macro_inst|trig_ctrl_inst|ram_wr_data_b [9],vcc,vcc,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\macro_inst|trig_ctrl_inst|ram_wr_data_b [11],\macro_inst|trig_ctrl_inst|ram_wr_data_b [10],\macro_inst|trig_ctrl_inst|ram_wr_data_b [9]}),
	.AddressA({\macro_inst|ahb2apb_inst|paddr [10],\macro_inst|ahb2apb_inst|paddr [9],\macro_inst|ahb2apb_inst|paddr [8],\macro_inst|ahb2apb_inst|paddr [7],\macro_inst|ahb2apb_inst|paddr [6],\macro_inst|ahb2apb_inst|paddr [5],\macro_inst|ahb2apb_inst|paddr [4],\macro_inst|ahb2apb_inst|paddr [3],\macro_inst|ahb2apb_inst|paddr [2],\macro_inst|ahb2apb_inst|paddr [1],vcc,vcc,vcc}),
	.AddressB({\macro_inst|trig_ctrl_inst|ram_wr_addr [9],\macro_inst|trig_ctrl_inst|ram_wr_addr [8],\macro_inst|trig_ctrl_inst|ram_wr_addr [7],\macro_inst|trig_ctrl_inst|ram_wr_addr [6],\macro_inst|trig_ctrl_inst|ram_wr_addr [5],\macro_inst|trig_ctrl_inst|ram_wr_addr [4],\macro_inst|trig_ctrl_inst|ram_wr_addr [3],\macro_inst|trig_ctrl_inst|ram_wr_addr [2],\macro_inst|trig_ctrl_inst|ram_wr_addr [1],\macro_inst|trig_ctrl_inst|ram_wr_addr [0],vcc,vcc,vcc}),
	.ByteEnA({vcc,vcc}),
	.ByteEnB({vcc,vcc}),
	.DataOutA(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA ),
	.DataOutB(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutB ),
	.Clk0(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn0(),
	.AsyncReset0(gnd),
	.Clk1(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn1(),
	.AsyncReset1(gnd),
	.AddressStallA(gnd),
	.WeA(\macro_inst|u_apb2ram|ram_wren~0_combout ),
	.ReA(\macro_inst|u_apb2ram|ram_rden~0_combout ),
	.AddressStallB(gnd),
	.WeB(\macro_inst|trig_ctrl_inst|ram_wren_b~q ),
	.ReB(gnd));
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .CLKMODE         = 2'b01;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .INIT_VAL        = 9216'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PACKEDMODE      = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_CLKIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_CLKOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_OUTREG    = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_RSTIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_RSTOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_WIDTH     = 5'b01000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTA_WRITETHRU = 1'b1;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_CLKIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_CLKOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_OUTREG    = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_RSTIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_RSTOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_WIDTH     = 5'b01000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .PORTB_WRITETHRU = 1'b1;
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [0] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [9];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [1] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [10];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [2] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [11];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [3] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [12];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [4] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [13];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [5] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [14];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [6] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [15];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [7] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [16];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [8] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9__DataOutA [7];
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .data_interleave_offset_in_bits = 1;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .data_interleave_width_in_bits = 1;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .logical_ram_name = "analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ALTSYNCRAM";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .operation_mode = "bidir_dual_port";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_address_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_address_width = 10;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_byte_enable_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_data_out_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_data_out_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_data_width = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_first_address = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_first_bit_number = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_last_address = 1023;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_logical_ram_depth = 1024;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_logical_ram_width = 16;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_a_read_during_write_mode = "new_data_with_nbe_read";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_address_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_address_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_address_width = 10;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_data_in_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_data_out_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_data_out_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_data_width = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_first_address = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_first_bit_number = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_last_address = 1023;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_logical_ram_depth = 1024;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_logical_ram_width = 16;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_read_during_write_mode = "new_data_with_nbe_read";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_read_enable_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .port_b_write_enable_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a9 .ram_block_type = "M9K";

// Location: M9K_X55_Y4_N0
wire [17:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA ;
wire [17:0] \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutB ;
alta_bram9k \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 (
	.DataInA({\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout ,\~GND~combout }),
	.DataInB({\macro_inst|trig_ctrl_inst|ram_wr_data_b [8],\macro_inst|trig_ctrl_inst|ram_wr_data_b [7],\macro_inst|trig_ctrl_inst|ram_wr_data_b [6],\macro_inst|trig_ctrl_inst|ram_wr_data_b [5],\macro_inst|trig_ctrl_inst|ram_wr_data_b [4],\macro_inst|trig_ctrl_inst|ram_wr_data_b [3],\macro_inst|trig_ctrl_inst|ram_wr_data_b [2],\macro_inst|trig_ctrl_inst|ram_wr_data_b [1],\macro_inst|trig_ctrl_inst|ram_wr_data_b [0],\macro_inst|trig_ctrl_inst|ram_wr_data_b [8],\macro_inst|trig_ctrl_inst|ram_wr_data_b [7],\macro_inst|trig_ctrl_inst|ram_wr_data_b [6],\macro_inst|trig_ctrl_inst|ram_wr_data_b [5],\macro_inst|trig_ctrl_inst|ram_wr_data_b [4],\macro_inst|trig_ctrl_inst|ram_wr_data_b [3],\macro_inst|trig_ctrl_inst|ram_wr_data_b [2],\macro_inst|trig_ctrl_inst|ram_wr_data_b [1],\macro_inst|trig_ctrl_inst|ram_wr_data_b [0]}),
	.AddressA({\macro_inst|ahb2apb_inst|paddr [10],\macro_inst|ahb2apb_inst|paddr [9],\macro_inst|ahb2apb_inst|paddr [8],\macro_inst|ahb2apb_inst|paddr [7],\macro_inst|ahb2apb_inst|paddr [6],\macro_inst|ahb2apb_inst|paddr [5],\macro_inst|ahb2apb_inst|paddr [4],\macro_inst|ahb2apb_inst|paddr [3],\macro_inst|ahb2apb_inst|paddr [2],\macro_inst|ahb2apb_inst|paddr [1],vcc,vcc,vcc}),
	.AddressB({\macro_inst|trig_ctrl_inst|ram_wr_addr [9],\macro_inst|trig_ctrl_inst|ram_wr_addr [8],\macro_inst|trig_ctrl_inst|ram_wr_addr [7],\macro_inst|trig_ctrl_inst|ram_wr_addr [6],\macro_inst|trig_ctrl_inst|ram_wr_addr [5],\macro_inst|trig_ctrl_inst|ram_wr_addr [4],\macro_inst|trig_ctrl_inst|ram_wr_addr [3],\macro_inst|trig_ctrl_inst|ram_wr_addr [2],\macro_inst|trig_ctrl_inst|ram_wr_addr [1],\macro_inst|trig_ctrl_inst|ram_wr_addr [0],vcc,vcc,vcc}),
	.ByteEnA({vcc,vcc}),
	.ByteEnB({vcc,vcc}),
	.DataOutA(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA ),
	.DataOutB(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutB ),
	.Clk0(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn0(),
	.AsyncReset0(gnd),
	.Clk1(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.ClkEn1(),
	.AsyncReset1(gnd),
	.AddressStallA(gnd),
	.WeA(\macro_inst|u_apb2ram|ram_wren~0_combout ),
	.ReA(\macro_inst|u_apb2ram|ram_rden~0_combout ),
	.AddressStallB(gnd),
	.WeB(\macro_inst|trig_ctrl_inst|ram_wren_b~q ),
	.ReB(gnd));
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .CLKMODE         = 2'b01;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .INIT_VAL        = 9216'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PACKEDMODE      = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_CLKIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_CLKOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_OUTREG    = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_RSTIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_RSTOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_WIDTH     = 5'b01000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTA_WRITETHRU = 1'b1;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_CLKIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_CLKOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_OUTREG    = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_RSTIN_EN  = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_RSTOUT_EN = 1'b0;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_WIDTH     = 5'b01000;
defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .PORTB_WRITETHRU = 1'b1;
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [0] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [9];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [1] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [10];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [2] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [11];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [3] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [12];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [4] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [13];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [5] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [14];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [6] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [15];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [7] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [16];
assign \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [8] = \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0__DataOutA [7];
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .data_interleave_offset_in_bits = 1;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .data_interleave_width_in_bits = 1;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .logical_ram_name = "analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ALTSYNCRAM";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .operation_mode = "bidir_dual_port";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_address_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_address_width = 10;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_byte_enable_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_data_out_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_data_out_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_data_width = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_first_address = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_first_bit_number = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_last_address = 1023;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_logical_ram_depth = 1024;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_logical_ram_width = 16;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_a_read_during_write_mode = "new_data_with_nbe_read";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_address_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_address_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_address_width = 10;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_data_in_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_data_out_clear = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_data_out_clock = "none";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_data_width = 9;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_first_address = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_first_bit_number = 0;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_last_address = 1023;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_logical_ram_depth = 1024;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_logical_ram_width = 16;
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_read_during_write_mode = "new_data_with_nbe_read";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_read_enable_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .port_b_write_enable_clock = "clock0";
//defparam \macro_inst|u_dual_port_ram|auto_generated|ram_block1a0 .ram_block_type = "M9K";

// Location: PLL_1
alta_pllve \pll_inst|auto_generated|pll1 (
	.clkin(\PLL_CLKIN~input_o ),
	.clkfb(\pll_inst|auto_generated|pll1~FBOUT ),
	.pfden(vcc),
	.resetn(!\PLL_ENABLE~combout ),
	.clkout0(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkout1(\pll_inst|auto_generated|pll1_CLK_bus [1]),
	.clkout2(\pll_inst|auto_generated|pll1_CLK_bus [2]),
	.clkout3(\pll_inst|auto_generated|pll1_CLK_bus [3]),
	.clkout4(\pll_inst|auto_generated|pll1_CLK_bus [4]),
	.phasecounterselect({gnd, gnd, gnd}),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.scandata(gnd),
	.configupdate(gnd),
	.scandataout(),
	.scandone(),
	.phasedone(),
	.clkfbout(\pll_inst|auto_generated|pll1~FBOUT ),
	.lock(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ));
defparam \pll_inst|auto_generated|pll1 .CLKDIV0_EN      = 1'h1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV1_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV2_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV3_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV4_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_BYPASS    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_DEL       = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKFB_HIGH      = 8'h19;
defparam \pll_inst|auto_generated|pll1 .CLKFB_LOW       = 8'h19;
defparam \pll_inst|auto_generated|pll1 .CLKFB_PHASE     = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_TRIM      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_BYPASS    = 1'h1;
defparam \pll_inst|auto_generated|pll1 .CLKIN_HIGH      = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKIN_LOW       = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKIN_TRIM      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_HIGH    = 8'h01;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_LOW     = 8'h01;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .FBDELAY_VAL     = 3'h4;
defparam \pll_inst|auto_generated|pll1 .FEEDBACK_MODE   = 3'h4;
defparam \pll_inst|auto_generated|pll1 .PLLOUTN_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .PLLOUTP_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .VCO_POST_DIV    = 1'h1;
//defparam \pll_inst|auto_generated|pll1 .auto_settings = "false";
//defparam \pll_inst|auto_generated|pll1 .bandwidth_type = "medium";
//defparam \pll_inst|auto_generated|pll1 .c0_high = 2;
//defparam \pll_inst|auto_generated|pll1 .c0_initial = 1;
//defparam \pll_inst|auto_generated|pll1 .c0_low = 1;
//defparam \pll_inst|auto_generated|pll1 .c0_mode = "odd";
//defparam \pll_inst|auto_generated|pll1 .c0_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c1_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c2_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c2_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c3_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c3_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c4_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c4_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .charge_pump_current_bits = 1;
//defparam \pll_inst|auto_generated|pll1 .clk0_counter = "c0";
//defparam \pll_inst|auto_generated|pll1 .clk0_divide_by = 1;
//defparam \pll_inst|auto_generated|pll1 .clk0_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk0_multiply_by = 13;
//defparam \pll_inst|auto_generated|pll1 .clk0_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk1_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk1_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk2_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk2_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk3_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk3_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk3_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk3_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk3_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk4_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk4_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .compensate_clock = "clock0";
//defparam \pll_inst|auto_generated|pll1 .inclk0_input_frequency = 125000;
//defparam \pll_inst|auto_generated|pll1 .inclk1_input_frequency = 0;
//defparam \pll_inst|auto_generated|pll1 .loop_filter_c_bits = 0;
//defparam \pll_inst|auto_generated|pll1 .loop_filter_r_bits = 20;
//defparam \pll_inst|auto_generated|pll1 .m = 39;
//defparam \pll_inst|auto_generated|pll1 .m_initial = 1;
//defparam \pll_inst|auto_generated|pll1 .m_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .n = 1;
//defparam \pll_inst|auto_generated|pll1 .operation_mode = "normal";
//defparam \pll_inst|auto_generated|pll1 .pfd_max = 200000;
//defparam \pll_inst|auto_generated|pll1 .pfd_min = 3076;
//defparam \pll_inst|auto_generated|pll1 .pll_compensation_delay = 7538;
//defparam \pll_inst|auto_generated|pll1 .self_reset_on_loss_lock = "off";
//defparam \pll_inst|auto_generated|pll1 .simulation_type = "timing";
//defparam \pll_inst|auto_generated|pll1 .switch_over_type = "auto";
//defparam \pll_inst|auto_generated|pll1 .vco_center = 1538;
//defparam \pll_inst|auto_generated|pll1 .vco_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .vco_frequency_control = "auto";
//defparam \pll_inst|auto_generated|pll1 .vco_max = 3333;
//defparam \pll_inst|auto_generated|pll1 .vco_min = 1538;
//defparam \pll_inst|auto_generated|pll1 .vco_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .vco_phase_shift_step = 400;
//defparam \pll_inst|auto_generated|pll1 .vco_post_scale = 2;

// Location: CLKCTRL_G16
alta_io_gclk \sys_resetn~clkctrl (
	.inclk (\sys_resetn~combout ),
	.outclk(\sys_resetn~clkctrl_outclk ));
//defparam \sys_resetn~clkctrl .clock_type = "global clock";
//defparam \sys_resetn~clkctrl .ena_register_mode = "none";

// Location: CLKCTRL_G17
alta_io_gclk \PLL_ENABLE~clkctrl (
	.inclk (\PLL_ENABLE~combout ),
	.outclk(\PLL_ENABLE~clkctrl_outclk ));
//defparam \PLL_ENABLE~clkctrl .clock_type = "global clock";
//defparam \PLL_ENABLE~clkctrl .ena_register_mode = "none";

// Location: CLKCTRL_G3
alta_gclksw \gclksw_inst|gclk_switch__alta_gclksw (
	.resetn(vcc),
	.clkin0(\PIN_HSI~input_o ),
	.clkin1(1'bx),
	.clkin2(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkin3(1'bx),
	.select({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.clkout(\gclksw_inst|gclk_switch__alta_gclksw__clkout ));

// Location: CLKCTRL_G3
alta_io_gclk \gclksw_inst|gclk_switch (
	.inclk (\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
//defparam \gclksw_inst|gclk_switch .clock_type = "global clock";
//defparam \gclksw_inst|gclk_switch .ena_register_mode = "none";

// Location: LCCOMB_X45_Y4_N0
// alta_lcell_comb \gpio4_io_in[0] (
alta_slice \gpio4_io_in[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[0]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[0] .mask = 16'h0000;
defparam \gpio4_io_in[0] .mode = "logic";
defparam \gpio4_io_in[0] .modeMux = 1'b0;
defparam \gpio4_io_in[0] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[0] .ShiftMux = 1'b0;
defparam \gpio4_io_in[0] .BypassEn = 1'b0;
defparam \gpio4_io_in[0] .CarryEnb = 1'b1;
defparam \gpio4_io_in[0] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[0] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N10
// alta_lcell_comb \gpio4_io_in[5] (
alta_slice \gpio4_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[5] .mask = 16'h0000;
defparam \gpio4_io_in[5] .mode = "logic";
defparam \gpio4_io_in[5] .modeMux = 1'b0;
defparam \gpio4_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[5] .ShiftMux = 1'b0;
defparam \gpio4_io_in[5] .BypassEn = 1'b0;
defparam \gpio4_io_in[5] .CarryEnb = 1'b1;
defparam \gpio4_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N12
// alta_lcell_comb \gpio4_io_in[6] (
alta_slice \gpio4_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[6] .mask = 16'h0000;
defparam \gpio4_io_in[6] .mode = "logic";
defparam \gpio4_io_in[6] .modeMux = 1'b0;
defparam \gpio4_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[6] .ShiftMux = 1'b0;
defparam \gpio4_io_in[6] .BypassEn = 1'b0;
defparam \gpio4_io_in[6] .CarryEnb = 1'b1;
defparam \gpio4_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N14
// alta_lcell_comb \gpio4_io_in[7] (
alta_slice \gpio4_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[7] .mask = 16'h0000;
defparam \gpio4_io_in[7] .mode = "logic";
defparam \gpio4_io_in[7] .modeMux = 1'b0;
defparam \gpio4_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[7] .ShiftMux = 1'b0;
defparam \gpio4_io_in[7] .BypassEn = 1'b0;
defparam \gpio4_io_in[7] .CarryEnb = 1'b1;
defparam \gpio4_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N6
// alta_lcell_comb \gpio4_io_in[3] (
alta_slice \gpio4_io_in[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[3]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[3] .mask = 16'h0000;
defparam \gpio4_io_in[3] .mode = "logic";
defparam \gpio4_io_in[3] .modeMux = 1'b0;
defparam \gpio4_io_in[3] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[3] .ShiftMux = 1'b0;
defparam \gpio4_io_in[3] .BypassEn = 1'b0;
defparam \gpio4_io_in[3] .CarryEnb = 1'b1;
defparam \gpio4_io_in[3] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[3] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N8
// alta_lcell_comb \gpio4_io_in[4] (
alta_slice \gpio4_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[4] .mask = 16'h0000;
defparam \gpio4_io_in[4] .mode = "logic";
defparam \gpio4_io_in[4] .modeMux = 1'b0;
defparam \gpio4_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[4] .ShiftMux = 1'b0;
defparam \gpio4_io_in[4] .BypassEn = 1'b0;
defparam \gpio4_io_in[4] .CarryEnb = 1'b1;
defparam \gpio4_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N0
// alta_lcell_ff \pll_inst|auto_generated|pll_lock_sync (
// Location: LCCOMB_X46_Y1_N0
// alta_lcell_comb \pll_inst|auto_generated|pll_lock_sync~feeder (
alta_slice \pll_inst|auto_generated|pll_lock_sync (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\pll_inst|auto_generated|pll_lock_sync~q ),
	.Clk(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.Cout(),
	.Q(\pll_inst|auto_generated|pll_lock_sync~q ));
defparam \pll_inst|auto_generated|pll_lock_sync .mask = 16'hFFFF;
defparam \pll_inst|auto_generated|pll_lock_sync .mode = "logic";
defparam \pll_inst|auto_generated|pll_lock_sync .modeMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .FeedbackMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .ShiftMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .BypassEn = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .CarryEnb = 1'b1;
defparam \pll_inst|auto_generated|pll_lock_sync .AsyncResetMux = 2'b10;
defparam \pll_inst|auto_generated|pll_lock_sync .SyncResetMux = 2'bxx;
defparam \pll_inst|auto_generated|pll_lock_sync .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N10
// alta_lcell_comb PLL_ENABLE(
alta_slice PLL_ENABLE(
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.sys_ctrl_pllEnable ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_ENABLE~combout ),
	.Cout(),
	.Q());
defparam PLL_ENABLE.mask = 16'h00FF;
defparam PLL_ENABLE.mode = "logic";
defparam PLL_ENABLE.modeMux = 1'b0;
defparam PLL_ENABLE.FeedbackMux = 1'b0;
defparam PLL_ENABLE.ShiftMux = 1'b0;
defparam PLL_ENABLE.BypassEn = 1'b0;
defparam PLL_ENABLE.CarryEnb = 1'b1;
defparam PLL_ENABLE.AsyncResetMux = 2'bxx;
defparam PLL_ENABLE.SyncResetMux = 2'bxx;
defparam PLL_ENABLE.SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N20
// alta_lcell_comb PLL_LOCK(
alta_slice PLL_LOCK(
	.A(vcc),
	.B(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ),
	.C(vcc),
	.D(\pll_inst|auto_generated|pll_lock_sync~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_LOCK~combout ),
	.Cout(),
	.Q());
defparam PLL_LOCK.mask = 16'hCC00;
defparam PLL_LOCK.mode = "logic";
defparam PLL_LOCK.modeMux = 1'b0;
defparam PLL_LOCK.FeedbackMux = 1'b0;
defparam PLL_LOCK.ShiftMux = 1'b0;
defparam PLL_LOCK.BypassEn = 1'b0;
defparam PLL_LOCK.CarryEnb = 1'b1;
defparam PLL_LOCK.AsyncResetMux = 2'bxx;
defparam PLL_LOCK.SyncResetMux = 2'bxx;
defparam PLL_LOCK.SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X46_Y1_N0
alta_clkenctrl clken_ctrl_X46_Y1_N0(.ClkIn(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_13_a8f89aa4d95b80e7_bp_X46_Y1_SIG_VCC ));
defparam clken_ctrl_X46_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X46_Y1_N0
alta_asyncctrl asyncreset_ctrl_X46_Y1_N0(.Din(\PLL_ENABLE~clkctrl_outclk ), .Dout(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X46_Y1_SIG ));
defparam asyncreset_ctrl_X46_Y1_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X46_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mask = 16'h660A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mask = 16'h660C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mask = 16'h660C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mask = 16'h660C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mask = 16'h660A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mask = 16'h3C44;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mask = 16'h1CD0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mask = 16'h1CD0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mask = 16'hCC0C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .mask = 16'h556A;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mask = 16'h3D40;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mask = 16'h3FC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mask = 16'h3C44;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .mask = 16'h5A5F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mask = 16'h3CF0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mask = 16'h34D0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mask = 16'h3CF0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~200 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~200 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~200_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .mask = 16'h3264;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~200 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~193 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~193 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~193_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .mask = 16'h4B4A;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~193 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~199 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~199 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~199_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .mask = 16'hE0F8;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~199 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~196 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~196 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~196_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .mask = 16'h318C;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~196 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~207 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~207 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~206_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~196_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~192_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~207_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .mask = 16'hD8AA;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~207 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~197 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~197 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~195_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~196_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~192_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~197_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .mask = 16'h27AA;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~197 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~205 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~205 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~205_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .mask = 16'h96B4;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~205 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~206 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~206 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~193_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~205_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~206_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .mask = 16'hCCB8;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~206 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~203 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~203 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~202_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~201_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~203_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .mask = 16'hF0F2;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~203 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mask = 16'h5FA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~194 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~194 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~194_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .mask = 16'h694A;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~194 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~202 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~202 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~202_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .mask = 16'h6DB6;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~202 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~201 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~201 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~200_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~199_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~201_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .mask = 16'hFC44;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~201 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~195 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~195 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~193_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~194_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~195_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .mask = 16'hD3D0;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~195 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~192 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~192 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~192_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .mask = 16'h5A5A;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~192 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N0
// alta_lcell_comb \gpio6_io_in[0] (
alta_slice \gpio6_io_in[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[0]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[0] .mask = 16'h0000;
defparam \gpio6_io_in[0] .mode = "logic";
defparam \gpio6_io_in[0] .modeMux = 1'b0;
defparam \gpio6_io_in[0] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[0] .ShiftMux = 1'b0;
defparam \gpio6_io_in[0] .BypassEn = 1'b0;
defparam \gpio6_io_in[0] .CarryEnb = 1'b1;
defparam \gpio6_io_in[0] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[0] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N10
// alta_lcell_comb \gpio6_io_in[5] (
alta_slice \gpio6_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[5] .mask = 16'h0000;
defparam \gpio6_io_in[5] .mode = "logic";
defparam \gpio6_io_in[5] .modeMux = 1'b0;
defparam \gpio6_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[5] .ShiftMux = 1'b0;
defparam \gpio6_io_in[5] .BypassEn = 1'b0;
defparam \gpio6_io_in[5] .CarryEnb = 1'b1;
defparam \gpio6_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N12
// alta_lcell_comb \gpio6_io_in[6] (
alta_slice \gpio6_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[6] .mask = 16'h0000;
defparam \gpio6_io_in[6] .mode = "logic";
defparam \gpio6_io_in[6] .modeMux = 1'b0;
defparam \gpio6_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[6] .ShiftMux = 1'b0;
defparam \gpio6_io_in[6] .BypassEn = 1'b0;
defparam \gpio6_io_in[6] .CarryEnb = 1'b1;
defparam \gpio6_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N14
// alta_lcell_comb \gpio6_io_in[7] (
alta_slice \gpio6_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[7] .mask = 16'h0000;
defparam \gpio6_io_in[7] .mode = "logic";
defparam \gpio6_io_in[7] .modeMux = 1'b0;
defparam \gpio6_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[7] .ShiftMux = 1'b0;
defparam \gpio6_io_in[7] .BypassEn = 1'b0;
defparam \gpio6_io_in[7] .CarryEnb = 1'b1;
defparam \gpio6_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N4
// alta_lcell_comb \gpio6_io_in[2] (
alta_slice \gpio6_io_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[2]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[2] .mask = 16'h0000;
defparam \gpio6_io_in[2] .mode = "logic";
defparam \gpio6_io_in[2] .modeMux = 1'b0;
defparam \gpio6_io_in[2] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[2] .ShiftMux = 1'b0;
defparam \gpio6_io_in[2] .BypassEn = 1'b0;
defparam \gpio6_io_in[2] .CarryEnb = 1'b1;
defparam \gpio6_io_in[2] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[2] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N8
// alta_lcell_comb \gpio6_io_in[4] (
alta_slice \gpio6_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[4] .mask = 16'h0000;
defparam \gpio6_io_in[4] .mode = "logic";
defparam \gpio6_io_in[4] .modeMux = 1'b0;
defparam \gpio6_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[4] .ShiftMux = 1'b0;
defparam \gpio6_io_in[4] .BypassEn = 1'b0;
defparam \gpio6_io_in[4] .CarryEnb = 1'b1;
defparam \gpio6_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mask = 16'h3CCC;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mask = 16'hECA0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
	.A(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mask = 16'h1CC4;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mask = 16'h1CC4;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [8]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .mask = 16'h1E3C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .mask = 16'hFFA0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mask = 16'h3CCC;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [8]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .mask = 16'hE0C0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .mask = 16'h336C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mask = 16'h366C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mask = 16'h468A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .mask = 16'hC33C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mask = 16'hECA0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] (
	.A(\macro_inst|apb_dac0_inst|phase_r [9]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .mask = 16'hAA00;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mask = 16'hC0C0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .mask = 16'hCC00;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mask = 16'h1AB0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .mask = 16'h3C3F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mask = 16'h5A22;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mask = 16'h5A22;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [9]),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mask = 16'h5A22;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~133 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~133 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~133_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .mask = 16'h6448;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~133 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~129 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~129 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~129_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .mask = 16'h2834;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~129 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~321 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~321 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~320_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~319_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~321_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .mask = 16'hFC11;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~321 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~315 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~315 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~313_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~314_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~315_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .mask = 16'h8A9B;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~315 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~324 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~324 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~317_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~323_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~324_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .mask = 16'hE5E0;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~324 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~314 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~314 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~314_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .mask = 16'h649E;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~314 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~323 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~323 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~321_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~318_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~322_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~323_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .mask = 16'hEA62;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~323 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~317 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~317 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~316_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~312_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~315_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~317_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .mask = 16'h53F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~317 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~320 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~320 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~320_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .mask = 16'h7248;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~320 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~312 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~312 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~312_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .mask = 16'hF3FE;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~312 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~319 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~319 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~319_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .mask = 16'hECF2;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~319 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~322 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~322 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~322_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .mask = 16'h3FD6;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~322 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~134 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~134 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~129_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~133_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~132_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~134_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .mask = 16'h35F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~134 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~318 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~318 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~318_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .mask = 16'h0F14;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~318 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~316 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~316 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~316_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .mask = 16'hC7C6;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~316 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~313 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~313 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~313_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .mask = 16'h9392;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~313 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .mask = 16'h5A5F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .mask = 16'hA55A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .mask = 16'hCC00;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .mask = 16'hAA00;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mask = 16'hAA00;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .mask = 16'h0088;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .mask = 16'h005F;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mask = 16'h66AA;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mask = 16'hECA0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mask = 16'h286C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mask = 16'h286C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mask = 16'h268C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [9]),
	.D(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mask = 16'h1E78;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mask = 16'h660C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mask = 16'hECA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mask = 16'h3C50;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mask = 16'hC0C0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mask = 16'hECA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mask = 16'h660A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mask = 16'hEAC0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mask = 16'h606A;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|cs2a[4]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mask = 16'hF888;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .mask = 16'h3C3F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mask = 16'h660C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~9_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mask = 16'hAA00;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mask = 16'h1CD0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mask = 16'h286C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mask = 16'h3C50;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mask = 16'h3C50;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .mask = 16'h3C3F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~33 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~33 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~35 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~35 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .mask = 16'h5AA5;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mask = 16'h52A2;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mask = 16'h606A;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mask = 16'h52A2;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mask = 16'h1AB0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mask = 16'h3CCC;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mask = 16'h1CD0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .mask = 16'h0088;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .mask = 16'h003F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_1~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mask = 16'h3C44;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mask = 16'h366C;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mask = 16'h366C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mask = 16'h5A22;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mask = 16'h34D0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~132 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~132 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~130_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~131_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~132_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .mask = 16'hCC8B;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~132 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mask = 16'hC4C4;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mask = 16'h34C4;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .mask = 16'h33CC;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mask = 16'h606C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mask = 16'h2878;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mask = 16'h1AB0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[9]~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add21_result[9]~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[10]~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[11]~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[12]~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[13]~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .mask = 16'h5A5F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|add17_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~75 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~75 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~75_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .mask = 16'hB06C;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~75 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~344 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~344 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~343_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~76_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~344_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .mask = 16'h8D4E;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~344 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~16 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~16 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~13_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~15_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .mask = 16'h2CEC;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .mask = 16'hFFA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~76 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~76 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~76_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .mask = 16'h2232;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~76 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mask = 16'h566A;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~14 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~14 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .mask = 16'h3F7C;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~343 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~343 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~75_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~76_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~343_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .mask = 16'hD4B1;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~343 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mask = 16'h5A22;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~15 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~15 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~6_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .mask = 16'hCBC8;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~13 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~13 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .mask = 16'hF005;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mask = 16'h566A;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~26 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~26 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~24_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~25_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~26_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .mask = 16'h1DB4;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~186 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~186 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~186_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .mask = 16'hD5AA;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~186 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~24 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~24 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~24_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .mask = 16'h7F80;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~29 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~29 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~23_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~28_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~29_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .mask = 16'hCC74;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~29 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~27 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~27 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~24_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~25_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~27_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .mask = 16'hF242;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~27 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~31 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~31 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~30_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~29_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~20_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~31_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .mask = 16'h47CC;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~31 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~36 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~36 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~23_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~35_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~36_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .mask = 16'hCCB8;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~37 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~37 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~30_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~36_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~20_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~37_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .mask = 16'hB8CC;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~37 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~187 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~187 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~187_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .mask = 16'hBB44;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~187 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~25 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~25 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~25_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .mask = 16'h0ECE;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~25 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~28 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~28 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~26_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~27_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~28_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .mask = 16'hFC0C;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~190 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~190 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~190_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .mask = 16'hCFD2;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~190 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~189 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~189 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~187_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~188_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~189_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .mask = 16'hCC74;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~189 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~191 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~191 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~190_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~189_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~186_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~191_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .mask = 16'hDAD0;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~191 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~30 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~30 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~6_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~30_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .mask = 16'hFEFE;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~188 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~188 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~188_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .mask = 16'h6466;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~188 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~293 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~293 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~293_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .mask = 16'hD342;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~293 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~310 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~310 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~310_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .mask = 16'hB24C;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~310 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N12
// alta_lcell_comb \~VCC (
alta_slice \~VCC (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\~VCC~combout ),
	.Cout(),
	.Q());
defparam \~VCC .mask = 16'hFFFF;
defparam \~VCC .mode = "logic";
defparam \~VCC .modeMux = 1'b0;
defparam \~VCC .FeedbackMux = 1'b0;
defparam \~VCC .ShiftMux = 1'b0;
defparam \~VCC .BypassEn = 1'b0;
defparam \~VCC .CarryEnb = 1'b1;
defparam \~VCC .AsyncResetMux = 2'bxx;
defparam \~VCC .SyncResetMux = 2'bxx;
defparam \~VCC .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~311 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~311 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~309_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~306_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~310_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~311_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .mask = 16'hCE46;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~311 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~294 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~294 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~294_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .mask = 16'h4202;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~294 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~298 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~298 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~293_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~297_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~296_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~298_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .mask = 16'hF588;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~298 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~130 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~130 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~130_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .mask = 16'h90D0;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~130 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~309 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~309 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~308_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~307_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~309_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .mask = 16'hC1CD;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~309 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~297 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~297 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~297_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .mask = 16'hFAF8;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~297 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~307 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~307 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~307_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .mask = 16'h2A28;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~307 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~308 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~308 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~308_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .mask = 16'h0848;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~308 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~296 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~296 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~294_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~295_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~296_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .mask = 16'hA2A7;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~296 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~306 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~306 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~306_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .mask = 16'h5704;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~306 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N4
// alta_lcell_comb sys_resetn(
alta_slice sys_resetn(
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.resetn_out ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\sys_resetn~combout ),
	.Cout(),
	.Q());
defparam sys_resetn.mask = 16'h00FF;
defparam sys_resetn.mode = "logic";
defparam sys_resetn.modeMux = 1'b0;
defparam sys_resetn.FeedbackMux = 1'b0;
defparam sys_resetn.ShiftMux = 1'b0;
defparam sys_resetn.BypassEn = 1'b0;
defparam sys_resetn.CarryEnb = 1'b1;
defparam sys_resetn.AsyncResetMux = 2'bxx;
defparam sys_resetn.SyncResetMux = 2'bxx;
defparam sys_resetn.SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~295 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~295 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~295_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .mask = 16'hA350;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~295 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~131 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~131 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~131_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .mask = 16'h15D6;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~131 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~161 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~161 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~161_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .mask = 16'h3510;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~161 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~174 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~174 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~174_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .mask = 16'h0C26;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~174 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~276 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~276 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~276_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .mask = 16'h841C;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~276 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~274 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~274 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~274_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .mask = 16'h02B2;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~274 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~177 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~177 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~175_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~172_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~176_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~177_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .mask = 16'h1ABA;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~177 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~173 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~173 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~173_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .mask = 16'h0532;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~173 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~277 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~277 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~275_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~276_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~277_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .mask = 16'hC8D9;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~277 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~278 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~278 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~278_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .mask = 16'h4A70;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~278 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~160 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~160 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~160_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .mask = 16'h1794;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~160 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~176 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~176 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~176_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .mask = 16'h5C4C;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~176 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~162 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~162 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~160_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~161_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~162_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .mask = 16'hF0A3;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~162 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~279 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~279 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~278_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~274_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~277_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~279_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .mask = 16'h77A0;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~279 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~275 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~275 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~275_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .mask = 16'hF47C;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~275 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mask = 16'h468C;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~175 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~175 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~174_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~173_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~175_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .mask = 16'hC1CD;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~175 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~172 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~172 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~172_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .mask = 16'hAFF5;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~172 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~180 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~180 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~180_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .mask = 16'h1A04;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~180 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~17 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~17 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~16_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~12_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~7_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~17_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .mask = 16'hB8CC;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~185 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~185 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~180_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~183_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~184_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~185_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .mask = 16'h58F8;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~185 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~182 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~182 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~182_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .mask = 16'hECF4;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~182 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~152 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~152 (
	.A(\macro_inst|apb_dac0_inst|phase_r [8]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~151_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~146_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~152_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .mask = 16'h5044;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~152 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~181 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~181 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~181_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .mask = 16'hBCE4;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~181 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~208 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~208 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~207_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~191_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~208_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .mask = 16'hF2C2;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~208 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~204 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~204 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~185_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~198_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~203_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~204_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .mask = 16'h1CDC;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~204 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~198 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~198 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~191_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~197_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~198_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .mask = 16'hA7A2;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~198 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~6 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~6 (
	.A(\macro_inst|apb_dac0_inst|phase_r [1]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .mask = 16'hFF80;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~209 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~209 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~185_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~208_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~203_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~209_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .mask = 16'hEC2C;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~209 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~183 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~183 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~182_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~181_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~183_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .mask = 16'h98DC;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~183 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~210 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~210 (
	.A(\macro_inst|apb_dac0_inst|phase_r [8]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~209_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~204_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~210_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .mask = 16'h5044;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~210 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~184 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~184 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~184_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .mask = 16'h4B14;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~184 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~38 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~38 (
	.A(\macro_inst|apb_dac0_inst|phase_r [8]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~31_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~37_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~38_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .mask = 16'h4450;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~38 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~246 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~246 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~246_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .mask = 16'h8000;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~246 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~33 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~33 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~32_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~33_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .mask = 16'hCC2E;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~33 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~35 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~35 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~21_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~34_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~33_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~35_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .mask = 16'hF588;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~35 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~256 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~256 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~4_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~255_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~256_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .mask = 16'h8C9D;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~256 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~21 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~21 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~21_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .mask = 16'h0F5F;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~3 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~3 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .mask = 16'h7EFE;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~5 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~5 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~4_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .mask = 16'hCD89;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~23 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~23 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~22_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~23_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .mask = 16'h6E4C;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~23 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~4 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~4 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .mask = 16'hFAF8;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~255 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~255 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~255_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .mask = 16'h0001;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~255 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~34 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~34 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~34_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .mask = 16'h7AFA;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~22 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~22 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~21_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .mask = 16'h8C9D;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~7 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~7 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~5_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~6_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .mask = 16'h2ECC;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~32 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~32 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~32_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .mask = 16'h7AF8;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~257 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~257 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~21_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~256_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~246_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~257_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .mask = 16'h52F2;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~257 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .mask = 16'h5F5F;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|_~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~332 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~332 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~331_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [8]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~305_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .mask = 16'hF4F8;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~332 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~326 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~326 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~326_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .mask = 16'hB1E4;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~326 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~331 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~331 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~330_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~324_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~311_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~331_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .mask = 16'hDAD0;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~331 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~330 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~330 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~325_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~328_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~329_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~330_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .mask = 16'h2ECC;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~330 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~328 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~328 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~326_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~327_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~328_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .mask = 16'hCC47;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~328 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~325 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~325 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~325_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .mask = 16'hF5F8;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~325 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~292 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~292 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~291_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~285_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~292_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .mask = 16'h98DC;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~292 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~327 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~327 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~327_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .mask = 16'h95B2;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~327 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~303 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~303 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~302_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~285_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~303_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .mask = 16'hDC98;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~303 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~329 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~329 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~329_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .mask = 16'h4AB4;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~329 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~305 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~305 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~304_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [8]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~299_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~305_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .mask = 16'h3022;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~305 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~304 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~304 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~298_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~279_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~303_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~304_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .mask = 16'hDDA0;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~304 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~299 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~299 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~298_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~279_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~292_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~299_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .mask = 16'h770A;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~299 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~178 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~178 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~177_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~171_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~158_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~178_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .mask = 16'hB8CC;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~178 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~167 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~167 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~167_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .mask = 16'hED40;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~167 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~169 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~169 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~169_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .mask = 16'h1FE6;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~169 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~139 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~139 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~138_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~137_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~139_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .mask = 16'hF2F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~139 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~148 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~148 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~138_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~135_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~148_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .mask = 16'h8D88;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~148 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~138 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~138 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~138_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .mask = 16'h758A;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~138 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~136 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~136 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~136_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .mask = 16'hF00E;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~136 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~166 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~166 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~166_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .mask = 16'h03C2;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~166 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~159 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~159 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~159_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .mask = 16'h4114;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~159 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~170 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~170 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~165_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~168_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~169_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~170_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .mask = 16'hF252;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~170 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~135 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~135 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~135_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .mask = 16'h67D0;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~135 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~171 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~171 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~164_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~170_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~171_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .mask = 16'hF0AC;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~171 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~137 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~137 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~136_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~135_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~137_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .mask = 16'h5044;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~137 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~168 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~168 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~167_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~166_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~168_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .mask = 16'hCDC1;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~168 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~164 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~164 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~159_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~163_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~162_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~164_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .mask = 16'h35F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~164 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~165 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~165 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~165_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .mask = 16'h01DA;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~165 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~126 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~126 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~125_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~124_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~126_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .mask = 16'hD560;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~126 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~125 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~125 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~125_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .mask = 16'hE46C;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~125 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~127 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~127 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~125_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~124_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~127_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .mask = 16'hAAB6;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~127 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~150 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~150 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~134_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~149_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~150_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .mask = 16'hD9C8;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~150 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~124 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~124 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~124_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .mask = 16'hD2D0;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~124 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~144 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~144 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~141_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~142_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~144_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .mask = 16'h1C44;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~144 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~149 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~149 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~147_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~148_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~149_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .mask = 16'hFFF0;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~149 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~142 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~142 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~142_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .mask = 16'hEC10;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~142 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~145 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~145 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~143_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~144_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~145_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .mask = 16'h30CF;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~145 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~128 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~128 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~127_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~126_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~128_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .mask = 16'h5599;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~128 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~147 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~147 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~147_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .mask = 16'h5514;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~147 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~151 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~151 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~150_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~145_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~128_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~151_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .mask = 16'hE6C4;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~151 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~146 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~146 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~140_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~145_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~128_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~146_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .mask = 16'h4C6E;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~146 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~140 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~140 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~134_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~139_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~140_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .mask = 16'hBB50;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~140 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~141 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~141 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~141_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .mask = 16'hA01C;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~141 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~143 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~143 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~141_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~142_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~143_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .mask = 16'hC5C0;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~143 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] (
// Location: LCCOMB_X54_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[6]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_adc0_inst|apb_db [6]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [6]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .mask = 16'hF0F0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[6] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] (
// Location: LCCOMB_X54_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[4]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [4]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [4]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[4] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] (
// Location: LCCOMB_X54_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[0]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [0]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [0]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[0] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] (
// Location: LCCOMB_X54_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[5]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [5]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [5]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[5] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] (
// Location: LCCOMB_X54_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[11]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [11]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[11]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [11]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[11] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] (
// Location: LCCOMB_X54_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[7]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_adc0_inst|apb_db [7]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [7]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .mask = 16'hF0F0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[7] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] (
// Location: LCCOMB_X54_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[8]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [8]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[8]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [8]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[8] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] (
// Location: LCCOMB_X54_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[3]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [3]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [3]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[3] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] (
// Location: LCCOMB_X54_Y4_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[1]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_adc0_inst|apb_db [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [1]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .mask = 16'hF0F0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[1] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wren_b (
// Location: LCCOMB_X54_Y4_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wren_b~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wren_b (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|ram_wren_b~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wren_b~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X54_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wren_b~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wren_b~q ));
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] (
// Location: LCCOMB_X54_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[2]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [2]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[2] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] (
// Location: LCCOMB_X54_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[10]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_adc0_inst|apb_db [10]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[10]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [10]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .mask = 16'hF0F0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[10] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] (
// Location: LCCOMB_X54_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_data_b[9]~feeder (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [9]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_data_b [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_data_b[9]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_data_b [9]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .mask = 16'hFF00;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wr_data_b[9] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X54_Y4_N0
alta_clkenctrl clken_ctrl_X54_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|ram_wren_b~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wren_b~0_combout_X54_Y4_SIG_SIG ));
defparam clken_ctrl_X54_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X54_Y4_N0
alta_asyncctrl asyncreset_ctrl_X54_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ));
defparam asyncreset_ctrl_X54_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X54_Y4_N1
alta_clkenctrl clken_ctrl_X54_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X54_Y4_SIG_VCC ));
defparam clken_ctrl_X54_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y4_N1.ClkEnMux = 2'b01;
// Location: FF_X56_Y10_N0
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[31] (
// Location: LCCOMB_X56_Y10_N0
// alta_lcell_comb \macro_inst|apb_prdata[31]~22 (
alta_slice \macro_inst|ahb2apb_inst|prdata[31] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [31]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [6]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [31]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[31]~22_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [31]));
defparam \macro_inst|ahb2apb_inst|prdata[31] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[31] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[31] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[31] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[31] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[31] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[31] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[31] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[31] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[31] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[12] (
// Location: LCCOMB_X56_Y10_N10
// alta_lcell_comb \macro_inst|apb_prdata[12]~3 (
alta_slice \macro_inst|ahb2apb_inst|prdata[12] (
	.A(\macro_inst|cfg_reg_inst|prdata [12]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|apb_prdata[10]~0_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [3]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[12]~3_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [12]));
defparam \macro_inst|ahb2apb_inst|prdata[12] .mask = 16'hE020;
defparam \macro_inst|ahb2apb_inst|prdata[12] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[12] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[12] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[12] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[12] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[12] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[12] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N12
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[30] (
// Location: LCCOMB_X56_Y10_N12
// alta_lcell_comb \macro_inst|apb_prdata[30]~21 (
alta_slice \macro_inst|ahb2apb_inst|prdata[30] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [30]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [5]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [30]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[30]~21_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [30]));
defparam \macro_inst|ahb2apb_inst|prdata[30] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[30] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[30] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[30] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[30] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[30] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[30] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[30] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[30] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[30] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N14
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[26] (
// Location: LCCOMB_X56_Y10_N14
// alta_lcell_comb \macro_inst|apb_prdata[26]~17 (
alta_slice \macro_inst|ahb2apb_inst|prdata[26] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [26]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [1]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [26]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[26]~17_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [26]));
defparam \macro_inst|ahb2apb_inst|prdata[26] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[26] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[26] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[26] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[26] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[26] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[26] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[26] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[26] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[26] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[10] (
// Location: LCCOMB_X56_Y10_N16
// alta_lcell_comb \macro_inst|apb_prdata[10]~1 (
alta_slice \macro_inst|ahb2apb_inst|prdata[10] (
	.A(\macro_inst|cfg_reg_inst|prdata [10]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|apb_prdata[10]~0_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [1]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[10]~1_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [10]));
defparam \macro_inst|ahb2apb_inst|prdata[10] .mask = 16'hE020;
defparam \macro_inst|ahb2apb_inst|prdata[10] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[10] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[10] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[10] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[10] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[10] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[10] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N18
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[21] (
// Location: LCCOMB_X56_Y10_N18
// alta_lcell_comb \macro_inst|apb_prdata[21]~12 (
alta_slice \macro_inst|ahb2apb_inst|prdata[21] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [21]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [21]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[21]~12_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [21]));
defparam \macro_inst|ahb2apb_inst|prdata[21] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[21] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[21] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[21] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[21] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[21] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[21] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[21] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[21] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[21] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[29] (
// Location: LCCOMB_X56_Y10_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~6 (
alta_slice \macro_inst|cfg_reg_inst|prdata[29] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|frequency [29]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [29]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~6_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [29]));
defparam \macro_inst|cfg_reg_inst|prdata[29] .mask = 16'h0800;
defparam \macro_inst|cfg_reg_inst|prdata[29] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[29] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[29] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[29] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[29] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[29] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[29] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[29] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[29] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N20
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[28] (
// Location: LCCOMB_X56_Y10_N20
// alta_lcell_comb \macro_inst|apb_prdata[28]~19 (
alta_slice \macro_inst|ahb2apb_inst|prdata[28] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [28]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [3]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [28]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[28]~19_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [28]));
defparam \macro_inst|ahb2apb_inst|prdata[28] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[28] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[28] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[28] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[28] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[28] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[28] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[28] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[28] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[28] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[26] (
// Location: LCCOMB_X56_Y10_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~3 (
alta_slice \macro_inst|cfg_reg_inst|prdata[26] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|cfg_reg_inst|frequency [26]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [26]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [26]));
defparam \macro_inst|cfg_reg_inst|prdata[26] .mask = 16'h0800;
defparam \macro_inst|cfg_reg_inst|prdata[26] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[26] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[26] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[26] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[26] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[26] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[26] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[26] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[26] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N24
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[29] (
// Location: LCCOMB_X56_Y10_N24
// alta_lcell_comb \macro_inst|apb_prdata[29]~20 (
alta_slice \macro_inst|ahb2apb_inst|prdata[29] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [4]),
	.D(\macro_inst|cfg_reg_inst|prdata [29]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [29]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[29]~20_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [29]));
defparam \macro_inst|ahb2apb_inst|prdata[29] .mask = 16'h5140;
defparam \macro_inst|ahb2apb_inst|prdata[29] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[29] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[29] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[29] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[29] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N26
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[11] (
// Location: LCCOMB_X56_Y10_N26
// alta_lcell_comb \macro_inst|apb_prdata[11]~2 (
alta_slice \macro_inst|ahb2apb_inst|prdata[11] (
	.A(\macro_inst|cfg_reg_inst|prdata [11]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|apb_prdata[10]~0_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[11]~2_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [11]));
defparam \macro_inst|ahb2apb_inst|prdata[11] .mask = 16'hE020;
defparam \macro_inst|ahb2apb_inst|prdata[11] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[11] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[11] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[11] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[11] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[11] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[11] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N28
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[15] (
// Location: LCCOMB_X56_Y10_N28
// alta_lcell_comb \macro_inst|apb_prdata[15]~6 (
alta_slice \macro_inst|ahb2apb_inst|prdata[15] (
	.A(\macro_inst|cfg_reg_inst|prdata [15]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|apb_prdata[10]~0_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [6]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[15]~6_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [15]));
defparam \macro_inst|ahb2apb_inst|prdata[15] .mask = 16'hE020;
defparam \macro_inst|ahb2apb_inst|prdata[15] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[15] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[15] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[15] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[15] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[15] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[15] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[30] (
// Location: LCCOMB_X56_Y10_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~7 (
alta_slice \macro_inst|cfg_reg_inst|prdata[30] (
	.A(\macro_inst|cfg_reg_inst|frequency [30]),
	.B(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|ahb2apb_inst|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [30]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~7_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [30]));
defparam \macro_inst|cfg_reg_inst|prdata[30] .mask = 16'h0800;
defparam \macro_inst|cfg_reg_inst|prdata[30] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[30] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[30] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[30] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[30] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[30] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[30] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[30] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[30] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[14] (
// Location: LCCOMB_X56_Y10_N4
// alta_lcell_comb \macro_inst|apb_prdata[14]~5 (
alta_slice \macro_inst|ahb2apb_inst|prdata[14] (
	.A(\macro_inst|cfg_reg_inst|prdata [14]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|apb_prdata[10]~0_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [5]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[14]~5_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [14]));
defparam \macro_inst|ahb2apb_inst|prdata[14] .mask = 16'hE020;
defparam \macro_inst|ahb2apb_inst|prdata[14] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[14] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[14] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N6
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[27] (
// Location: LCCOMB_X56_Y10_N6
// alta_lcell_comb \macro_inst|apb_prdata[27]~18 (
alta_slice \macro_inst|ahb2apb_inst|prdata[27] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|cfg_reg_inst|prdata [27]),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [27]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[27]~18_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [27]));
defparam \macro_inst|ahb2apb_inst|prdata[27] .mask = 16'h5410;
defparam \macro_inst|ahb2apb_inst|prdata[27] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[27] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[27] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[27] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[27] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[27] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[27] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[27] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[27] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[13] (
// Location: LCCOMB_X56_Y10_N8
// alta_lcell_comb \macro_inst|apb_prdata[13]~4 (
alta_slice \macro_inst|ahb2apb_inst|prdata[13] (
	.A(\macro_inst|cfg_reg_inst|prdata [13]),
	.B(\macro_inst|apb_prdata[10]~0_combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [4]),
	.D(\macro_inst|mem_apb_psel~combout ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[13]~4_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [13]));
defparam \macro_inst|ahb2apb_inst|prdata[13] .mask = 16'hC088;
defparam \macro_inst|ahb2apb_inst|prdata[13] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[13] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[13] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[13] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[13] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[13] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[13] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y10_N0
alta_clkenctrl clken_ctrl_X56_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y10_SIG_SIG ));
defparam clken_ctrl_X56_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y10_N0
alta_asyncctrl asyncreset_ctrl_X56_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ));
defparam asyncreset_ctrl_X56_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y10_N1
alta_clkenctrl clken_ctrl_X56_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X56_Y10_SIG_SIG ));
defparam clken_ctrl_X56_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y10_N1.ClkEnMux = 2'b10;
// Location: FF_X56_Y11_N0
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[19] (
// Location: LCCOMB_X56_Y11_N0
// alta_lcell_comb \macro_inst|apb_prdata[19]~10 (
alta_slice \macro_inst|ahb2apb_inst|prdata[19] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]),
	.D(\macro_inst|cfg_reg_inst|prdata [19]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [19]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[19]~10_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [19]));
defparam \macro_inst|ahb2apb_inst|prdata[19] .mask = 16'h3120;
defparam \macro_inst|ahb2apb_inst|prdata[19] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[19] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[19] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[19] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[19] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[19] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[19] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[19] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[19] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[7] (
// Location: LCCOMB_X56_Y11_N10
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[7]~7 (
alta_slice \macro_inst|ahb2apb_inst|prdata[7] (
	.A(\macro_inst|trig_ctrl_inst|prdata [7]),
	.B(\macro_inst|cfg_reg_inst|prdata [7]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]),
	.D(\macro_inst|pr_select [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X56_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X56_Y11_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[7]~7_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [7]));
defparam \macro_inst|ahb2apb_inst|prdata[7] .mask = 16'hAACC;
defparam \macro_inst|ahb2apb_inst|prdata[7] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[7] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[7] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[7] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[7] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y11_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[25] (
alta_slice \macro_inst|cfg_reg_inst|frequency[25] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[25] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [25]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[25]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [25]));
defparam \macro_inst|cfg_reg_inst|frequency[25] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[25] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[25] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[25] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[25] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[25] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[25] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[25] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[25] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[25] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[12] (
alta_slice \macro_inst|cfg_reg_inst|frequency[12] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[12] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[12]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [12]));
defparam \macro_inst|cfg_reg_inst|frequency[12] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[12] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[12] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[12] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[12] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[12] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[12] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[12] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[9] (
// Location: LCCOMB_X56_Y11_N16
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[9]~9 (
alta_slice \macro_inst|ahb2apb_inst|prdata[9] (
	.A(\macro_inst|trig_ctrl_inst|prdata [9]),
	.B(\macro_inst|cfg_reg_inst|prdata [9]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]),
	.D(\macro_inst|pr_select [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X56_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X56_Y11_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[9]~9_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [9]));
defparam \macro_inst|ahb2apb_inst|prdata[9] .mask = 16'hAACC;
defparam \macro_inst|ahb2apb_inst|prdata[9] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[9] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[9] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[9] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y11_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[18] (
alta_slice \macro_inst|cfg_reg_inst|frequency[18] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[18] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [18]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[18]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [18]));
defparam \macro_inst|cfg_reg_inst|frequency[18] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[18] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[18] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[18] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[18] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[18] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[18] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[18] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[18] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[18] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[16] (
alta_slice \macro_inst|cfg_reg_inst|frequency[16] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[16] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [16]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[16]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [16]));
defparam \macro_inst|cfg_reg_inst|frequency[16] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[16] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[16] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[16] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[16] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[16] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[16] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[16] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[16] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[16] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[23] (
alta_slice \macro_inst|cfg_reg_inst|frequency[23] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[23] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [23]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[23]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [23]));
defparam \macro_inst|cfg_reg_inst|frequency[23] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[23] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[23] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[23] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[23] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[23] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[23] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[23] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[23] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[23] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N22
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[23] (
// Location: LCCOMB_X56_Y11_N22
// alta_lcell_comb \macro_inst|apb_prdata[23]~14 (
alta_slice \macro_inst|ahb2apb_inst|prdata[23] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [7]),
	.D(\macro_inst|cfg_reg_inst|prdata [23]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [23]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[23]~14_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [23]));
defparam \macro_inst|ahb2apb_inst|prdata[23] .mask = 16'h3120;
defparam \macro_inst|ahb2apb_inst|prdata[23] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[23] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[23] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[23] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[23] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[23] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[23] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[23] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[23] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[9] (
// Location: LCCOMB_X56_Y11_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[9]~1 (
alta_slice \macro_inst|cfg_reg_inst|frequency[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[9]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [9]));
defparam \macro_inst|cfg_reg_inst|frequency[9] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|frequency[9] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[9] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[9] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[9] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N26
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[20] (
// Location: LCCOMB_X56_Y11_N26
// alta_lcell_comb \macro_inst|apb_prdata[20]~11 (
alta_slice \macro_inst|ahb2apb_inst|prdata[20] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|cfg_reg_inst|prdata [20]),
	.C(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [20]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[20]~11_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [20]));
defparam \macro_inst|ahb2apb_inst|prdata[20] .mask = 16'h0E04;
defparam \macro_inst|ahb2apb_inst|prdata[20] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[20] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[20] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[20] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[20] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[20] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[20] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[20] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[20] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N28
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[3] (
// Location: LCCOMB_X56_Y11_N28
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[3]~3 (
alta_slice \macro_inst|ahb2apb_inst|prdata[3] (
	.A(\macro_inst|trig_ctrl_inst|prdata [3]),
	.B(\macro_inst|cfg_reg_inst|prdata [3]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [3]),
	.D(\macro_inst|pr_select [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X56_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X56_Y11_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[3]~3_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [3]));
defparam \macro_inst|ahb2apb_inst|prdata[3] .mask = 16'hAACC;
defparam \macro_inst|ahb2apb_inst|prdata[3] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[3] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[3] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[3] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[3] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y11_N30
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[25] (
// Location: LCCOMB_X56_Y11_N30
// alta_lcell_comb \macro_inst|apb_prdata[25]~16 (
alta_slice \macro_inst|ahb2apb_inst|prdata[25] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a9_PORTADATAOUT_bus [0]),
	.D(\macro_inst|cfg_reg_inst|prdata [25]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [25]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[25]~16_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [25]));
defparam \macro_inst|ahb2apb_inst|prdata[25] .mask = 16'h3120;
defparam \macro_inst|ahb2apb_inst|prdata[25] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[25] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[25] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[25] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[25] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[25] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[25] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[25] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[25] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[2] (
// Location: LCCOMB_X56_Y11_N4
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[2]~2 (
alta_slice \macro_inst|ahb2apb_inst|prdata[2] (
	.A(\macro_inst|cfg_reg_inst|prdata [2]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]),
	.D(\macro_inst|trig_ctrl_inst|prdata [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X56_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X56_Y11_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[2]~2_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [2]));
defparam \macro_inst|ahb2apb_inst|prdata[2] .mask = 16'hEE22;
defparam \macro_inst|ahb2apb_inst|prdata[2] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[2] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[2] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[2] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[2] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y11_N6
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[18] (
// Location: LCCOMB_X56_Y11_N6
// alta_lcell_comb \macro_inst|apb_prdata[18]~9 (
alta_slice \macro_inst|ahb2apb_inst|prdata[18] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [2]),
	.D(\macro_inst|cfg_reg_inst|prdata [18]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [18]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[18]~9_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [18]));
defparam \macro_inst|ahb2apb_inst|prdata[18] .mask = 16'h3120;
defparam \macro_inst|ahb2apb_inst|prdata[18] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[18] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[18] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[18] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[18] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[18] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[18] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[18] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[18] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[16] (
// Location: LCCOMB_X56_Y11_N8
// alta_lcell_comb \macro_inst|apb_prdata[16]~7 (
alta_slice \macro_inst|ahb2apb_inst|prdata[16] (
	.A(\macro_inst|mem_apb_psel~combout ),
	.B(\macro_inst|cfg_reg_inst|prdata [16]),
	.C(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [16]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[16]~7_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [16]));
defparam \macro_inst|ahb2apb_inst|prdata[16] .mask = 16'h0E04;
defparam \macro_inst|ahb2apb_inst|prdata[16] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[16] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[16] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[16] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[16] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[16] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[16] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[16] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[16] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y11_N0
alta_clkenctrl clken_ctrl_X56_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y11_SIG_SIG ));
defparam clken_ctrl_X56_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y11_N0
alta_asyncctrl asyncreset_ctrl_X56_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y11_SIG ));
defparam asyncreset_ctrl_X56_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y11_N1
alta_clkenctrl clken_ctrl_X56_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X56_Y11_SIG_SIG ));
defparam clken_ctrl_X56_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y11_N0
alta_syncctrl syncreset_ctrl_X56_Y11(.Din(\macro_inst|ahb2apb_inst|prdata[9]~11_combout ), .Dout(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X56_Y11_SIG ));
defparam syncreset_ctrl_X56_Y11.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X56_Y11_N1
alta_syncctrl syncload_ctrl_X56_Y11(.Din(\macro_inst|mem_apb_psel~combout ), .Dout(\macro_inst|mem_apb_psel~combout__SyncLoad_X56_Y11_SIG ));
defparam syncload_ctrl_X56_Y11.SyncCtrlMux = 2'b10;
// Location: FF_X56_Y12_N14
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[24] (
// Location: LCCOMB_X56_Y12_N14
// alta_lcell_comb \macro_inst|apb_prdata[24]~15 (
alta_slice \macro_inst|ahb2apb_inst|prdata[24] (
	.A(\macro_inst|cfg_reg_inst|prdata [24]),
	.B(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.C(\macro_inst|mem_apb_psel~combout ),
	.D(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [24]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[24]~15_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [24]));
defparam \macro_inst|ahb2apb_inst|prdata[24] .mask = 16'h3202;
defparam \macro_inst|ahb2apb_inst|prdata[24] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[24] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[24] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[24] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[24] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[24] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[24] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[24] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[24] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y12_N0
alta_clkenctrl clken_ctrl_X56_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X56_Y12_SIG_SIG ));
defparam clken_ctrl_X56_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y12_N0
alta_asyncctrl asyncreset_ctrl_X56_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ));
defparam asyncreset_ctrl_X56_Y12_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X56_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~270 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~270 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~270_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .mask = 16'hFEAA;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~270 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~333 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~333 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~255_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~333_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .mask = 16'h0002;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~333 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~263 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~263 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~263_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .mask = 16'h0055;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~263 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~334 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~334 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~333_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~268_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [9]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~334_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .mask = 16'h0F1C;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~334 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~267 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~267 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~266_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~267_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .mask = 16'h3908;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~267 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~272 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~272 (
	.A(\macro_inst|apb_dac0_inst|phase_r [8]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~271_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [9]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~269_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~272_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .mask = 16'hF4A4;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~272 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~337 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~337 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~337_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .mask = 16'h0001;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~337 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~269 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~269 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~163_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~268_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~21_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~269_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .mask = 16'h3230;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~269 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~338 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~338 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~255_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~337_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .mask = 16'h7333;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~338 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~271 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~271 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~261_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~270_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~271_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .mask = 16'h1C10;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~271 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~163 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~163 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~163_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .mask = 16'h00F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~163 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~265 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~265 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~255_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~265_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .mask = 16'h2367;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~265 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~261 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~261 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~261_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .mask = 16'hAA80;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~261 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~335 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~335 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~263_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~335_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .mask = 16'h7737;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~335 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~266 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~266 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~263_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~265_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~266_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .mask = 16'h0E02;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~266 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~268 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~268 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~261_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~268_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .mask = 16'hE0E0;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~268 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|diff[1]~2 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|diff[2]~4 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|diff[3]~6 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|diff[4]~8 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [4]),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|diff[5]~10 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|diff[6]~12 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [6]),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[6]~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[7]~14 (
alta_slice \macro_inst|apb_dac0_inst|diff[7]~14 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[7]~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[8]~16 (
alta_slice \macro_inst|apb_dac0_inst|diff[8]~16 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|diff[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[8]~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[9]~18 (
alta_slice \macro_inst|apb_dac0_inst|diff[9]~18 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [9]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.Cin(\macro_inst|apb_dac0_inst|diff[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .mask = 16'h5AA5;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux2~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux2~1 (
	.A(\macro_inst|apb_dac0_inst|Add5~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux2~0_combout ),
	.D(\macro_inst|apb_dac0_inst|max_vol_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux2~1 .mask = 16'hBCB0;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux2~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .mask = 16'h0000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|diff[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|diff[0]~0 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [0]),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|diff[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .mask = 16'h66BB;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|diff[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~264 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~264 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~262_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~340_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~264_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .mask = 16'h17F3;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~264 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~262 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~262 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~261_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~262_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .mask = 16'hE222;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~262 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~273 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~273 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~267_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~264_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~272_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~273_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .mask = 16'h3CFA;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~273 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~340 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~340 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~340_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .mask = 16'hAAA8;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~340 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~260 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~260 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~244_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~259_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~260_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .mask = 16'h44C0;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~260 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~123 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~123 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~122_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~123_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .mask = 16'h3C00;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~123 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~228 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~228 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~222_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~227_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~228_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .mask = 16'hAAD8;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~228 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~77 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~77 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~344_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~66_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~74_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~77_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .mask = 16'hBBC0;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~77 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~78 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~78 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~60_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~77_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [8]),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .mask = 16'hBAEA;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~78 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~233 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~233 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~232_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~210_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .mask = 16'hF6F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~233 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~232 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~232 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~231_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~216_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~228_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~232_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .mask = 16'hACF0;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~232 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~254 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~254 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~244_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~253_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~254_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .mask = 16'h2230;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~254 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~1 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.B(\macro_inst|apb_adc0_inst|apb_db [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~1_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .mask = 16'h0044;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~11 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~11 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.B(\macro_inst|apb_adc0_inst|apb_db [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~11_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~13 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~13 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.B(\macro_inst|apb_adc0_inst|apb_db [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~13_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~13 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y4_N14
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[7] (
// Location: LCCOMB_X56_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~15 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[7] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.B(\macro_inst|apb_adc0_inst|apb_db [7]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[7] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~13_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~15_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [7]));
defparam \macro_inst|apb_adc0_inst|apb_db[7] .mask = 16'h002B;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[7] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~17 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~17 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.B(\macro_inst|apb_adc0_inst|apb_db [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~17_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~17 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y4_N18
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[9] (
// Location: LCCOMB_X56_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~19 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[9] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.B(\macro_inst|apb_adc0_inst|apb_db [9]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[9] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~17_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~19_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [9]));
defparam \macro_inst|apb_adc0_inst|apb_db[9] .mask = 16'h002B;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[9] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[9] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y4_N2
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_eoc (
// Location: LCCOMB_X56_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~3 (
alta_slice \macro_inst|apb_adc0_inst|apb_eoc (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.B(\macro_inst|apb_adc0_inst|apb_db [1]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.eoc ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~1_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_eoc~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~3_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_eoc~q ));
defparam \macro_inst|apb_adc0_inst|apb_eoc .mask = 16'h002B;
defparam \macro_inst|apb_adc0_inst|apb_eoc .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_eoc .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_eoc .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_eoc .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_eoc .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_eoc .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_eoc .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_eoc .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_eoc .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~21 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~21 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.B(\macro_inst|apb_adc0_inst|apb_db [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~21_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~22 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~22 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|apb_db [11]),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~21_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan5~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .mask = 16'hFAA0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~22 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y4_N24
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[5] (
alta_slice \macro_inst|apb_adc0_inst|apb_db[5] (
	.A(),
	.B(),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[5] ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [5]));
defparam \macro_inst|apb_adc0_inst|apb_db[5] .mask = 16'hFFFF;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[5] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N26
// alta_lcell_comb \macro_inst|apb_adc0_inst|adc_eoc_out (
// Location: FF_X56_Y4_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_eoc_sync1 (
alta_slice \macro_inst|trig_ctrl_inst|adc_eoc_sync1 (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|apb_eoc~q ),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|adc_inst.eoc ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_eoc_sync1~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|adc_eoc_out~combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_eoc_sync1~q ));
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .mask = 16'h00CC;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync1 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y4_N28
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[1] (
// Location: LCCOMB_X56_Y4_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always4~2 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[1] (
	.A(\macro_inst|trig_ctrl_inst|LessThan5~22_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_level~q ),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[1] ),
	.D(\macro_inst|trig_ctrl_inst|LessThan3~22_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|always4~2_combout ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [1]));
defparam \macro_inst|apb_adc0_inst|apb_db[1] .mask = 16'hEE22;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .mode = "logic";
defparam \macro_inst|apb_adc0_inst|apb_db[1] .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N30
// alta_lcell_comb \macro_inst|apb_adc0_inst|always1~0 (
// Location: FF_X56_Y4_N30
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[3] (
alta_slice \macro_inst|apb_adc0_inst|apb_db[3] (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|apb_adc0_inst|apb_eoc~q ),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[3] ),
	.D(\macro_inst|apb_adc0_inst|adc_inst.eoc ),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(\macro_inst|apb_adc0_inst|always1~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [3]));
defparam \macro_inst|apb_adc0_inst|apb_db[3] .mask = 16'h0088;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .mode = "logic";
defparam \macro_inst|apb_adc0_inst|apb_db[3] .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~5 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~5 (
	.A(\macro_inst|apb_adc0_inst|apb_db [2]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~5_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~7 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~7 (
	.A(\macro_inst|apb_adc0_inst|apb_db [3]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~7_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan5~9 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan5~9 (
	.A(\macro_inst|apb_adc0_inst|apb_db [4]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan5~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan5~9_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan5~9 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y4_N0
alta_clkenctrl clken_ctrl_X56_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|apb_adc0_inst|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X56_Y4_SIG_SIG ));
defparam clken_ctrl_X56_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y4_N0
alta_asyncctrl asyncreset_ctrl_X56_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ));
defparam asyncreset_ctrl_X56_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y4_N1
alta_clkenctrl clken_ctrl_X56_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y4_SIG_VCC ));
defparam clken_ctrl_X56_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y4_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X56_Y4_N0
alta_syncctrl syncreset_ctrl_X56_Y4(.Din(), .Dout(SyncReset_X56_Y4_GND));
defparam syncreset_ctrl_X56_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y4_N1
alta_syncctrl syncload_ctrl_X56_Y4(.Din(), .Dout(SyncLoad_X56_Y4_VCC));
defparam syncload_ctrl_X56_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X56_Y5_N10
// alta_lcell_comb \gpio0_io_in[5] (
alta_slice \gpio0_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[5] .mask = 16'h0000;
defparam \gpio0_io_in[5] .mode = "logic";
defparam \gpio0_io_in[5] .modeMux = 1'b0;
defparam \gpio0_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[5] .ShiftMux = 1'b0;
defparam \gpio0_io_in[5] .BypassEn = 1'b0;
defparam \gpio0_io_in[5] .CarryEnb = 1'b1;
defparam \gpio0_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N12
// alta_lcell_comb \gpio0_io_in[6] (
alta_slice \gpio0_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[6] .mask = 16'h0000;
defparam \gpio0_io_in[6] .mode = "logic";
defparam \gpio0_io_in[6] .modeMux = 1'b0;
defparam \gpio0_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[6] .ShiftMux = 1'b0;
defparam \gpio0_io_in[6] .BypassEn = 1'b0;
defparam \gpio0_io_in[6] .CarryEnb = 1'b1;
defparam \gpio0_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N14
// alta_lcell_comb \gpio0_io_in[7] (
alta_slice \gpio0_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[7] .mask = 16'h0000;
defparam \gpio0_io_in[7] .mode = "logic";
defparam \gpio0_io_in[7] .modeMux = 1'b0;
defparam \gpio0_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[7] .ShiftMux = 1'b0;
defparam \gpio0_io_in[7] .BypassEn = 1'b0;
defparam \gpio0_io_in[7] .CarryEnb = 1'b1;
defparam \gpio0_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N2
// alta_lcell_comb \gpio0_io_in[1] (
alta_slice \gpio0_io_in[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[1]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[1] .mask = 16'h0000;
defparam \gpio0_io_in[1] .mode = "logic";
defparam \gpio0_io_in[1] .modeMux = 1'b0;
defparam \gpio0_io_in[1] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[1] .ShiftMux = 1'b0;
defparam \gpio0_io_in[1] .BypassEn = 1'b0;
defparam \gpio0_io_in[1] .CarryEnb = 1'b1;
defparam \gpio0_io_in[1] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[1] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N4
// alta_lcell_comb \gpio0_io_in[2] (
alta_slice \gpio0_io_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[2]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[2] .mask = 16'h0000;
defparam \gpio0_io_in[2] .mode = "logic";
defparam \gpio0_io_in[2] .modeMux = 1'b0;
defparam \gpio0_io_in[2] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[2] .ShiftMux = 1'b0;
defparam \gpio0_io_in[2] .BypassEn = 1'b0;
defparam \gpio0_io_in[2] .CarryEnb = 1'b1;
defparam \gpio0_io_in[2] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[2] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N6
// alta_lcell_comb \gpio0_io_in[3] (
alta_slice \gpio0_io_in[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[3]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[3] .mask = 16'h0000;
defparam \gpio0_io_in[3] .mode = "logic";
defparam \gpio0_io_in[3] .modeMux = 1'b0;
defparam \gpio0_io_in[3] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[3] .ShiftMux = 1'b0;
defparam \gpio0_io_in[3] .BypassEn = 1'b0;
defparam \gpio0_io_in[3] .CarryEnb = 1'b1;
defparam \gpio0_io_in[3] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[3] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N8
// alta_lcell_comb \gpio0_io_in[4] (
alta_slice \gpio0_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio0_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio0_io_in[4] .mask = 16'h0000;
defparam \gpio0_io_in[4] .mode = "logic";
defparam \gpio0_io_in[4] .modeMux = 1'b0;
defparam \gpio0_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio0_io_in[4] .ShiftMux = 1'b0;
defparam \gpio0_io_in[4] .BypassEn = 1'b0;
defparam \gpio0_io_in[4] .CarryEnb = 1'b1;
defparam \gpio0_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio0_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio0_io_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~220 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~220 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~218_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~219_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~220_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .mask = 16'hD0D3;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~220 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~218 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~218 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~218_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .mask = 16'hB194;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~218 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~241 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~241 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~241_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .mask = 16'h5444;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~241 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~242 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~242 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~237_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~240_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~241_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~242_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .mask = 16'hF858;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~242 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~219 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~219 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~219_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .mask = 16'h4E6E;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~219 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~237 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~237 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~237_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .mask = 16'h0F00;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~237 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~238 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~238 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~238_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .mask = 16'h00F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~238 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~250 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~250 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~249_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~238_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~250_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .mask = 16'hF1A1;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~250 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~222 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~222 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~221_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~217_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~220_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~222_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .mask = 16'hBB0C;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~222 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~249 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~249 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~249_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .mask = 16'hCF0F;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~249 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~239 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~239 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~239_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .mask = 16'hF0F3;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~239 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~252 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~252 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~251_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~237_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~250_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~252_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .mask = 16'hAFC0;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~252 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~221 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~221 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~221_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .mask = 16'hEC1E;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~221 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~217 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~217 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~217_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .mask = 16'hE96E;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~217 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~251 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~251 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~251_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .mask = 16'hD554;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~251 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~240 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~240 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~239_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~238_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~240_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .mask = 16'hCEC2;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~240 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~229 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~229 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~229_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .mask = 16'h9966;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~229 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~216 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~216 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~215_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~214_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~211_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~216_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .mask = 16'h7C70;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~216 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~213 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~213 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~213_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .mask = 16'h04D6;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~213 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~231 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~231 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~342_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~229_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~230_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~231_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .mask = 16'h1BAA;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~231 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~211 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~211 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~211_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .mask = 16'h2A98;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~211 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~212 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~212 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~212_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .mask = 16'h004A;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~212 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~341 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~341 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~341_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .mask = 16'h2692;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~341 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~223 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~223 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~223_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .mask = 16'hB366;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~223 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~215 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~215 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~215_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .mask = 16'h0FF0;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~215 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~225 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~225 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~223_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~224_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~225_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .mask = 16'h03BB;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~225 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~226 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~226 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~226_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .mask = 16'h6118;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~226 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~227 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~227 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~225_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~226_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~227_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .mask = 16'hAEAA;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~227 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~214 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~214 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~213_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~212_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~214_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .mask = 16'hC2F2;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~214 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~230 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~230 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~230_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .mask = 16'h9566;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~230 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~342 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~342 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~341_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~342_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .mask = 16'hF0E2;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~342 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~224 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~224 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~224_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .mask = 16'hD0D2;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~224 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux3~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux3~0 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [6]),
	.B(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Add4~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux3~0 .mask = 16'hE3E0;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux3~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~6 (
alta_slice \macro_inst|apb_dac0_inst|Add4~6 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~6 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Add4~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~8 (
alta_slice \macro_inst|apb_dac0_inst|Add4~8 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~8 .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|Add4~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~10 (
// Location: FF_X56_Y8_N14
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[3] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[3] (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28_combout ),
	.C(\macro_inst|cfg_reg_inst|max_vol [3]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~9 ),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(SyncReset_X56_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~11 ),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [3]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y8_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~12 (
// Location: FF_X56_Y8_N16
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[6] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[6] (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [6]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30_combout ),
	.C(\macro_inst|cfg_reg_inst|max_vol [6]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~11 ),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(SyncReset_X56_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~13 ),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [6]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y8_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~14 (
alta_slice \macro_inst|apb_dac0_inst|Add4~14 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~14 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Add4~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux2~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux2~0 (
	.A(\macro_inst|apb_dac0_inst|Add3~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Add4~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux2~0 .mask = 16'hCBC8;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux2~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~16 (
alta_slice \macro_inst|apb_dac0_inst|Add4~16 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [8]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~16 .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|Add4~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~18 (
// Location: FF_X56_Y8_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[4] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[4] (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [9]),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|max_vol [4]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Add4~17 ),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(SyncReset_X56_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~18_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [4]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .mask = 16'h5AA5;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y8_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~4 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~4 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [2]),
	.C(\macro_inst|apb_dac0_inst|Add4~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~4 .mask = 16'hAAD8;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~4 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux1~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux1~0 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [8]),
	.B(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Add4~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux1~0 .mask = 16'hE3E0;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux1~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux4~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux4~0 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Add4~10_combout ),
	.D(\macro_inst|apb_dac0_inst|Add3~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux4~0 .mask = 16'hDC98;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux4~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux9~0 (
// Location: FF_X56_Y8_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[0] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[0] (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Add4~0_combout ),
	.C(\macro_inst|cfg_reg_inst|max_vol [0]),
	.D(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(SyncReset_X56_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Mux9~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [0]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .mask = 16'hAAE4;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .FeedbackMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y8_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~0 (
alta_slice \macro_inst|apb_dac0_inst|Add4~0 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [0]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~0 .mask = 16'h66BB;
defparam \macro_inst|apb_dac0_inst|Add4~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~2 (
alta_slice \macro_inst|apb_dac0_inst|Add4~2 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~2 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Add4~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add4~4 (
alta_slice \macro_inst|apb_dac0_inst|Add4~4 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add4~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add4~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add4~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add4~4 .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|Add4~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add4~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add4~4 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y8_N0
alta_clkenctrl clken_ctrl_X56_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X56_Y8_SIG_VCC ));
defparam clken_ctrl_X56_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y8_N0
alta_asyncctrl asyncreset_ctrl_X56_Y8_N0(.Din(), .Dout(AsyncReset_X56_Y8_GND));
defparam asyncreset_ctrl_X56_Y8_N0.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y8_N0
alta_syncctrl syncreset_ctrl_X56_Y8(.Din(), .Dout(SyncReset_X56_Y8_GND));
defparam syncreset_ctrl_X56_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y8_N1
alta_syncctrl syncload_ctrl_X56_Y8(.Din(), .Dout(SyncLoad_X56_Y8_VCC));
defparam syncload_ctrl_X56_Y8.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X56_Y9_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~104 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~104 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~104_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .mask = 16'h78E2;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~104 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~113 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~113 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~111_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~110_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~113_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .mask = 16'hAF7C;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~113 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~114 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~114 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~112_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~113_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~114_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .mask = 16'hC0CF;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~114 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~120 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~120 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~120_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .mask = 16'h2400;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~120 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~121 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~121 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~119_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~120_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~121_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .mask = 16'hE966;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~121 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~112 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~112 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~111_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~110_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~112_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .mask = 16'h06D2;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~112 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~106 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~106 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~106_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .mask = 16'h9F3C;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~106 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~110 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~110 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~110_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .mask = 16'h1C0A;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~110 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~122 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~122 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~118_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~109_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~121_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~122_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .mask = 16'hEA62;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~122 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~105 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~105 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~105_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .mask = 16'hA71C;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~105 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~119 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~119 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~119_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .mask = 16'h2044;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~119 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~108 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~108 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~108_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .mask = 16'h9C60;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~108 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~111 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~111 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~111_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .mask = 16'hFCF0;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~111 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~109 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~109 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~108_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~107_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~104_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~109_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .mask = 16'h7A70;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~109 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~118 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~118 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~114_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~117_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~118_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .mask = 16'hE3E0;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~118 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~107 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~107 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~106_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [2]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~105_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~107_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .mask = 16'hF1A1;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~107 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N0
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[26] (
alta_slice \macro_inst|cfg_reg_inst|frequency[26] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[26] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [26]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[26]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [26]));
defparam \macro_inst|cfg_reg_inst|frequency[26] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[26] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[26] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[26] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[26] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[26] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[26] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[26] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[26] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[26] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector13~2 (
// Location: FF_X57_Y10_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[12] (
alta_slice \macro_inst|cfg_reg_inst|prdata[12] (
	.A(\macro_inst|cfg_reg_inst|frequency [12]),
	.B(\macro_inst|cfg_reg_inst|Selector13~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector13~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector13~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [12]));
defparam \macro_inst|cfg_reg_inst|prdata[12] .mask = 16'hA0EC;
defparam \macro_inst|cfg_reg_inst|prdata[12] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[12] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[12] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[12] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[12] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[12] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[12] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector10~1 (
// Location: FF_X57_Y10_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[15] (
alta_slice \macro_inst|cfg_reg_inst|prdata[15] (
	.A(\macro_inst|cfg_reg_inst|frequency [15]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector10~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector13~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector10~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [15]));
defparam \macro_inst|cfg_reg_inst|prdata[15] .mask = 16'h88F8;
defparam \macro_inst|cfg_reg_inst|prdata[15] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[15] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[15] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[15] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[15] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[15] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[15] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[28] (
alta_slice \macro_inst|cfg_reg_inst|frequency[28] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[28] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [28]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[28]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [28]));
defparam \macro_inst|cfg_reg_inst|frequency[28] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[28] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[28] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[28] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[28] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[28] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[28] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[28] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[28] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[28] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[13] (
alta_slice \macro_inst|cfg_reg_inst|frequency[13] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[13] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[13]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [13]));
defparam \macro_inst|cfg_reg_inst|frequency[13] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[13] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[13] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[13] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[13] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[13] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[13] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[13] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[29] (
alta_slice \macro_inst|cfg_reg_inst|frequency[29] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[29] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [29]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[29]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [29]));
defparam \macro_inst|cfg_reg_inst|frequency[29] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[29] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[29] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[29] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[29] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[29] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[29] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[29] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[29] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[29] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[31] (
alta_slice \macro_inst|cfg_reg_inst|frequency[31] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[31] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [31]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[31]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [31]));
defparam \macro_inst|cfg_reg_inst|frequency[31] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[31] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[31] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[31] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[31] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[31] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[31] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector4~0 (
// Location: FF_X57_Y10_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[21] (
alta_slice \macro_inst|cfg_reg_inst|prdata[21] (
	.A(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\macro_inst|cfg_reg_inst|min_vol [5]),
	.D(\macro_inst|cfg_reg_inst|frequency [21]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [21]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [21]));
defparam \macro_inst|cfg_reg_inst|prdata[21] .mask = 16'hCE0A;
defparam \macro_inst|cfg_reg_inst|prdata[21] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[21] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[21] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[21] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[21] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[21] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[21] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[21] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[21] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[27] (
alta_slice \macro_inst|cfg_reg_inst|frequency[27] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[27] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [27]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[27]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [27]));
defparam \macro_inst|cfg_reg_inst|frequency[27] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[27] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[27] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[27] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[27] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[27] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[27] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[27] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[27] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[27] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector12~1 (
// Location: FF_X57_Y10_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[13] (
alta_slice \macro_inst|cfg_reg_inst|prdata[13] (
	.A(\macro_inst|cfg_reg_inst|Selector12~0_combout ),
	.B(\macro_inst|cfg_reg_inst|frequency [13]),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector13~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector12~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [13]));
defparam \macro_inst|cfg_reg_inst|prdata[13] .mask = 16'hC0EA;
defparam \macro_inst|cfg_reg_inst|prdata[13] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[13] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[13] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[13] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[13] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[13] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[13] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[27] (
// Location: LCCOMB_X57_Y10_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~4 (
alta_slice \macro_inst|cfg_reg_inst|prdata[27] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|frequency [27]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [27]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [27]));
defparam \macro_inst|cfg_reg_inst|prdata[27] .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|prdata[27] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[27] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[27] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[27] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[27] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[27] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[27] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[27] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[27] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[31]~0 (
alta_slice \macro_inst|cfg_reg_inst|frequency[31]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[31]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[28] (
// Location: LCCOMB_X57_Y10_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~5 (
alta_slice \macro_inst|cfg_reg_inst|prdata[28] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|frequency [28]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [28]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [28]));
defparam \macro_inst|cfg_reg_inst|prdata[28] .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|prdata[28] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[28] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[28] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[28] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[28] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[28] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[28] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[28] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[28] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|wave_type[1]~0 (
alta_slice \macro_inst|cfg_reg_inst|wave_type[1]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|wave_type[1]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .mask = 16'h1000;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|wave_type[1]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[30] (
alta_slice \macro_inst|cfg_reg_inst|frequency[30] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[30] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [30]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[30]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [30]));
defparam \macro_inst|cfg_reg_inst|frequency[30] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[30] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[30] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[30] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[30] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[30] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[30] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[30] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[30] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[30] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[31] (
// Location: LCCOMB_X57_Y10_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata~8 (
alta_slice \macro_inst|cfg_reg_inst|prdata[31] (
	.A(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|frequency [31]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [31]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata~8_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [31]));
defparam \macro_inst|cfg_reg_inst|prdata[31] .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|prdata[31] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[31] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[31] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[31] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[31] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[31] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[31] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[31] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[31] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y10_N0
alta_clkenctrl clken_ctrl_X57_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y10_SIG_SIG ));
defparam clken_ctrl_X57_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y10_N0
alta_asyncctrl asyncreset_ctrl_X57_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ));
defparam asyncreset_ctrl_X57_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y10_N1
alta_clkenctrl clken_ctrl_X57_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y10_SIG_SIG ));
defparam clken_ctrl_X57_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y10_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X57_Y11_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|min_vol[0]~0 (
alta_slice \macro_inst|cfg_reg_inst|min_vol[0]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[0]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[9] (
// Location: LCCOMB_X57_Y11_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|max_vol[9]~0 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[9] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|max_vol[9]~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [9]));
defparam \macro_inst|cfg_reg_inst|max_vol[9] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[9] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|max_vol[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector9~0 (
// Location: FF_X57_Y11_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[16] (
alta_slice \macro_inst|cfg_reg_inst|prdata[16] (
	.A(\macro_inst|cfg_reg_inst|frequency [16]),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|min_vol [0]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [16]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector9~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [16]));
defparam \macro_inst|cfg_reg_inst|prdata[16] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|prdata[16] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[16] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[16] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[16] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[16] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[16] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[16] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[16] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[16] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal9~0 (
// Location: FF_X57_Y11_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[4] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[4] (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\rv32.mem_ahb_hwdata[20] ),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [4]));
defparam \macro_inst|cfg_reg_inst|min_vol[4] .mask = 16'h2200;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|min_vol[4] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|min_vol[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[0] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[16] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [0]));
defparam \macro_inst|cfg_reg_inst|min_vol[0] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[0] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector16~0 (
alta_slice \macro_inst|cfg_reg_inst|Selector16~0 (
	.A(\macro_inst|cfg_reg_inst|frequency [9]),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|max_vol [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector16~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector16~0 .mask = 16'h50DC;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector16~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector16~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector0~0 (
// Location: FF_X57_Y11_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[25] (
alta_slice \macro_inst|cfg_reg_inst|prdata[25] (
	.A(\macro_inst|cfg_reg_inst|frequency [25]),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|min_vol [9]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [25]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [25]));
defparam \macro_inst|cfg_reg_inst|prdata[25] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|prdata[25] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[25] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[25] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[25] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[25] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[25] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[25] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[25] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[25] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector2~0 (
// Location: FF_X57_Y11_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[23] (
alta_slice \macro_inst|cfg_reg_inst|prdata[23] (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|min_vol [7]),
	.C(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.D(\macro_inst|cfg_reg_inst|frequency [23]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [23]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [23]));
defparam \macro_inst|cfg_reg_inst|prdata[23] .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|prdata[23] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[23] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[23] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[23] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[23] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[23] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[23] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[23] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[23] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector6~0 (
// Location: FF_X57_Y11_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[19] (
alta_slice \macro_inst|cfg_reg_inst|prdata[19] (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|min_vol [3]),
	.C(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.D(\macro_inst|cfg_reg_inst|frequency [19]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [19]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector6~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [19]));
defparam \macro_inst|cfg_reg_inst|prdata[19] .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|prdata[19] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[19] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[19] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[19] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[19] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[19] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[19] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[19] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[19] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[3] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[19] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [3]));
defparam \macro_inst|cfg_reg_inst|min_vol[3] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[3] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[3] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[7] (
// Location: LCCOMB_X57_Y11_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|max_vol[7]~2 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[7] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|max_vol[7]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [7]));
defparam \macro_inst|cfg_reg_inst|max_vol[7] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[7] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|max_vol[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector7~0 (
// Location: FF_X57_Y11_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[18] (
alta_slice \macro_inst|cfg_reg_inst|prdata[18] (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|min_vol [2]),
	.D(\macro_inst|cfg_reg_inst|frequency [18]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [18]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector7~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [18]));
defparam \macro_inst|cfg_reg_inst|prdata[18] .mask = 16'hAE0C;
defparam \macro_inst|cfg_reg_inst|prdata[18] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[18] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[18] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[18] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[18] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[18] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[18] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[18] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[18] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[2] (
// Location: LCCOMB_X57_Y11_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|min_vol[2]~1 (
alta_slice \macro_inst|cfg_reg_inst|min_vol[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[18] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [2]));
defparam \macro_inst|cfg_reg_inst|min_vol[2] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|min_vol[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[2] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[7] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[23] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [7]));
defparam \macro_inst|cfg_reg_inst|min_vol[7] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[7] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[7] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[9] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[9] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[25] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[9]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [9]));
defparam \macro_inst|cfg_reg_inst|min_vol[9] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[9] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector5~0 (
// Location: FF_X57_Y11_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[20] (
alta_slice \macro_inst|cfg_reg_inst|prdata[20] (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|min_vol [4]),
	.C(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.D(\macro_inst|cfg_reg_inst|frequency [20]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [20]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector5~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [20]));
defparam \macro_inst|cfg_reg_inst|prdata[20] .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|prdata[20] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[20] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[20] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[20] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[20] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[20] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[20] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[20] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[20] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y11_N0
alta_clkenctrl clken_ctrl_X57_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y11_SIG_SIG ));
defparam clken_ctrl_X57_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y11_N0
alta_asyncctrl asyncreset_ctrl_X57_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ));
defparam asyncreset_ctrl_X57_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y11_N1
alta_clkenctrl clken_ctrl_X57_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y11_SIG_SIG ));
defparam clken_ctrl_X57_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X57_Y11_N0
alta_syncctrl syncreset_ctrl_X57_Y11(.Din(), .Dout(SyncReset_X57_Y11_GND));
defparam syncreset_ctrl_X57_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y11_N1
alta_syncctrl syncload_ctrl_X57_Y11(.Din(), .Dout(SyncLoad_X57_Y11_VCC));
defparam syncload_ctrl_X57_Y11.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y12_N10
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[9]~11 (
alta_slice \macro_inst|ahb2apb_inst|prdata[9]~11 (
	.A(\macro_inst|mem_apb_psel~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [1]),
	.C(\macro_inst|ahb2apb_inst|prdata[9]~10_combout ),
	.D(\macro_inst|ahb2apb_inst|paddr [14]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[9]~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .mask = 16'hD8F0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[9]~11 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[19] (
alta_slice \macro_inst|cfg_reg_inst|frequency[19] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[19] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [19]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[19]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [19]));
defparam \macro_inst|cfg_reg_inst|frequency[19] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[19] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[19] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[19] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[19] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[19] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[19] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[19] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[19] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[19] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[20] (
alta_slice \macro_inst|cfg_reg_inst|frequency[20] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[20] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [20]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[20]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [20]));
defparam \macro_inst|cfg_reg_inst|frequency[20] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[20] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[20] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[20] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[20] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[20] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[20] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[20] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[20] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[20] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y12_N16
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[29]~13 (
alta_slice \macro_inst|ahb2apb_inst|prdata[29]~13 (
	.A(\macro_inst|ahb2apb_inst|paddr [14]),
	.B(\macro_inst|ahb2apb_inst|paddr [1]),
	.C(\macro_inst|mem_apb_psel~0_combout ),
	.D(\macro_inst|ahb2apb_inst|prdata[14]~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .mask = 16'h7F20;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[29]~13 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[8] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[8] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[24] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[8]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [8]));
defparam \macro_inst|cfg_reg_inst|min_vol[8] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[8] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[8] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[24] (
alta_slice \macro_inst|cfg_reg_inst|frequency[24] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[24] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [24]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[24]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [24]));
defparam \macro_inst|cfg_reg_inst|frequency[24] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[24] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[24] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[24] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[24] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[24] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[24] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[24] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[24] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[24] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[6] (
// Location: LCCOMB_X57_Y12_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|min_vol[6]~3 (
alta_slice \macro_inst|cfg_reg_inst|min_vol[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[22] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[6]~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [6]));
defparam \macro_inst|cfg_reg_inst|min_vol[6] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|min_vol[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[6] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[21] (
alta_slice \macro_inst|cfg_reg_inst|frequency[21] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[21] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [21]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[21]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [21]));
defparam \macro_inst|cfg_reg_inst|frequency[21] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[21] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[21] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[21] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[21] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[21] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[21] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[21] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[21] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[21] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[22] (
alta_slice \macro_inst|cfg_reg_inst|frequency[22] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[22] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [22]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[22]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [22]));
defparam \macro_inst|cfg_reg_inst|frequency[22] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[22] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[22] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[22] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[22] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[22] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[22] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[22] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[22] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[22] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y12_N6
// alta_lcell_comb \macro_inst|apb_prdata[10]~0 (
alta_slice \macro_inst|apb_prdata[10]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [14]),
	.B(\macro_inst|ahb2apb_inst|paddr [1]),
	.C(\macro_inst|mem_apb_psel~0_combout ),
	.D(\macro_inst|ahb2apb_inst|prdata[14]~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[10]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_prdata[10]~0 .mask = 16'h207F;
defparam \macro_inst|apb_prdata[10]~0 .mode = "logic";
defparam \macro_inst|apb_prdata[10]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_prdata[10]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_prdata[10]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_prdata[10]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_prdata[10]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_prdata[10]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_prdata[10]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_prdata[10]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[5] (
// Location: LCCOMB_X57_Y12_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|min_vol[5]~2 (
alta_slice \macro_inst|cfg_reg_inst|min_vol[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[21] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[5]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [5]));
defparam \macro_inst|cfg_reg_inst|min_vol[5] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|min_vol[5] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[5] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y12_N0
alta_clkenctrl clken_ctrl_X57_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X57_Y12_SIG_SIG ));
defparam clken_ctrl_X57_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y12_N0
alta_asyncctrl asyncreset_ctrl_X57_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ));
defparam asyncreset_ctrl_X57_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y12_N1
alta_clkenctrl clken_ctrl_X57_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y12_SIG_SIG ));
defparam clken_ctrl_X57_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y12_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X57_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mask = 16'hD8A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mask = 16'hD8A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mask = 16'hBC80;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mask = 16'h3C50;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mask = 16'hACC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mask = 16'hE828;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mask = 16'h286C;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mask = 16'hD8A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~336 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~336 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~334_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [8]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~335_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .mask = 16'h2EE2;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~336 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~60 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~60 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~59_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [9]),
	.C(\macro_inst|apb_dac0_inst|phase_r [8]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~52_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~60_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .mask = 16'h0E02;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~60 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mask = 16'hACC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mask = 16'hACC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux8~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux8~1 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux8~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Add5~2_combout ),
	.D(\macro_inst|apb_dac0_inst|max_vol_r [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux8~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux8~1 .mask = 16'hE6C4;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux8~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux8~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~0 (
alta_slice \macro_inst|apb_dac0_inst|Add5~0 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Add5~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add5~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~2 (
alta_slice \macro_inst|apb_dac0_inst|Add5~2 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~2 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add5~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~4 (
alta_slice \macro_inst|apb_dac0_inst|Add5~4 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add5~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~6 (
alta_slice \macro_inst|apb_dac0_inst|Add5~6 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add5~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .mask = 16'hC0C0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~8 (
alta_slice \macro_inst|apb_dac0_inst|Add5~8 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add5~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~10 (
alta_slice \macro_inst|apb_dac0_inst|Add5~10 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add5~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~12 (
alta_slice \macro_inst|apb_dac0_inst|Add5~12 (
	.A(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add5~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~14 (
alta_slice \macro_inst|apb_dac0_inst|Add5~14 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add5~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~16 (
alta_slice \macro_inst|apb_dac0_inst|Add5~16 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add5~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add5~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add5~18 (
alta_slice \macro_inst|apb_dac0_inst|Add5~18 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.B(\macro_inst|apb_dac0_inst|Mult3|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add5~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add5~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add5~18 .mask = 16'h9696;
defparam \macro_inst|apb_dac0_inst|Add5~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add5~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add5~18 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add5~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add5~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~41 (
alta_slice \macro_inst|apb_dac0_inst|Add2~41 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~41_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~41 .mask = 16'h8B88;
defparam \macro_inst|apb_dac0_inst|Add2~41 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~41 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~41 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~41 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~41 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~41 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~41 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~41 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~41 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~103_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~123_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mask = 16'h3F6A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[11] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N10
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[9] (
// Location: LCCOMB_X57_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~18 (
alta_slice \macro_inst|apb_dac0_inst|phase_r[9] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~17_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [31]),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y3_GND),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~18_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [9]));
defparam \macro_inst|apb_dac0_inst|phase_r[9] .mask = 16'h3C00;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .FeedbackMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~103_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~123_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .mask = 16'hFFEA;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~339 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~339 (
	.A(\macro_inst|apb_dac0_inst|phase_r [9]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~17_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~38_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~339_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .mask = 16'hF6F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~339 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~254_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~260_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .mask = 16'h1E1E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mask = 16'h486A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~254_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~260_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~273_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mask = 16'h1FE0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[11] (
// Location: FF_X57_Y3_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[8] (
alta_slice \macro_inst|apb_dac0_inst|phase_r[8] (
	.A(\macro_inst|apb_dac0_inst|phase_r [9]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~178_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [30]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~152_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y3_GND),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [8]));
defparam \macro_inst|apb_dac0_inst|phase_r[8] .mask = 16'hFF60;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .FeedbackMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[8] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~18_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~38_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .mask = 16'hFEFA;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~339_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mask = 16'h52B0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mask = 16'h0CC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~18_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~38_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mask = 16'h36FA;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .mask = 16'h33CC;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~78_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~339_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mask = 16'h1E78;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~103 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~103 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~102_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~97_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [9]),
	.D(\macro_inst|apb_dac0_inst|phase_r [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~103_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .mask = 16'h00CA;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~103 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~254_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~260_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[2]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~273_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .mask = 16'hFFE0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y3_N0
alta_clkenctrl clken_ctrl_X57_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y3_SIG_VCC ));
defparam clken_ctrl_X57_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y3_N0
alta_asyncctrl asyncreset_ctrl_X57_Y3_N0(.Din(), .Dout(AsyncReset_X57_Y3_GND));
defparam asyncreset_ctrl_X57_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y3_N0
alta_syncctrl syncreset_ctrl_X57_Y3(.Din(), .Dout(SyncReset_X57_Y3_GND));
defparam syncreset_ctrl_X57_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y3_N1
alta_syncctrl syncload_ctrl_X57_Y3(.Din(), .Dout(SyncLoad_X57_Y3_VCC));
defparam syncload_ctrl_X57_Y3.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y4_N0
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[0] (
alta_slice \macro_inst|apb_adc0_inst|apb_db[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|adc_inst.db[0] ),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|apb_db[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [0]));
defparam \macro_inst|apb_adc0_inst|apb_db[0] .mask = 16'hFF00;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[0] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|apb_db[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~5 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan3~5 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.B(\macro_inst|apb_adc0_inst|apb_db [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~5_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~5 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[3] (
// Location: LCCOMB_X57_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~7 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[3] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.B(\macro_inst|apb_adc0_inst|apb_db [3]),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~5_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~7_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [3]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .mask = 16'h004D;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[3] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N14
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[4] (
// Location: LCCOMB_X57_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~9 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[4] (
	.A(\macro_inst|apb_adc0_inst|apb_db [4]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[4] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~7_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~9_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [4]));
defparam \macro_inst|apb_adc0_inst|apb_db[4] .mask = 16'h004D;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[4] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[5] (
// Location: LCCOMB_X57_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~11 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[5] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.B(\macro_inst|apb_adc0_inst|apb_db [5]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~9_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~11_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [5]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .mask = 16'h004D;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[5] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N18
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[6] (
// Location: LCCOMB_X57_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~13 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[6] (
	.A(\macro_inst|apb_adc0_inst|apb_db [6]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[6] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~11_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~13_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [6]));
defparam \macro_inst|apb_adc0_inst|apb_db[6] .mask = 16'h004D;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[6] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[6] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[11] (
// Location: LCCOMB_X57_Y4_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_threshold[11]~1 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[11] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[11]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [11]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[7] (
// Location: LCCOMB_X57_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~15 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[7] (
	.A(\macro_inst|apb_adc0_inst|apb_db [7]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~13_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~15_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [7]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .mask = 16'h002B;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[7] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N22
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[8] (
// Location: LCCOMB_X57_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~17 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[8] (
	.A(\macro_inst|apb_adc0_inst|apb_db [8]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[8] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~15_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~17_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [8]));
defparam \macro_inst|apb_adc0_inst|apb_db[8] .mask = 16'h004D;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[8] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[8] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[9] (
// Location: LCCOMB_X57_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~19 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[9] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.B(\macro_inst|apb_adc0_inst|apb_db [9]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~17_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~19_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [9]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .mask = 16'h004D;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[9] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N26
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[10] (
// Location: LCCOMB_X57_Y4_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~21 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[10] (
	.A(\macro_inst|apb_adc0_inst|apb_db [10]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[10] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~19_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~21_cout ),
	.Q(\macro_inst|apb_adc0_inst|apb_db [10]));
defparam \macro_inst|apb_adc0_inst|apb_db[10] .mask = 16'h004D;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[10] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[10] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N28
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[11] (
// Location: LCCOMB_X57_Y4_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~22 (
alta_slice \macro_inst|apb_adc0_inst|apb_db[11] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|apb_db [11]),
	.C(\macro_inst|apb_adc0_inst|adc_inst.db[11] ),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~21_cout ),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y4_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan3~22_combout ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [11]));
defparam \macro_inst|apb_adc0_inst|apb_db[11] .mask = 16'h30F3;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[11] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_adc0_inst|apb_db[11] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y4_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[1] (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [1]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N4
// alta_lcell_ff \macro_inst|apb_adc0_inst|apb_db[2] (
alta_slice \macro_inst|apb_adc0_inst|apb_db[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|adc_inst.db[2] ),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|apb_db [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|apb_db[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|apb_db [2]));
defparam \macro_inst|apb_adc0_inst|apb_db[2] .mask = 16'hFF00;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|apb_db[2] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|apb_db[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan3~1 (
	.A(\macro_inst|apb_adc0_inst|apb_db [0]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~1_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .mask = 16'h0044;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan3~3 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan3~3 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.B(\macro_inst|apb_adc0_inst|apb_db [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan3~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan3~3_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan3~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y4_N0
alta_clkenctrl clken_ctrl_X57_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|apb_adc0_inst|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|apb_adc0_inst|always1~0_combout_X57_Y4_SIG_SIG ));
defparam clken_ctrl_X57_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y4_N0
alta_asyncctrl asyncreset_ctrl_X57_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ));
defparam asyncreset_ctrl_X57_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y4_N1
alta_clkenctrl clken_ctrl_X57_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X57_Y4_SIG_SIG ));
defparam clken_ctrl_X57_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X57_Y4_N0
alta_syncctrl syncreset_ctrl_X57_Y4(.Din(), .Dout(SyncReset_X57_Y4_GND));
defparam syncreset_ctrl_X57_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y4_N1
alta_syncctrl syncload_ctrl_X57_Y4(.Din(), .Dout(SyncLoad_X57_Y4_VCC));
defparam syncload_ctrl_X57_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y5_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~47 (
alta_slice \macro_inst|apb_dac0_inst|Add2~47 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.B(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux0~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~47_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~47 .mask = 16'hAA30;
defparam \macro_inst|apb_dac0_inst|Add2~47 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~47 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~47 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~47 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~47 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~47 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~47 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~47 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~47 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux0~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux0~1 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [9]),
	.B(\macro_inst|apb_dac0_inst|Mux0~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Add5~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux0~1 .mask = 16'hEC2C;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux0~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~57 (
alta_slice \macro_inst|apb_dac0_inst|Add2~57 (
	.A(\macro_inst|cfg_reg_inst|wave_type [1]),
	.B(\macro_inst|apb_dac0_inst|Add2~42_combout ),
	.C(\macro_inst|apb_dac0_inst|Add2~41_combout ),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~57_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~57 .mask = 16'hF4F0;
defparam \macro_inst|apb_dac0_inst|Add2~57 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~57 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~57 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~57 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~57 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~57 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~57 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~57 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~57 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~23 (
alta_slice \macro_inst|apb_dac0_inst|Add2~23 (
	.A(\macro_inst|apb_dac0_inst|Mux8~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.C(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.D(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~23_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~23 .mask = 16'hC0E2;
defparam \macro_inst|apb_dac0_inst|Add2~23 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~23 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~23 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~23 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~23 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~23 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~23 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~23 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~23 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~29 (
alta_slice \macro_inst|apb_dac0_inst|Add2~29 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux6~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~29_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~29 .mask = 16'hAA30;
defparam \macro_inst|apb_dac0_inst|Add2~29 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~29 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~29 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~29 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~29 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~29 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~29 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~29 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~29 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux6~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux6~1 (
	.A(\macro_inst|apb_dac0_inst|Add5~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux6~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|max_vol_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux6~1 .mask = 16'hBC8C;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux6~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~3 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~3 (
	.A(\macro_inst|cfg_reg_inst|wave_type [1]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~3 .mask = 16'h5500;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~3 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~35 (
alta_slice \macro_inst|apb_dac0_inst|Add2~35 (
	.A(\macro_inst|apb_dac0_inst|Mux4~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.C(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.D(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~35_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~35 .mask = 16'hF022;
defparam \macro_inst|apb_dac0_inst|Add2~35 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~35 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~35 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~35 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~35 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~35 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~35 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~35 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~35 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux0~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux0~0 (
	.A(\macro_inst|apb_dac0_inst|Add4~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Add3~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux0~0 .mask = 16'hCEC2;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux0~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~38 (
alta_slice \macro_inst|apb_dac0_inst|Add2~38 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.B(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux3~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~38_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~38 .mask = 16'hAA30;
defparam \macro_inst|apb_dac0_inst|Add2~38 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~38 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~38 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~38 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~38 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~38 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~38 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~38 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~38 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~56 (
alta_slice \macro_inst|apb_dac0_inst|Add2~56 (
	.A(\macro_inst|cfg_reg_inst|wave_type [1]),
	.B(\macro_inst|apb_dac0_inst|Add2~39_combout ),
	.C(\macro_inst|apb_dac0_inst|Add2~38_combout ),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~56_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~56 .mask = 16'hF4F0;
defparam \macro_inst|apb_dac0_inst|Add2~56 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~56 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~56 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~56 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~56 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~56 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~56 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~56 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~56 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux4~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux4~1 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [5]),
	.B(\macro_inst|apb_dac0_inst|Add5~10_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux4~1 .mask = 16'hCFA0;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux4~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~5 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~5 (
	.A(\macro_inst|apb_dac0_inst|Mux7~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Add5~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Add3~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~5 .mask = 16'hD8AA;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~5 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~5 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y6_N0
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[6] (
// Location: LCCOMB_X57_Y6_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~253 (
alta_slice \macro_inst|apb_dac0_inst|phase_r[6] (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~252_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [28]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~248_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y6_GND),
	.SyncReset(SyncReset_X57_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y6_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~253_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [6]));
defparam \macro_inst|apb_dac0_inst|phase_r[6] .mask = 16'hFF04;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .FeedbackMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y6_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~248 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~248 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~247_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~245_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~248_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .mask = 16'hEEA0;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~248 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~12 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~12 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~11_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .mask = 16'hDC98;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~259 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~259 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~258_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~245_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~259_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .mask = 16'hAABA;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~259 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~247 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~247 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~246_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~247_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .mask = 16'hF7C7;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~247 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~236 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~236 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~236_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .mask = 16'h838F;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~236 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~9 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~9 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|cs2a[1]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .mask = 16'h9C90;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~243 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~243 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~242_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~236_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~243_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .mask = 16'hAC0C;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~243 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y6_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[5] (
// Location: LCCOMB_X57_Y6_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~11 (
alta_slice \macro_inst|apb_dac0_inst|phase_r[5] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~10_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [27]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y6_GND),
	.SyncReset(SyncReset_X57_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y6_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~11_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [5]));
defparam \macro_inst|apb_dac0_inst|phase_r[5] .mask = 16'h3F3F;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .FeedbackMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y6_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~8 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~8 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .mask = 16'hFFEA;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~235 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~235 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~235_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .mask = 16'hF7D7;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~235 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux3~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux3~1 (
	.A(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux3~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Add3~12_combout ),
	.D(\macro_inst|apb_dac0_inst|Add5~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux3~1 .mask = 16'hEC64;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux3~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~234 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~234 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~234_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .mask = 16'h0001;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~234 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~244 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~244 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~234_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~235_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~243_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~244_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .mask = 16'hFF32;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~244 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~258 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~258 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~247_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~257_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~258_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .mask = 16'h1150;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~258 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~10 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~10 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .mask = 16'hC800;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~10 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y6_N0
alta_clkenctrl clken_ctrl_X57_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y6_SIG_VCC ));
defparam clken_ctrl_X57_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y6_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y6_N0
alta_asyncctrl asyncreset_ctrl_X57_Y6_N0(.Din(), .Dout(AsyncReset_X57_Y6_GND));
defparam asyncreset_ctrl_X57_Y6_N0.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y6_N0
alta_syncctrl syncreset_ctrl_X57_Y6(.Din(), .Dout(SyncReset_X57_Y6_GND));
defparam syncreset_ctrl_X57_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y6_N1
alta_syncctrl syncload_ctrl_X57_Y6(.Din(), .Dout(SyncLoad_X57_Y6_VCC));
defparam syncload_ctrl_X57_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y7_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~54 (
alta_slice \macro_inst|apb_dac0_inst|Add2~54 (
	.A(\macro_inst|cfg_reg_inst|wave_type [1]),
	.B(\macro_inst|cfg_reg_inst|wave_type [0]),
	.C(\macro_inst|apb_dac0_inst|Add2~32_combout ),
	.D(\macro_inst|apb_dac0_inst|Add2~33_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~54_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~54 .mask = 16'hF4F0;
defparam \macro_inst|apb_dac0_inst|Add2~54 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~54 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~54 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~54 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~54 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~54 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~54 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~54 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~54 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector14 (
// Location: FF_X57_Y7_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[11] (
alta_slice \macro_inst|cfg_reg_inst|prdata[11] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [11]),
	.C(\macro_inst|cfg_reg_inst|prdata[10]~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector14~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector14~combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [11]));
defparam \macro_inst|cfg_reg_inst|prdata[11] .mask = 16'hCF50;
defparam \macro_inst|cfg_reg_inst|prdata[11] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[11] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[11] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[11] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[11] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[11] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector16~2 (
// Location: FF_X57_Y7_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[9] (
alta_slice \macro_inst|cfg_reg_inst|prdata[9] (
	.A(\macro_inst|cfg_reg_inst|Selector16~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector16~1_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.D(\macro_inst|cfg_reg_inst|trig_auto_timeout [9]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector16~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [9]));
defparam \macro_inst|cfg_reg_inst|prdata[9] .mask = 16'hFEEE;
defparam \macro_inst|cfg_reg_inst|prdata[9] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[9] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector16~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector16~1 (
	.A(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.C(\macro_inst|cfg_reg_inst|trig_pulse_width [9]),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector16~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector16~1 .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector16~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector16~1 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[2] (
// Location: LCCOMB_X57_Y7_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|min_vol_r[2]~0 (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|min_vol [2]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|min_vol_r[2]~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [2]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|min_vol_r[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~32 (
alta_slice \macro_inst|apb_dac0_inst|Add2~32 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.B(\macro_inst|apb_dac0_inst|Mux5~1_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~32_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~32 .mask = 16'hA0AC;
defparam \macro_inst|apb_dac0_inst|Add2~32 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~32 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~32 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux5~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux5~0 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [4]),
	.C(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Add4~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux5~0 .mask = 16'hADA8;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux5~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux5~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata[10]~0 (
alta_slice \macro_inst|cfg_reg_inst|prdata[10]~0 (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata[10]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .mask = 16'h0504;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[9] (
// Location: LCCOMB_X57_Y7_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|max_vol_r[9]~0 (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|max_vol [9]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|max_vol_r[9]~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [9]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .mask = 16'h00FF;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|max_vol_r[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux5~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux5~1 (
	.A(\macro_inst|apb_dac0_inst|Add5~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mux5~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Add3~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux5~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux5~1 .mask = 16'hBC8C;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux5~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux5~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector15 (
// Location: FF_X57_Y7_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[10] (
alta_slice \macro_inst|cfg_reg_inst|prdata[10] (
	.A(\macro_inst|cfg_reg_inst|prdata[10]~0_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [10]),
	.C(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.D(\macro_inst|cfg_reg_inst|Selector15~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector15~combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [10]));
defparam \macro_inst|cfg_reg_inst|prdata[10] .mask = 16'hDDA0;
defparam \macro_inst|cfg_reg_inst|prdata[10] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[10] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y7_N0
alta_clkenctrl clken_ctrl_X57_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y7_SIG_SIG ));
defparam clken_ctrl_X57_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y7_N0
alta_asyncctrl asyncreset_ctrl_X57_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ));
defparam asyncreset_ctrl_X57_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y7_N1
alta_clkenctrl clken_ctrl_X57_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y7_SIG_VCC ));
defparam clken_ctrl_X57_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y7_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y7_N1
alta_asyncctrl asyncreset_ctrl_X57_Y7_N1(.Din(), .Dout(AsyncReset_X57_Y7_GND));
defparam asyncreset_ctrl_X57_Y7_N1.AsyncCtrlMux = 2'b00;
// Location: LCCOMB_X57_Y8_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~0 (
// Location: FF_X57_Y8_N0
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[1] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[1] (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18_combout ),
	.C(\macro_inst|cfg_reg_inst|max_vol [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~1 ),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [1]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~10 (
alta_slice \macro_inst|apb_dac0_inst|Add3~10 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add3~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add3~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add3~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add3~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~12 (
alta_slice \macro_inst|apb_dac0_inst|Add3~12 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add3~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add3~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add3~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add3~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~14 (
// Location: FF_X57_Y8_N14
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[7] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[7] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.C(\macro_inst|cfg_reg_inst|min_vol [7]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~13 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~15 ),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [7]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~16 (
// Location: FF_X57_Y8_N16
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[8] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[8] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.C(\macro_inst|cfg_reg_inst|min_vol [8]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~15 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~17 ),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [8]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[8] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~18 (
// Location: FF_X57_Y8_N18
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[9] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[9] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.C(\macro_inst|cfg_reg_inst|min_vol [9]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Add3~17 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~18_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [9]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .mask = 16'hC33C;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~2 (
// Location: FF_X57_Y8_N2
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[1] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[1] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.C(\macro_inst|cfg_reg_inst|min_vol [1]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~1 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~3 ),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [1]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector8~0 (
// Location: FF_X57_Y8_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[17] (
alta_slice \macro_inst|cfg_reg_inst|prdata[17] (
	.A(\macro_inst|cfg_reg_inst|frequency [17]),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|min_vol [1]),
	.D(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [17]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector8~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [17]));
defparam \macro_inst|cfg_reg_inst|prdata[17] .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|prdata[17] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[17] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[17] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[17] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[17] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[17] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[17] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[17] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[17] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector1~0 (
// Location: FF_X57_Y8_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[24] (
alta_slice \macro_inst|cfg_reg_inst|prdata[24] (
	.A(\macro_inst|cfg_reg_inst|min_vol [8]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.D(\macro_inst|cfg_reg_inst|frequency [24]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [24]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [24]));
defparam \macro_inst|cfg_reg_inst|prdata[24] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|prdata[24] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[24] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[24] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[24] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[24] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[24] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[24] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[24] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[24] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector3~0 (
// Location: FF_X57_Y8_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[22] (
alta_slice \macro_inst|cfg_reg_inst|prdata[22] (
	.A(\macro_inst|cfg_reg_inst|min_vol [6]),
	.B(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.C(\macro_inst|cfg_reg_inst|frequency [22]),
	.D(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [22]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [22]));
defparam \macro_inst|cfg_reg_inst|prdata[22] .mask = 16'hF444;
defparam \macro_inst|cfg_reg_inst|prdata[22] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[22] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[22] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[22] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[22] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[22] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[22] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[22] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[22] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N26
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[0] (
// Location: LCCOMB_X57_Y8_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|min_vol_r[0]~feeder (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|min_vol [0]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|min_vol_r[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [0]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .mask = 16'hFF00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|min_vol_r[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N28
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[6] (
// Location: LCCOMB_X57_Y8_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|min_vol_r[6]~2 (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[6] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|min_vol [6]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|min_vol_r[6]~2_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [6]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|min_vol_r[6] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[5] (
// Location: LCCOMB_X57_Y8_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|min_vol_r[5]~1 (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|min_vol [5]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|min_vol_r[5]~1_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [5]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .mask = 16'h00FF;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|min_vol_r[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~4 (
alta_slice \macro_inst|apb_dac0_inst|Add3~4 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add3~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add3~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add3~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add3~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add3~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add3~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~6 (
// Location: FF_X57_Y8_N6
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[3] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[3] (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24_combout ),
	.C(\macro_inst|cfg_reg_inst|min_vol [3]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~5 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~7 ),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [3]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add3~8 (
// Location: FF_X57_Y8_N8
// alta_lcell_ff \macro_inst|apb_dac0_inst|min_vol_r[4] (
alta_slice \macro_inst|apb_dac0_inst|min_vol_r[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.C(\macro_inst|cfg_reg_inst|min_vol [4]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add3~7 ),
	.Qin(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y8_GND),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|Add3~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add3~9 ),
	.Q(\macro_inst|apb_dac0_inst|min_vol_r [4]));
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|min_vol_r[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y8_N0
alta_clkenctrl clken_ctrl_X57_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y8_SIG_VCC ));
defparam clken_ctrl_X57_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y8_N0
alta_asyncctrl asyncreset_ctrl_X57_Y8_N0(.Din(), .Dout(AsyncReset_X57_Y8_GND));
defparam asyncreset_ctrl_X57_Y8_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X57_Y8_N1
alta_clkenctrl clken_ctrl_X57_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X57_Y8_SIG_SIG ));
defparam clken_ctrl_X57_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y8_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y8_N1
alta_asyncctrl asyncreset_ctrl_X57_Y8_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ));
defparam asyncreset_ctrl_X57_Y8_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X57_Y8_N0
alta_syncctrl syncreset_ctrl_X57_Y8(.Din(), .Dout(SyncReset_X57_Y8_GND));
defparam syncreset_ctrl_X57_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y8_N1
alta_syncctrl syncload_ctrl_X57_Y8(.Din(), .Dout(SyncLoad_X57_Y8_VCC));
defparam syncload_ctrl_X57_Y8.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y9_N0
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[2] (
// Location: LCCOMB_X57_Y9_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|max_vol_r[2]~3 (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|max_vol [2]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|max_vol_r[2]~3_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [2]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|max_vol_r[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~3 (
alta_slice \macro_inst|apb_dac0_inst|LessThan0~3 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~20_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~3_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .mask = 16'h002B;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~5 (
alta_slice \macro_inst|apb_dac0_inst|LessThan0~5 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~22_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~5_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .mask = 16'h004D;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~7 (
alta_slice \macro_inst|apb_dac0_inst|LessThan0~7 (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [3]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~7_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .mask = 16'h004D;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~9 (
// Location: FF_X57_Y9_N16
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[4] (
alta_slice \macro_inst|apb_dac0_inst|phase_r[4] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~26_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_acc [26]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~7_cout ),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~9_cout ),
	.Q(\macro_inst|apb_dac0_inst|phase_r [4]));
defparam \macro_inst|apb_dac0_inst|phase_r[4] .mask = 16'h004D;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_r[4] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y9_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~11 (
// Location: FF_X57_Y9_N18
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[5] (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~28_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [5]),
	.C(\macro_inst|cfg_reg_inst|max_vol [5]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~9_cout ),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~11_cout ),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [5]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .mask = 16'h002B;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[5] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y9_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[8] (
// Location: LCCOMB_X57_Y9_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|max_vol[8]~1 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[8] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[8] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|max_vol[8]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [8]));
defparam \macro_inst|cfg_reg_inst|max_vol[8] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[8] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|max_vol[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~13 (
// Location: FF_X57_Y9_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[0] (
alta_slice \macro_inst|apb_dac0_inst|phase_r[0] (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [6]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~30_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [22]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~11_cout ),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~13_cout ),
	.Q(\macro_inst|apb_dac0_inst|phase_r [0]));
defparam \macro_inst|apb_dac0_inst|phase_r[0] .mask = 16'h002B;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_r[0] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y9_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~15 (
// Location: FF_X57_Y9_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[7] (
alta_slice \macro_inst|apb_dac0_inst|phase_r[7] (
	.A(\macro_inst|apb_dac0_inst|max_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~32_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_acc [29]),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~13_cout ),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~15_cout ),
	.Q(\macro_inst|apb_dac0_inst|phase_r [7]));
defparam \macro_inst|apb_dac0_inst|phase_r[7] .mask = 16'h004D;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_r[7] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y9_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~17 (
// Location: FF_X57_Y9_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[5] (
alta_slice \macro_inst|cfg_reg_inst|max_vol[5] (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~34_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [8]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~15_cout ),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~17_cout ),
	.Q(\macro_inst|cfg_reg_inst|max_vol [5]));
defparam \macro_inst|cfg_reg_inst|max_vol[5] .mask = 16'h004D;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|max_vol[5] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|max_vol[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y9_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~18 (
// Location: FF_X57_Y9_N26
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[1] (
alta_slice \macro_inst|apb_dac0_inst|phase_r[1] (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [9]),
	.C(\macro_inst|apb_dac0_inst|phase_acc [23]),
	.D(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~36_combout ),
	.Cin(\macro_inst|apb_dac0_inst|LessThan0~17_cout ),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(SyncReset_X57_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_VCC),
	.LutOut(\macro_inst|apb_dac0_inst|LessThan0~18_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [1]));
defparam \macro_inst|apb_dac0_inst|phase_r[1] .mask = 16'hC0FC;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_r[1] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .SyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[1] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y9_N28
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[8] (
// Location: LCCOMB_X57_Y9_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|max_vol_r[8]~1 (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[8] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|max_vol [8]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|max_vol_r[8]~1_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [8]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .mask = 16'h00FF;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|max_vol_r[8] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|max_vol_r[7] (
// Location: LCCOMB_X57_Y9_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|max_vol_r[7]~2 (
alta_slice \macro_inst|apb_dac0_inst|max_vol_r[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|max_vol [7]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|max_vol_r [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|max_vol_r[7]~2_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|max_vol_r [7]));
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .mask = 16'h00FF;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|max_vol_r[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N4
// alta_lcell_comb \macro_inst|u_apb2ram|ram_rden~0 (
alta_slice \macro_inst|u_apb2ram|ram_rden~0 (
	.A(\macro_inst|ahb2apb_inst|penable~q ),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|paddr [14]),
	.D(\macro_inst|mem_apb_psel~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb2ram|ram_rden~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_apb2ram|ram_rden~0 .mask = 16'h2000;
defparam \macro_inst|u_apb2ram|ram_rden~0 .mode = "logic";
defparam \macro_inst|u_apb2ram|ram_rden~0 .modeMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_rden~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_rden~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_rden~0 .BypassEn = 1'b0;
defparam \macro_inst|u_apb2ram|ram_rden~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_apb2ram|ram_rden~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_apb2ram|ram_rden~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_apb2ram|ram_rden~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N6
// alta_lcell_comb \macro_inst|u_apb2ram|ram_wren~0 (
alta_slice \macro_inst|u_apb2ram|ram_wren~0 (
	.A(\macro_inst|ahb2apb_inst|penable~q ),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|paddr [14]),
	.D(\macro_inst|mem_apb_psel~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb2ram|ram_wren~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_apb2ram|ram_wren~0 .mask = 16'h8000;
defparam \macro_inst|u_apb2ram|ram_wren~0 .mode = "logic";
defparam \macro_inst|u_apb2ram|ram_wren~0 .modeMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_wren~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_wren~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_apb2ram|ram_wren~0 .BypassEn = 1'b0;
defparam \macro_inst|u_apb2ram|ram_wren~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_apb2ram|ram_wren~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_apb2ram|ram_wren~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_apb2ram|ram_wren~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|LessThan0~1 (
alta_slice \macro_inst|apb_dac0_inst|LessThan0~1 (
	.A(\macro_inst|apb_dac0_inst|Mult2|auto_generated|mac_mult1|auto_generated|mult1|op_5~18_combout ),
	.B(\macro_inst|apb_dac0_inst|max_vol_r [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|LessThan0~1_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .mask = 16'h0044;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|LessThan0~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y9_N0
alta_clkenctrl clken_ctrl_X57_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X57_Y9_SIG_VCC ));
defparam clken_ctrl_X57_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y9_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y9_N0
alta_asyncctrl asyncreset_ctrl_X57_Y9_N0(.Din(), .Dout(AsyncReset_X57_Y9_GND));
defparam asyncreset_ctrl_X57_Y9_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X57_Y9_N1
alta_clkenctrl clken_ctrl_X57_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X57_Y9_SIG_SIG ));
defparam clken_ctrl_X57_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y9_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y9_N1
alta_asyncctrl asyncreset_ctrl_X57_Y9_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ));
defparam asyncreset_ctrl_X57_Y9_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X57_Y9_N0
alta_syncctrl syncreset_ctrl_X57_Y9(.Din(), .Dout(SyncReset_X57_Y9_GND));
defparam syncreset_ctrl_X57_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y9_N1
alta_syncctrl syncload_ctrl_X57_Y9(.Din(), .Dout(SyncLoad_X57_Y9_VCC));
defparam syncload_ctrl_X57_Y9.SyncCtrlMux = 2'b01;
// Location: FF_X58_Y10_N0
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[16] (
// Location: LCCOMB_X58_Y10_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[16]~64 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[16] (
	.A(\macro_inst|cfg_reg_inst|frequency [16]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [16]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[15]~63 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [16]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[16]~64_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[16]~65 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [16]));
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[16] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N10
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[21] (
// Location: LCCOMB_X58_Y10_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[21]~74 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[21] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [21]),
	.B(\macro_inst|cfg_reg_inst|frequency [21]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[20]~73 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [21]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[21]~74_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[21]~75 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [21]));
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[21] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N12
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[22] (
// Location: LCCOMB_X58_Y10_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[22]~76 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[22] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [22]),
	.B(\macro_inst|cfg_reg_inst|frequency [22]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[21]~75 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [22]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[22]~76_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[22]~77 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [22]));
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[22] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N14
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[23] (
// Location: LCCOMB_X58_Y10_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[23]~78 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[23] (
	.A(\macro_inst|cfg_reg_inst|frequency [23]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [23]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[22]~77 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [23]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[23]~78_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[23]~79 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [23]));
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[23] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N16
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[24] (
// Location: LCCOMB_X58_Y10_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[24]~80 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[24] (
	.A(\macro_inst|cfg_reg_inst|frequency [24]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [24]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[23]~79 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [24]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[24]~80_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[24]~81 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [24]));
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[24] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N18
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[25] (
// Location: LCCOMB_X58_Y10_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[25]~82 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[25] (
	.A(\macro_inst|cfg_reg_inst|frequency [25]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [25]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[24]~81 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [25]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[25]~82_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[25]~83 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [25]));
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[25] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N2
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[17] (
// Location: LCCOMB_X58_Y10_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[17]~66 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[17] (
	.A(\macro_inst|cfg_reg_inst|frequency [17]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [17]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[16]~65 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [17]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[17]~66_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[17]~67 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [17]));
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[17] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[26] (
// Location: LCCOMB_X58_Y10_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[26]~84 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[26] (
	.A(\macro_inst|cfg_reg_inst|frequency [26]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [26]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[25]~83 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [26]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[26]~84_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[26]~85 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [26]));
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[26] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[27] (
// Location: LCCOMB_X58_Y10_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[27]~86 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[27] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [27]),
	.B(\macro_inst|cfg_reg_inst|frequency [27]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[26]~85 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [27]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[27]~86_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[27]~87 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [27]));
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[27] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N24
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[28] (
// Location: LCCOMB_X58_Y10_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[28]~88 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[28] (
	.A(\macro_inst|cfg_reg_inst|frequency [28]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [28]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[27]~87 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [28]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[28]~88_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[28]~89 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [28]));
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[28] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N26
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[29] (
// Location: LCCOMB_X58_Y10_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[29]~90 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[29] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [29]),
	.B(\macro_inst|cfg_reg_inst|frequency [29]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[28]~89 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [29]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[29]~90_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[29]~91 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [29]));
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[29] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N28
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[30] (
// Location: LCCOMB_X58_Y10_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[30]~92 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[30] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [30]),
	.B(\macro_inst|cfg_reg_inst|frequency [30]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[29]~91 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [30]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[30]~92_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[30]~93 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [30]));
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[30] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[31] (
// Location: LCCOMB_X58_Y10_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[31]~94 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[31] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [31]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|frequency [31]),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[30]~93 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [31]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[31]~94_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [31]));
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .mask = 16'hA55A;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[31] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N4
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[18] (
// Location: LCCOMB_X58_Y10_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[18]~68 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[18] (
	.A(\macro_inst|cfg_reg_inst|frequency [18]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [18]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[17]~67 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [18]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[18]~68_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[18]~69 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [18]));
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[18] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N6
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[19] (
// Location: LCCOMB_X58_Y10_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[19]~70 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[19] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [19]),
	.B(\macro_inst|cfg_reg_inst|frequency [19]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[18]~69 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [19]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[19]~70_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[19]~71 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [19]));
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[19] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N8
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[20] (
// Location: LCCOMB_X58_Y10_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[20]~72 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[20] (
	.A(\macro_inst|cfg_reg_inst|frequency [20]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [20]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[19]~71 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [20]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[20]~72_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[20]~73 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [20]));
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[20] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X58_Y10_N0
alta_clkenctrl clken_ctrl_X58_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y10_SIG_VCC ));
defparam clken_ctrl_X58_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y10_N0
alta_asyncctrl asyncreset_ctrl_X58_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ));
defparam asyncreset_ctrl_X58_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y10_N0
alta_syncctrl syncreset_ctrl_X58_Y10(.Din(\macro_inst|apb_dac0_inst|always0~0_combout ), .Dout(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y10_SIG ));
defparam syncreset_ctrl_X58_Y10.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y10_N1
alta_syncctrl syncload_ctrl_X58_Y10(.Din(), .Dout(SyncLoad_X58_Y10_GND));
defparam syncload_ctrl_X58_Y10.SyncCtrlMux = 2'b00;
// Location: FF_X58_Y11_N0
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[0] (
// Location: LCCOMB_X58_Y11_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[0]~32 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[0] (
	.A(\macro_inst|cfg_reg_inst|frequency [0]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[0]~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[0]~33 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [0]));
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[0] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N10
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[5] (
// Location: LCCOMB_X58_Y11_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[5]~42 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[5] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [5]),
	.B(\macro_inst|cfg_reg_inst|frequency [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[4]~41 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[5]~42_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[5]~43 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [5]));
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[5] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N12
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[6] (
// Location: LCCOMB_X58_Y11_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[6]~44 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[6] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [6]),
	.B(\macro_inst|cfg_reg_inst|frequency [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[5]~43 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[6]~44_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[6]~45 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [6]));
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[6] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N14
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[7] (
// Location: LCCOMB_X58_Y11_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[7]~46 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[7] (
	.A(\macro_inst|cfg_reg_inst|frequency [7]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[6]~45 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[7]~46_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[7]~47 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [7]));
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[7] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N16
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[8] (
// Location: LCCOMB_X58_Y11_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[8]~48 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[8] (
	.A(\macro_inst|cfg_reg_inst|frequency [8]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[7]~47 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[8]~48_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[8]~49 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [8]));
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .mask = 16'h964D;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[8] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N18
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[9] (
// Location: LCCOMB_X58_Y11_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[9]~50 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[9] (
	.A(\macro_inst|cfg_reg_inst|frequency [9]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[8]~49 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[9]~50_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[9]~51 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [9]));
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[9] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N2
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[1] (
// Location: LCCOMB_X58_Y11_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[1]~34 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[1] (
	.A(\macro_inst|cfg_reg_inst|frequency [1]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[0]~33 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[1]~34_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[1]~35 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [1]));
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[1] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[10] (
// Location: LCCOMB_X58_Y11_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[10]~52 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[10] (
	.A(\macro_inst|cfg_reg_inst|frequency [10]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[9]~51 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[10]~52_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[10]~53 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [10]));
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[10] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[11] (
// Location: LCCOMB_X58_Y11_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[11]~54 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[11] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [11]),
	.B(\macro_inst|cfg_reg_inst|frequency [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[10]~53 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[11]~54_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[11]~55 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [11]));
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[11] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N24
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[12] (
// Location: LCCOMB_X58_Y11_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[12]~56 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[12] (
	.A(\macro_inst|cfg_reg_inst|frequency [12]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [12]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[11]~55 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[12]~56_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[12]~57 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [12]));
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[12] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N26
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[13] (
// Location: LCCOMB_X58_Y11_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[13]~58 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[13] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [13]),
	.B(\macro_inst|cfg_reg_inst|frequency [13]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[12]~57 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[13]~58_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[13]~59 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [13]));
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[13] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N28
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[14] (
// Location: LCCOMB_X58_Y11_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[14]~60 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[14] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [14]),
	.B(\macro_inst|cfg_reg_inst|frequency [14]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[13]~59 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[14]~60_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[14]~61 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [14]));
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[14] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N30
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[15] (
// Location: LCCOMB_X58_Y11_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[15]~62 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[15] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [15]),
	.B(\macro_inst|cfg_reg_inst|frequency [15]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[14]~61 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[15]~62_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[15]~63 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [15]));
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[15] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N4
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[2] (
// Location: LCCOMB_X58_Y11_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[2]~36 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[2] (
	.A(\macro_inst|cfg_reg_inst|frequency [2]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[1]~35 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[2]~36_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[2]~37 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [2]));
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[2] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N6
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[3] (
// Location: LCCOMB_X58_Y11_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[3]~38 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[3] (
	.A(\macro_inst|apb_dac0_inst|phase_acc [3]),
	.B(\macro_inst|cfg_reg_inst|frequency [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[2]~37 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[3]~38_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[3]~39 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [3]));
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[3] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y11_N8
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_acc[4] (
// Location: LCCOMB_X58_Y11_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_acc[4]~40 (
alta_slice \macro_inst|apb_dac0_inst|phase_acc[4] (
	.A(\macro_inst|cfg_reg_inst|frequency [4]),
	.B(\macro_inst|apb_dac0_inst|phase_acc [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|phase_acc[3]~39 ),
	.Qin(\macro_inst|apb_dac0_inst|phase_acc [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ),
	.SyncReset(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_GND),
	.LutOut(\macro_inst|apb_dac0_inst|phase_acc[4]~40_combout ),
	.Cout(\macro_inst|apb_dac0_inst|phase_acc[4]~41 ),
	.Q(\macro_inst|apb_dac0_inst|phase_acc [4]));
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_dac0_inst|phase_acc[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X58_Y11_N0
alta_clkenctrl clken_ctrl_X58_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y11_SIG_VCC ));
defparam clken_ctrl_X58_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y11_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y11_N0
alta_asyncctrl asyncreset_ctrl_X58_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y11_SIG ));
defparam asyncreset_ctrl_X58_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y11_N0
alta_syncctrl syncreset_ctrl_X58_Y11(.Din(\macro_inst|apb_dac0_inst|always0~0_combout ), .Dout(\macro_inst|apb_dac0_inst|always0~0_combout__SyncReset_X58_Y11_SIG ));
defparam syncreset_ctrl_X58_Y11.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y11_N1
alta_syncctrl syncload_ctrl_X58_Y11(.Din(), .Dout(SyncLoad_X58_Y11_GND));
defparam syncload_ctrl_X58_Y11.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X58_Y12_N0
// alta_lcell_comb \macro_inst|ahb2apb_inst|always2~0 (
// Location: FF_X58_Y12_N0
// alta_lcell_ff \macro_inst|ahb2apb_inst|pvalid (
alta_slice \macro_inst|ahb2apb_inst|pvalid (
	.A(\macro_inst|ahb2apb_inst|psel~q ),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.D(\macro_inst|ahb2apb_inst|pdone~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pvalid~q ));
defparam \macro_inst|ahb2apb_inst|pvalid .mask = 16'h0050;
defparam \macro_inst|ahb2apb_inst|pvalid .mode = "logic";
defparam \macro_inst|ahb2apb_inst|pvalid .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pvalid .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|pvalid .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|pvalid .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|pvalid .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N10
// alta_lcell_comb \macro_inst|ahb2apb_inst|Selector0~0 (
// Location: FF_X58_Y12_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|apbState.apbIdle (
alta_slice \macro_inst|ahb2apb_inst|apbState.apbIdle (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|pvalid~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ));
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .mask = 16'hFFCC;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .mode = "logic";
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|apbState.apbIdle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N12
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[9]~10 (
alta_slice \macro_inst|ahb2apb_inst|prdata[9]~10 (
	.A(\macro_inst|pr_select [2]),
	.B(\macro_inst|pr_select [3]),
	.C(\macro_inst|pr_select [1]),
	.D(\macro_inst|pr_select [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[9]~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .mask = 16'hFFED;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[9]~10 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N14
// alta_lcell_ff \macro_inst|ahb2apb_inst|hreadyout (
// Location: LCCOMB_X58_Y12_N14
// alta_lcell_comb \macro_inst|ahb2apb_inst|hreadyout~0 (
alta_slice \macro_inst|ahb2apb_inst|hreadyout (
	.A(\rv32.mem_ahb_htrans[1] ),
	.B(\macro_inst|ahb2apb_inst|hdone~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|pdone~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|hreadyout~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hreadyout~q ));
defparam \macro_inst|ahb2apb_inst|hreadyout .mask = 16'h3AFA;
defparam \macro_inst|ahb2apb_inst|hreadyout .mode = "logic";
defparam \macro_inst|ahb2apb_inst|hreadyout .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hreadyout .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|hreadyout .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|hreadyout .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|hreadyout .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|hreadyout .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N16
// alta_lcell_comb \macro_inst|ahb2apb_inst|Selector25~0 (
// Location: FF_X58_Y12_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|penable (
alta_slice \macro_inst|ahb2apb_inst|penable (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|penable~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|Selector25~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|penable~q ));
defparam \macro_inst|ahb2apb_inst|penable .mask = 16'hFF30;
defparam \macro_inst|ahb2apb_inst|penable .mode = "logic";
defparam \macro_inst|ahb2apb_inst|penable .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|penable .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|penable .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|penable .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|penable .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|penable .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N18
// alta_lcell_ff \macro_inst|ahb2apb_inst|apbState.apbSetup (
// Location: LCCOMB_X58_Y12_N18
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[7]~0 (
alta_slice \macro_inst|ahb2apb_inst|apbState.apbSetup (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[7]~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ));
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .mask = 16'h0F00;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .mode = "logic";
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|apbState.apbSetup .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N2
// alta_lcell_ff \macro_inst|ahb2apb_inst|hdone (
// Location: LCCOMB_X58_Y12_N2
// alta_lcell_comb \macro_inst|ahb2apb_inst|hdone~0 (
alta_slice \macro_inst|ahb2apb_inst|hdone (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|pvalid~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hdone~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|hdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hdone~q ));
defparam \macro_inst|ahb2apb_inst|hdone .mask = 16'hCCC0;
defparam \macro_inst|ahb2apb_inst|hdone .mode = "logic";
defparam \macro_inst|ahb2apb_inst|hdone .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hdone .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|hdone .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|hdone .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|hdone .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|hdone .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N20
// alta_lcell_comb \macro_inst|ShiftLeft0~2 (
// Location: FF_X58_Y12_N20
// alta_lcell_ff \macro_inst|pr_select[0] (
alta_slice \macro_inst|pr_select[0] (
	.A(\macro_inst|ahb2apb_inst|paddr [12]),
	.B(\macro_inst|ahb2apb_inst|paddr [15]),
	.C(\macro_inst|ahb2apb_inst|paddr [13]),
	.D(\macro_inst|ahb2apb_inst|paddr [14]),
	.Cin(),
	.Qin(\macro_inst|pr_select [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|always0~0_combout_X58_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ShiftLeft0~2_combout ),
	.Cout(),
	.Q(\macro_inst|pr_select [0]));
defparam \macro_inst|pr_select[0] .mask = 16'h0001;
defparam \macro_inst|pr_select[0] .mode = "logic";
defparam \macro_inst|pr_select[0] .modeMux = 1'b0;
defparam \macro_inst|pr_select[0] .FeedbackMux = 1'b0;
defparam \macro_inst|pr_select[0] .ShiftMux = 1'b0;
defparam \macro_inst|pr_select[0] .BypassEn = 1'b0;
defparam \macro_inst|pr_select[0] .CarryEnb = 1'b1;
defparam \macro_inst|pr_select[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|pr_select[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|pr_select[0] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N22
// alta_lcell_ff \macro_inst|ahb2apb_inst|psel (
// Location: LCCOMB_X58_Y12_N22
// alta_lcell_comb \macro_inst|ahb2apb_inst|psel~0 (
alta_slice \macro_inst|ahb2apb_inst|psel (
	.A(\macro_inst|ahb2apb_inst|apbState.apbIdle~q ),
	.B(\macro_inst|ahb2apb_inst|pvalid~q ),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|apbState.apbSetup~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|psel~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|psel~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|psel~q ));
defparam \macro_inst|ahb2apb_inst|psel .mask = 16'hF4DC;
defparam \macro_inst|ahb2apb_inst|psel .mode = "logic";
defparam \macro_inst|ahb2apb_inst|psel .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|psel .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|psel .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|psel .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|psel .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|psel .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N24
// alta_lcell_ff \macro_inst|ahb2apb_inst|pdone (
// Location: LCCOMB_X58_Y12_N24
// alta_lcell_comb \macro_inst|ahb2apb_inst|pdone~0 (
alta_slice \macro_inst|ahb2apb_inst|pdone (
	.A(\macro_inst|ahb2apb_inst|psel~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|penable~q ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pdone~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|pdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pdone~q ));
defparam \macro_inst|ahb2apb_inst|pdone .mask = 16'h0A00;
defparam \macro_inst|ahb2apb_inst|pdone .mode = "logic";
defparam \macro_inst|ahb2apb_inst|pdone .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|pdone .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|pdone .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|pdone .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|pdone .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|pdone .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N26
// alta_lcell_comb \macro_inst|always0~0 (
alta_slice \macro_inst|always0~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|psel~q ),
	.D(\macro_inst|ahb2apb_inst|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|always0~0 .mask = 16'h00F0;
defparam \macro_inst|always0~0 .mode = "logic";
defparam \macro_inst|always0~0 .modeMux = 1'b0;
defparam \macro_inst|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N28
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[14]~12 (
alta_slice \macro_inst|ahb2apb_inst|prdata[14]~12 (
	.A(\macro_inst|pr_select [2]),
	.B(\macro_inst|pr_select [3]),
	.C(\macro_inst|pr_select [1]),
	.D(\macro_inst|pr_select [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[14]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .mask = 16'hFFEF;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[14]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N30
// alta_lcell_comb \macro_inst|ahb2apb_inst|comb~0 (
alta_slice \macro_inst|ahb2apb_inst|comb~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|psel~q ),
	.D(\macro_inst|ahb2apb_inst|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|comb~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|comb~0 .mask = 16'hF000;
defparam \macro_inst|ahb2apb_inst|comb~0 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|comb~0 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|comb~0 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|comb~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|comb~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|comb~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N4
// alta_lcell_ff \macro_inst|pr_select[2] (
alta_slice \macro_inst|pr_select[2] (
	.A(),
	.B(),
	.C(\macro_inst|ShiftLeft0~1_combout ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|pr_select [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|always0~0_combout_X58_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y12_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|pr_select [2]));
defparam \macro_inst|pr_select[2] .mask = 16'hFFFF;
defparam \macro_inst|pr_select[2] .mode = "ripple";
defparam \macro_inst|pr_select[2] .modeMux = 1'b1;
defparam \macro_inst|pr_select[2] .FeedbackMux = 1'b0;
defparam \macro_inst|pr_select[2] .ShiftMux = 1'b0;
defparam \macro_inst|pr_select[2] .BypassEn = 1'b1;
defparam \macro_inst|pr_select[2] .CarryEnb = 1'b1;
defparam \macro_inst|pr_select[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|pr_select[2] .SyncResetMux = 2'b00;
defparam \macro_inst|pr_select[2] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y12_N6
// alta_lcell_ff \macro_inst|pr_select[1] (
// Location: LCCOMB_X58_Y12_N6
// alta_lcell_comb \~GND (
alta_slice \macro_inst|pr_select[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|ShiftLeft0~0_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|pr_select [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|always0~0_combout_X58_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y12_VCC),
	.LutOut(\~GND~combout ),
	.Cout(),
	.Q(\macro_inst|pr_select [1]));
defparam \macro_inst|pr_select[1] .mask = 16'h0000;
defparam \macro_inst|pr_select[1] .mode = "logic";
defparam \macro_inst|pr_select[1] .modeMux = 1'b0;
defparam \macro_inst|pr_select[1] .FeedbackMux = 1'b0;
defparam \macro_inst|pr_select[1] .ShiftMux = 1'b0;
defparam \macro_inst|pr_select[1] .BypassEn = 1'b1;
defparam \macro_inst|pr_select[1] .CarryEnb = 1'b1;
defparam \macro_inst|pr_select[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|pr_select[1] .SyncResetMux = 2'b00;
defparam \macro_inst|pr_select[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y12_N8
// alta_lcell_comb \macro_inst|ShiftLeft0~3 (
// Location: FF_X58_Y12_N8
// alta_lcell_ff \macro_inst|pr_select[3] (
alta_slice \macro_inst|pr_select[3] (
	.A(\macro_inst|ahb2apb_inst|paddr [12]),
	.B(\macro_inst|ahb2apb_inst|paddr [15]),
	.C(\macro_inst|ahb2apb_inst|paddr [13]),
	.D(\macro_inst|ahb2apb_inst|paddr [14]),
	.Cin(),
	.Qin(\macro_inst|pr_select [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|always0~0_combout_X58_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ShiftLeft0~3_combout ),
	.Cout(),
	.Q(\macro_inst|pr_select [3]));
defparam \macro_inst|pr_select[3] .mask = 16'h0020;
defparam \macro_inst|pr_select[3] .mode = "logic";
defparam \macro_inst|pr_select[3] .modeMux = 1'b0;
defparam \macro_inst|pr_select[3] .FeedbackMux = 1'b0;
defparam \macro_inst|pr_select[3] .ShiftMux = 1'b0;
defparam \macro_inst|pr_select[3] .BypassEn = 1'b0;
defparam \macro_inst|pr_select[3] .CarryEnb = 1'b1;
defparam \macro_inst|pr_select[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|pr_select[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|pr_select[3] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y12_N0
alta_clkenctrl clken_ctrl_X58_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X58_Y12_SIG_VCC ));
defparam clken_ctrl_X58_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y12_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y12_N0
alta_asyncctrl asyncreset_ctrl_X58_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ));
defparam asyncreset_ctrl_X58_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y12_N1
alta_clkenctrl clken_ctrl_X58_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|always0~0_combout_X58_Y12_SIG_SIG ));
defparam clken_ctrl_X58_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y12_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y12_N0
alta_syncctrl syncreset_ctrl_X58_Y12(.Din(), .Dout(SyncReset_X58_Y12_GND));
defparam syncreset_ctrl_X58_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y12_N1
alta_syncctrl syncload_ctrl_X58_Y12(.Din(), .Dout(SyncLoad_X58_Y12_VCC));
defparam syncload_ctrl_X58_Y12.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .mask = 16'h3C3F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mask = 16'h1AB0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mask = 16'h606C;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mask = 16'h2878;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[5]~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[10]~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|~QUARTUS_CREATED_GND~I_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~33 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .mask = 16'hA55A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .mask = 16'hA0A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[6]~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mask = 16'h8800;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .mask = 16'hA0A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .mask = 16'hA0A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs2a[3]~5_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~336_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mask = 16'hE828;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [5]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[8]~16_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[9]~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mask = 16'h7878;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mask = 16'h606A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mask = 16'h4788;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .mask = 16'h5A5F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mask = 16'h1BA0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[1]~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[2]~4_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [0]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[3]~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[4]~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mask = 16'h606A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mask = 16'h52A2;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[3] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y4_N0
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[4] (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [4]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~9 (
// Location: FF_X58_Y4_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[4] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[4] (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [4]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~8_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~7_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~9_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [4]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~11 (
// Location: FF_X58_Y4_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[1] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[1] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [5]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~11_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~9_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~11_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [1]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~13 (
// Location: FF_X58_Y4_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[2] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[2] (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [6]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~10_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~11_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~13_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [2]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~15 (
// Location: FF_X58_Y4_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[6] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[6] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [7]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~6_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~13_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~15_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [6]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[6] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y4_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[8] (
// Location: LCCOMB_X58_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~17 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[8] (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [8]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~15_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~17_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [8]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .mask = 16'h002B;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[8] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~1 (
// Location: FF_X58_Y4_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[9] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[9] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [0]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~3_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~1_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [9]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .mask = 16'h0044;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~19 (
// Location: FF_X58_Y4_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[3] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[3] (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [9]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~9_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~17_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~19_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [3]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[3] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y4_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[10] (
// Location: LCCOMB_X58_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~21 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[10] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [10]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~19_cout ),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~21_cout ),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [10]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .mask = 16'h004D;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[10] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~22 (
// Location: FF_X58_Y4_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[0] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[0] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~12_combout ),
	.D(\macro_inst|trig_ctrl_inst|adc_data_prev [11]),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~21_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan4~22_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [0]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .mask = 16'hFAA0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[0] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y4_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[0] (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [0]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[0] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y4_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[6] (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [6]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[6] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y4_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_threshold[2] (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_threshold [2]));
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~3 (
// Location: FF_X58_Y4_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[7] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[7] (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [1]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~5_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~1_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~3_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [7]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~5 (
// Location: FF_X58_Y4_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[5] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[5] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [2]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~7_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~3_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~5_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [5]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan4~7 (
// Location: FF_X58_Y4_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[8] (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[8] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [3]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~4_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan4~5_cout ),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan4~7_cout ),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [8]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[8] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X58_Y4_N0
alta_clkenctrl clken_ctrl_X58_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout_X58_Y4_SIG_SIG ));
defparam clken_ctrl_X58_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y4_N0
alta_asyncctrl asyncreset_ctrl_X58_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ));
defparam asyncreset_ctrl_X58_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y4_N1
alta_clkenctrl clken_ctrl_X58_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X58_Y4_SIG_SIG ));
defparam clken_ctrl_X58_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y4_N0
alta_syncctrl syncreset_ctrl_X58_Y4(.Din(), .Dout(SyncReset_X58_Y4_GND));
defparam syncreset_ctrl_X58_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y4_N1
alta_syncctrl syncload_ctrl_X58_Y4(.Din(), .Dout(SyncLoad_X58_Y4_VCC));
defparam syncload_ctrl_X58_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y5_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~51 (
alta_slice \macro_inst|apb_dac0_inst|Add2~51 (
	.A(\macro_inst|apb_dac0_inst|Add2~24_combout ),
	.B(\macro_inst|cfg_reg_inst|wave_type [0]),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|apb_dac0_inst|Add2~23_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~51_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~51 .mask = 16'hFF08;
defparam \macro_inst|apb_dac0_inst|Add2~51 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~51 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~51 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~51 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~51 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~51 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~51 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~51 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~51 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~30 (
alta_slice \macro_inst|apb_dac0_inst|Add2~30 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~28 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add2~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~33 (
alta_slice \macro_inst|apb_dac0_inst|Add2~33 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [4]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~33_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~34 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~33 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add2~33 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~33 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~33 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~33 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~33 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~33 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~33 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~33 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~33 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~36 (
alta_slice \macro_inst|apb_dac0_inst|Add2~36 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~34 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~36_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~37 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~36 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add2~36 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~36 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~36 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~36 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~36 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~36 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~39 (
alta_slice \macro_inst|apb_dac0_inst|Add2~39 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~37 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~39_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~40 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~39 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add2~39 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~39 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~39 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~39 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~39 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~39 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~39 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~39 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~39 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~42 (
alta_slice \macro_inst|apb_dac0_inst|Add2~42 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [7]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~40 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~42_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~43 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~42 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add2~42 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~42 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~42 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~42 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~42 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~42 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~42 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~42 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~42 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~52 (
alta_slice \macro_inst|apb_dac0_inst|Add2~52 (
	.A(\macro_inst|apb_dac0_inst|Add2~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Add2~27_combout ),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~52_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~52 .mask = 16'hAEAA;
defparam \macro_inst|apb_dac0_inst|Add2~52 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~52 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~52 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~52 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~52 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~52 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~52 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~52 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~52 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~45 (
alta_slice \macro_inst|apb_dac0_inst|Add2~45 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~43 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~45_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~46 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~45 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add2~45 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~45 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~45 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~45 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~45 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~45 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~45 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~45 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~45 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~48 (
alta_slice \macro_inst|apb_dac0_inst|Add2~48 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [9]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Add2~46 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~48_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~48 .mask = 16'hA55A;
defparam \macro_inst|apb_dac0_inst|Add2~48 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~48 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~48 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~48 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~48 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~48 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~48 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~48 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~48 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~53 (
alta_slice \macro_inst|apb_dac0_inst|Add2~53 (
	.A(\macro_inst|apb_dac0_inst|Add2~30_combout ),
	.B(\macro_inst|cfg_reg_inst|wave_type [0]),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|apb_dac0_inst|Add2~29_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~53_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~53 .mask = 16'hFF08;
defparam \macro_inst|apb_dac0_inst|Add2~53 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~53 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~53 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~53 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~53 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~53 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~53 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~53 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~53 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~26 (
alta_slice \macro_inst|apb_dac0_inst|Add2~26 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.B(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux7~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~26_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~26 .mask = 16'hA3A0;
defparam \macro_inst|apb_dac0_inst|Add2~26 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~26 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~26 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~55 (
alta_slice \macro_inst|apb_dac0_inst|Add2~55 (
	.A(\macro_inst|apb_dac0_inst|Add2~35_combout ),
	.B(\macro_inst|apb_dac0_inst|Add2~36_combout ),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~55_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~55 .mask = 16'hAEAA;
defparam \macro_inst|apb_dac0_inst|Add2~55 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~55 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~55 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~55 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~55 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~55 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~55 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~55 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~55 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~59 (
alta_slice \macro_inst|apb_dac0_inst|Add2~59 (
	.A(\macro_inst|apb_dac0_inst|Add2~48_combout ),
	.B(\macro_inst|cfg_reg_inst|wave_type [0]),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|apb_dac0_inst|Add2~47_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~59_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~59 .mask = 16'hFF08;
defparam \macro_inst|apb_dac0_inst|Add2~59 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~59 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~59 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~59 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~59 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~59 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~59 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~59 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~59 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~21 (
alta_slice \macro_inst|apb_dac0_inst|Add2~21 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~21_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~22 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~21 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Add2~21 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~21 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~21 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~21 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~21 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~21 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~24 (
alta_slice \macro_inst|apb_dac0_inst|Add2~24 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~22 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~24 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Add2~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~27 (
alta_slice \macro_inst|apb_dac0_inst|Add2~27 (
	.A(\macro_inst|apb_dac0_inst|min_vol_r [2]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Add2~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~27_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Add2~28 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~27 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Add2~27 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Add2~27 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~27 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~27 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~27 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~27 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~27 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] (
// Location: LCCOMB_X58_Y6_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~12 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~12_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~13 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [0]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .mask = 16'h33CC;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] (
// Location: LCCOMB_X58_Y6_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~22 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~21 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~23 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [5]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[5] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] (
// Location: LCCOMB_X58_Y6_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~24 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[5]~23 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~25 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [6]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[6] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] (
// Location: LCCOMB_X58_Y6_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~26 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[6]~25 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~26_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~27 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [7]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] (
// Location: LCCOMB_X58_Y6_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~28 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~27 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~28_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~29 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [8]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[8] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] (
// Location: LCCOMB_X58_Y6_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[9]~30 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt [9]),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[8]~29 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[9]~30_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [9]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .mask = 16'h0FF0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[9] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] (
// Location: LCCOMB_X58_Y6_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~14 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[0]~13 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~14_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~15 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [1]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[1] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X58_Y6_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .mask = 16'hEFCF;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~1 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~1 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|auto_wait_cnt [7]),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .mask = 16'hF000;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 (
	.A(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.D(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .mask = 16'hFF5D;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~2 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~2 (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt [5]),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [8]),
	.C(\macro_inst|trig_ctrl_inst|auto_wait_cnt [4]),
	.D(\macro_inst|trig_ctrl_inst|trig_hit_comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~0 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~0 (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt [3]),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [0]),
	.C(\macro_inst|trig_ctrl_inst|auto_wait_cnt [2]),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] (
// Location: LCCOMB_X58_Y6_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~16 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[1]~15 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~16_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~17 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [2]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] (
// Location: LCCOMB_X58_Y6_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~18 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[2]~17 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~19 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [3]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y6_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] (
// Location: LCCOMB_X58_Y6_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~20 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|auto_wait_cnt[3]~19 ),
	.Qin(\macro_inst|trig_ctrl_inst|auto_wait_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[4]~21 ),
	.Q(\macro_inst|trig_ctrl_inst|auto_wait_cnt [4]));
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X58_Y6_N1
alta_clkenctrl clken_ctrl_X58_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35_combout_X58_Y6_SIG_SIG ));
defparam clken_ctrl_X58_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y6_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y6_N1
alta_asyncctrl asyncreset_ctrl_X58_Y6_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ));
defparam asyncreset_ctrl_X58_Y6_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y6_N0
alta_syncctrl syncreset_ctrl_X58_Y6(.Din(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout ), .Dout(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~36_combout__SyncReset_X58_Y6_SIG ));
defparam syncreset_ctrl_X58_Y6.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y6_N1
alta_syncctrl syncload_ctrl_X58_Y6(.Din(), .Dout(SyncLoad_X58_Y6_GND));
defparam syncload_ctrl_X58_Y6.SyncCtrlMux = 2'b00;
// Location: FF_X58_Y7_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[0] (
// Location: LCCOMB_X58_Y7_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[0]~19 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[0] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[0]~19_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[0]~20 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [0]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .mask = 16'h33CC;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[5] (
// Location: LCCOMB_X58_Y7_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[5]~29 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[5] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[4]~28 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[5]~29_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[5]~30 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [5]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[5] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[6] (
// Location: LCCOMB_X58_Y7_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[6]~31 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[6] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[5]~30 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[6]~31_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[6]~32 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [6]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[6] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[7] (
// Location: LCCOMB_X58_Y7_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[7]~33 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[6]~32 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[7]~33_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[7]~34 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [7]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[7] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[8] (
// Location: LCCOMB_X58_Y7_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[8]~35 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[8] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[7]~34 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[8]~35_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[8]~36 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [8]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[8] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[9] (
// Location: LCCOMB_X58_Y7_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[9]~37 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[9] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[8]~36 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[9]~37_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[9]~38 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [9]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[9] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[1] (
// Location: LCCOMB_X58_Y7_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[1]~21 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[1] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[0]~20 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[1]~21_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[1]~22 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [1]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[10] (
// Location: LCCOMB_X58_Y7_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[10]~39 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[10] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[9]~38 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[10]~39_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[10]~40 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [10]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[10] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[11] (
// Location: LCCOMB_X58_Y7_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[11]~41 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[11] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [11]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[10]~40 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[11]~41_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[11]~42 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [11]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[11] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[12] (
// Location: LCCOMB_X58_Y7_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~43 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [12]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[11]~42 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~43_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~44 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [12]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[13] (
// Location: LCCOMB_X58_Y7_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[13]~45 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[13] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [13]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~44 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[13]~45_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[13]~46 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [13]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[13] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[14] (
// Location: LCCOMB_X58_Y7_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[14]~47 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[14] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [14]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[13]~46 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[14]~47_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[14]~48 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [14]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[14] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[15] (
// Location: LCCOMB_X58_Y7_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[15]~49 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[15] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [15]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[14]~48 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[15]~49_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [15]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .mask = 16'h5A5A;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[15] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[2] (
// Location: LCCOMB_X58_Y7_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[2]~23 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[1]~22 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[2]~23_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[2]~24 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [2]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[3] (
// Location: LCCOMB_X58_Y7_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[3]~25 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[3] (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[2]~24 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[3]~25_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[3]~26 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [3]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y7_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_cnt[4] (
// Location: LCCOMB_X58_Y7_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[4]~27 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|pulse_cnt[3]~26 ),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[4]~27_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|pulse_cnt[4]~28 ),
	.Q(\macro_inst|trig_ctrl_inst|pulse_cnt [4]));
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X58_Y7_N1
alta_clkenctrl clken_ctrl_X58_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout_X58_Y7_SIG_SIG ));
defparam clken_ctrl_X58_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y7_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y7_N1
alta_asyncctrl asyncreset_ctrl_X58_Y7_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ));
defparam asyncreset_ctrl_X58_Y7_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y7_N0
alta_syncctrl syncreset_ctrl_X58_Y7(.Din(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout ), .Dout(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout__SyncReset_X58_Y7_SIG ));
defparam syncreset_ctrl_X58_Y7.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y7_N1
alta_syncctrl syncload_ctrl_X58_Y7(.Din(), .Dout(SyncLoad_X58_Y7_GND));
defparam syncload_ctrl_X58_Y7.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X58_Y8_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux9~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux9~1 (
	.A(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Add5~0_combout ),
	.C(\macro_inst|apb_dac0_inst|Add3~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux9~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux9~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux9~1 .mask = 16'hDDA0;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux9~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux9~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~20 (
alta_slice \macro_inst|apb_dac0_inst|Add2~20 (
	.A(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [0]),
	.C(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux9~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~20_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~20 .mask = 16'h8D88;
defparam \macro_inst|apb_dac0_inst|Add2~20 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~20 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~20 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~20 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|min_vol[1] (
alta_slice \macro_inst|cfg_reg_inst|min_vol[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[17] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|min_vol [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X58_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|min_vol[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|min_vol [1]));
defparam \macro_inst|cfg_reg_inst|min_vol[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|min_vol[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|min_vol[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux6~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux6~0 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Add3~6_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Add4~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux6~0 .mask = 16'hE5E0;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux6~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~1 (
	.A(\macro_inst|cfg_reg_inst|max_vol [1]),
	.B(\macro_inst|cfg_reg_inst|wave_type [1]),
	.C(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~1 .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~2 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~2 .mask = 16'hFF0F;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~50 (
alta_slice \macro_inst|apb_dac0_inst|Add2~50 (
	.A(\macro_inst|apb_dac0_inst|Add2~20_combout ),
	.B(\macro_inst|apb_dac0_inst|Add2~21_combout ),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~50_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~50 .mask = 16'hAEAA;
defparam \macro_inst|apb_dac0_inst|Add2~50 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~50 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~50 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~50 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~50 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~50 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~50 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~50 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~50 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|wave_type[0] (
alta_slice \macro_inst|cfg_reg_inst|wave_type[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|wave_type[1]~0_combout_X58_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|wave_type[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|wave_type [0]));
defparam \macro_inst|cfg_reg_inst|wave_type[0] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|wave_type[0] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|wave_type[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~0 (
	.A(\macro_inst|apb_dac0_inst|phase_r [9]),
	.B(\macro_inst|apb_dac0_inst|LessThan0~18_combout ),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~0 .mask = 16'h002A;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux1~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux1~1 (
	.A(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Add5~16_combout ),
	.C(\macro_inst|apb_dac0_inst|Add3~16_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux1~1 .mask = 16'hDDA0;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux1~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~44 (
alta_slice \macro_inst|apb_dac0_inst|Add2~44 (
	.A(\macro_inst|apb_dac0_inst|Mux7~3_combout ),
	.B(\macro_inst|apb_dac0_inst|min_vol_r [8]),
	.C(\macro_inst|apb_dac0_inst|Mux7~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mux1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~44_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~44 .mask = 16'hC5C0;
defparam \macro_inst|apb_dac0_inst|Add2~44 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~44 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~44 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~44 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~44 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~44 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~44 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~44 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~44 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux8~0 (
alta_slice \macro_inst|apb_dac0_inst|Mux8~0 (
	.A(\macro_inst|apb_dac0_inst|Mux7~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Add4~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Add3~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux8~0 .mask = 16'hF4A4;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux8~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mux7~1 (
alta_slice \macro_inst|apb_dac0_inst|Mux7~1 (
	.A(\macro_inst|apb_dac0_inst|phase_r [9]),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|wave_type [1]),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mux7~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mux7~1 .mask = 16'hF050;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mux7~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mux7~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|wave_type[1] (
alta_slice \macro_inst|cfg_reg_inst|wave_type[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|wave_type [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|wave_type[1]~0_combout_X58_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|wave_type[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|wave_type [1]));
defparam \macro_inst|cfg_reg_inst|wave_type[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|wave_type[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|wave_type[1] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[1] (
alta_slice \macro_inst|cfg_reg_inst|max_vol[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X58_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|max_vol[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [1]));
defparam \macro_inst|cfg_reg_inst|max_vol[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|max_vol[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|max_vol[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Add2~58 (
alta_slice \macro_inst|apb_dac0_inst|Add2~58 (
	.A(\macro_inst|apb_dac0_inst|Add2~44_combout ),
	.B(\macro_inst|cfg_reg_inst|wave_type [1]),
	.C(\macro_inst|apb_dac0_inst|Add2~45_combout ),
	.D(\macro_inst|cfg_reg_inst|wave_type [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Add2~58_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Add2~58 .mask = 16'hBAAA;
defparam \macro_inst|apb_dac0_inst|Add2~58 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Add2~58 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~58 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~58 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~58 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Add2~58 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Add2~58 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~58 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Add2~58 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y8_N0
alta_clkenctrl clken_ctrl_X58_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X58_Y8_SIG_SIG ));
defparam clken_ctrl_X58_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y8_N0
alta_asyncctrl asyncreset_ctrl_X58_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ));
defparam asyncreset_ctrl_X58_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y8_N1
alta_clkenctrl clken_ctrl_X58_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|wave_type[1]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|wave_type[1]~0_combout_X58_Y8_SIG_SIG ));
defparam clken_ctrl_X58_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y8_N1.ClkEnMux = 2'b10;
// Location: FF_X58_Y9_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[5] (
// Location: LCCOMB_X58_Y9_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[5]~5 (
alta_slice \macro_inst|cfg_reg_inst|frequency[5] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[5]~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [5]));
defparam \macro_inst|cfg_reg_inst|frequency[5] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|frequency[5] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[5] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[5] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[5] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[17] (
alta_slice \macro_inst|cfg_reg_inst|frequency[17] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[17] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [17]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[17]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [17]));
defparam \macro_inst|cfg_reg_inst|frequency[17] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[17] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[17] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[17] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[17] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[17] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[17] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[17] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[17] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[17] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~0 (
alta_slice \macro_inst|cfg_reg_inst|Selector20~0 (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.C(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.D(\macro_inst|cfg_reg_inst|frequency [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector20~0 .mask = 16'hC0EA;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector20~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~2 (
// Location: FF_X58_Y9_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[5] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[5] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [5]),
	.B(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(SyncReset_X58_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y9_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [5]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[5] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y9_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[15] (
alta_slice \macro_inst|cfg_reg_inst|frequency[15] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[15] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[15]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [15]));
defparam \macro_inst|cfg_reg_inst|frequency[15] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[15] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[15] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[15] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[15] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[15] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[15] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[15] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector18~3 (
// Location: FF_X58_Y9_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[7] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[7] (
	.A(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|cfg_reg_inst|max_vol [7]),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(SyncReset_X58_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y9_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector18~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [7]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .mask = 16'hC0EA;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y9_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector15~0 (
alta_slice \macro_inst|cfg_reg_inst|Selector15~0 (
	.A(\macro_inst|cfg_reg_inst|prdata[10]~2_combout ),
	.B(\macro_inst|cfg_reg_inst|frequency [10]),
	.C(\macro_inst|cfg_reg_inst|trig_auto_timeout [10]),
	.D(\macro_inst|cfg_reg_inst|prdata[10]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector15~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector15~0 .mask = 16'h8DAA;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector15~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector15~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[11] (
alta_slice \macro_inst|cfg_reg_inst|frequency[11] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[11]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [11]));
defparam \macro_inst|cfg_reg_inst|frequency[11] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[11] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[11] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[11] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[11] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[11] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[11] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[11] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[10] (
// Location: LCCOMB_X58_Y9_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_auto_timeout[10]~1 (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[10] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[10] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_auto_timeout[10]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [10]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector17~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector17~1 (
	.A(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.B(\macro_inst|cfg_reg_inst|frequency [8]),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|max_vol [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector17~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector17~1 .mask = 16'h30BA;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector17~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector17~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[8] (
// Location: LCCOMB_X58_Y9_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[8]~2 (
alta_slice \macro_inst|cfg_reg_inst|frequency[8] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[8]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [8]));
defparam \macro_inst|cfg_reg_inst|frequency[8] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|frequency[8] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[8] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[8] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[8] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[8] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[0] (
alta_slice \macro_inst|cfg_reg_inst|frequency[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [0]));
defparam \macro_inst|cfg_reg_inst|frequency[0] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[0] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[0] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector14~0 (
// Location: FF_X58_Y9_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[11] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[11] (
	.A(\macro_inst|cfg_reg_inst|prdata[10]~2_combout ),
	.B(\macro_inst|cfg_reg_inst|frequency [11]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|cfg_reg_inst|prdata[10]~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(SyncReset_X58_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y9_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector14~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [11]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .mask = 16'hD8AA;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[11] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y9_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[10] (
alta_slice \macro_inst|cfg_reg_inst|frequency[10] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[10] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[10]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [10]));
defparam \macro_inst|cfg_reg_inst|frequency[10] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[10] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[10] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[10] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[10] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[10] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[10] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[10] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y9_N0
alta_clkenctrl clken_ctrl_X58_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X58_Y9_SIG_SIG ));
defparam clken_ctrl_X58_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y9_N0
alta_asyncctrl asyncreset_ctrl_X58_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ));
defparam asyncreset_ctrl_X58_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y9_N1
alta_clkenctrl clken_ctrl_X58_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X58_Y9_SIG_SIG ));
defparam clken_ctrl_X58_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y9_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y9_N0
alta_syncctrl syncreset_ctrl_X58_Y9(.Din(), .Dout(SyncReset_X58_Y9_GND));
defparam syncreset_ctrl_X58_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y9_N1
alta_syncctrl syncload_ctrl_X58_Y9(.Din(), .Dout(SyncLoad_X58_Y9_VCC));
defparam syncload_ctrl_X58_Y9.SyncCtrlMux = 2'b01;
// Location: FF_X59_Y10_N0
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[8] (
alta_slice \macro_inst|ahb2apb_inst|haddr[8] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[8] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[8]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [8]));
defparam \macro_inst|ahb2apb_inst|haddr[8] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[8] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[8] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[8] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[8] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[8] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[8] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[8] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[0] (
// Location: LCCOMB_X59_Y10_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal0~1 (
alta_slice \macro_inst|ahb2apb_inst|paddr[0] (
	.A(\macro_inst|ahb2apb_inst|paddr [7]),
	.B(\macro_inst|ahb2apb_inst|paddr [1]),
	.C(\macro_inst|ahb2apb_inst|haddr [0]),
	.D(\macro_inst|ahb2apb_inst|paddr [6]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(SyncReset_X59_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [0]));
defparam \macro_inst|ahb2apb_inst|paddr[0] .mask = 16'h0001;
defparam \macro_inst|ahb2apb_inst|paddr[0] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[0] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[0] .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[0] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[0] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[0] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[0] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[0] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y10_N12
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[9] (
alta_slice \macro_inst|ahb2apb_inst|paddr[9] (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|haddr [9]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(SyncReset_X59_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y10_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [9]));
defparam \macro_inst|ahb2apb_inst|paddr[9] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|paddr[9] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|paddr[9] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[9] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[9] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[9] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[9] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[9] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[9] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y10_N14
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[11] (
// Location: LCCOMB_X59_Y10_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal0~0 (
alta_slice \macro_inst|ahb2apb_inst|paddr[11] (
	.A(\macro_inst|ahb2apb_inst|paddr [9]),
	.B(\macro_inst|ahb2apb_inst|paddr [10]),
	.C(\macro_inst|ahb2apb_inst|haddr [11]),
	.D(\macro_inst|ahb2apb_inst|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(SyncReset_X59_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [11]));
defparam \macro_inst|ahb2apb_inst|paddr[11] .mask = 16'h0001;
defparam \macro_inst|ahb2apb_inst|paddr[11] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[11] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[11] .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[11] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[11] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[11] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[11] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[11] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y10_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[10] (
alta_slice \macro_inst|ahb2apb_inst|paddr[10] (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|haddr [10]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(SyncReset_X59_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y10_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [10]));
defparam \macro_inst|ahb2apb_inst|paddr[10] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|paddr[10] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|paddr[10] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[10] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[10] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[10] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[10] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[10] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[10] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y10_N18
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[8] (
// Location: LCCOMB_X59_Y10_N18
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[8]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[8] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [8]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[8]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [8]));
defparam \macro_inst|ahb2apb_inst|paddr[8] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[8] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[8] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[8] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[8] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[8] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[8] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[8] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N2
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[1] (
alta_slice \macro_inst|ahb2apb_inst|haddr[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[1] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [1]));
defparam \macro_inst|ahb2apb_inst|haddr[1] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[1] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[1] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[1] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[1] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[1] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[1] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N20
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[6] (
alta_slice \macro_inst|ahb2apb_inst|haddr[6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[6] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [6]));
defparam \macro_inst|ahb2apb_inst|haddr[6] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[6] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[6] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[6] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[6] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[6] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[6] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[6] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N22
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[9] (
alta_slice \macro_inst|ahb2apb_inst|haddr[9] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[9] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[9]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [9]));
defparam \macro_inst|ahb2apb_inst|haddr[9] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[9] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[9] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[9] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[9] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[9] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[9] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[9] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N24
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[1] (
// Location: LCCOMB_X59_Y10_N24
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[1]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [1]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [1]));
defparam \macro_inst|ahb2apb_inst|paddr[1] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[1] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[1] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[1] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[1] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[1] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[1] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N26
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[10] (
alta_slice \macro_inst|ahb2apb_inst|haddr[10] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[10] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[10]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [10]));
defparam \macro_inst|ahb2apb_inst|haddr[10] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[10] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[10] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[10] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[10] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[10] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[10] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[10] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N28
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[6] (
// Location: LCCOMB_X59_Y10_N28
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[6]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [6]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [6]));
defparam \macro_inst|ahb2apb_inst|paddr[6] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[6] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[6] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[6] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[6] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[6] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[6] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[6] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N30
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[7] (
alta_slice \macro_inst|ahb2apb_inst|haddr[7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[7] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [7]));
defparam \macro_inst|ahb2apb_inst|haddr[7] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[7] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[7] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[7] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[7] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[7] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[7] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[11] (
alta_slice \macro_inst|ahb2apb_inst|haddr[11] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[11] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[11]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [11]));
defparam \macro_inst|ahb2apb_inst|haddr[11] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[11] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[11] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[11] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[11] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[11] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[11] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[11] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N6
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[7] (
alta_slice \macro_inst|ahb2apb_inst|paddr[7] (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|haddr [7]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(SyncReset_X59_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y10_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [7]));
defparam \macro_inst|ahb2apb_inst|paddr[7] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|paddr[7] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|paddr[7] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[7] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[7] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[7] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[7] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[7] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y10_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[0] (
alta_slice \macro_inst|ahb2apb_inst|haddr[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[0] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [0]));
defparam \macro_inst|ahb2apb_inst|haddr[0] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[0] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[0] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[0] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[0] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[0] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[0] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y10_N0
alta_clkenctrl clken_ctrl_X59_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y10_SIG_SIG ));
defparam clken_ctrl_X59_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y10_N0
alta_asyncctrl asyncreset_ctrl_X59_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ));
defparam asyncreset_ctrl_X59_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y10_N1
alta_clkenctrl clken_ctrl_X59_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|paddr[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y10_SIG_SIG ));
defparam clken_ctrl_X59_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y10_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y10_N0
alta_syncctrl syncreset_ctrl_X59_Y10(.Din(), .Dout(SyncReset_X59_Y10_GND));
defparam syncreset_ctrl_X59_Y10.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y10_N1
alta_syncctrl syncload_ctrl_X59_Y10(.Din(), .Dout(SyncLoad_X59_Y10_VCC));
defparam syncload_ctrl_X59_Y10.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y11_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~0 (
// Location: FF_X59_Y11_N0
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[3] (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[3] (
	.A(\macro_inst|cfg_reg_inst|frequency [3]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [3]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .mask = 16'hF444;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|duty_cycle[3] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y11_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[1] (
// Location: LCCOMB_X59_Y11_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|duty_cycle[1]~1 (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|duty_cycle[1]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [1]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|duty_cycle[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[6] (
// Location: LCCOMB_X59_Y11_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[6]~4 (
alta_slice \macro_inst|cfg_reg_inst|frequency[6] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[6]~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [6]));
defparam \macro_inst|cfg_reg_inst|frequency[6] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|frequency[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[6] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~0 (
// Location: FF_X59_Y11_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[0] (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[0] (
	.A(\macro_inst|cfg_reg_inst|wave_type [0]),
	.B(\macro_inst|cfg_reg_inst|Equal8~0_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [0]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~0 (
// Location: FF_X59_Y11_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[2] (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[2] (
	.A(\macro_inst|cfg_reg_inst|frequency [2]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [2]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|duty_cycle[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal11~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal11~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal11~0 .mask = 16'hA000;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal11~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal11~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[5] (
// Location: LCCOMB_X59_Y11_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|duty_cycle[5]~3 (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|duty_cycle[5]~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [5]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|duty_cycle[5] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[1] (
alta_slice \macro_inst|cfg_reg_inst|frequency[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [1]));
defparam \macro_inst|cfg_reg_inst|frequency[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector18~0 (
// Location: FF_X59_Y11_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[7] (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[7] (
	.A(\macro_inst|cfg_reg_inst|frequency [7]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector18~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [7]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .mask = 16'hF444;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|duty_cycle[7] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y11_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[4] (
// Location: LCCOMB_X59_Y11_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|duty_cycle[4]~2 (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[4] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|duty_cycle[4]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [4]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|duty_cycle[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~0 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~0 (
	.A(\macro_inst|cfg_reg_inst|duty_cycle [1]),
	.B(\macro_inst|cfg_reg_inst|frequency [1]),
	.C(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~0 .mask = 16'hD5C0;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[3] (
// Location: LCCOMB_X59_Y11_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[3]~6 (
alta_slice \macro_inst|cfg_reg_inst|frequency[3] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[3]~6_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [3]));
defparam \macro_inst|cfg_reg_inst|frequency[3] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|frequency[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|duty_cycle[0]~0 (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[0]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .mask = 16'h8000;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|duty_cycle[0]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[2] (
alta_slice \macro_inst|cfg_reg_inst|frequency[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [2]));
defparam \macro_inst|cfg_reg_inst|frequency[2] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[2] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[2] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[2] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[7] (
// Location: LCCOMB_X59_Y11_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|frequency[7]~3 (
alta_slice \macro_inst|cfg_reg_inst|frequency[7] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[7]~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [7]));
defparam \macro_inst|cfg_reg_inst|frequency[7] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|frequency[7] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|frequency[7] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[7] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector19~0 (
// Location: FF_X59_Y11_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|duty_cycle[6] (
alta_slice \macro_inst|cfg_reg_inst|duty_cycle[6] (
	.A(\macro_inst|cfg_reg_inst|frequency [6]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|duty_cycle [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector19~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|duty_cycle [6]));
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .mask = 16'hF444;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|duty_cycle[6] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y11_N0
alta_clkenctrl clken_ctrl_X59_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|duty_cycle[0]~0_combout_X59_Y11_SIG_SIG ));
defparam clken_ctrl_X59_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y11_N0
alta_asyncctrl asyncreset_ctrl_X59_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y11_SIG ));
defparam asyncreset_ctrl_X59_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y11_N1
alta_clkenctrl clken_ctrl_X59_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y11_SIG_SIG ));
defparam clken_ctrl_X59_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y11_N0
alta_syncctrl syncreset_ctrl_X59_Y11(.Din(), .Dout(SyncReset_X59_Y11_GND));
defparam syncreset_ctrl_X59_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y11_N1
alta_syncctrl syncload_ctrl_X59_Y11(.Din(), .Dout(SyncLoad_X59_Y11_VCC));
defparam syncload_ctrl_X59_Y11.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y12_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|always1~2 (
alta_slice \macro_inst|cfg_reg_inst|always1~2 (
	.A(\macro_inst|ahb2apb_inst|penable~q ),
	.B(\macro_inst|ahb2apb_inst|psel~q ),
	.C(\macro_inst|ahb2apb_inst|pwrite~q ),
	.D(\macro_inst|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|always1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|always1~2 .mask = 16'h0400;
defparam \macro_inst|cfg_reg_inst|always1~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|always1~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|always1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|always1~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|always1~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|always1~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|always1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|always1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|always1~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N12
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[13] (
alta_slice \macro_inst|ahb2apb_inst|paddr[13] (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|haddr [13]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [13]));
defparam \macro_inst|ahb2apb_inst|paddr[13] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|paddr[13] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|paddr[13] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[13] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[13] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[13] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[13] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[13] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[13] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y12_N14
// alta_lcell_comb \macro_inst|mem_apb_psel (
alta_slice \macro_inst|mem_apb_psel (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|paddr [14]),
	.C(vcc),
	.D(\macro_inst|mem_apb_psel~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|mem_apb_psel~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|mem_apb_psel .mask = 16'hCC00;
defparam \macro_inst|mem_apb_psel .mode = "logic";
defparam \macro_inst|mem_apb_psel .modeMux = 1'b0;
defparam \macro_inst|mem_apb_psel .FeedbackMux = 1'b0;
defparam \macro_inst|mem_apb_psel .ShiftMux = 1'b0;
defparam \macro_inst|mem_apb_psel .BypassEn = 1'b0;
defparam \macro_inst|mem_apb_psel .CarryEnb = 1'b1;
defparam \macro_inst|mem_apb_psel .AsyncResetMux = 2'bxx;
defparam \macro_inst|mem_apb_psel .SyncResetMux = 2'bxx;
defparam \macro_inst|mem_apb_psel .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[15] (
// Location: LCCOMB_X59_Y12_N16
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[15]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[15] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [15]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[15]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [15]));
defparam \macro_inst|ahb2apb_inst|paddr[15] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[15] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[15] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[15] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[15] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N18
// alta_lcell_comb \macro_inst|ShiftLeft0~0 (
alta_slice \macro_inst|ShiftLeft0~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [13]),
	.B(\macro_inst|ahb2apb_inst|paddr [15]),
	.C(\macro_inst|ahb2apb_inst|paddr [14]),
	.D(\macro_inst|ahb2apb_inst|paddr [12]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ShiftLeft0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ShiftLeft0~0 .mask = 16'h0100;
defparam \macro_inst|ShiftLeft0~0 .mode = "logic";
defparam \macro_inst|ShiftLeft0~0 .modeMux = 1'b0;
defparam \macro_inst|ShiftLeft0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ShiftLeft0~0 .ShiftMux = 1'b0;
defparam \macro_inst|ShiftLeft0~0 .BypassEn = 1'b0;
defparam \macro_inst|ShiftLeft0~0 .CarryEnb = 1'b1;
defparam \macro_inst|ShiftLeft0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ShiftLeft0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|ShiftLeft0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N2
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[12] (
alta_slice \macro_inst|ahb2apb_inst|haddr[12] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[12] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[12]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [12]));
defparam \macro_inst|ahb2apb_inst|haddr[12] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[12] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[12] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[12] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[12] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[12] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[12] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[12] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N20
// alta_lcell_comb \macro_inst|ahb2apb_inst|always0~0 (
alta_slice \macro_inst|ahb2apb_inst|always0~0 (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_htrans[1] ),
	.D(\macro_inst|ahb2apb_inst|hreadyout~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ahb2apb_inst|always0~0 .mask = 16'h00F0;
defparam \macro_inst|ahb2apb_inst|always0~0 .mode = "logic";
defparam \macro_inst|ahb2apb_inst|always0~0 .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N22
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[13] (
alta_slice \macro_inst|ahb2apb_inst|haddr[13] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[13] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[13]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [13]));
defparam \macro_inst|ahb2apb_inst|haddr[13] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[13] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[13] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[13] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[13] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[13] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[13] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[13] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N24
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[15] (
alta_slice \macro_inst|ahb2apb_inst|haddr[15] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_haddr[15] ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|haddr[15]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [15]));
defparam \macro_inst|ahb2apb_inst|haddr[15] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|haddr[15] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|haddr[15] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[15] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[15] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|haddr[15] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N26
// alta_lcell_comb \macro_inst|ShiftLeft0~1 (
alta_slice \macro_inst|ShiftLeft0~1 (
	.A(\macro_inst|ahb2apb_inst|paddr [13]),
	.B(\macro_inst|ahb2apb_inst|paddr [15]),
	.C(\macro_inst|ahb2apb_inst|paddr [14]),
	.D(\macro_inst|ahb2apb_inst|paddr [12]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ShiftLeft0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|ShiftLeft0~1 .mask = 16'h0002;
defparam \macro_inst|ShiftLeft0~1 .mode = "logic";
defparam \macro_inst|ShiftLeft0~1 .modeMux = 1'b0;
defparam \macro_inst|ShiftLeft0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|ShiftLeft0~1 .ShiftMux = 1'b0;
defparam \macro_inst|ShiftLeft0~1 .BypassEn = 1'b0;
defparam \macro_inst|ShiftLeft0~1 .CarryEnb = 1'b1;
defparam \macro_inst|ShiftLeft0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|ShiftLeft0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|ShiftLeft0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N28
// alta_lcell_comb \macro_inst|mem_apb_psel~0 (
alta_slice \macro_inst|mem_apb_psel~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [12]),
	.B(\macro_inst|ahb2apb_inst|psel~q ),
	.C(\macro_inst|ahb2apb_inst|paddr [15]),
	.D(\macro_inst|ahb2apb_inst|paddr [13]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|mem_apb_psel~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|mem_apb_psel~0 .mask = 16'h0400;
defparam \macro_inst|mem_apb_psel~0 .mode = "logic";
defparam \macro_inst|mem_apb_psel~0 .modeMux = 1'b0;
defparam \macro_inst|mem_apb_psel~0 .FeedbackMux = 1'b0;
defparam \macro_inst|mem_apb_psel~0 .ShiftMux = 1'b0;
defparam \macro_inst|mem_apb_psel~0 .BypassEn = 1'b0;
defparam \macro_inst|mem_apb_psel~0 .CarryEnb = 1'b1;
defparam \macro_inst|mem_apb_psel~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|mem_apb_psel~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|mem_apb_psel~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always11~2 (
alta_slice \macro_inst|trig_ctrl_inst|always11~2 (
	.A(\macro_inst|ShiftLeft0~1_combout ),
	.B(\macro_inst|ahb2apb_inst|pwrite~q ),
	.C(\macro_inst|ahb2apb_inst|penable~q ),
	.D(\macro_inst|ahb2apb_inst|psel~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always11~2 .mask = 16'h0200;
defparam \macro_inst|trig_ctrl_inst|always11~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always11~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|pwrite (
// Location: LCCOMB_X59_Y12_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|always0~0 (
alta_slice \macro_inst|ahb2apb_inst|pwrite (
	.A(\macro_inst|ahb2apb_inst|penable~q ),
	.B(\macro_inst|ahb2apb_inst|psel~q ),
	.C(\macro_inst|ahb2apb_inst|hwrite~q ),
	.D(\macro_inst|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|pwrite~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|pwrite~q ));
defparam \macro_inst|ahb2apb_inst|pwrite .mask = 16'h8000;
defparam \macro_inst|ahb2apb_inst|pwrite .mode = "logic";
defparam \macro_inst|ahb2apb_inst|pwrite .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|pwrite .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|pwrite .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|pwrite .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|pwrite .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|pwrite .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|pwrite .SyncLoadMux = 2'b01;
// Location: FF_X59_Y12_N6
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[12] (
// Location: LCCOMB_X59_Y12_N6
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[12]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[12] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [12]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[12]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [12]));
defparam \macro_inst|ahb2apb_inst|paddr[12] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[12] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[12] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[12] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[12] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[12] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[12] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[12] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|hwrite (
alta_slice \macro_inst|ahb2apb_inst|hwrite (
	.A(),
	.B(),
	.C(\rv32.mem_ahb_hwrite ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|hwrite~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|hwrite~q ));
defparam \macro_inst|ahb2apb_inst|hwrite .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|hwrite .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|hwrite .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|hwrite .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hwrite .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|hwrite .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|hwrite .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|hwrite .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|hwrite .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|hwrite .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y12_N0
alta_clkenctrl clken_ctrl_X59_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|paddr[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X59_Y12_SIG_SIG ));
defparam clken_ctrl_X59_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y12_N0
alta_asyncctrl asyncreset_ctrl_X59_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ));
defparam asyncreset_ctrl_X59_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y12_N1
alta_clkenctrl clken_ctrl_X59_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X59_Y12_SIG_SIG ));
defparam clken_ctrl_X59_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y12_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y12_N0
alta_syncctrl syncreset_ctrl_X59_Y12(.Din(), .Dout(SyncReset_X59_Y12_GND));
defparam syncreset_ctrl_X59_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y12_N1
alta_syncctrl syncload_ctrl_X59_Y12(.Din(), .Dout(SyncLoad_X59_Y12_VCC));
defparam syncload_ctrl_X59_Y12.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mask = 16'h468A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mask = 16'h468A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|sine_rom~338_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .mask = 16'hF000;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mask = 16'h53A0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mask = 16'h5A30;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mask = 16'h486A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] (
	.A(\macro_inst|apb_dac0_inst|diff[5]~10_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [6]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[2]~4_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mask = 16'h2788;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] (
	.A(\macro_inst|apb_dac0_inst|diff[3]~6_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[4]~8_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mask = 16'h3C50;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[3]~2_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mask = 16'h88AA;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~282 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~282 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~282_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .mask = 16'h4C48;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~282 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~284 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~284 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~284_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .mask = 16'hB3C0;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~284 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~285 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~285 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~283_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~280_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~284_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~285_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .mask = 16'hAE26;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~285 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~288 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~288 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~288_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .mask = 16'hA5A4;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~288 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~281 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~281 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~281_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .mask = 16'hF878;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~281 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~287 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~287 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~287_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .mask = 16'hD7BA;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~287 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~289 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~289 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~288_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~287_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~289_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .mask = 16'hA4AE;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~289 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~280 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~280 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~280_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .mask = 16'h0082;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~280 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~283 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~283 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~281_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~282_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~283_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .mask = 16'hF50C;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~283 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y3_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[0] (
// Location: LCCOMB_X59_Y3_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[0]~18 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[0] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[0]~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[0]~19 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [0]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .mask = 16'h33CC;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[5] (
// Location: LCCOMB_X59_Y3_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[5]~28 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[5] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[4]~27 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[5]~28_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[5]~29 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [5]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[5] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[6] (
// Location: LCCOMB_X59_Y3_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[6]~30 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[6] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[5]~29 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[6]~30_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[6]~31 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [6]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[6] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[7] (
// Location: LCCOMB_X59_Y3_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[7]~32 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[6]~31 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[7]~32_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[7]~33 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [7]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[7] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[8] (
// Location: LCCOMB_X59_Y3_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[8]~34 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[8] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[7]~33 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~34_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~35 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [8]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[9] (
// Location: LCCOMB_X59_Y3_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[9]~36 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[9] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~35 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[9]~36_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[9]~37 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [9]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[9] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[1] (
// Location: LCCOMB_X59_Y3_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[1]~20 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[1] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[0]~19 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[1]~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[1]~21 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [1]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[10] (
// Location: LCCOMB_X59_Y3_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[10]~38 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[10] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[9]~37 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[10]~38_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[10]~39 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [10]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[10] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[11] (
// Location: LCCOMB_X59_Y3_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[11]~40 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[11] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [11]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[10]~39 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[11]~40_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[11]~41 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [11]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[11] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[12] (
// Location: LCCOMB_X59_Y3_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[12]~42 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[12] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [12]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[11]~41 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[12]~42_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[12]~43 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [12]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[12] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[13] (
// Location: LCCOMB_X59_Y3_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[13]~44 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[13] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [13]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[12]~43 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[13]~44_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[13]~45 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [13]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[13] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[14] (
// Location: LCCOMB_X59_Y3_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[14]~46 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[14] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [14]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[13]~45 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[14]~46_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[14]~47 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [14]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[14] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[15] (
// Location: LCCOMB_X59_Y3_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[15]~48 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[15] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [15]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[14]~47 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[15]~48_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [15]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .mask = 16'h5A5A;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[15] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[2] (
// Location: LCCOMB_X59_Y3_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[2]~22 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[1]~21 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[2]~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[2]~23 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [2]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[3] (
// Location: LCCOMB_X59_Y3_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[3]~24 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[3] (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[2]~23 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[3]~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[3]~25 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [3]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y3_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|eoc_cnt[4] (
// Location: LCCOMB_X59_Y3_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[4]~26 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|eoc_cnt[3]~25 ),
	.Qin(\macro_inst|trig_ctrl_inst|eoc_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[4]~26_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|eoc_cnt[4]~27 ),
	.Q(\macro_inst|trig_ctrl_inst|eoc_cnt [4]));
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X59_Y3_N1
alta_clkenctrl clken_ctrl_X59_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout_X59_Y3_SIG_SIG ));
defparam clken_ctrl_X59_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y3_N1
alta_asyncctrl asyncreset_ctrl_X59_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ));
defparam asyncreset_ctrl_X59_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y3_N0
alta_syncctrl syncreset_ctrl_X59_Y3(.Din(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout ), .Dout(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout__SyncReset_X59_Y3_SIG ));
defparam syncreset_ctrl_X59_Y3.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y3_N1
alta_syncctrl syncload_ctrl_X59_Y3(.Din(), .Dout(SyncLoad_X59_Y3_GND));
defparam syncload_ctrl_X59_Y3.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X59_Y4_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~12 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~12 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(vcc),
	.C(\macro_inst|apb_adc0_inst|apb_db [0]),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .mask = 16'hF050;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~5 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~5 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [2]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~5_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~7 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~7 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [3]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~7_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~9 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~9 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~9_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~11 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~11 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [5]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~11_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~13 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~13 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [6]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~13_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~13 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y4_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[11] (
// Location: LCCOMB_X59_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~11 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[11] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|apb_adc0_inst|apb_db [1]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~0_combout ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X59_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ),
	.SyncReset(SyncReset_X59_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y4_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~11_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [11]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .mask = 16'hCC44;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[11] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~15 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~15 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~15_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~17 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~17 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [8]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~17_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~19 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~19 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [9]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~19_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~21 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~21 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [10]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~21_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~22 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~22 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [11]),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [11]),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~21_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan2~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .mask = 16'h30F3;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~22 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y4_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_data_prev[10] (
// Location: LCCOMB_X59_Y4_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~6 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[10] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|apb_adc0_inst|apb_db [6]),
	.C(\macro_inst|trig_ctrl_inst|adc_data_prev~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_data_prev [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X59_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ),
	.SyncReset(SyncReset_X59_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y4_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~6_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_data_prev [10]));
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .mask = 16'hCC44;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|edge_trigger~3 (
alta_slice \macro_inst|trig_ctrl_inst|edge_trigger~3 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|LessThan2~22_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|LessThan3~22_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|edge_trigger~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .mask = 16'h00CC;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~1 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.B(\macro_inst|trig_ctrl_inst|adc_data_prev [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~1_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .mask = 16'h0022;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan2~3 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan2~3 (
	.A(\macro_inst|trig_ctrl_inst|adc_data_prev [1]),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan2~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan2~3_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan2~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y4_N0
alta_clkenctrl clken_ctrl_X59_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout_X59_Y4_SIG_SIG ));
defparam clken_ctrl_X59_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y4_N0
alta_asyncctrl asyncreset_ctrl_X59_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ));
defparam asyncreset_ctrl_X59_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y4_N0
alta_syncctrl syncreset_ctrl_X59_Y4(.Din(), .Dout(SyncReset_X59_Y4_GND));
defparam syncreset_ctrl_X59_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y4_N1
alta_syncctrl syncload_ctrl_X59_Y4(.Din(), .Dout(SyncLoad_X59_Y4_VCC));
defparam syncload_ctrl_X59_Y4.SyncCtrlMux = 2'b01;
// Location: FF_X59_Y5_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] (
// Location: LCCOMB_X59_Y5_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~11 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~11_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~12 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [0]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .mask = 16'h33CC;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[0] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] (
// Location: LCCOMB_X59_Y5_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~26 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] (
	.A(\macro_inst|trig_ctrl_inst|gap_cnt_auto [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~25 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~26_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~27 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [5]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[5] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] (
// Location: LCCOMB_X59_Y5_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~28 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] (
	.A(\macro_inst|trig_ctrl_inst|gap_cnt_auto [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[5]~27 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~28_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~29 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [6]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[6] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] (
// Location: LCCOMB_X59_Y5_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~30 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[6]~29 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~30_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~31 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [7]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[7] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] (
// Location: LCCOMB_X59_Y5_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~32 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[7]~31 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~32_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~33 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [8]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[8] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] (
// Location: LCCOMB_X59_Y5_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~34 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[8]~33 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~34_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~35 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [9]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[9] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] (
// Location: LCCOMB_X59_Y5_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~18 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[0]~12 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~19 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [1]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[1] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] (
// Location: LCCOMB_X59_Y5_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[10]~36 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto [10]),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[9]~35 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[10]~36_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [10]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .mask = 16'hF00F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[10] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X59_Y5_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 (
	.A(\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ),
	.B(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .mask = 16'hC8FF;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 (
	.A(\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ),
	.B(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.C(\macro_inst|trig_ctrl_inst|pulse_trigger~q ),
	.D(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .mask = 16'hFCF8;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan7~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan7~1 (
	.A(\macro_inst|trig_ctrl_inst|gap_cnt_auto [5]),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [4]),
	.C(\macro_inst|trig_ctrl_inst|gap_cnt_auto [7]),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan7~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .mask = 16'h7FFF;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 (
	.A(\macro_inst|trig_ctrl_inst|sample_valid~combout ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.C(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13_combout ),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .mask = 16'hFAF8;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan7~0 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan7~0 (
	.A(\macro_inst|trig_ctrl_inst|gap_cnt_auto [3]),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [0]),
	.C(\macro_inst|trig_ctrl_inst|gap_cnt_auto [2]),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan7~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .mask = 16'h7FFF;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y5_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] (
// Location: LCCOMB_X59_Y5_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~20 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[1]~19 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~21 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [2]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] (
// Location: LCCOMB_X59_Y5_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~22 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] (
	.A(\macro_inst|trig_ctrl_inst|gap_cnt_auto [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~21 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~23 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [3]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[3] .SyncLoadMux = 2'b00;
// Location: FF_X59_Y5_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] (
// Location: LCCOMB_X59_Y5_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~24 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|gap_cnt_auto[3]~23 ),
	.Qin(\macro_inst|trig_ctrl_inst|gap_cnt_auto [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[4]~25 ),
	.Q(\macro_inst|trig_ctrl_inst|gap_cnt_auto [4]));
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X59_Y5_N1
alta_clkenctrl clken_ctrl_X59_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~17_combout_X59_Y5_SIG_SIG ));
defparam clken_ctrl_X59_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y5_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y5_N1
alta_asyncctrl asyncreset_ctrl_X59_Y5_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ));
defparam asyncreset_ctrl_X59_Y5_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y5_N0
alta_syncctrl syncreset_ctrl_X59_Y5(.Din(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout ), .Dout(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~15_combout__SyncReset_X59_Y5_SIG ));
defparam syncreset_ctrl_X59_Y5.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y5_N1
alta_syncctrl syncload_ctrl_X59_Y5(.Din(), .Dout(SyncLoad_X59_Y5_GND));
defparam syncload_ctrl_X59_Y5.SyncCtrlMux = 2'b00;
// Location: FF_X59_Y6_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_time_slot[0] (
// Location: LCCOMB_X59_Y6_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_time_slot[0]~0 (
alta_slice \macro_inst|cfg_reg_inst|trig_time_slot[0] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_time_slot[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_time_slot [0]));
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector17~0 (
// Location: FF_X59_Y6_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[8] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[8] (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(SyncReset_X59_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector17~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [8]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[8] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y6_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_mode[1] (
alta_slice \macro_inst|cfg_reg_inst|trig_mode[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_mode [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_mode[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_mode [1]));
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_mode[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_time_slot[4] (
alta_slice \macro_inst|cfg_reg_inst|trig_time_slot[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[8] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_time_slot[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_time_slot [4]));
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 (
	.A(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.B(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.C(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .mask = 16'hBFBB;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 (
	.A(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_run~q ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~33_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .mask = 16'h00C4;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~3 (
// Location: FF_X59_Y6_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[4] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[4] (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(SyncReset_X59_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [4]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .mask = 16'hF222;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y6_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~3 (
// Location: FF_X59_Y6_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[3] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[3] (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_mode [1]),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(SyncReset_X59_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [3]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[3] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y6_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_mode[0] (
alta_slice \macro_inst|cfg_reg_inst|trig_mode[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_mode [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_mode[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_mode [0]));
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_mode[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 (
alta_slice \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_mode [1]),
	.C(\macro_inst|cfg_reg_inst|trig_mode [0]),
	.D(\macro_inst|trig_ctrl_inst|LessThan7~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .mask = 16'hFFFC;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~32 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y6_N0
alta_clkenctrl clken_ctrl_X59_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_mode[1]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X59_Y6_SIG_SIG ));
defparam clken_ctrl_X59_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y6_N0
alta_asyncctrl asyncreset_ctrl_X59_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ));
defparam asyncreset_ctrl_X59_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y6_N1
alta_clkenctrl clken_ctrl_X59_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X59_Y6_SIG_SIG ));
defparam clken_ctrl_X59_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y6_N0
alta_syncctrl syncreset_ctrl_X59_Y6(.Din(), .Dout(SyncReset_X59_Y6_GND));
defparam syncreset_ctrl_X59_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y6_N1
alta_syncctrl syncload_ctrl_X59_Y6(.Din(), .Dout(SyncLoad_X59_Y6_VCC));
defparam syncload_ctrl_X59_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y7_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 (
	.A(\macro_inst|trig_ctrl_inst|pulse_level~q ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~55_combout ),
	.C(\macro_inst|trig_ctrl_inst|LessThan5~22_combout ),
	.D(\macro_inst|trig_ctrl_inst|LessThan3~22_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .mask = 16'h048C;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~18 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y7_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_level (
// Location: LCCOMB_X59_Y7_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_level~3 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_level (
	.A(\macro_inst|trig_ctrl_inst|pulse_level~4_combout ),
	.B(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|pulse_level~2_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_level~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_level~3_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|pulse_level~q ));
defparam \macro_inst|trig_ctrl_inst|pulse_level .mask = 16'h1230;
defparam \macro_inst|trig_ctrl_inst|pulse_level .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_level .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_level .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_level .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_level .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_level .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_active~0 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_active~0 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_active~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .mask = 16'h3030;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_active~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 (
	.A(\macro_inst|trig_ctrl_inst|Add3~32_combout ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|LessThan6~30_combout ),
	.D(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~51_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .mask = 16'h0AFF;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~51 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y7_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_rst_sync1 (
// Location: LCCOMB_X59_Y7_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_active~1 (
alta_slice \macro_inst|trig_ctrl_inst|adc_rst_sync1 (
	.A(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.B(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.C(\macro_inst|cfg_reg_inst|adc_restart~q ),
	.D(\macro_inst|trig_ctrl_inst|always4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_rst_sync1~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_active~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_rst_sync1~q ));
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .mask = 16'h44CC;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync1 .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_level~2 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_level~2 (
	.A(\macro_inst|trig_ctrl_inst|pulse_level~q ),
	.B(\macro_inst|trig_ctrl_inst|LessThan1~2_combout ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~3_combout ),
	.D(\macro_inst|trig_ctrl_inst|edge_trigger~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_level~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .mask = 16'h1210;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_level~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_active~2 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_active~2 (
	.A(\macro_inst|trig_ctrl_inst|Add3~32_combout ),
	.B(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.C(\macro_inst|trig_ctrl_inst|LessThan6~30_combout ),
	.D(\macro_inst|trig_ctrl_inst|pulse_active~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_active~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .mask = 16'hF700;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_active~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.D(\macro_inst|trig_ctrl_inst|always4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~55_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .mask = 16'hC400;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~55 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_level~4 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_level~4 (
	.A(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|always4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_level~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .mask = 16'h4000;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_level~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 (
	.A(\macro_inst|trig_ctrl_inst|edge_trigger~4_combout ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~3_combout ),
	.D(\macro_inst|trig_ctrl_inst|LessThan1~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~53_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .mask = 16'hFF37;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~53 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 (
	.A(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|always4~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~52_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .mask = 16'h0080;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~52 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~52_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~53_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~54_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .mask = 16'hD5F5;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_cnt[12]~54 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y7_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_rst_sync2 (
alta_slice \macro_inst|trig_ctrl_inst|adc_rst_sync2 (
	.A(),
	.B(),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync1~q ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ));
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .mask = 16'hFFFF;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync2 .SyncLoadMux = 2'b01;
// Location: FF_X59_Y7_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_trigger (
// Location: LCCOMB_X59_Y7_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_trigger~0 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_trigger (
	.A(\macro_inst|trig_ctrl_inst|Add3~32_combout ),
	.B(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.C(\macro_inst|trig_ctrl_inst|LessThan6~30_combout ),
	.D(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~18_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_trigger~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_trigger~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|pulse_trigger~q ));
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .mask = 16'h0800;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_trigger .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|edge_trigger~4 (
alta_slice \macro_inst|trig_ctrl_inst|edge_trigger~4 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|LessThan5~22_combout ),
	.D(\macro_inst|trig_ctrl_inst|LessThan4~22_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|edge_trigger~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~4 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y7_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|pulse_active (
// Location: LCCOMB_X59_Y7_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|pulse_active~3 (
alta_slice \macro_inst|trig_ctrl_inst|pulse_active (
	.A(\macro_inst|trig_ctrl_inst|pulse_active~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~53_combout ),
	.C(\macro_inst|trig_ctrl_inst|pulse_cnt[12]~52_combout ),
	.D(\macro_inst|trig_ctrl_inst|pulse_active~2_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|pulse_active~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|pulse_active~3_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|pulse_active~q ));
defparam \macro_inst|trig_ctrl_inst|pulse_active .mask = 16'hF020;
defparam \macro_inst|trig_ctrl_inst|pulse_active .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|pulse_active .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|pulse_active .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|pulse_active .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|pulse_active .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|pulse_active .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y7_N0
alta_clkenctrl clken_ctrl_X59_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X59_Y7_SIG_VCC ));
defparam clken_ctrl_X59_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y7_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X59_Y7_N0
alta_asyncctrl asyncreset_ctrl_X59_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ));
defparam asyncreset_ctrl_X59_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y7_N0
alta_syncctrl syncreset_ctrl_X59_Y7(.Din(), .Dout(SyncReset_X59_Y7_GND));
defparam syncreset_ctrl_X59_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y7_N1
alta_syncctrl syncload_ctrl_X59_Y7(.Din(), .Dout(SyncLoad_X59_Y7_VCC));
defparam syncload_ctrl_X59_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y8_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal5~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal5~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal5~0 .mask = 16'h0A00;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal5~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal5~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[9] (
// Location: LCCOMB_X59_Y8_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~8 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[9] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [9]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|ahb2apb_inst|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~8_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [9]));
defparam \macro_inst|trig_ctrl_inst|prdata[9] .mask = 16'h0800;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[9] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[9] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N12
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[1] (
// Location: LCCOMB_X59_Y8_N12
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[1]~1 (
alta_slice \macro_inst|ahb2apb_inst|prdata[1] (
	.A(\macro_inst|trig_ctrl_inst|prdata [1]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]),
	.D(\macro_inst|cfg_reg_inst|prdata [1]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[1]~1_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [1]));
defparam \macro_inst|ahb2apb_inst|prdata[1] .mask = 16'hBB88;
defparam \macro_inst|ahb2apb_inst|prdata[1] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[1] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[1] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[1] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[1] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X59_Y8_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_threshold[11]~0 (
alta_slice \macro_inst|cfg_reg_inst|trig_threshold[11]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_threshold[11]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .mask = 16'h4000;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_threshold[11]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[8] (
// Location: LCCOMB_X59_Y8_N16
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[8]~8 (
alta_slice \macro_inst|ahb2apb_inst|prdata[8] (
	.A(\macro_inst|cfg_reg_inst|prdata [8]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [8]),
	.D(\macro_inst|trig_ctrl_inst|prdata [8]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[8]~8_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [8]));
defparam \macro_inst|ahb2apb_inst|prdata[8] .mask = 16'hEE22;
defparam \macro_inst|ahb2apb_inst|prdata[8] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[8] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[8] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[8] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[8] .SyncLoadMux = 2'b10;
// Location: FF_X59_Y8_N18
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[22] (
// Location: LCCOMB_X59_Y8_N18
// alta_lcell_comb \macro_inst|apb_prdata[22]~13 (
alta_slice \macro_inst|ahb2apb_inst|prdata[22] (
	.A(\macro_inst|cfg_reg_inst|prdata [22]),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]),
	.D(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [22]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[22]~13_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [22]));
defparam \macro_inst|ahb2apb_inst|prdata[22] .mask = 16'h00E2;
defparam \macro_inst|ahb2apb_inst|prdata[22] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[22] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[22] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[22] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[22] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[22] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[22] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[22] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[22] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N2
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[17] (
// Location: LCCOMB_X59_Y8_N2
// alta_lcell_comb \macro_inst|apb_prdata[17]~8 (
alta_slice \macro_inst|ahb2apb_inst|prdata[17] (
	.A(\macro_inst|ahb2apb_inst|prdata[29]~13_combout ),
	.B(\macro_inst|mem_apb_psel~combout ),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [1]),
	.D(\macro_inst|cfg_reg_inst|prdata [17]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [17]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_prdata[17]~8_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [17]));
defparam \macro_inst|ahb2apb_inst|prdata[17] .mask = 16'h5140;
defparam \macro_inst|ahb2apb_inst|prdata[17] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[17] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[17] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[17] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[17] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[17] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[17] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[17] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|prdata[17] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_mode[1]~0 (
alta_slice \macro_inst|cfg_reg_inst|trig_mode[1]~0 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_mode[1]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .mask = 16'h0400;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_mode[1]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[4] (
// Location: LCCOMB_X59_Y8_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~3 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[4] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [4]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|ahb2apb_inst|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~3_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [4]));
defparam \macro_inst|trig_ctrl_inst|prdata[4] .mask = 16'h0800;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[4] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[4] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[5] (
// Location: LCCOMB_X59_Y8_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~4 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[5] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [5]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|ahb2apb_inst|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~4_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [5]));
defparam \macro_inst|trig_ctrl_inst|prdata[5] .mask = 16'h0800;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[5] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .mask = 16'h8000;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0]~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N28
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[6] (
// Location: LCCOMB_X59_Y8_N28
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[6]~6 (
alta_slice \macro_inst|ahb2apb_inst|prdata[6] (
	.A(\macro_inst|trig_ctrl_inst|prdata [6]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [6]),
	.D(\macro_inst|cfg_reg_inst|prdata [6]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[6]~6_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [6]));
defparam \macro_inst|ahb2apb_inst|prdata[6] .mask = 16'hBB88;
defparam \macro_inst|ahb2apb_inst|prdata[6] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[6] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[6] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[6] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[6] .SyncLoadMux = 2'b10;
// Location: FF_X59_Y8_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[6] (
// Location: LCCOMB_X59_Y8_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~5 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[6] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [6]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|ahb2apb_inst|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~5_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [6]));
defparam \macro_inst|trig_ctrl_inst|prdata[6] .mask = 16'h0800;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[6] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[6] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[5] (
// Location: LCCOMB_X59_Y8_N4
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[5]~5 (
alta_slice \macro_inst|ahb2apb_inst|prdata[5] (
	.A(\macro_inst|cfg_reg_inst|prdata [5]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [5]),
	.D(\macro_inst|trig_ctrl_inst|prdata [5]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[5]~5_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [5]));
defparam \macro_inst|ahb2apb_inst|prdata[5] .mask = 16'hEE22;
defparam \macro_inst|ahb2apb_inst|prdata[5] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[5] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[5] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[5] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[5] .SyncLoadMux = 2'b10;
// Location: FF_X59_Y8_N6
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[0] (
// Location: LCCOMB_X59_Y8_N6
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[0]~0 (
alta_slice \macro_inst|ahb2apb_inst|prdata[0] (
	.A(\macro_inst|cfg_reg_inst|prdata [0]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [0]),
	.D(\macro_inst|trig_ctrl_inst|prdata [0]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [0]));
defparam \macro_inst|ahb2apb_inst|prdata[0] .mask = 16'hEE22;
defparam \macro_inst|ahb2apb_inst|prdata[0] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[0] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[0] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[0] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[0] .SyncLoadMux = 2'b10;
// Location: FF_X59_Y8_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|prdata[4] (
// Location: LCCOMB_X59_Y8_N8
// alta_lcell_comb \macro_inst|ahb2apb_inst|prdata[4]~4 (
alta_slice \macro_inst|ahb2apb_inst|prdata[4] (
	.A(\macro_inst|trig_ctrl_inst|prdata [4]),
	.B(\macro_inst|pr_select [2]),
	.C(\macro_inst|u_dual_port_ram|auto_generated|ram_block1a0_PORTADATAOUT_bus [4]),
	.D(\macro_inst|cfg_reg_inst|prdata [4]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ),
	.LutOut(\macro_inst|ahb2apb_inst|prdata[4]~4_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|prdata [4]));
defparam \macro_inst|ahb2apb_inst|prdata[4] .mask = 16'hBB88;
defparam \macro_inst|ahb2apb_inst|prdata[4] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|prdata[4] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|prdata[4] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[4] .SyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|prdata[4] .SyncLoadMux = 2'b10;

// Location: CLKENCTRL_X59_Y8_N0
alta_clkenctrl clken_ctrl_X59_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|always11~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X59_Y8_SIG_SIG ));
defparam clken_ctrl_X59_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y8_N0
alta_asyncctrl asyncreset_ctrl_X59_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ));
defparam asyncreset_ctrl_X59_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y8_N1
alta_clkenctrl clken_ctrl_X59_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|comb~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|comb~0_combout_X59_Y8_SIG_SIG ));
defparam clken_ctrl_X59_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y8_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y8_N0
alta_syncctrl syncreset_ctrl_X59_Y8(.Din(\macro_inst|ahb2apb_inst|prdata[9]~11_combout ), .Dout(\macro_inst|ahb2apb_inst|prdata[9]~11_combout__SyncReset_X59_Y8_SIG ));
defparam syncreset_ctrl_X59_Y8.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X59_Y8_N1
alta_syncctrl syncload_ctrl_X59_Y8(.Din(\macro_inst|mem_apb_psel~combout ), .Dout(\macro_inst|mem_apb_psel~combout__SyncLoad_X59_Y8_SIG ));
defparam syncload_ctrl_X59_Y8.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X59_Y9_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~5 (
// Location: FF_X59_Y9_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[4] (
alta_slice \macro_inst|cfg_reg_inst|prdata[4] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|Selector21~4_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector21~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector21~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [4]));
defparam \macro_inst|cfg_reg_inst|prdata[4] .mask = 16'hFFFC;
defparam \macro_inst|cfg_reg_inst|prdata[4] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[4] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector11~1 (
// Location: FF_X59_Y9_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[14] (
alta_slice \macro_inst|cfg_reg_inst|prdata[14] (
	.A(\macro_inst|cfg_reg_inst|frequency [14]),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|Selector11~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector11~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [14]));
defparam \macro_inst|cfg_reg_inst|prdata[14] .mask = 16'hFAF0;
defparam \macro_inst|cfg_reg_inst|prdata[14] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[14] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[14] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[14] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[14] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[14] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[14] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~4 (
alta_slice \macro_inst|cfg_reg_inst|Selector21~4 (
	.A(\macro_inst|cfg_reg_inst|adc_chnl_sel [3]),
	.B(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector21~3_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector21~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector21~4 .mask = 16'hFFF4;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector21~4 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata[10]~1 (
alta_slice \macro_inst|cfg_reg_inst|prdata[10]~1 (
	.A(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata[10]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .mask = 16'h3808;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector17~3 (
// Location: FF_X59_Y9_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[8] (
alta_slice \macro_inst|cfg_reg_inst|prdata[8] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|Selector17~1_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector17~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector17~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector17~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [8]));
defparam \macro_inst|cfg_reg_inst|prdata[8] .mask = 16'hFFFC;
defparam \macro_inst|cfg_reg_inst|prdata[8] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[8] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|prdata[10]~2 (
alta_slice \macro_inst|cfg_reg_inst|prdata[10]~2 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|prdata[10]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .mask = 16'hFF80;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[10]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal8~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal8~0 (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal8~0 .mask = 16'h0300;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal8~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector18~4 (
// Location: FF_X59_Y9_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[7] (
alta_slice \macro_inst|cfg_reg_inst|prdata[7] (
	.A(\macro_inst|cfg_reg_inst|Selector18~3_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector18~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector18~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector18~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector18~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [7]));
defparam \macro_inst|cfg_reg_inst|prdata[7] .mask = 16'hFFFE;
defparam \macro_inst|cfg_reg_inst|prdata[7] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[7] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~3 (
alta_slice \macro_inst|cfg_reg_inst|Selector20~3 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|max_vol [5]),
	.D(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector20~3 .mask = 16'h4000;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector20~3 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~3 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[4] (
alta_slice \macro_inst|cfg_reg_inst|frequency[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [4]));
defparam \macro_inst|cfg_reg_inst|frequency[4] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[4] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[4] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~5 (
// Location: FF_X59_Y9_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[5] (
alta_slice \macro_inst|cfg_reg_inst|prdata[5] (
	.A(\macro_inst|cfg_reg_inst|Selector20~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector20~4_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector20~2_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector20~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [5]));
defparam \macro_inst|cfg_reg_inst|prdata[5] .mask = 16'hFFFE;
defparam \macro_inst|cfg_reg_inst|prdata[5] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[5] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~4 (
alta_slice \macro_inst|cfg_reg_inst|Selector20~4 (
	.A(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.B(\macro_inst|cfg_reg_inst|duty_cycle [5]),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|Selector20~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector20~4 .mask = 16'hFF22;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector20~4 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~4 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|frequency[14] (
alta_slice \macro_inst|cfg_reg_inst|frequency[14] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[14] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|frequency [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|frequency[14]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|frequency [14]));
defparam \macro_inst|cfg_reg_inst|frequency[14] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|frequency[14] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|frequency[14] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[14] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[14] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[14] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|frequency[14] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|frequency[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|frequency[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|frequency[14] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~0 (
alta_slice \macro_inst|cfg_reg_inst|Selector21~0 (
	.A(\macro_inst|cfg_reg_inst|frequency [4]),
	.B(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.C(\macro_inst|cfg_reg_inst|duty_cycle [4]),
	.D(\macro_inst|cfg_reg_inst|Equal11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector21~0 .mask = 16'h8F88;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector21~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y9_N0
alta_clkenctrl clken_ctrl_X59_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X59_Y9_SIG_SIG ));
defparam clken_ctrl_X59_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y9_N0
alta_asyncctrl asyncreset_ctrl_X59_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ));
defparam asyncreset_ctrl_X59_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y9_N1
alta_clkenctrl clken_ctrl_X59_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|frequency[31]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|frequency[31]~0_combout_X59_Y9_SIG_SIG ));
defparam clken_ctrl_X59_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y9_N1.ClkEnMux = 2'b10;
// Location: FF_X60_Y10_N0
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[5] (
alta_slice \macro_inst|ahb2apb_inst|paddr[5] (
	.A(),
	.B(),
	.C(\macro_inst|ahb2apb_inst|haddr [5]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [5]));
defparam \macro_inst|ahb2apb_inst|paddr[5] .mask = 16'hFFFF;
defparam \macro_inst|ahb2apb_inst|paddr[5] .mode = "ripple";
defparam \macro_inst|ahb2apb_inst|paddr[5] .modeMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[5] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[5] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[5] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[5] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[5] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[5] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y10_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[3] (
// Location: LCCOMB_X60_Y10_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal10~1 (
alta_slice \macro_inst|ahb2apb_inst|paddr[3] (
	.A(\macro_inst|ahb2apb_inst|paddr [4]),
	.B(vcc),
	.C(\macro_inst|ahb2apb_inst|haddr [3]),
	.D(\macro_inst|ahb2apb_inst|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal10~1_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [3]));
defparam \macro_inst|ahb2apb_inst|paddr[3] .mask = 16'h5000;
defparam \macro_inst|ahb2apb_inst|paddr[3] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[3] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[3] .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[3] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[3] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[3] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[3] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y10_N12
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[14] (
// Location: LCCOMB_X60_Y10_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal4~1 (
alta_slice \macro_inst|ahb2apb_inst|haddr[14] (
	.A(\macro_inst|ahb2apb_inst|paddr [4]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\rv32.mem_ahb_haddr[14] ),
	.D(\macro_inst|ahb2apb_inst|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal4~1_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [14]));
defparam \macro_inst|ahb2apb_inst|haddr[14] .mask = 16'h0022;
defparam \macro_inst|ahb2apb_inst|haddr[14] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|haddr[14] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[14] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[14] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[14] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[14] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[14] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|haddr[14] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y10_N14
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[5] (
// Location: LCCOMB_X60_Y10_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal0~3 (
alta_slice \macro_inst|ahb2apb_inst|haddr[5] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\rv32.mem_ahb_haddr[5] ),
	.D(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [5]));
defparam \macro_inst|ahb2apb_inst|haddr[5] .mask = 16'h1100;
defparam \macro_inst|ahb2apb_inst|haddr[5] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|haddr[5] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[5] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[5] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[5] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[5] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[5] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|haddr[5] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y10_N16
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[2] (
// Location: LCCOMB_X60_Y10_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal2~0 (
alta_slice \macro_inst|ahb2apb_inst|haddr[2] (
	.A(\macro_inst|ahb2apb_inst|paddr [4]),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\rv32.mem_ahb_haddr[2] ),
	.D(\macro_inst|ahb2apb_inst|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal2~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [2]));
defparam \macro_inst|ahb2apb_inst|haddr[2] .mask = 16'h1100;
defparam \macro_inst|ahb2apb_inst|haddr[2] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|haddr[2] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[2] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[2] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[2] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[2] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[2] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|haddr[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y10_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal10~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal10~0 (
	.A(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\macro_inst|ahb2apb_inst|paddr [4]),
	.D(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal10~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal10~0 .mask = 16'h0800;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal10~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal10~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal4~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal4~0 (
	.A(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\macro_inst|ahb2apb_inst|paddr [4]),
	.D(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal4~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal4~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal2~1 (
alta_slice \macro_inst|cfg_reg_inst|Equal2~1 (
	.A(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|Equal2~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal2~1 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal2~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal4~2 (
alta_slice \macro_inst|cfg_reg_inst|Equal4~2 (
	.A(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\macro_inst|cfg_reg_inst|Equal4~1_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal4~2 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal4~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~4 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~4 (
	.A(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector24~2_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector24~3_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~4 .mask = 16'h8000;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~4 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal1~1 (
alta_slice \macro_inst|cfg_reg_inst|Equal1~1 (
	.A(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal1~0_combout ),
	.C(\macro_inst|ahb2apb_inst|paddr [4]),
	.D(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal1~1 .mask = 16'h0800;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal1~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal1~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y10_N28
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[2] (
// Location: LCCOMB_X60_Y10_N28
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[2]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [2]));
defparam \macro_inst|ahb2apb_inst|paddr[2] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[2] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[2] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[2] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[2] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[2] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[2] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[2] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y10_N30
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[4] (
// Location: LCCOMB_X60_Y10_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal0~2 (
alta_slice \macro_inst|ahb2apb_inst|paddr[4] (
	.A(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\macro_inst|ahb2apb_inst|haddr [4]),
	.D(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [4]));
defparam \macro_inst|ahb2apb_inst|paddr[4] .mask = 16'h0200;
defparam \macro_inst|ahb2apb_inst|paddr[4] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[4] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[4] .FeedbackMux = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[4] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[4] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[4] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[4] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|paddr[4] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y10_N4
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[3] (
// Location: LCCOMB_X60_Y10_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal1~0 (
alta_slice \macro_inst|ahb2apb_inst|haddr[3] (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\rv32.mem_ahb_haddr[3] ),
	.D(\macro_inst|ahb2apb_inst|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Equal1~0_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [3]));
defparam \macro_inst|ahb2apb_inst|haddr[3] .mask = 16'h1100;
defparam \macro_inst|ahb2apb_inst|haddr[3] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|haddr[3] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[3] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[3] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[3] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[3] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[3] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|haddr[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y10_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal10~2 (
alta_slice \macro_inst|cfg_reg_inst|Equal10~2 (
	.A(\macro_inst|cfg_reg_inst|Equal0~1_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|Equal10~1_combout ),
	.D(\macro_inst|cfg_reg_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal10~2 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal10~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal10~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y10_N8
// alta_lcell_ff \macro_inst|ahb2apb_inst|haddr[4] (
// Location: LCCOMB_X60_Y10_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~2 (
alta_slice \macro_inst|ahb2apb_inst|haddr[4] (
	.A(\macro_inst|ahb2apb_inst|paddr [4]),
	.B(\macro_inst|ahb2apb_inst|paddr [5]),
	.C(\rv32.mem_ahb_haddr[4] ),
	.D(\macro_inst|ahb2apb_inst|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|haddr [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y10_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~2_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|haddr [4]));
defparam \macro_inst|ahb2apb_inst|haddr[4] .mask = 16'h2200;
defparam \macro_inst|ahb2apb_inst|haddr[4] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|haddr[4] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[4] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[4] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|haddr[4] .BypassEn = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[4] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|haddr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|haddr[4] .SyncResetMux = 2'b00;
defparam \macro_inst|ahb2apb_inst|haddr[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X60_Y10_N0
alta_clkenctrl clken_ctrl_X60_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|paddr[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y10_SIG_SIG ));
defparam clken_ctrl_X60_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y10_N0
alta_asyncctrl asyncreset_ctrl_X60_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ));
defparam asyncreset_ctrl_X60_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y10_N1
alta_clkenctrl clken_ctrl_X60_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|always0~0_combout_X60_Y10_SIG_SIG ));
defparam clken_ctrl_X60_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y10_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y10_N0
alta_syncctrl syncreset_ctrl_X60_Y10(.Din(), .Dout(SyncReset_X60_Y10_GND));
defparam syncreset_ctrl_X60_Y10.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y10_N1
alta_syncctrl syncload_ctrl_X60_Y10(.Din(), .Dout(SyncLoad_X60_Y10_VCC));
defparam syncload_ctrl_X60_Y10.SyncCtrlMux = 2'b01;
// Location: FF_X60_Y11_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_chnl_sel[2] (
// Location: LCCOMB_X60_Y11_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_chnl_sel[2]~1 (
alta_slice \macro_inst|cfg_reg_inst|adc_chnl_sel[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_chnl_sel [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_chnl_sel[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_chnl_sel [2]));
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~9 (
// Location: FF_X60_Y11_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[1] (
alta_slice \macro_inst|cfg_reg_inst|prdata[1] (
	.A(\macro_inst|cfg_reg_inst|Selector24~0_combout ),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|Selector24~1_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector24~8_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~9_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [1]));
defparam \macro_inst|cfg_reg_inst|prdata[1] .mask = 16'hFFFA;
defparam \macro_inst|cfg_reg_inst|prdata[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[1] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y11_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_chnl_sel[0] (
// Location: LCCOMB_X60_Y11_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_chnl_sel[0]~0 (
alta_slice \macro_inst|cfg_reg_inst|adc_chnl_sel[0] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_chnl_sel [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_chnl_sel[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_chnl_sel [0]));
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~4 (
// Location: FF_X60_Y11_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_chnl_sel[1] (
alta_slice \macro_inst|cfg_reg_inst|adc_chnl_sel[1] (
	.A(\macro_inst|cfg_reg_inst|Selector23~2_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|cfg_reg_inst|Selector23~3_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_chnl_sel [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_chnl_sel [1]));
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .mask = 16'hFFEA;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~4 (
alta_slice \macro_inst|cfg_reg_inst|Selector22~4 (
	.A(\macro_inst|cfg_reg_inst|Selector22~2_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector22~3_combout ),
	.D(\macro_inst|cfg_reg_inst|adc_chnl_sel [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector22~4 .mask = 16'hFAFE;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector22~4 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector22~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~5 (
// Location: FF_X60_Y11_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[3] (
alta_slice \macro_inst|cfg_reg_inst|prdata[3] (
	.A(\macro_inst|cfg_reg_inst|Selector22~0_combout ),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|Selector22~1_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector22~4_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [3]));
defparam \macro_inst|cfg_reg_inst|prdata[3] .mask = 16'hFFFA;
defparam \macro_inst|cfg_reg_inst|prdata[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~5 (
// Location: FF_X60_Y11_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[2] (
alta_slice \macro_inst|cfg_reg_inst|prdata[2] (
	.A(\macro_inst|cfg_reg_inst|Selector23~0_combout ),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|Selector23~4_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector23~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [2]));
defparam \macro_inst|cfg_reg_inst|prdata[2] .mask = 16'hFFFA;
defparam \macro_inst|cfg_reg_inst|prdata[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[2] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y11_N0
alta_clkenctrl clken_ctrl_X60_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_en~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y11_SIG_SIG ));
defparam clken_ctrl_X60_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y11_N0
alta_asyncctrl asyncreset_ctrl_X60_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ));
defparam asyncreset_ctrl_X60_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y11_N1
alta_clkenctrl clken_ctrl_X60_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X60_Y11_SIG_SIG ));
defparam clken_ctrl_X60_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y11_N0
alta_syncctrl syncreset_ctrl_X60_Y11(.Din(), .Dout(SyncReset_X60_Y11_GND));
defparam syncreset_ctrl_X60_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y11_N1
alta_syncctrl syncload_ctrl_X60_Y11(.Din(), .Dout(SyncLoad_X60_Y11_VCC));
defparam syncload_ctrl_X60_Y11.SyncCtrlMux = 2'b01;
// Location: FF_X60_Y12_N10
// alta_lcell_ff \macro_inst|ahb2apb_inst|paddr[14] (
// Location: LCCOMB_X60_Y12_N10
// alta_lcell_comb \macro_inst|ahb2apb_inst|paddr[14]~feeder (
alta_slice \macro_inst|ahb2apb_inst|paddr[14] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|ahb2apb_inst|haddr [14]),
	.Cin(),
	.Qin(\macro_inst|ahb2apb_inst|paddr [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|ahb2apb_inst|paddr[14]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|ahb2apb_inst|paddr [14]));
defparam \macro_inst|ahb2apb_inst|paddr[14] .mask = 16'hFF00;
defparam \macro_inst|ahb2apb_inst|paddr[14] .mode = "logic";
defparam \macro_inst|ahb2apb_inst|paddr[14] .modeMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[14] .FeedbackMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[14] .ShiftMux = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[14] .BypassEn = 1'b0;
defparam \macro_inst|ahb2apb_inst|paddr[14] .CarryEnb = 1'b1;
defparam \macro_inst|ahb2apb_inst|paddr[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|ahb2apb_inst|paddr[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|ahb2apb_inst|paddr[14] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y12_N0
alta_clkenctrl clken_ctrl_X60_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|ahb2apb_inst|paddr[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|ahb2apb_inst|paddr[7]~0_combout_X60_Y12_SIG_SIG ));
defparam clken_ctrl_X60_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y12_N0
alta_asyncctrl asyncreset_ctrl_X60_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ));
defparam asyncreset_ctrl_X60_Y12_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X60_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le9a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .mask = 16'h692B;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .mask = 16'h3C3F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [6]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [10]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le8a [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add22_result[11]~22_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .mask = 16'h694D;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .mask = 16'hF00F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [4]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [3]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le7a [2]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .mask = 16'h6688;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .mask = 16'h0F0F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mask = 16'h2878;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mask = 16'hA0F0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] (
	.A(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mask = 16'h34C4;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [9]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mask = 16'h606A;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mask = 16'h286C;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[9]~18_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mask = 16'h7B00;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[2]~1_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [11]),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mask = 16'h268C;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] (
	.A(\macro_inst|apb_dac0_inst|diff[6]~12_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [7]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] (
	.A(\macro_inst|apb_dac0_inst|diff[7]~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.C(\macro_inst|apb_dac0_inst|diff[8]~16_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [8]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mask = 16'h1DC0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [7]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [8]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le6a [9]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~9 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .mask = 16'h962B;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|add26_result[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|LessThan0~30_combout ),
	.D(\macro_inst|trig_ctrl_inst|Add0~32_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~51_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .mask = 16'h4F44;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~51 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|sample_valid (
alta_slice \macro_inst|trig_ctrl_inst|sample_valid (
	.A(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.C(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.D(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|sample_valid~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|sample_valid .mask = 16'hE000;
defparam \macro_inst|trig_ctrl_inst|sample_valid .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|sample_valid .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|sample_valid .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|sample_valid .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|sample_valid .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|sample_valid .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|sample_valid .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|sample_valid .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|sample_valid .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector2~2 (
// Location: FF_X60_Y3_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|curr_state.SAMPLING (
alta_slice \macro_inst|trig_ctrl_inst|curr_state.SAMPLING (
	.A(\macro_inst|trig_ctrl_inst|Selector2~1_combout ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ));
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .mask = 16'h2232;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|curr_state.SAMPLING .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~0 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~0 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.C(\macro_inst|trig_ctrl_inst|trig_hit_reg~q ),
	.D(\macro_inst|cfg_reg_inst|adc_run~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .mask = 16'hFDFF;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_en (
// Location: LCCOMB_X60_Y3_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always1~2 (
alta_slice \macro_inst|cfg_reg_inst|adc_en (
	.A(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|adc_eoc_sync2~q ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|trig_ctrl_inst|always1~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_en~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(SyncReset_X60_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y3_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|always1~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_en~q ));
defparam \macro_inst|cfg_reg_inst|adc_en .mask = 16'hFFDD;
defparam \macro_inst|cfg_reg_inst|adc_en .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_en .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_en .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_en .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_en .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|adc_en .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y3_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector1~0 (
alta_slice \macro_inst|trig_ctrl_inst|Selector1~0 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|Selector0~1_combout ),
	.D(\macro_inst|trig_ctrl_inst|Selector0~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .mask = 16'h0007;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector1~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_eoc_sync2 (
// Location: LCCOMB_X60_Y3_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always9~0 (
alta_slice \macro_inst|trig_ctrl_inst|adc_eoc_sync2 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_eoc_sync1~q ),
	.D(\macro_inst|cfg_reg_inst|adc_run~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_eoc_sync2~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(SyncReset_X60_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y3_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_eoc_sync2~q ));
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .mask = 16'h2200;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_eoc_sync2 .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y3_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always1~1 (
alta_slice \macro_inst|trig_ctrl_inst|always1~1 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_eoc_sync1~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always1~1 .mask = 16'h01FF;
defparam \macro_inst|trig_ctrl_inst|always1~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always1~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always1~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always1~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always1~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector2~1 (
alta_slice \macro_inst|trig_ctrl_inst|Selector2~1 (
	.A(\macro_inst|trig_ctrl_inst|sample_valid~combout ),
	.B(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.D(\macro_inst|trig_ctrl_inst|always5~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|write_strobe (
// Location: LCCOMB_X60_Y3_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|write_strobe~0 (
alta_slice \macro_inst|trig_ctrl_inst|write_strobe (
	.A(\macro_inst|trig_ctrl_inst|LessThan0~30_combout ),
	.B(\macro_inst|trig_ctrl_inst|always1~2_combout ),
	.C(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.D(\macro_inst|trig_ctrl_inst|Add0~32_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|write_strobe~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|write_strobe~q ));
defparam \macro_inst|trig_ctrl_inst|write_strobe .mask = 16'h0100;
defparam \macro_inst|trig_ctrl_inst|write_strobe .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|write_strobe .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|write_strobe .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|write_strobe .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|write_strobe .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|write_strobe .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|write_strobe .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|write_strobe .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|write_strobe .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~1 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~1 (
	.A(\macro_inst|trig_ctrl_inst|sample_valid~combout ),
	.B(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.D(\macro_inst|trig_ctrl_inst|always5~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .mask = 16'hB030;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|single_shot_lock (
// Location: LCCOMB_X60_Y3_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|single_shot_lock~3 (
alta_slice \macro_inst|trig_ctrl_inst|single_shot_lock (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|single_shot_lock~2_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|single_shot_lock~3_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|single_shot_lock~q ));
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .mask = 16'hBB00;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 (
	.A(\macro_inst|trig_ctrl_inst|always5~3_combout ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.D(\macro_inst|trig_ctrl_inst|always5~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .mask = 16'hF8F0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 (
alta_slice \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 (
	.A(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|adc_eoc_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.D(\macro_inst|trig_ctrl_inst|always1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|eoc_cnt[8]~50_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .mask = 16'hF0F2;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|eoc_cnt[8]~50 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always5~3 (
alta_slice \macro_inst|trig_ctrl_inst|always5~3 (
	.A(\macro_inst|cfg_reg_inst|adc_run~q ),
	.B(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.C(\macro_inst|cfg_reg_inst|adc_en~q ),
	.D(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always5~3 .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|always5~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always5~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector1~1 (
// Location: FF_X60_Y3_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL (
alta_slice \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL (
	.A(\macro_inst|trig_ctrl_inst|Selector1~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector1~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ));
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .mask = 16'h2230;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|curr_state.PRE_FILL .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y3_N0
alta_clkenctrl clken_ctrl_X60_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y3_SIG_VCC ));
defparam clken_ctrl_X60_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X60_Y3_N0
alta_asyncctrl asyncreset_ctrl_X60_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ));
defparam asyncreset_ctrl_X60_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y3_N1
alta_clkenctrl clken_ctrl_X60_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_en~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y3_SIG_SIG ));
defparam clken_ctrl_X60_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y3_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y3_N0
alta_syncctrl syncreset_ctrl_X60_Y3(.Din(), .Dout(SyncReset_X60_Y3_GND));
defparam syncreset_ctrl_X60_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y3_N1
alta_syncctrl syncload_ctrl_X60_Y3(.Din(), .Dout(SyncLoad_X60_Y3_VCC));
defparam syncload_ctrl_X60_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~5 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~5 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~4 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~4 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~10 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~10 (
	.A(\macro_inst|apb_adc0_inst|apb_db [2]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .mask = 16'hAA0A;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~8 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~8 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~9 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~9 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~3 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~3 (
	.A(\macro_inst|apb_adc0_inst|apb_db [9]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .mask = 16'hAA0A;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~7 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~7 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|apb_adc0_inst|apb_db [5]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .mask = 16'hCC44;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~7 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y4_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_time_slot[3] (
alta_slice \macro_inst|cfg_reg_inst|trig_time_slot[3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_time_slot[3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_time_slot [3]));
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~0 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~0 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y4_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_time_slot[1] (
alta_slice \macro_inst|cfg_reg_inst|trig_time_slot[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_time_slot[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_time_slot [1]));
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev~2 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev~2 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|apb_adc0_inst|apb_db [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y4_N0
alta_clkenctrl clken_ctrl_X60_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_mode[1]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y4_SIG_SIG ));
defparam clken_ctrl_X60_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y4_N0
alta_asyncctrl asyncreset_ctrl_X60_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ));
defparam asyncreset_ctrl_X60_Y4_N0.AsyncCtrlMux = 2'b10;
// Location: FF_X60_Y5_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[1] (
// Location: LCCOMB_X60_Y5_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~3 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[1] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~3_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [1]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .mask = 16'hAA22;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[1] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] (
// Location: LCCOMB_X60_Y5_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge~0 (
alta_slice \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [9]));
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .mask = 16'h0F03;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|last_trig_end_addr_edge[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan7~2 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan7~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|gap_cnt_auto [8]),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan7~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .mask = 16'h0FFF;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[0] (
// Location: LCCOMB_X60_Y5_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~0 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[0] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [0]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .mask = 16'hBB00;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[0] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[3] (
// Location: LCCOMB_X60_Y5_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~5 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[3] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~5_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [3]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .mask = 16'hAA22;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[5] (
// Location: LCCOMB_X60_Y5_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~7 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[5] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~7_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [5]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .mask = 16'h88CC;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~3 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~3 (
	.A(\macro_inst|trig_ctrl_inst|LessThan7~3_combout ),
	.B(\macro_inst|trig_ctrl_inst|auto_wait_cnt [9]),
	.C(\macro_inst|trig_ctrl_inst|trig_hit_comb~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|trig_hit_comb~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .mask = 16'h5444;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~3 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[7] (
// Location: LCCOMB_X60_Y5_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~9 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[7] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~9_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [7]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .mask = 16'hBB00;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[7] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[9] (
// Location: LCCOMB_X60_Y5_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~11 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[9] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~11_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [9]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .mask = 16'hF030;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~6 (
// Location: FF_X60_Y5_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trig_hit_reg (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_reg (
	.A(\macro_inst|trig_ctrl_inst|pulse_trigger~q ),
	.B(\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trig_hit_reg~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~6_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trig_hit_reg~q ));
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .mask = 16'hFEAA;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_reg .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[4] (
// Location: LCCOMB_X60_Y5_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~6 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[4] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~6_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [4]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .mask = 16'h88CC;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 (
	.A(\macro_inst|trig_ctrl_inst|pulse_trigger~q ),
	.B(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|trig_hit_comb~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr[2]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .mask = 16'hEEEA;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan7~3 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan7~3 (
	.A(\macro_inst|trig_ctrl_inst|LessThan7~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|gap_cnt_auto [10]),
	.C(\macro_inst|trig_ctrl_inst|LessThan7~1_combout ),
	.D(\macro_inst|trig_ctrl_inst|LessThan7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan7~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .mask = 16'h3332;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan7~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 (
alta_slice \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|pulse_trigger~q ),
	.D(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~13_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .mask = 16'h000F;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|gap_cnt_auto[2]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 (
	.A(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr[2]~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .mask = 16'hEAAA;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2]~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[6] (
// Location: LCCOMB_X60_Y5_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~8 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[6] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~8_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [6]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .mask = 16'hF030;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[6] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y5_N0
alta_clkenctrl clken_ctrl_X60_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X60_Y5_SIG_SIG ));
defparam clken_ctrl_X60_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y5_N0
alta_asyncctrl asyncreset_ctrl_X60_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ));
defparam asyncreset_ctrl_X60_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y5_N1
alta_clkenctrl clken_ctrl_X60_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X60_Y5_SIG_VCC ));
defparam clken_ctrl_X60_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y5_N1.ClkEnMux = 2'b01;
// Location: FF_X60_Y6_N0
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_edge[1] (
// Location: LCCOMB_X60_Y6_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|edge_trigger~1 (
alta_slice \macro_inst|cfg_reg_inst|trig_edge[1] (
	.A(\macro_inst|cfg_reg_inst|trig_edge [0]),
	.B(\macro_inst|trig_ctrl_inst|LessThan4~22_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|trig_ctrl_inst|LessThan5~22_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_edge [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|edge_trigger~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_edge [1]));
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .mask = 16'h0048;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_edge[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~5 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~5 (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [1]),
	.B(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.C(\macro_inst|cfg_reg_inst|adc_clk_div [1]),
	.D(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~5 .mask = 16'h8F88;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~5 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~7 (
// Location: FF_X60_Y6_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[1] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[1] (
	.A(\macro_inst|cfg_reg_inst|trig_edge [1]),
	.B(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~7_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [1]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector3~0 (
alta_slice \macro_inst|trig_ctrl_inst|Selector3~0 (
	.A(\macro_inst|trig_ctrl_inst|Selector0~0_combout ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.D(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .mask = 16'hA000;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y6_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_edge[0] (
// Location: LCCOMB_X60_Y6_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always4~0 (
alta_slice \macro_inst|cfg_reg_inst|trig_edge[0] (
	.A(\macro_inst|cfg_reg_inst|trig_edge [1]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_edge [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|always4~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_edge [0]));
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .mask = 16'hA0A0;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_edge[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~8 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~8 (
	.A(\macro_inst|cfg_reg_inst|Selector24~7_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_chnl_sel [0]),
	.C(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector24~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~8 .mask = 16'hFFBA;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~8 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~8 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y6_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_time_slot[2] (
alta_slice \macro_inst|cfg_reg_inst|trig_time_slot[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_time_slot[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_time_slot [2]));
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_time_slot[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~2 (
// Location: FF_X60_Y6_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[0] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[0] (
	.A(\macro_inst|cfg_reg_inst|trig_edge [0]),
	.B(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [0]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|single_shot_lock~2 (
alta_slice \macro_inst|trig_ctrl_inst|single_shot_lock~2 (
	.A(\macro_inst|cfg_reg_inst|trig_mode [1]),
	.B(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.C(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.D(\macro_inst|cfg_reg_inst|trig_mode [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|single_shot_lock~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .mask = 16'hF0F8;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|single_shot_lock~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector19~2 (
// Location: FF_X60_Y6_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[6] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[6] (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector19~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [6]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~6 (
alta_slice \macro_inst|cfg_reg_inst|Selector24~6 (
	.A(\macro_inst|cfg_reg_inst|Selector24~5_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [1]),
	.C(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector24~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector24~6 .mask = 16'hFFBA;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector24~6 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector24~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|edge_trigger~2 (
alta_slice \macro_inst|trig_ctrl_inst|edge_trigger~2 (
	.A(\macro_inst|trig_ctrl_inst|LessThan1~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|always4~0_combout ),
	.C(\macro_inst|trig_ctrl_inst|edge_trigger~0_combout ),
	.D(\macro_inst|trig_ctrl_inst|edge_trigger~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|edge_trigger~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .mask = 16'h1110;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|edge_trigger~0 (
alta_slice \macro_inst|trig_ctrl_inst|edge_trigger~0 (
	.A(\macro_inst|cfg_reg_inst|trig_edge [0]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|LessThan2~22_combout ),
	.D(\macro_inst|trig_ctrl_inst|LessThan3~22_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|edge_trigger~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .mask = 16'h0050;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|edge_trigger~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always4~1 (
alta_slice \macro_inst|trig_ctrl_inst|always4~1 (
	.A(\macro_inst|cfg_reg_inst|trig_edge [0]),
	.B(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.C(\macro_inst|cfg_reg_inst|trig_edge [1]),
	.D(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always4~1 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|always4~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always4~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always4~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always4~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always4~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~5 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~5 (
	.A(\macro_inst|trig_ctrl_inst|single_shot_lock~q ),
	.B(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.C(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.D(\macro_inst|trig_ctrl_inst|trig_hit_comb~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .mask = 16'h4000;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~5 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y6_N0
alta_clkenctrl clken_ctrl_X60_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_mode[1]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_mode[1]~0_combout_X60_Y6_SIG_SIG ));
defparam clken_ctrl_X60_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y6_N0
alta_asyncctrl asyncreset_ctrl_X60_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ));
defparam asyncreset_ctrl_X60_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y6_N1
alta_clkenctrl clken_ctrl_X60_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y6_SIG_SIG ));
defparam clken_ctrl_X60_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y6_N0
alta_syncctrl syncreset_ctrl_X60_Y6(.Din(), .Dout(SyncReset_X60_Y6_GND));
defparam syncreset_ctrl_X60_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y6_N1
alta_syncctrl syncload_ctrl_X60_Y6(.Din(), .Dout(SyncLoad_X60_Y6_VCC));
defparam syncload_ctrl_X60_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y7_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~16 (
alta_slice \macro_inst|trig_ctrl_inst|Add3~16 (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [8]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~16_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~17 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add3~16 .mask = 16'h5AAF;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add3~16 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~16 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y7_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[13] (
// Location: LCCOMB_X60_Y7_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~26 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[13] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [13]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[13] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~25 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~26_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~27 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [13]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .mask = 16'hA505;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[13] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[14] (
// Location: LCCOMB_X60_Y7_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~28 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[14] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [14]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[14] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~27 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~28_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~29 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [14]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .mask = 16'h5AAF;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[14] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[15] (
// Location: LCCOMB_X60_Y7_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~30 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[15] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [15]),
	.C(\rv32.mem_ahb_hwdata[15] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~29 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~30_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~31 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [15]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .mask = 16'hC303;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[15] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[9] (
// Location: LCCOMB_X60_Y7_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~32 (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[9] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~31 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~32_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [9]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector13~1 (
// Location: FF_X60_Y7_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[9] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[9] (
	.A(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector13~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [9]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .mask = 16'hAABB;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~18 (
alta_slice \macro_inst|trig_ctrl_inst|Add3~18 (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~19 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add3~18 .mask = 16'hC303;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add3~18 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~3 (
// Location: FF_X60_Y7_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[2] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[2] (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_mode [0]),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [2]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector10~0 (
// Location: FF_X60_Y7_N22
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[15] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[15] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [15]),
	.C(\rv32.mem_ahb_hwdata[15] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector10~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [15]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .mask = 16'hF0CC;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[15] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector11~0 (
// Location: FF_X60_Y7_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[14] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[14] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [14]),
	.B(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.C(\rv32.mem_ahb_hwdata[14] ),
	.D(\macro_inst|cfg_reg_inst|Selector13~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector11~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [14]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .mask = 16'h00E2;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[14] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector13~0 (
// Location: FF_X60_Y7_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[12] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[12] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [12]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector13~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [12]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .mask = 16'hF0CC;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[12] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector12~0 (
// Location: FF_X60_Y7_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_auto_timeout[13] (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[13] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [13]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[13] ),
	.D(\macro_inst|cfg_reg_inst|Equal5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_auto_timeout [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector12~0_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_auto_timeout [13]));
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .mask = 16'hF0AA;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[13] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector17~2 (
// Location: FF_X60_Y7_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[8] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[8] (
	.A(\macro_inst|cfg_reg_inst|trig_threshold [8]),
	.B(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector17~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [8]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[8] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[10] (
// Location: LCCOMB_X60_Y7_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~20 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[10] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [10]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~19 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~21 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [10]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .mask = 16'h3CCF;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[10] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[11] (
// Location: LCCOMB_X60_Y7_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~22 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[11] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [11]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~21 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~23 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [11]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .mask = 16'hA505;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[11] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[12] (
// Location: LCCOMB_X60_Y7_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~24 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[12] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [12]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~23 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~25 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [12]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .mask = 16'h3CCF;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[12] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X60_Y7_N0
alta_clkenctrl clken_ctrl_X60_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y7_SIG_SIG ));
defparam clken_ctrl_X60_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y7_N0
alta_asyncctrl asyncreset_ctrl_X60_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ));
defparam asyncreset_ctrl_X60_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y7_N1
alta_clkenctrl clken_ctrl_X60_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout_X60_Y7_SIG_SIG ));
defparam clken_ctrl_X60_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y7_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y7_N0
alta_syncctrl syncreset_ctrl_X60_Y7(.Din(), .Dout(SyncReset_X60_Y7_GND));
defparam syncreset_ctrl_X60_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y7_N1
alta_syncctrl syncload_ctrl_X60_Y7(.Din(), .Dout(SyncLoad_X60_Y7_VCC));
defparam syncload_ctrl_X60_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y8_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~1 (
// Location: FF_X60_Y8_N0
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[4] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[4] (
	.A(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.B(\macro_inst|cfg_reg_inst|max_vol [4]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [4]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~5 (
// Location: FF_X60_Y8_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[0] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[0] (
	.A(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.B(\macro_inst|cfg_reg_inst|max_vol [0]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~5_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [0]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[0] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[3] (
// Location: LCCOMB_X60_Y8_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_pulse_width[3]~4 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[3] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_pulse_width[3]~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [3]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector19~1 (
// Location: FF_X60_Y8_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[6] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[6] (
	.A(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.B(\macro_inst|cfg_reg_inst|max_vol [6]),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector19~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [6]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .mask = 16'hECA0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[6] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N16
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[0] (
// Location: LCCOMB_X60_Y8_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~0 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[0] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [0]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~0_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~1 ),
	.Q(\macro_inst|cfg_reg_inst|max_vol [0]));
defparam \macro_inst|cfg_reg_inst|max_vol[0] .mask = 16'h55AA;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|max_vol[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~2 (
alta_slice \macro_inst|trig_ctrl_inst|Add3~2 (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~2_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~3 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add3~2 .mask = 16'h3C0C;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add3~2 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[1] (
// Location: LCCOMB_X60_Y8_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_pulse_width[1]~3 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_pulse_width[1]~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [1]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~4 (
alta_slice \macro_inst|trig_ctrl_inst|Add3~4 (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~4_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~5 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add3~4 .mask = 16'h3CCF;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add3~4 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~6 (
alta_slice \macro_inst|trig_ctrl_inst|Add3~6 (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~6_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~7 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add3~6 .mask = 16'h5A0A;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add3~6 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add3~6 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[4] (
// Location: LCCOMB_X60_Y8_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~8 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[4] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [4]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~7 ),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~8_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~9 ),
	.Q(\macro_inst|cfg_reg_inst|max_vol [4]));
defparam \macro_inst|cfg_reg_inst|max_vol[4] .mask = 16'h3CCF;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|max_vol[4] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|max_vol[4] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[5] (
// Location: LCCOMB_X60_Y8_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~10 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[5] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [5]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~9 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~10_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~11 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [5]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .mask = 16'hA505;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[5] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[6] (
// Location: LCCOMB_X60_Y8_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~12 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[6] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_pulse_width [6]),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~11 ),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~12_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~13 ),
	.Q(\macro_inst|cfg_reg_inst|max_vol [6]));
defparam \macro_inst|cfg_reg_inst|max_vol[6] .mask = 16'h3CCF;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|max_vol[6] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|max_vol[6] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[7] (
// Location: LCCOMB_X60_Y8_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add3~14 (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[7] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [7]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add3~13 ),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add3~14_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add3~15 ),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [7]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .mask = 16'hA505;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .CarryEnb = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~1 (
// Location: FF_X60_Y8_N4
// alta_lcell_ff \macro_inst|cfg_reg_inst|trig_pulse_width[2] (
alta_slice \macro_inst|cfg_reg_inst|trig_pulse_width[2] (
	.A(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.B(\macro_inst|cfg_reg_inst|max_vol [2]),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|trig_pulse_width [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|trig_pulse_width [2]));
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .mask = 16'hB3A0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|trig_pulse_width[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~1 (
// Location: FF_X60_Y8_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[3] (
alta_slice \macro_inst|cfg_reg_inst|max_vol[3] (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [3]),
	.B(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|cfg_reg_inst|Equal9~0_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [3]));
defparam \macro_inst|cfg_reg_inst|max_vol[3] .mask = 16'hF444;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .FeedbackMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|max_vol[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N8
// alta_lcell_ff \macro_inst|cfg_reg_inst|max_vol[2] (
// Location: LCCOMB_X60_Y8_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|max_vol[2]~3 (
alta_slice \macro_inst|cfg_reg_inst|max_vol[2] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|max_vol [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|max_vol[2]~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|max_vol [2]));
defparam \macro_inst|cfg_reg_inst|max_vol[2] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|max_vol[2] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|max_vol[2] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y8_N0
alta_clkenctrl clken_ctrl_X60_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|trig_pulse_width[0]~2_combout_X60_Y8_SIG_SIG ));
defparam clken_ctrl_X60_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y8_N0
alta_asyncctrl asyncreset_ctrl_X60_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ));
defparam asyncreset_ctrl_X60_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y8_N1
alta_clkenctrl clken_ctrl_X60_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|min_vol[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|min_vol[0]~0_combout_X60_Y8_SIG_SIG ));
defparam clken_ctrl_X60_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y8_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y8_N0
alta_syncctrl syncreset_ctrl_X60_Y8(.Din(), .Dout(SyncReset_X60_Y8_GND));
defparam syncreset_ctrl_X60_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y8_N1
alta_syncctrl syncload_ctrl_X60_Y8(.Din(), .Dout(SyncLoad_X60_Y8_VCC));
defparam syncload_ctrl_X60_Y8.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y9_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7]~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_chnl_sel[3] (
// Location: LCCOMB_X60_Y9_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_chnl_sel[3]~2 (
alta_slice \macro_inst|cfg_reg_inst|adc_chnl_sel[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_chnl_sel [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_chnl_sel[3]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_chnl_sel [3]));
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_chnl_sel[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[7] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [7]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector18~2 (
alta_slice \macro_inst|cfg_reg_inst|Selector18~2 (
	.A(\macro_inst|cfg_reg_inst|trig_pulse_width [7]),
	.B(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector18~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector18~2 .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector18~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector18~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N16
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector23~2 (
alta_slice \macro_inst|cfg_reg_inst|Selector23~2 (
	.A(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [2]),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector23~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector23~2 .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector23~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector23~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N18
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[5] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [5]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[5] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N2
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[3] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [3]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N20
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[4] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [4]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N22
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector21~2 (
alta_slice \macro_inst|cfg_reg_inst|Selector21~2 (
	.A(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [4]),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector21~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector21~2 .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector21~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector21~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector18~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector18~1 (
	.A(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [7]),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector18~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector18~1 .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector18~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector18~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N26
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[2] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[2] (
	.A(),
	.B(),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(SyncReset_X60_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y9_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [2]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .mask = 16'hFFFF;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y9_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector20~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector20~1 (
	.A(\macro_inst|cfg_reg_inst|Equal4~2_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector20~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector20~1 .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector20~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector20~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N30
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_en~0 (
alta_slice \macro_inst|cfg_reg_inst|adc_en~0 (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_en~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|adc_en~0 .mask = 16'h0200;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_en~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_en~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 (
alta_slice \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 (
	.A(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|trig_auto_timeout[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector22~2 (
alta_slice \macro_inst|cfg_reg_inst|Selector22~2 (
	.A(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [3]),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector22~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector22~2 .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector22~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector22~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N8
// alta_lcell_comb \macro_inst|cfg_reg_inst|Equal3~0 (
alta_slice \macro_inst|cfg_reg_inst|Equal3~0 (
	.A(vcc),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|ahb2apb_inst|paddr [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Equal3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Equal3~0 .mask = 16'hC000;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Equal3~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Equal3~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y9_N0
alta_clkenctrl clken_ctrl_X60_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_en~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_en~0_combout_X60_Y9_SIG_SIG ));
defparam clken_ctrl_X60_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y9_N0
alta_asyncctrl asyncreset_ctrl_X60_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ));
defparam asyncreset_ctrl_X60_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y9_N1
alta_clkenctrl clken_ctrl_X60_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X60_Y9_SIG_SIG ));
defparam clken_ctrl_X60_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y9_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y9_N0
alta_syncctrl syncreset_ctrl_X60_Y9(.Din(), .Dout(SyncReset_X60_Y9_GND));
defparam syncreset_ctrl_X60_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y9_N1
alta_syncctrl syncload_ctrl_X60_Y9(.Din(), .Dout(SyncLoad_X60_Y9_VCC));
defparam syncload_ctrl_X60_Y9.SyncCtrlMux = 2'b01;
// Location: FF_X61_Y10_N10
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[6] (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X61_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [6]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[6] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N12
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[1] (
// Location: LCCOMB_X61_Y10_N12
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_clk_div[1]~2 (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X61_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[1]~2_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [1]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N14
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~3 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~3 (
	.A(\macro_inst|cfg_reg_inst|adc_clk_div [6]),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [6]),
	.C(\macro_inst|apb_adc0_inst|sclk_counter [7]),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~3 .mask = 16'h9009;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~3 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N16
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[7]~18 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[7]~18 (
	.A(\macro_inst|apb_adc0_inst|Equal0~6_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_en~q ),
	.C(\macro_inst|apb_adc0_inst|Equal0~5_combout ),
	.D(\macro_inst|apb_adc0_inst|Equal0~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .mask = 16'hB333;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N18
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~4 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~4 (
	.A(\macro_inst|apb_adc0_inst|Equal0~2_combout ),
	.B(\macro_inst|apb_adc0_inst|Equal0~1_combout ),
	.C(\macro_inst|apb_adc0_inst|Equal0~3_combout ),
	.D(\macro_inst|apb_adc0_inst|Equal0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~4 .mask = 16'h8000;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~4 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N20
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~1 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~1 (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [2]),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [2]),
	.C(\macro_inst|cfg_reg_inst|adc_clk_div [3]),
	.D(\macro_inst|apb_adc0_inst|sclk_counter [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~1 .mask = 16'h9009;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~1 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N22
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~5 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~5 (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [8]),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [9]),
	.C(\macro_inst|apb_adc0_inst|sclk_counter [10]),
	.D(\macro_inst|apb_adc0_inst|sclk_counter [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~5 .mask = 16'h0001;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~5 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~5 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_clk_div[0] (
// Location: LCCOMB_X61_Y10_N24
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_clk_div[0]~1 (
alta_slice \macro_inst|cfg_reg_inst|adc_clk_div[0] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_clk_div [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X61_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_clk_div[0]~1_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_clk_div [0]));
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .mask = 16'h0F0F;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_clk_div[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N26
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~6 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~6 (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [12]),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [13]),
	.C(\macro_inst|apb_adc0_inst|sclk_counter [15]),
	.D(\macro_inst|apb_adc0_inst|sclk_counter [14]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~6 .mask = 16'h0001;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~6 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N28
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~0 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~0 (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [1]),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [0]),
	.C(\macro_inst|apb_adc0_inst|sclk_counter [0]),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~0 .mask = 16'h1428;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~0 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N30
// alta_lcell_comb \macro_inst|apb_adc0_inst|Equal0~2 (
alta_slice \macro_inst|apb_adc0_inst|Equal0~2 (
	.A(\macro_inst|cfg_reg_inst|adc_clk_div [5]),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [4]),
	.C(\macro_inst|apb_adc0_inst|sclk_counter [5]),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_adc0_inst|Equal0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_adc0_inst|Equal0~2 .mask = 16'h8421;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .mode = "logic";
defparam \macro_inst|apb_adc0_inst|Equal0~2 .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_adc0_inst|Equal0~2 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N6
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk (
// Location: LCCOMB_X61_Y10_N6
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk~0 (
alta_slice \macro_inst|apb_adc0_inst|sclk (
	.A(\macro_inst|apb_adc0_inst|Equal0~6_combout ),
	.B(\macro_inst|apb_adc0_inst|Equal0~5_combout ),
	.C(vcc),
	.D(\macro_inst|apb_adc0_inst|Equal0~4_combout ),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|sclk~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(\macro_inst|cfg_reg_inst|adc_en~q__SyncReset_X61_Y10_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk~0_combout ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|sclk~q ));
defparam \macro_inst|apb_adc0_inst|sclk .mask = 16'h78F0;
defparam \macro_inst|apb_adc0_inst|sclk .mode = "logic";
defparam \macro_inst|apb_adc0_inst|sclk .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk .FeedbackMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk .SyncResetMux = 2'b11;
defparam \macro_inst|apb_adc0_inst|sclk .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X61_Y10_N0
alta_clkenctrl clken_ctrl_X61_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y10_SIG_VCC ));
defparam clken_ctrl_X61_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y10_N0.ClkEnMux = 2'b01;

// Location: CLKENCTRL_X61_Y10_N1
alta_clkenctrl clken_ctrl_X61_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_clk_div[7]~0_combout_X61_Y10_SIG_SIG ));
defparam clken_ctrl_X61_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y10_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y10_N1
alta_asyncctrl asyncreset_ctrl_X61_Y10_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ));
defparam asyncreset_ctrl_X61_Y10_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y10_N0
alta_syncctrl syncreset_ctrl_X61_Y10(.Din(\macro_inst|cfg_reg_inst|adc_en~q ), .Dout(\macro_inst|cfg_reg_inst|adc_en~q__SyncReset_X61_Y10_INV ));
defparam syncreset_ctrl_X61_Y10.SyncCtrlMux = 2'b11;

// Location: SYNCCTRL_X61_Y10_N1
alta_syncctrl syncload_ctrl_X61_Y10(.Din(), .Dout(SyncLoad_X61_Y10_GND));
defparam syncload_ctrl_X61_Y10.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X61_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~22_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~24_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~26_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~30_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~33 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~34 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~32_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~35 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~36 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~34_combout ),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~30_combout ),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~37 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .mask = 16'hC33C;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~38 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~14_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~21 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~22 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~300 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~300 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~300_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .mask = 16'h33CC;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~300 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~302 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~302 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~301_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~290_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~286_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~302_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .mask = 16'hA2E6;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~302 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~291 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~291 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~289_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~290_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~286_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~291_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .mask = 16'h6E2A;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~291 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~301 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~301 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~287_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~300_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~301_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .mask = 16'hE3E0;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~301 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~286 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~286 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~286_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .mask = 16'hCFEE;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~286 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~290 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~290 (
	.A(\macro_inst|apb_dac0_inst|phase_r [2]),
	.B(\macro_inst|apb_dac0_inst|phase_r [6]),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~290_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .mask = 16'hCC70;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~290 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~16_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~24 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~22_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~18_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mask = 16'h9617;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~24_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28_combout ),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~29 ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mask = 16'h698E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .mask = 16'h0FF0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|cs3a[1]~0_combout ),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mask = 16'h35C0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .mask = 16'h0088;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .mask = 16'h005F;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [1]),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~0_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~4_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~2_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~4_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~6_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~8_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .mask = 16'h008E;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 (
	.A(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_3~10_combout ),
	.B(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_2~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19_cout ),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .mask = 16'h0017;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .mode = "ripple";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .modeMux = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .CarryEnb = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|op_1~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mask = 16'h5AF0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] (
	.A(\macro_inst|apb_dac0_inst|sine_rom~332_combout ),
	.B(\macro_inst|apb_dac0_inst|diff[1]~2_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [1]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mask = 16'h2878;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
alta_slice \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] (
	.A(\macro_inst|apb_dac0_inst|diff[0]~0_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~233_combout ),
	.C(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le4a [11]),
	.D(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [11]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a [0]),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mask = 16'hD728;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|Mult0|auto_generated|mac_mult1|auto_generated|mult1|le5a[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~1 (
	.A(\macro_inst|trig_ctrl_inst|Add0~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~1_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .mask = 16'h0022;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~11 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~11 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [5]),
	.B(\macro_inst|trig_ctrl_inst|Add0~10_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~11_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~13 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~13 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [6]),
	.B(\macro_inst|trig_ctrl_inst|Add0~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~13_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~15 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~15 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [7]),
	.B(\macro_inst|trig_ctrl_inst|Add0~14_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~15_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~17 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~17 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [8]),
	.B(\macro_inst|trig_ctrl_inst|Add0~16_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~17_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~19 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~19 (
	.A(\macro_inst|trig_ctrl_inst|Add0~18_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~19_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~3 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~3 (
	.A(\macro_inst|trig_ctrl_inst|Add0~2_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~3_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~21 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~21 (
	.A(\macro_inst|trig_ctrl_inst|Add0~20_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~21_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~23 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~23 (
	.A(\macro_inst|trig_ctrl_inst|Add0~22_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [11]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~21_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~23_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~23 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~25 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~25 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [12]),
	.B(\macro_inst|trig_ctrl_inst|Add0~24_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~23_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~25_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~25 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~27 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~27 (
	.A(\macro_inst|trig_ctrl_inst|Add0~26_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [13]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~25_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~27_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~27 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~29 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~29 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [14]),
	.B(\macro_inst|trig_ctrl_inst|Add0~28_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~27_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~29_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~29 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~30 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~30 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [15]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Add0~30_combout ),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~29_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan0~30_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .mask = 16'hF550;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~5 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~5 (
	.A(\macro_inst|trig_ctrl_inst|Add0~4_combout ),
	.B(\macro_inst|trig_ctrl_inst|eoc_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~5_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~7 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~7 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [3]),
	.B(\macro_inst|trig_ctrl_inst|Add0~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~7_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan0~9 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan0~9 (
	.A(\macro_inst|trig_ctrl_inst|eoc_cnt [4]),
	.B(\macro_inst|trig_ctrl_inst|Add0~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan0~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan0~9_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan0~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|decim_factor~1 (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor~1 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|decim_factor~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .mask = 16'h0208;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr5~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr5~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .mask = 16'hAC80;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr5~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr3~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr3~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .mask = 16'h20F0;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr4~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr4~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .mask = 16'h04E0;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr7~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr7~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr7~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .mask = 16'h0504;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr7~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Decoder0~1 (
alta_slice \macro_inst|trig_ctrl_inst|Decoder0~1 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Decoder0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .mask = 16'h1000;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Decoder0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr6~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr6~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .mask = 16'h1150;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr8~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr8~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .mask = 16'hBFFC;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan1~2 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan1~2 (
	.A(\macro_inst|trig_ctrl_inst|LessThan1~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16_combout ),
	.C(\macro_inst|trig_ctrl_inst|LessThan1~1_combout ),
	.D(\macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .mask = 16'hFBFF;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [4]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~9 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .mask = 16'h964D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~11 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .mask = 16'h694D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [6]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~13 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .mask = 16'h964D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]),
	.B(\macro_inst|trig_ctrl_inst|trigger_ptr [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~15 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .mask = 16'h694D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [8]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~17 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .mask = 16'h964D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[8]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [0]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~1 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .mask = 16'h66DD;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 (
	.A(\macro_inst|trig_ctrl_inst|last_trig_end_addr_edge [9]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[8]~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .mask = 16'h5AA5;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[9]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan1~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan1~1 (
	.A(\macro_inst|trig_ctrl_inst|addr_diff_edge[4]~8_combout ),
	.B(\macro_inst|trig_ctrl_inst|addr_diff_edge[7]~14_combout ),
	.C(\macro_inst|trig_ctrl_inst|addr_diff_edge[6]~12_combout ),
	.D(\macro_inst|trig_ctrl_inst|addr_diff_edge[5]~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .mask = 16'h7FFF;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan1~0 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan1~0 (
	.A(\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4_combout ),
	.B(\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2_combout ),
	.C(\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6_combout ),
	.D(\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .mask = 16'h7FFF;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan1~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y5_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[8] (
// Location: LCCOMB_X61_Y5_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~10 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[8] (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~10_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [8]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .mask = 16'hAF00;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[8] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y5_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trigger_ptr[2] (
// Location: LCCOMB_X61_Y5_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trigger_ptr~4 (
alta_slice \macro_inst|trig_ctrl_inst|trigger_ptr[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trigger_ptr [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trigger_ptr~4_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trigger_ptr [2]));
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .mask = 16'hCC0C;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trigger_ptr[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [1]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[0]~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~3 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .mask = 16'h692B;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[1]~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [2]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[1]~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~5 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .mask = 16'h964D;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[2]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 (
alta_slice \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 (
	.A(\macro_inst|trig_ctrl_inst|trigger_ptr [3]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|addr_diff_edge[2]~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|addr_diff_edge[3]~7 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .mask = 16'h692B;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|addr_diff_edge[3]~6 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y5_N0
alta_clkenctrl clken_ctrl_X61_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|trigger_ptr[2]~2_combout_X61_Y5_SIG_SIG ));
defparam clken_ctrl_X61_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y5_N0
alta_asyncctrl asyncreset_ctrl_X61_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ));
defparam asyncreset_ctrl_X61_Y5_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X61_Y6_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_restart_ris (
alta_slice \macro_inst|trig_ctrl_inst|adc_restart_ris (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .mask = 16'h00F0;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_restart_ris .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .mask = 16'hC0EA;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 (
alta_slice \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|adc_data_prev[10]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .mask = 16'hFF20;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|adc_data_prev[10]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector3~1 (
// Location: FF_X61_Y6_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG (
alta_slice \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG (
	.A(\macro_inst|trig_ctrl_inst|Selector3~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ));
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .mask = 16'h2232;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|curr_state.POST_TRIG .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y6_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|adc_rst_sync3 (
// Location: LCCOMB_X61_Y6_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12 (
alta_slice \macro_inst|trig_ctrl_inst|adc_rst_sync3 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ),
	.B(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ));
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .mask = 16'h0CAE;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|adc_rst_sync3 .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y6_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wren_b~0 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wren_b~0 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.C(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wren_b~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .mask = 16'h0020;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|ram_wren_b~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~6 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~6 (
	.A(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.D(\macro_inst|trig_ctrl_inst|Selector1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .mask = 16'h50FF;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector4~1 (
// Location: FF_X61_Y6_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|curr_state.DONE (
alta_slice \macro_inst|trig_ctrl_inst|curr_state.DONE (
	.A(\macro_inst|trig_ctrl_inst|Selector4~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ));
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .mask = 16'h2232;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|curr_state.DONE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector4~0 (
alta_slice \macro_inst|trig_ctrl_inst|Selector4~0 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.C(\macro_inst|trig_ctrl_inst|Selector0~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|Selector0~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~7 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~7 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.C(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .mask = 16'h44C4;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~5 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~5 (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.C(\macro_inst|trig_ctrl_inst|Selector0~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|Selector0~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .mask = 16'hC444;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~8 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~8 (
	.A(\macro_inst|trig_ctrl_inst|always9~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.PRE_FILL~q ),
	.C(\macro_inst|trig_ctrl_inst|Selector0~5_combout ),
	.D(\macro_inst|trig_ctrl_inst|curr_state.SAMPLING~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .mask = 16'h0504;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~10 (
// Location: FF_X61_Y6_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|curr_state.IDLE (
alta_slice \macro_inst|trig_ctrl_inst|curr_state.IDLE (
	.A(\macro_inst|trig_ctrl_inst|Selector0~9_combout ),
	.B(\macro_inst|trig_ctrl_inst|Selector0~7_combout ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Selector0~6_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~10_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|curr_state.IDLE~q ));
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .mask = 16'h1130;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|curr_state.IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_hit_comb~4 (
alta_slice \macro_inst|trig_ctrl_inst|trig_hit_comb~4 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|adc_en~q ),
	.D(\macro_inst|cfg_reg_inst|adc_run~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_hit_comb~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .mask = 16'hF000;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_hit_comb~4 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y6_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_run (
// Location: LCCOMB_X61_Y6_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~9 (
alta_slice \macro_inst|cfg_reg_inst|adc_run (
	.A(\macro_inst|cfg_reg_inst|adc_en~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.POST_TRIG~q ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|trig_ctrl_inst|Selector0~8_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_run~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_run~0_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~9_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_run~q ));
defparam \macro_inst|cfg_reg_inst|adc_run .mask = 16'hFF44;
defparam \macro_inst|cfg_reg_inst|adc_run .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_run .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_run .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_run .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_run .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|adc_run .SyncLoadMux = 2'b01;
// Location: FF_X61_Y6_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|trig_done (
// Location: LCCOMB_X61_Y6_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|trig_done~0 (
alta_slice \macro_inst|trig_ctrl_inst|trig_done (
	.A(\macro_inst|trig_ctrl_inst|adc_rst_sync2~q ),
	.B(\macro_inst|trig_ctrl_inst|curr_state.DONE~q ),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|adc_rst_sync3~q ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|trig_done~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|trig_done~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|trig_done~q ));
defparam \macro_inst|trig_ctrl_inst|trig_done .mask = 16'hFC54;
defparam \macro_inst|trig_ctrl_inst|trig_done .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|trig_done .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_done .FeedbackMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_done .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_done .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|trig_done .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|trig_done .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|trig_done .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|trig_done .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y6_N0
alta_clkenctrl clken_ctrl_X61_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X61_Y6_SIG_VCC ));
defparam clken_ctrl_X61_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y6_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y6_N0
alta_asyncctrl asyncreset_ctrl_X61_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ));
defparam asyncreset_ctrl_X61_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y6_N1
alta_clkenctrl clken_ctrl_X61_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_run~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_run~0_combout_X61_Y6_SIG_SIG ));
defparam clken_ctrl_X61_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y6_N0
alta_syncctrl syncreset_ctrl_X61_Y6(.Din(), .Dout(SyncReset_X61_Y6_GND));
defparam syncreset_ctrl_X61_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y6_N1
alta_syncctrl syncload_ctrl_X61_Y6(.Din(), .Dout(SyncLoad_X61_Y6_VCC));
defparam syncload_ctrl_X61_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X61_Y7_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~1 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~1 (
	.A(\macro_inst|trig_ctrl_inst|Add3~0_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~1_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .mask = 16'h0022;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~11 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~11 (
	.A(\macro_inst|trig_ctrl_inst|Add3~10_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~9_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~11_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~13 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~13 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [6]),
	.B(\macro_inst|trig_ctrl_inst|Add3~12_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~11_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~13_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~15 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~15 (
	.A(\macro_inst|trig_ctrl_inst|Add3~14_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~13_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~15_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~17 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~17 (
	.A(\macro_inst|trig_ctrl_inst|Add3~16_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~15_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~17_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~19 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~19 (
	.A(\macro_inst|trig_ctrl_inst|Add3~18_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~17_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~19_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~3 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~3 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [1]),
	.B(\macro_inst|trig_ctrl_inst|Add3~2_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~3_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~21 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~21 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [10]),
	.B(\macro_inst|trig_ctrl_inst|Add3~20_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~19_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~21_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~23 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~23 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [11]),
	.B(\macro_inst|trig_ctrl_inst|Add3~22_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~21_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~23_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~23 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~25 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~25 (
	.A(\macro_inst|trig_ctrl_inst|Add3~24_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [12]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~23_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~25_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~25 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~27 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~27 (
	.A(\macro_inst|trig_ctrl_inst|Add3~26_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [13]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~25_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~27_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~27 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~29 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~29 (
	.A(\macro_inst|trig_ctrl_inst|Add3~28_combout ),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [14]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~27_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~29_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~29 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~30 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~30 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|pulse_cnt [15]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|Add3~30_combout ),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~29_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|LessThan6~30_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .mask = 16'hF330;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~5 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~5 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [2]),
	.B(\macro_inst|trig_ctrl_inst|Add3~4_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~5_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~7 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~7 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [3]),
	.B(\macro_inst|trig_ctrl_inst|Add3~6_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~5_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~7_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .mask = 16'h002B;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|LessThan6~9 (
alta_slice \macro_inst|trig_ctrl_inst|LessThan6~9 (
	.A(\macro_inst|trig_ctrl_inst|pulse_cnt [4]),
	.B(\macro_inst|trig_ctrl_inst|Add3~8_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|LessThan6~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|trig_ctrl_inst|LessThan6~9_cout ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .mask = 16'h004D;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|LessThan6~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N0
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~3 (
alta_slice \macro_inst|cfg_reg_inst|Selector25~3 (
	.A(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_clk_div [0]),
	.C(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.D(\macro_inst|cfg_reg_inst|trig_threshold [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector25~3 .mask = 16'hF222;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector25~3 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N10
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~1 (
alta_slice \macro_inst|cfg_reg_inst|Selector25~1 (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|cfg_reg_inst|dac_en~q ),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|adc_run~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector25~1 .mask = 16'hD080;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector25~1 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N14
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector19~4 (
// Location: FF_X61_Y8_N14
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[6] (
alta_slice \macro_inst|cfg_reg_inst|prdata[6] (
	.A(\macro_inst|cfg_reg_inst|Selector19~0_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector19~2_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector19~3_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector19~1_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector19~4_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [6]));
defparam \macro_inst|cfg_reg_inst|prdata[6] .mask = 16'hFFFE;
defparam \macro_inst|cfg_reg_inst|prdata[6] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[6] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[6] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[2] (
// Location: LCCOMB_X61_Y8_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~1 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[2] (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [2]));
defparam \macro_inst|trig_ctrl_inst|prdata[2] .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[2] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N18
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~6 (
alta_slice \macro_inst|cfg_reg_inst|Selector25~6 (
	.A(\macro_inst|cfg_reg_inst|Selector25~5_combout ),
	.B(\macro_inst|cfg_reg_inst|Selector25~3_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector25~4_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector25~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector25~6 .mask = 16'hFFFE;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector25~6 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N2
// alta_lcell_comb \macro_inst|cfg_reg_inst|dac_en~_wirecell (
alta_slice \macro_inst|cfg_reg_inst|dac_en~_wirecell (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|dac_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|dac_en~_wirecell_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .mask = 16'h00FF;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .mode = "logic";
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|dac_en~_wirecell .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector5~0 (
// Location: FF_X61_Y8_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[0] (
alta_slice \macro_inst|trig_ctrl_inst|prdata[0] (
	.A(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.B(\macro_inst|trig_ctrl_inst|trig_done~q ),
	.C(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [0]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector5~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [0]));
defparam \macro_inst|trig_ctrl_inst|prdata[0] .mask = 16'hF888;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[3] (
// Location: LCCOMB_X61_Y8_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~2 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[3] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [3]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~2_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [3]));
defparam \macro_inst|trig_ctrl_inst|prdata[3] .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[3] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N26
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~4 (
alta_slice \macro_inst|cfg_reg_inst|Selector25~4 (
	.A(\macro_inst|cfg_reg_inst|Equal0~3_combout ),
	.B(\macro_inst|cfg_reg_inst|adc_en~q ),
	.C(\macro_inst|cfg_reg_inst|frequency [0]),
	.D(\macro_inst|cfg_reg_inst|Equal10~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector25~4 .mask = 16'hF888;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector25~4 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector25~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector25~7 (
// Location: FF_X61_Y8_N28
// alta_lcell_ff \macro_inst|cfg_reg_inst|prdata[0] (
alta_slice \macro_inst|cfg_reg_inst|prdata[0] (
	.A(\macro_inst|cfg_reg_inst|Selector25~1_combout ),
	.B(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.C(\macro_inst|cfg_reg_inst|Selector25~0_combout ),
	.D(\macro_inst|cfg_reg_inst|Selector25~6_combout ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector25~7_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|prdata [0]));
defparam \macro_inst|cfg_reg_inst|prdata[0] .mask = 16'hFFF8;
defparam \macro_inst|cfg_reg_inst|prdata[0] .mode = "logic";
defparam \macro_inst|cfg_reg_inst|prdata[0] .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[0] .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|prdata[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|prdata[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[8] (
// Location: LCCOMB_X61_Y8_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~7 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[8] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [8]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~7_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [8]));
defparam \macro_inst|trig_ctrl_inst|prdata[8] .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[8] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N4
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector19~3 (
alta_slice \macro_inst|cfg_reg_inst|Selector19~3 (
	.A(\macro_inst|cfg_reg_inst|Equal1~1_combout ),
	.B(\macro_inst|cfg_reg_inst|trig_threshold [6]),
	.C(\macro_inst|cfg_reg_inst|Equal2~1_combout ),
	.D(\macro_inst|cfg_reg_inst|adc_clk_div [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|Selector19~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|Selector19~3 .mask = 16'hEAC0;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|Selector19~3 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|Selector19~3 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[1] (
// Location: LCCOMB_X61_Y8_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~0 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[1] (
	.A(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|ahb2apb_inst|paddr [2]),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [1]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [1]));
defparam \macro_inst|trig_ctrl_inst|prdata[1] .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[1] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[1] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|prdata[7] (
// Location: LCCOMB_X61_Y8_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|prdata~6 (
alta_slice \macro_inst|trig_ctrl_inst|prdata[7] (
	.A(\macro_inst|ahb2apb_inst|paddr [2]),
	.B(\macro_inst|ahb2apb_inst|paddr [3]),
	.C(\macro_inst|cfg_reg_inst|Equal0~2_combout ),
	.D(\macro_inst|trig_ctrl_inst|trigger_ptr [7]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|prdata~6_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|prdata [7]));
defparam \macro_inst|trig_ctrl_inst|prdata[7] .mask = 16'h2000;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|prdata[7] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|prdata[7] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y8_N0
alta_clkenctrl clken_ctrl_X61_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|always1~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|always1~2_combout_X61_Y8_SIG_SIG ));
defparam clken_ctrl_X61_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y8_N0
alta_asyncctrl asyncreset_ctrl_X61_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ));
defparam asyncreset_ctrl_X61_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y8_N1
alta_clkenctrl clken_ctrl_X61_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|always11~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|always11~2_combout_X61_Y8_SIG_SIG ));
defparam clken_ctrl_X61_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y8_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X61_Y9_N20
// alta_lcell_comb \macro_inst|cfg_reg_inst|dac_en~2 (
alta_slice \macro_inst|cfg_reg_inst|dac_en~2 (
	.A(\macro_inst|ahb2apb_inst|paddr [3]),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|dac_en~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|dac_en~2 .mask = 16'h8000;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|dac_en~2 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|dac_en~2 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N24
// alta_lcell_ff \macro_inst|cfg_reg_inst|dac_run (
alta_slice \macro_inst|cfg_reg_inst|dac_run (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|dac_run~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|dac_en~2_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|dac_run__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|dac_run~q ));
defparam \macro_inst|cfg_reg_inst|dac_run .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|dac_run .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|dac_run .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_run .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_run .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_run .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_run .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_run .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|dac_run .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|dac_run .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y9_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|always0~0 (
alta_slice \macro_inst|apb_dac0_inst|always0~0 (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|dac_run~q ),
	.C(vcc),
	.D(\macro_inst|cfg_reg_inst|dac_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|always0~0 .mask = 16'h33FF;
defparam \macro_inst|apb_dac0_inst|always0~0 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|always0~0 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y9_N28
// alta_lcell_comb \macro_inst|cfg_reg_inst|adc_run~0 (
alta_slice \macro_inst|cfg_reg_inst|adc_run~0 (
	.A(\macro_inst|cfg_reg_inst|Equal4~0_combout ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\macro_inst|ahb2apb_inst|paddr [3]),
	.D(\macro_inst|cfg_reg_inst|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_run~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|cfg_reg_inst|adc_run~0 .mask = 16'h2000;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .mode = "logic";
defparam \macro_inst|cfg_reg_inst|adc_run~0 .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_run~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N30
// alta_lcell_ff \macro_inst|cfg_reg_inst|adc_restart (
alta_slice \macro_inst|cfg_reg_inst|adc_restart (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|adc_restart~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_run~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|cfg_reg_inst|adc_restart__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|adc_restart~q ));
defparam \macro_inst|cfg_reg_inst|adc_restart .mask = 16'hFF00;
defparam \macro_inst|cfg_reg_inst|adc_restart .mode = "ripple";
defparam \macro_inst|cfg_reg_inst|adc_restart .modeMux = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_restart .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_restart .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_restart .BypassEn = 1'b0;
defparam \macro_inst|cfg_reg_inst|adc_restart .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|adc_restart .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|adc_restart .SyncResetMux = 2'bxx;
defparam \macro_inst|cfg_reg_inst|adc_restart .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y9_N6
// alta_lcell_comb \macro_inst|cfg_reg_inst|Selector24~3 (
// Location: FF_X61_Y9_N6
// alta_lcell_ff \macro_inst|cfg_reg_inst|dac_en (
alta_slice \macro_inst|cfg_reg_inst|dac_en (
	.A(\macro_inst|cfg_reg_inst|adc_restart~q ),
	.B(\macro_inst|ahb2apb_inst|paddr [2]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|cfg_reg_inst|dac_run~q ),
	.Cin(),
	.Qin(\macro_inst|cfg_reg_inst|dac_en~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|dac_en~2_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(SyncReset_X61_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y9_VCC),
	.LutOut(\macro_inst|cfg_reg_inst|Selector24~3_combout ),
	.Cout(),
	.Q(\macro_inst|cfg_reg_inst|dac_en~q ));
defparam \macro_inst|cfg_reg_inst|dac_en .mask = 16'hEE22;
defparam \macro_inst|cfg_reg_inst|dac_en .mode = "logic";
defparam \macro_inst|cfg_reg_inst|dac_en .modeMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en .FeedbackMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en .ShiftMux = 1'b0;
defparam \macro_inst|cfg_reg_inst|dac_en .BypassEn = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_en .CarryEnb = 1'b1;
defparam \macro_inst|cfg_reg_inst|dac_en .AsyncResetMux = 2'b10;
defparam \macro_inst|cfg_reg_inst|dac_en .SyncResetMux = 2'b00;
defparam \macro_inst|cfg_reg_inst|dac_en .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X61_Y9_N0
alta_clkenctrl clken_ctrl_X61_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|dac_en~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|dac_en~2_combout_X61_Y9_SIG_SIG ));
defparam clken_ctrl_X61_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y9_N0
alta_asyncctrl asyncreset_ctrl_X61_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ));
defparam asyncreset_ctrl_X61_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y9_N1
alta_clkenctrl clken_ctrl_X61_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|cfg_reg_inst|adc_run~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|cfg_reg_inst|adc_run~0_combout_X61_Y9_SIG_SIG ));
defparam clken_ctrl_X61_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y9_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y9_N0
alta_syncctrl syncreset_ctrl_X61_Y9(.Din(), .Dout(SyncReset_X61_Y9_GND));
defparam syncreset_ctrl_X61_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y9_N1
alta_syncctrl syncload_ctrl_X61_Y9(.Din(), .Dout(SyncLoad_X61_Y9_VCC));
defparam syncload_ctrl_X61_Y9.SyncCtrlMux = 2'b01;
// Location: FF_X62_Y10_N0
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[0] (
// Location: LCCOMB_X62_Y10_N0
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[0]~16 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[0] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[0]~16_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[0]~17 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [0]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .mask = 16'h33CC;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .mode = "logic";
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .modeMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N10
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[5] (
// Location: LCCOMB_X62_Y10_N10
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[5]~27 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[5] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [5]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[4]~26 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[5]~27_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[5]~28 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [5]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .mask = 16'h5A5F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[5] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N12
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[6] (
// Location: LCCOMB_X62_Y10_N12
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[6]~29 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[6] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[5]~28 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[6]~29_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[6]~30 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [6]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .mask = 16'hA50A;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[6] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N14
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[7] (
// Location: LCCOMB_X62_Y10_N14
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[7]~31 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[7] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[6]~30 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[7]~31_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[7]~32 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [7]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .mask = 16'h3C3F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[7] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N16
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[8] (
// Location: LCCOMB_X62_Y10_N16
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[8]~33 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[8] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [8]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[7]~32 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[8]~33_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[8]~34 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [8]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[8] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N18
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[9] (
// Location: LCCOMB_X62_Y10_N18
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[9]~35 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[9] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[8]~34 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[9]~35_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[9]~36 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [9]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .mask = 16'h3C3F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[9] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N2
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[1] (
// Location: LCCOMB_X62_Y10_N2
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[1]~19 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[1] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[0]~17 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[1]~19_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[1]~20 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [1]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .mask = 16'h3C3F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N20
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[10] (
// Location: LCCOMB_X62_Y10_N20
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[10]~37 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[10] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[9]~36 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[10]~37_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[10]~38 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [10]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[10] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N22
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[11] (
// Location: LCCOMB_X62_Y10_N22
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[11]~39 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[11] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [11]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[10]~38 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[11]~39_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[11]~40 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [11]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .mask = 16'h5A5F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[11] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N24
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[12] (
// Location: LCCOMB_X62_Y10_N24
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[12]~41 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[12] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [12]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[11]~40 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[12]~41_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[12]~42 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [12]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[12] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N26
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[13] (
// Location: LCCOMB_X62_Y10_N26
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[13]~43 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[13] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [13]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[12]~42 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[13]~43_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[13]~44 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [13]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .mask = 16'h5A5F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[13] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N28
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[14] (
// Location: LCCOMB_X62_Y10_N28
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[14]~45 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[14] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [14]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[13]~44 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[14]~45_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[14]~46 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [14]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[14] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N30
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[15] (
// Location: LCCOMB_X62_Y10_N30
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[15]~47 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[15] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [15]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[14]~46 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [15]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[15]~47_combout ),
	.Cout(),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [15]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .mask = 16'h5A5A;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .CarryEnb = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[15] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N4
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[2] (
// Location: LCCOMB_X62_Y10_N4
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[2]~21 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[2] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[1]~20 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[2]~21_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[2]~22 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [2]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N6
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[3] (
// Location: LCCOMB_X62_Y10_N6
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[3]~23 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[3] (
	.A(\macro_inst|apb_adc0_inst|sclk_counter [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[2]~22 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[3]~23_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[3]~24 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [3]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .mask = 16'h5A5F;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[3] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N8
// alta_lcell_ff \macro_inst|apb_adc0_inst|sclk_counter[4] (
// Location: LCCOMB_X62_Y10_N8
// alta_lcell_comb \macro_inst|apb_adc0_inst|sclk_counter[4]~25 (
alta_slice \macro_inst|apb_adc0_inst|sclk_counter[4] (
	.A(vcc),
	.B(\macro_inst|apb_adc0_inst|sclk_counter [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|apb_adc0_inst|sclk_counter[3]~24 ),
	.Qin(\macro_inst|apb_adc0_inst|sclk_counter [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|apb_adc0_inst|sclk_counter[4]~25_combout ),
	.Cout(\macro_inst|apb_adc0_inst|sclk_counter[4]~26 ),
	.Q(\macro_inst|apb_adc0_inst|sclk_counter [4]));
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .mask = 16'hC30C;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .mode = "ripple";
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .modeMux = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .ShiftMux = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .BypassEn = 1'b1;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .CarryEnb = 1'b0;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .SyncResetMux = 2'b10;
defparam \macro_inst|apb_adc0_inst|sclk_counter[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X62_Y10_N0
alta_clkenctrl clken_ctrl_X62_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y10_SIG_VCC ));
defparam clken_ctrl_X62_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y10_N0
alta_asyncctrl asyncreset_ctrl_X62_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ));
defparam asyncreset_ctrl_X62_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y10_N0
alta_syncctrl syncreset_ctrl_X62_Y10(.Din(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout ), .Dout(\macro_inst|apb_adc0_inst|sclk_counter[7]~18_combout__SyncReset_X62_Y10_SIG ));
defparam syncreset_ctrl_X62_Y10.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y10_N1
alta_syncctrl syncload_ctrl_X62_Y10(.Din(), .Dout(SyncLoad_X62_Y10_GND));
defparam syncload_ctrl_X62_Y10.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X62_Y1_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~346 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~346 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~345_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~346_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .mask = 16'h958A;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~346 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~54 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~54 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~54_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .mask = 16'hECC8;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~54 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~58 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~58 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~42_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~57_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~58_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .mask = 16'hE5E0;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~58 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~59 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~59 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~58_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~51_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~346_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~59_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .mask = 16'hDA8A;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~59 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~345 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~345 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~345_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .mask = 16'h7FEA;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~345 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~43 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~43 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~43_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .mask = 16'hBC8E;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~43 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~46 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~46 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~44_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~43_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~46_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .mask = 16'h6662;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~46 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~57 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~57 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~56_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~53_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~55_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~57_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .mask = 16'hBB0C;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~57 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~44 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~44 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~44_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .mask = 16'hB2B0;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~44 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~47 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~47 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~45_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~46_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~47_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .mask = 16'hCF30;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~47 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~52 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~52 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~48_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~51_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~346_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~52_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .mask = 16'h2A7A;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~52 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~55 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~55 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~54_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~55_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .mask = 16'hA4A2;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~55 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~48 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~48 (
	.A(\macro_inst|apb_dac0_inst|phase_r [7]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~42_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~47_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~48_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .mask = 16'hB5B0;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~48 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~53 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~53 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~53_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .mask = 16'hDC00;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~53 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~56 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~56 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~56_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .mask = 16'hBF44;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~56 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~45 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~45 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~44_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~43_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~45_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .mask = 16'hDD3E;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~45 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~63 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~63 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~63_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .mask = 16'h6C68;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~63 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~153 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~153 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~153_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .mask = 16'hF406;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~153 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~66 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~66 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~61_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~65_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~64_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~66_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .mask = 16'h3FA0;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~66 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~158 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~158 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~153_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~157_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~156_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~158_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .mask = 16'h3FA0;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~158 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~42 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~42 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~41_combout ),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~40_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~42_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .mask = 16'h05FA;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~42 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~64 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~64 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~62_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~63_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~64_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .mask = 16'hC7C4;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~64 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~154 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~154 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~154_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .mask = 16'hEF32;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~154 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~156 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~156 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~155_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~154_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~156_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .mask = 16'hC1CD;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~156 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~61 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~61 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~61_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .mask = 16'hD65E;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~61 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~157 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~157 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~157_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .mask = 16'hF7FE;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~157 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~41 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~41 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~39_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~41_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .mask = 16'hA228;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~41 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~40 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~40 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~39_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~40_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .mask = 16'hC96E;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~40 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~62 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~62 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~62_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .mask = 16'hD64E;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~62 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~65 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~65 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~65_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .mask = 16'h96D6;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~65 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~155 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~155 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~155_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .mask = 16'hEA10;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~155 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~39 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~39 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~39_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .mask = 16'hB2F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~39 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~16 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~16 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [8]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~15 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~16_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~17 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~16 .mask = 16'h5AAF;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~16 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~26 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~26 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [13]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~25 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~26_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~27 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~26 .mask = 16'hA505;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~26 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~28 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~28 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [14]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~27 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~28_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~29 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~28 .mask = 16'h5AAF;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~28 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~30 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~30 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~29 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~30_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~31 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~30 .mask = 16'h0F0F;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~30 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~30 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~32 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~32 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~31 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~32_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~32 .mask = 16'h0F0F;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~32 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~32 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr2~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr2~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .mask = 16'h448C;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~18 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~18 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [9]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~17 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~19 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~18 .mask = 16'hC303;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~18 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr0~1 (
// Location: FF_X62_Y3_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[10] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[10] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|WideOr0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr0~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [10]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .mask = 16'h3300;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Decoder0~0 (
// Location: FF_X62_Y3_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[14] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[14] (
	.A(\macro_inst|trig_ctrl_inst|Decoder1~0_combout ),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [14]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Decoder0~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [14]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .mask = 16'hA0A0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[14] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr1~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr1~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .mask = 16'hC488;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr2~1 (
// Location: FF_X62_Y3_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[8] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[8] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|WideOr2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr2~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [8]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .mask = 16'h3300;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr1~1 (
// Location: FF_X62_Y3_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[9] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[9] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|WideOr1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr1~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [9]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .mask = 16'h3300;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Decoder0~2 (
// Location: FF_X62_Y3_N30
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[13] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[13] (
	.A(vcc),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.C(\macro_inst|trig_ctrl_inst|Decoder0~1_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [13]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Decoder0~2_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [13]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .mask = 16'h3030;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[13] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~20 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~20 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [10]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~19 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~21 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~20 .mask = 16'h3CCF;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~20 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~22 (
// Location: FF_X62_Y3_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[11] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[11] (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [11]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|Decoder1~0_combout ),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~21 ),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [11]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(SyncReset_X62_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y3_VCC),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~23 ),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [11]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .mask = 16'hA505;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .SyncResetMux = 2'b00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[11] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X62_Y3_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~24 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~24 (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~23 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~25 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~24 .mask = 16'hF00F;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~24 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~24 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y3_N0
alta_clkenctrl clken_ctrl_X62_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y3_SIG_VCC ));
defparam clken_ctrl_X62_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y3_N0
alta_asyncctrl asyncreset_ctrl_X62_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ));
defparam asyncreset_ctrl_X62_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y3_N0
alta_syncctrl syncreset_ctrl_X62_Y3(.Din(), .Dout(SyncReset_X62_Y3_GND));
defparam syncreset_ctrl_X62_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y3_N1
alta_syncctrl syncload_ctrl_X62_Y3(.Din(), .Dout(SyncLoad_X62_Y3_VCC));
defparam syncload_ctrl_X62_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X62_Y4_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr4~1 (
// Location: FF_X62_Y4_N0
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[6] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[6] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|WideOr4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr4~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [6]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr8~1 (
// Location: FF_X62_Y4_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[0] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|WideOr8~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr8~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [0]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[1] (
// Location: LCCOMB_X62_Y4_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|decim_factor~2 (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|decim_factor~1_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|decim_factor~2_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [1]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr7~1 (
// Location: FF_X62_Y4_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[2] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|WideOr7~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr7~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [2]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~0 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~0 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [0]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~0_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~1 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~0 .mask = 16'hAA55;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Add0~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~2 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~2 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~1 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~2_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~3 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~2 .mask = 16'hA505;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~2 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N2
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr6~1 (
// Location: FF_X62_Y4_N2
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[4] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[4] (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|WideOr6~0_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr6~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [4]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .mask = 16'h5050;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~4 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~4 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~3 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~4_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~5 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~4 .mask = 16'h3CCF;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~4 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~6 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~6 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~5 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~6_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~7 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~6 .mask = 16'hC303;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~6 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~8 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~8 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~7 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~8_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~9 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~8 .mask = 16'h3CCF;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~8 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~10 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~10 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~9 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~10_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~11 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~10 .mask = 16'hC303;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~10 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~12 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~12 (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|decim_factor [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~11 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~12_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~13 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~12 .mask = 16'h3CCF;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~12 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Add0~14 (
alta_slice \macro_inst|trig_ctrl_inst|Add0~14 (
	.A(\macro_inst|trig_ctrl_inst|decim_factor [7]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|Add0~13 ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Add0~14_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|Add0~15 ),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Add0~14 .mask = 16'hA505;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|Add0~14 .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Add0~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr5~1 (
// Location: FF_X62_Y4_N4
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[5] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[5] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|WideOr5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr5~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [5]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y4_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr3~1 (
// Location: FF_X62_Y4_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[7] (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|trig_ctrl_inst|WideOr3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr3~1_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [7]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .mask = 16'h0F00;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|decim_factor[3] (
// Location: LCCOMB_X62_Y4_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|decim_factor~0 (
alta_slice \macro_inst|trig_ctrl_inst|decim_factor[3] (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|decim_factor [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|decim_factor~0_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|decim_factor [3]));
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .mask = 16'h0408;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|decim_factor[3] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y4_N0
alta_clkenctrl clken_ctrl_X62_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y4_SIG_VCC ));
defparam clken_ctrl_X62_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y4_N0
alta_asyncctrl asyncreset_ctrl_X62_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ));
defparam asyncreset_ctrl_X62_Y4_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X62_Y5_N0
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always5~0 (
alta_slice \macro_inst|trig_ctrl_inst|always5~0 (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]),
	.C(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always5~0 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|always5~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always5~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[0] (
// Location: LCCOMB_X62_Y5_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[0]~10 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[0] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]),
	.B(\macro_inst|trig_ctrl_inst|write_strobe~q ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[0]~10_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[0]~11 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [0]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .mask = 16'h6688;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[1] (
// Location: LCCOMB_X62_Y5_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[1]~13 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[1] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[0]~11 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[1]~13_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[1]~14 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [1]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[2] (
// Location: LCCOMB_X62_Y5_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[2]~15 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[2] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[1]~14 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[2]~15_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[2]~16 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [2]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[3] (
// Location: LCCOMB_X62_Y5_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[3]~17 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[3] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[2]~16 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[3]~17_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[3]~18 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [3]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[3] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[4] (
// Location: LCCOMB_X62_Y5_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[4]~19 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[3]~18 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[4]~19_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[4]~20 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[4] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[5] (
// Location: LCCOMB_X62_Y5_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[5]~21 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[5] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[4]~20 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[5]~21_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[5]~22 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[5] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[6] (
// Location: LCCOMB_X62_Y5_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[6]~23 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[6] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[5]~22 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~23_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~24 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[6] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N24
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[7] (
// Location: LCCOMB_X62_Y5_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[7]~25 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~24 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[7]~25_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[7]~26 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[7] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N26
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[8] (
// Location: LCCOMB_X62_Y5_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[8]~27 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[8] (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[7]~26 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[8]~27_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|ram_wr_addr[8]~28 ),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[8] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y5_N28
// alta_lcell_ff \macro_inst|trig_ctrl_inst|ram_wr_addr[9] (
// Location: LCCOMB_X62_Y5_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|ram_wr_addr[9]~29 (
alta_slice \macro_inst|trig_ctrl_inst|ram_wr_addr[9] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.Cin(\macro_inst|trig_ctrl_inst|ram_wr_addr[8]~28 ),
	.Qin(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|ram_wr_addr[9]~29_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]));
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .mask = 16'h0FF0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|ram_wr_addr[9] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y5_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always5~1 (
alta_slice \macro_inst|trig_ctrl_inst|always5~1 (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [5]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [4]),
	.C(\macro_inst|trig_ctrl_inst|ram_wr_addr [6]),
	.D(\macro_inst|trig_ctrl_inst|ram_wr_addr [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always5~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always5~1 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|always5~1 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always5~1 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~1 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~1 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~1 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~1 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always5~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y5_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|always5~2 (
alta_slice \macro_inst|trig_ctrl_inst|always5~2 (
	.A(\macro_inst|trig_ctrl_inst|ram_wr_addr [8]),
	.B(\macro_inst|trig_ctrl_inst|ram_wr_addr [9]),
	.C(\macro_inst|trig_ctrl_inst|always5~1_combout ),
	.D(\macro_inst|trig_ctrl_inst|always5~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|always5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|always5~2 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|always5~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|always5~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|always5~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|always5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|always5~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y5_N1
alta_clkenctrl clken_ctrl_X62_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|ram_wr_addr[6]~12_combout_X62_Y5_SIG_SIG ));
defparam clken_ctrl_X62_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y5_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y5_N1
alta_asyncctrl asyncreset_ctrl_X62_Y5_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ));
defparam asyncreset_ctrl_X62_Y5_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y5_N0
alta_syncctrl syncreset_ctrl_X62_Y5(.Din(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ), .Dout(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y5_SIG ));
defparam syncreset_ctrl_X62_Y5.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y5_N1
alta_syncctrl syncload_ctrl_X62_Y5(.Din(), .Dout(SyncLoad_X62_Y5_GND));
defparam syncload_ctrl_X62_Y5.SyncCtrlMux = 2'b00;
// Location: FF_X62_Y6_N10
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[2] (
// Location: LCCOMB_X62_Y6_N10
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[2]~14 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[2] (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[1]~13 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[2]~14_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[2]~15 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [2]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N12
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[3] (
// Location: LCCOMB_X62_Y6_N12
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[3]~16 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[3] (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[2]~15 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[3]~16_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[3]~17 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [3]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .mask = 16'h5A5F;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N14
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[4] (
// Location: LCCOMB_X62_Y6_N14
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[4]~18 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[4] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[3]~17 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[4]~18_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[4]~19 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [4]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[4] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N16
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[5] (
// Location: LCCOMB_X62_Y6_N16
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[5]~20 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[5] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[4]~19 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[5]~20_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[5]~21 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [5]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[5] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N18
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[6] (
// Location: LCCOMB_X62_Y6_N18
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[6]~22 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[6] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[5]~21 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[6]~22_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[6]~23 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [6]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .mask = 16'hC30C;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[6] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N20
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[7] (
// Location: LCCOMB_X62_Y6_N20
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[7]~24 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[7] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [7]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[6]~23 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[7]~24_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[7]~25 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [7]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[7] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N22
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[8] (
// Location: LCCOMB_X62_Y6_N22
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[8]~26 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[8] (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [8]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[7]~25 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[8]~26_combout ),
	.Cout(),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [8]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .mask = 16'hA5A5;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[8] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y6_N24
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~3 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~3 (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [6]),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [5]),
	.C(\macro_inst|trig_ctrl_inst|post_trig_cnt [4]),
	.D(\macro_inst|trig_ctrl_inst|post_trig_cnt [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N26
// alta_lcell_comb \macro_inst|trig_ctrl_inst|WideOr0~0 (
alta_slice \macro_inst|trig_ctrl_inst|WideOr0~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [1]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|WideOr0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .mask = 16'hA028;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|WideOr0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N28
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Decoder1~0 (
alta_slice \macro_inst|trig_ctrl_inst|Decoder1~0 (
	.A(\macro_inst|cfg_reg_inst|trig_time_slot [4]),
	.B(\macro_inst|cfg_reg_inst|trig_time_slot [2]),
	.C(\macro_inst|cfg_reg_inst|trig_time_slot [0]),
	.D(\macro_inst|cfg_reg_inst|trig_time_slot [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Decoder1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .mask = 16'h4000;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Decoder1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N30
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~2 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~2 (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [2]),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [1]),
	.C(\macro_inst|trig_ctrl_inst|post_trig_cnt [3]),
	.D(\macro_inst|trig_ctrl_inst|post_trig_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .mask = 16'h8000;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N4
// alta_lcell_comb \macro_inst|trig_ctrl_inst|Selector0~4 (
alta_slice \macro_inst|trig_ctrl_inst|Selector0~4 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|trig_ctrl_inst|post_trig_cnt [8]),
	.D(\macro_inst|trig_ctrl_inst|Selector0~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|trig_ctrl_inst|Selector0~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .mask = 16'hF000;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .BypassEn = 1'b0;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .CarryEnb = 1'b1;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|trig_ctrl_inst|Selector0~4 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N6
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[0] (
// Location: LCCOMB_X62_Y6_N6
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[0]~9 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[0] (
	.A(\macro_inst|trig_ctrl_inst|post_trig_cnt [0]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[0]~9_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[0]~10 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [0]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .mask = 16'h55AA;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .mode = "logic";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y6_N8
// alta_lcell_ff \macro_inst|trig_ctrl_inst|post_trig_cnt[1] (
// Location: LCCOMB_X62_Y6_N8
// alta_lcell_comb \macro_inst|trig_ctrl_inst|post_trig_cnt[1]~12 (
alta_slice \macro_inst|trig_ctrl_inst|post_trig_cnt[1] (
	.A(vcc),
	.B(\macro_inst|trig_ctrl_inst|post_trig_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|trig_ctrl_inst|post_trig_cnt[0]~10 ),
	.Qin(\macro_inst|trig_ctrl_inst|post_trig_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_GND),
	.LutOut(\macro_inst|trig_ctrl_inst|post_trig_cnt[1]~12_combout ),
	.Cout(\macro_inst|trig_ctrl_inst|post_trig_cnt[1]~13 ),
	.Q(\macro_inst|trig_ctrl_inst|post_trig_cnt [1]));
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .mode = "ripple";
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|trig_ctrl_inst|post_trig_cnt[1] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X62_Y6_N1
alta_clkenctrl clken_ctrl_X62_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|trig_ctrl_inst|post_trig_cnt[8]~11_combout_X62_Y6_SIG_SIG ));
defparam clken_ctrl_X62_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y6_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y6_N1
alta_asyncctrl asyncreset_ctrl_X62_Y6_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ));
defparam asyncreset_ctrl_X62_Y6_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y6_N0
alta_syncctrl syncreset_ctrl_X62_Y6(.Din(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout ), .Dout(\macro_inst|trig_ctrl_inst|adc_restart_ris~combout__SyncReset_X62_Y6_SIG ));
defparam syncreset_ctrl_X62_Y6.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y6_N1
alta_syncctrl syncload_ctrl_X62_Y6(.Din(), .Dout(SyncLoad_X62_Y6_GND));
defparam syncload_ctrl_X62_Y6.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X62_Y7_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~89 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~89 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~87_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~84_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~88_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~89_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .mask = 16'hEA4A;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~89 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~19 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~19 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~19_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .mask = 16'h8080;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~88 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~88 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~88_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .mask = 16'h41FC;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~88 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~245 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~245 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~19_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~245_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .mask = 16'hFA03;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~245 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~94 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~94 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~94_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .mask = 16'h3F55;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~94 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~86 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~86 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~86_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .mask = 16'hE916;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~86 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~95 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~95 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~94_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~19_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~95_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .mask = 16'h5F54;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~95 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~85 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~85 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~85_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .mask = 16'h03C8;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~85 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~87 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~87 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~85_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~86_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~87_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .mask = 16'hADA8;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~87 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~84 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~84 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~84_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .mask = 16'h7E96;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~84 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~20 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~20 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~19_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~20_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .mask = 16'h05C3;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~20 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~2 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~2 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .mask = 16'hAA80;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~96 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~96 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~95_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(\macro_inst|apb_dac0_inst|phase_r [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~96_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .mask = 16'hFEAA;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~96 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~83 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~83 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|sine_rom~82_combout ),
	.C(\macro_inst|apb_dac0_inst|sine_rom~81_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~83_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .mask = 16'h0F33;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~83 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~99 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~99 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~99_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .mask = 16'h1500;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~99 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~101 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~101 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~100_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~89_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~101_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .mask = 16'hBA98;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~101 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~92 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~92 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~90_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [3]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~91_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~92_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .mask = 16'h3692;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~92 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~97 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~97 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~96_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~93_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~83_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~97_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .mask = 16'h707C;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~97 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~91 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~91 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~91_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .mask = 16'h3300;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~91 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~79 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~79 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~79_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .mask = 16'hB5E8;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~79 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~80 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~80 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [0]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~80_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .mask = 16'hEA00;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~80 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~82 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~82 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~80_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~79_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~82_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .mask = 16'h94A4;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~82 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~81 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~81 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~80_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~79_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~81_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .mask = 16'hE654;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~81 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~98 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~98 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~98_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .mask = 16'hF0FE;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~98 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~102 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~102 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~96_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [7]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~101_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~83_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~102_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .mask = 16'hBCB0;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~102 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~93 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~93 (
	.A(\macro_inst|apb_dac0_inst|phase_r [6]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~89_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [7]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~92_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~93_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .mask = 16'hA7A2;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~93 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~90 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~90 (
	.A(\macro_inst|apb_dac0_inst|phase_r [5]),
	.B(\macro_inst|apb_dac0_inst|phase_r [4]),
	.C(\macro_inst|apb_dac0_inst|phase_r [0]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~90_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .mask = 16'hEAFE;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~90 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y8_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~100 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~100 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~99_combout ),
	.B(\macro_inst|apb_dac0_inst|sine_rom~98_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~100_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .mask = 16'hBD4A;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~100 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N0
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~74 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~74 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~73_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [5]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~70_combout ),
	.D(\macro_inst|apb_dac0_inst|phase_r [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~74_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .mask = 16'hCCE2;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~74 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N10
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~73 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~73 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~72_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~71_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~73_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .mask = 16'hBF1F;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~73 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N12
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~116 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~116 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~116_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .mask = 16'hE0CE;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~116 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N14
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~50 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~50 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~50_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .mask = 16'h0C10;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~50 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N16
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~71 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~71 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~71_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .mask = 16'h10F0;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~71 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N18
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~67 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~67 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~67_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .mask = 16'hCF0E;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~67 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N2
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~72 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~72 (
	.A(\macro_inst|apb_dac0_inst|phase_r [0]),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [4]),
	.D(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~72_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .mask = 16'h0070;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~72 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N20
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[2] (
// Location: LCCOMB_X62_Y9_N20
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_r[2]~feeder (
alta_slice \macro_inst|apb_dac0_inst|phase_r[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|apb_dac0_inst|phase_acc [24]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X62_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|phase_r[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [2]));
defparam \macro_inst|apb_dac0_inst|phase_r[2] .mask = 16'hF0F0;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[2] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|phase_r[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N22
// alta_lcell_ff \macro_inst|apb_dac0_inst|phase_r[3] (
// Location: LCCOMB_X62_Y9_N22
// alta_lcell_comb \macro_inst|apb_dac0_inst|phase_r[3]~feeder (
alta_slice \macro_inst|apb_dac0_inst|phase_r[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|apb_dac0_inst|phase_acc [25]),
	.Cin(),
	.Qin(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X62_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|phase_r[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|apb_dac0_inst|phase_r [3]));
defparam \macro_inst|apb_dac0_inst|phase_r[3] .mask = 16'hFF00;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .mode = "logic";
defparam \macro_inst|apb_dac0_inst|phase_r[3] .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|phase_r[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N24
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~49 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~49 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [3]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~49_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .mask = 16'h0404;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~49 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N26
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~69 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~69 (
	.A(vcc),
	.B(\macro_inst|apb_dac0_inst|phase_r [1]),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~69_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .mask = 16'hC300;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~69 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N28
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~117 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~117 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|sine_rom~115_combout ),
	.D(\macro_inst|apb_dac0_inst|sine_rom~116_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~117_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .mask = 16'hA78F;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~117 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N30
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~115 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~115 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~72_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [5]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~115_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .mask = 16'hB0B0;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~115 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N4
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~51 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~51 (
	.A(\macro_inst|apb_dac0_inst|phase_r [3]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~50_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~49_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~51_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .mask = 16'hFFF2;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~51 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N6
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~68 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~68 (
	.A(\macro_inst|apb_dac0_inst|phase_r [4]),
	.B(\macro_inst|apb_dac0_inst|sine_rom~67_combout ),
	.C(\macro_inst|apb_dac0_inst|phase_r [6]),
	.D(\macro_inst|apb_dac0_inst|phase_r [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~68_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .mask = 16'hBB45;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~68 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N8
// alta_lcell_comb \macro_inst|apb_dac0_inst|sine_rom~70 (
alta_slice \macro_inst|apb_dac0_inst|sine_rom~70 (
	.A(\macro_inst|apb_dac0_inst|sine_rom~69_combout ),
	.B(\macro_inst|apb_dac0_inst|phase_r [2]),
	.C(\macro_inst|apb_dac0_inst|phase_r [1]),
	.D(\macro_inst|apb_dac0_inst|sine_rom~68_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|apb_dac0_inst|sine_rom~70_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .mask = 16'h7D80;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .mode = "logic";
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .modeMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .FeedbackMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .ShiftMux = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .BypassEn = 1'b0;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .CarryEnb = 1'b1;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .AsyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .SyncResetMux = 2'bxx;
defparam \macro_inst|apb_dac0_inst|sine_rom~70 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y9_N0
alta_clkenctrl clken_ctrl_X62_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X62_Y9_SIG_VCC ));
defparam clken_ctrl_X62_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y9_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y9_N0
alta_asyncctrl asyncreset_ctrl_X62_Y9_N0(.Din(), .Dout(AsyncReset_X62_Y9_GND));
defparam asyncreset_ctrl_X62_Y9_N0.AsyncCtrlMux = 2'b00;
endmodule