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9102_APP
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alta_db
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fmax.rpt

fmax.rpt 7.6 KB
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  1. Fmax report
    2. 

  2.   User constraint:   8.000MHz, Fmax: 118.329MHz, Clock: PIN_HSE
    3. 

  3.   User constraint:  10.000MHz, Fmax: 118.329MHz, Clock: PIN_HSI
    4. 

  4.   User constraint: 104.000MHz, Fmax: 118.329MHz, Clock: pll_inst|auto_generated|pll1|clk[0]
    5. 

  5. 

  6. 

  7. 

  8. Setup from macro_inst|cfg_reg_inst|trig_threshold[0] to clken_ctrl_X58_Y6_N1, clock pll_inst|auto_generated|pll1|clk[0], constraint 9.615, skew -0.332, data 8.029
    9. 

  9.   Slack:   1.164
    10. 

  10.     Arrival Time:    8.966
    11. 

  11.         0.000    0.000   R                         Launch Clock Edge
    12. 

  12.       Launch Clock Path:
    13. 

  13.         0.000    0.000   RR                  example_board|PLL_CLKIN =>                    PLL_CLKIN~input|padio 
    14. 

  14.         1.309    1.309   RR                    PLL_CLKIN~input|padio =>                  PLL_CLKIN~input|combout 
    15. 

  15.         1.546    0.237   RR                  PLL_CLKIN~input|combout =>       pll_inst|auto_generated|pll1|clkin 
    16. 

  16.       Compensation Path:
    17. 

  17.        -2.390   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
    18. 

  18.        -2.390   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
    19. 

  19.       Compensation Path End
    20. 

  20.        -1.410    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout0 D
    21. 

  21.        -1.410    0.000   RR     pll_inst|auto_generated|pll1|clkout0 => gclksw_inst|gclk_switch__alta_gclksw|clkin2 D
    22. 

  22.        -1.008    0.402   RR gclksw_inst|gclk_switch__alta_gclksw|clkin2 => gclksw_inst|gclk_switch__alta_gclksw|clkout 
    23. 

  23.        -0.895    0.113   RR gclksw_inst|gclk_switch__alta_gclksw|clkout =>            gclksw_inst|gclk_switch|inclk 
    24. 

  24.        -0.895    0.000   RR            gclksw_inst|gclk_switch|inclk =>           gclksw_inst|gclk_switch|outclk 
    25. 

  25.         0.656    1.551   RR           gclksw_inst|gclk_switch|outclk =>               clken_ctrl_X58_Y4_N0|ClkIn 
    26. 

  26.         0.804    0.148   RR               clken_ctrl_X58_Y4_N0|ClkIn =>              clken_ctrl_X58_Y4_N0|ClkOut 
    27. 

  27.         0.937    0.133   RR              clken_ctrl_X58_Y4_N0|ClkOut => macro_inst|cfg_reg_inst|trig_threshold[0]|Clk 
    28. 

  28.       Data Path:
    29. 

  29.         1.172    0.235   RF macro_inst|cfg_reg_inst|trig_threshold[0]|Clk => macro_inst|cfg_reg_inst|trig_threshold[0]|Q D
    30. 

  30.         2.530    1.358   FF macro_inst|cfg_reg_inst|trig_threshold[0]|Q =>  macro_inst|trig_ctrl_inst|LessThan3~1|B 
    31. 

  31.         2.980    0.450   FF  macro_inst|trig_ctrl_inst|LessThan3~1|B => macro_inst|trig_ctrl_inst|LessThan3~1|Cout 
    32. 

  32.         2.980    0.000   FF macro_inst|trig_ctrl_inst|LessThan3~1|Cout => macro_inst|trig_ctrl_inst|LessThan3~3|Cin 
    33. 

  33.         3.046    0.066   FR macro_inst|trig_ctrl_inst|LessThan3~3|Cin => macro_inst|trig_ctrl_inst|LessThan3~3|Cout 
    34. 

  34.         3.046    0.000   RR macro_inst|trig_ctrl_inst|LessThan3~3|Cout => macro_inst|trig_ctrl_inst|LessThan3~5|Cin 
    35. 

  35.         3.111    0.065   RF macro_inst|trig_ctrl_inst|LessThan3~5|Cin => macro_inst|trig_ctrl_inst|LessThan3~5|Cout 
    36. 

  36.         3.111    0.000   FF macro_inst|trig_ctrl_inst|LessThan3~5|Cout => macro_inst|cfg_reg_inst|trig_threshold[3]|Cin 
    37. 

  37.         3.177    0.066   FR macro_inst|cfg_reg_inst|trig_threshold[3]|Cin => macro_inst|cfg_reg_inst|trig_threshold[3]|Cout 
    38. 

  38.         3.177    0.000   RR macro_inst|cfg_reg_inst|trig_threshold[3]|Cout =>   macro_inst|apb_adc0_inst|apb_db[4]|Cin 
    39. 

  39.         3.242    0.065   RF   macro_inst|apb_adc0_inst|apb_db[4]|Cin =>  macro_inst|apb_adc0_inst|apb_db[4]|Cout 
    40. 

  40.         3.242    0.000   FF  macro_inst|apb_adc0_inst|apb_db[4]|Cout => macro_inst|cfg_reg_inst|trig_threshold[5]|Cin 
    41. 

  41.         3.308    0.066   FR macro_inst|cfg_reg_inst|trig_threshold[5]|Cin => macro_inst|cfg_reg_inst|trig_threshold[5]|Cout 
    42. 

  42.         3.308    0.000   RR macro_inst|cfg_reg_inst|trig_threshold[5]|Cout =>   macro_inst|apb_adc0_inst|apb_db[6]|Cin 
    43. 

  43.         3.373    0.065   RF   macro_inst|apb_adc0_inst|apb_db[6]|Cin =>  macro_inst|apb_adc0_inst|apb_db[6]|Cout 
    44. 

  44.         3.373    0.000   FF  macro_inst|apb_adc0_inst|apb_db[6]|Cout => macro_inst|cfg_reg_inst|trig_threshold[7]|Cin 
    45. 

  45.         3.439    0.066   FR macro_inst|cfg_reg_inst|trig_threshold[7]|Cin => macro_inst|cfg_reg_inst|trig_threshold[7]|Cout 
    46. 

  46.         3.439    0.000   RR macro_inst|cfg_reg_inst|trig_threshold[7]|Cout =>   macro_inst|apb_adc0_inst|apb_db[8]|Cin 
    47. 

  47.         3.504    0.065   RF   macro_inst|apb_adc0_inst|apb_db[8]|Cin =>  macro_inst|apb_adc0_inst|apb_db[8]|Cout 
    48. 

  48.         3.504    0.000   FF  macro_inst|apb_adc0_inst|apb_db[8]|Cout => macro_inst|cfg_reg_inst|trig_threshold[9]|Cin 
    49. 

  49.         3.570    0.066   FR macro_inst|cfg_reg_inst|trig_threshold[9]|Cin => macro_inst|cfg_reg_inst|trig_threshold[9]|Cout 
    50. 

  50.         3.570    0.000   RR macro_inst|cfg_reg_inst|trig_threshold[9]|Cout =>  macro_inst|apb_adc0_inst|apb_db[10]|Cin 
    51. 

  51.         3.635    0.065   RF  macro_inst|apb_adc0_inst|apb_db[10]|Cin => macro_inst|apb_adc0_inst|apb_db[10]|Cout 
    52. 

  52.         3.635    0.000   FF macro_inst|apb_adc0_inst|apb_db[10]|Cout =>  macro_inst|apb_adc0_inst|apb_db[11]|Cin 
    53. 

  53.         4.059    0.424   FF  macro_inst|apb_adc0_inst|apb_db[11]|Cin => macro_inst|apb_adc0_inst|apb_db[11]|LutOut 
    54. 

  54.         5.137    1.078   FF macro_inst|apb_adc0_inst|apb_db[11]|LutOut => macro_inst|trig_ctrl_inst|edge_trigger~0|B 
    55. 

  55.         5.671    0.534   FR macro_inst|trig_ctrl_inst|edge_trigger~0|B => macro_inst|trig_ctrl_inst|edge_trigger~0|LutOut 
    56. 

  56.         6.072    0.401   RR macro_inst|trig_ctrl_inst|edge_trigger~0|LutOut => macro_inst|trig_ctrl_inst|edge_trigger~2|C 
    57. 

  57.         6.355    0.283   RR macro_inst|trig_ctrl_inst|edge_trigger~2|C => macro_inst|trig_ctrl_inst|edge_trigger~2|LutOut 
    58. 

  58.         7.234    0.879   RR macro_inst|trig_ctrl_inst|edge_trigger~2|LutOut => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|D 
    59. 

  59.         7.335    0.101   RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|D => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|LutOut 
    60. 

  60.         8.209    0.874   RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|LutOut => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|D 
    61. 

  61.         8.310    0.101   RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|D => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|LutOut 
    62. 

  62.         8.966    0.656   RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|LutOut =>               clken_ctrl_X58_Y6_N1|ClkEn E
    63. 

  63.     Required Time:  10.130
    64. 

  64.         9.615    9.615   R                          Latch Clock Edge
    65. 

  65.       Latch Clock Path:
    66. 

  66.         9.615    0.000   RR                  example_board|PLL_CLKIN =>                    PLL_CLKIN~input|padio 
    67. 

  67.        10.924    1.309   RR                    PLL_CLKIN~input|padio =>                  PLL_CLKIN~input|combout 
    68. 

  68.        11.151    0.227   RR                  PLL_CLKIN~input|combout =>       pll_inst|auto_generated|pll1|clkin 
    69. 

  69.       Compensation Path:
    70. 

  70.         7.215   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
    71. 

  71.         7.215   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
    72. 

  72.       Compensation Path End
    73. 

  73.         8.195    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout0 D
    74. 

  74.         8.195    0.000   RR     pll_inst|auto_generated|pll1|clkout0 => gclksw_inst|gclk_switch__alta_gclksw|clkin2 D
    75. 

  75.         8.597    0.402   RR gclksw_inst|gclk_switch__alta_gclksw|clkin2 => gclksw_inst|gclk_switch__alta_gclksw|clkout 
    76. 

  76.         8.710    0.113   RR gclksw_inst|gclk_switch__alta_gclksw|clkout =>            gclksw_inst|gclk_switch|inclk 
    77. 

  77.         8.710    0.000   RR            gclksw_inst|gclk_switch|inclk =>           gclksw_inst|gclk_switch|outclk 
    78. 

  78.        10.220    1.510   RR           gclksw_inst|gclk_switch|outclk =>               clken_ctrl_X58_Y6_N1|ClkIn 
    79. 

  79.        10.120   -0.100   R                                     Setup
    80. 

  80.        10.130    0.010                               Clock Variation
    81. 

  81.