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Pierakstīties
P_9102
/
9102_APP
2
0
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Faili Problēmas 0 Izmaiņu pieprasījumi 0 Vikivietne
Koks: f926a092c7
Atzari Tagi
9102_APP
/
logic
/
db
/
example_board.map.qmsg

example_board.map.qmsg 754 KB
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  1. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778307515584 ""}
    2. 

  2. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778307515585 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:18:35 2026 " "Processing started: Sat May 09 14:18:35 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778307515585 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778307515585 ""}
    3. 

  3. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board " "Command: quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778307515585 ""}
    4. 

  4. { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1778307515960 ""}
    5. 

  5. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "POST_TRIG_CNT post_trig_cnt trig_ctrl.v(26) " "Verilog HDL Declaration information at trig_ctrl.v(26): object \"POST_TRIG_CNT\" differs only in case from object \"post_trig_cnt\" in the same scope" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 26 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778307516004 ""}
    6. 

  6. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trig_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file trig_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 trig_ctrl " "Found entity 1: trig_ctrl" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516006 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516006 ""}
    7. 

  7. { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "cfg_reg.v(121) " "Verilog HDL information at cfg_reg.v(121): always construct contains both blocking and non-blocking assignments" {  } { { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 121 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1778307516009 ""}
    8. 

  8. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cfg_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file cfg_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 cfg_reg " "Found entity 1: cfg_reg" {  } { { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516009 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516009 ""}
    9. 

  9. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "apb2ram.v 1 1 " "Found 1 design units, including 1 entities, in source file apb2ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 apb2ram " "Found entity 1: apb2ram" {  } { { "apb2ram.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516011 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516011 ""}
    10. 

  10. { "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "baud_detect.v(49) " "Verilog HDL information at baud_detect.v(49): always construct contains both blocking and non-blocking assignments" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 49 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1778307516013 ""}
    11. 

  11. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_detect.v 1 1 " "Found 1 design units, including 1 entities, in source file baud_detect.v" { { "Info" "ISGN_ENTITY_NAME" "1 baud_detect " "Found entity 1: baud_detect" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516014 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516014 ""}
    12. 

  12. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ahb2apb.v 1 1 " "Found 1 design units, including 1 entities, in source file ahb2apb.v" { { "Info" "ISGN_ENTITY_NAME" "1 ahb2apb " "Found entity 1: ahb2apb" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516019 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516019 ""}
    13. 

  13. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "example_board.v 1 1 " "Found 1 design units, including 1 entities, in source file example_board.v" { { "Info" "ISGN_ENTITY_NAME" "1 example_board " "Found entity 1: example_board" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516022 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516022 ""}
    14. 

  14. { "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "analog_ip.v(314) " "Verilog HDL Module Instantiation warning at analog_ip.v(314): ignored dangling comma in List of Port Connections" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "Quartus II" 0 -1 1778307516024 ""}
    15. 

  15. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BAUD_RATE baud_rate analog_ip.v(4) " "Verilog HDL Declaration information at analog_ip.v(4): object \"BAUD_RATE\" differs only in case from object \"baud_rate\" in the same scope" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 4 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778307516025 ""}
    16. 

  16. { "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ram_style analog_ip.v(634) " "Unrecognized synthesis attribute \"ram_style\" at analog_ip.v(634)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 634 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1778307516025 ""}
    17. 

  17. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "analog_ip.v 3 3 " "Found 3 design units, including 3 entities, in source file analog_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 analog_ip " "Found entity 1: analog_ip" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516026 ""} { "Info" "ISGN_ENTITY_NAME" "2 apb_adc " "Found entity 2: apb_adc" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 497 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516026 ""} { "Info" "ISGN_ENTITY_NAME" "3 apb_dac " "Found entity 3: apb_dac" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 591 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516026 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516026 ""}
    18. 

  18. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4171) " "Verilog HDL Declaration information at alta_sim.v(4171): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4171 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778307516033 ""}
    19. 

  19. { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "alta_sim.v(4325) " "Verilog HDL warning at alta_sim.v(4325): extended using \"x\" or \"z\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4325 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1778307516033 ""}
    20. 

  20. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4376) " "Verilog HDL Declaration information at alta_sim.v(4376): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4376 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778307516034 ""}
    21. 

  21. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v 57 57 " "Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" { { "Info" "ISGN_ENTITY_NAME" "1 alta_slice " "Found entity 1: alta_slice" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "2 alta_clkenctrl_rst " "Found entity 2: alta_clkenctrl_rst" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 85 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "3 alta_clkenctrl " "Found entity 3: alta_clkenctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "4 alta_asyncctrl " "Found entity 4: alta_asyncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 118 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "5 alta_syncctrl " "Found entity 5: alta_syncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 132 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "6 alta_io_gclk " "Found entity 6: alta_io_gclk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 146 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "7 alta_gclksel " "Found entity 7: alta_gclksel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 159 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "8 alta_gclkgen " "Found entity 8: alta_gclkgen" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 171 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "9 alta_gclkgen0 " "Found entity 9: alta_gclkgen0" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 184 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "10 alta_gclkgen2 " "Found entity 10: alta_gclkgen2" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "11 alta_io " "Found entity 11: alta_io" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 209 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "12 alta_rio " "Found entity 12: alta_rio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 275 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "13 alta_srff " "Found entity 13: alta_srff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 343 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "14 alta_dff " "Found entity 14: alta_dff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 366 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "15 alta_ufm_gddd " "Found entity 15: alta_ufm_gddd" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 373 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "16 alta_dff_stall " "Found entity 16: alta_dff_stall" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 377 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "17 alta_srlat " "Found entity 17: alta_srlat" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "18 alta_dio " "Found entity 18: alta_dio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 402 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "19 alta_indel " "Found entity 19: alta_indel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "20 alta_dpclkdel " "Found entity 20: alta_dpclkdel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 509 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "21 alta_ufms " "Found entity 21: alta_ufms" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 520 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "22 alta_ufms_sim " "Found entity 22: alta_ufms_sim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 546 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "23 alta_pll " "Found entity 23: alta_pll" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 902 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "24 alta_pllx " "Found entity 24: alta_pllx" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 960 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "25 pll_clk_trim " "Found entity 25: pll_clk_trim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "26 alta_pllv " "Found entity 26: alta_pllv" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1999 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "27 alta_pllve " "Found entity 27: alta_pllve" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "28 alta_sram " "Found entity 28: alta_sram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2310 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "29 alta_dpram16x4 " "Found entity 29: alta_dpram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2349 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "30 alta_spram16x4 " "Found entity 30: alta_spram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2367 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "31 alta_wram " "Found entity 31: alta_wram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "32 alta_bram_pulse_generator " "Found entity 32: alta_bram_pulse_generator" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2423 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "33 alta_bram " "Found entity 33: alta_bram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2440 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "34 alta_boot " "Found entity 34: alta_boot" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2611 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "35 alta_osc " "Found entity 35: alta_osc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2625 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "36 alta_ufml " "Found entity 36: alta_ufml" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2640 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "37 alta_jtag " "Found entity 37: alta_jtag" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2649 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "38 alta_mult " "Found entity 38: alta_mult" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2682 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "39 alta_dff_en " "Found entity 39: alta_dff_en" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2754 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "40 alta_multm_add " "Found entity 40: alta_multm_add" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2762 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "41 alta_multm " "Found entity 41: alta_multm" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2785 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "42 alta_i2c " "Found entity 42: alta_i2c" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3020 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "43 alta_spi " "Found entity 43: alta_spi" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3057 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "44 alta_irda " "Found entity 44: alta_irda" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3104 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "45 alta_bram9k " "Found entity 45: alta_bram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3124 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "46 alta_mcu " "Found entity 46: alta_mcu" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3365 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "47 alta_mcu_m3 " "Found entity 47: alta_mcu_m3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3494 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "48 alta_remote " "Found entity 48: alta_remote" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3657 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "49 alta_saradc " "Found entity 49: alta_saradc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3668 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "50 alta_gclksw " "Found entity 50: alta_gclksw" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3683 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "51 alta_rv32 " "Found entity 51: alta_rv32" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3715 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "52 alta_mipi_clk " "Found entity 52: alta_mipi_clk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3906 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "53 alta_adc " "Found entity 53: alta_adc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3922 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "54 alta_dac " "Found entity 54: alta_dac" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "55 alta_cmp " "Found entity 55: alta_cmp" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4006 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "56 alta_ram4k " "Found entity 56: alta_ram4k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4062 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""} { "Info" "ISGN_ENTITY_NAME" "57 alta_ram9k " "Found entity 57: alta_ram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4241 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516037 ""}
    22. 

  22. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_10_in example_board.v(39) " "Verilog HDL Implicit Net warning at example_board.v(39): created implicit net for \"PIN_10_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 39 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    23. 

  23. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_21_in example_board.v(55) " "Verilog HDL Implicit Net warning at example_board.v(55): created implicit net for \"PIN_21_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 55 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    24. 

  24. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_29_in example_board.v(58) " "Verilog HDL Implicit Net warning at example_board.v(58): created implicit net for \"PIN_29_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 58 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    25. 

  25. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_31_in example_board.v(69) " "Verilog HDL Implicit Net warning at example_board.v(69): created implicit net for \"PIN_31_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 69 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    26. 

  26. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSE_in example_board.v(75) " "Verilog HDL Implicit Net warning at example_board.v(75): created implicit net for \"PIN_HSE_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 75 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    27. 

  27. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSI_in example_board.v(78) " "Verilog HDL Implicit Net warning at example_board.v(78): created implicit net for \"PIN_HSI_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 78 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    28. 

  28. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_OSC_in example_board.v(81) " "Verilog HDL Implicit Net warning at example_board.v(81): created implicit net for \"PIN_OSC_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 81 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    29. 

  29. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "usb0_xcvr_clk example_board.v(204) " "Verilog HDL Implicit Net warning at example_board.v(204): created implicit net for \"usb0_xcvr_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 204 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    30. 

  30. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "bus_clk example_board.v(205) " "Verilog HDL Implicit Net warning at example_board.v(205): created implicit net for \"bus_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 205 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    31. 

  31. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sys_clk example_board.v(216) " "Verilog HDL Implicit Net warning at example_board.v(216): created implicit net for \"sys_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 216 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    32. 

  32. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "csn_out_data example_board.v(269) " "Verilog HDL Implicit Net warning at example_board.v(269): created implicit net for \"csn_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 269 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    33. 

  33. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "csn_out_en example_board.v(270) " "Verilog HDL Implicit Net warning at example_board.v(270): created implicit net for \"csn_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 270 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    34. 

  34. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd1_ip_in example_board.v(271) " "Verilog HDL Implicit Net warning at example_board.v(271): created implicit net for \"rxd1_ip_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 271 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    35. 

  35. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sck_out_data example_board.v(272) " "Verilog HDL Implicit Net warning at example_board.v(272): created implicit net for \"sck_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 272 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    36. 

  36. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sck_out_en example_board.v(273) " "Verilog HDL Implicit Net warning at example_board.v(273): created implicit net for \"sck_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 273 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    37. 

  37. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_in example_board.v(274) " "Verilog HDL Implicit Net warning at example_board.v(274): created implicit net for \"so_io1_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 274 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    38. 

  38. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_out_data example_board.v(275) " "Verilog HDL Implicit Net warning at example_board.v(275): created implicit net for \"so_io1_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 275 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    39. 

  39. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_out_en example_board.v(276) " "Verilog HDL Implicit Net warning at example_board.v(276): created implicit net for \"so_io1_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 276 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    40. 

  40. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd1_ip_out_data example_board.v(277) " "Verilog HDL Implicit Net warning at example_board.v(277): created implicit net for \"txd1_ip_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 277 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    41. 

  41. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd1_ip_out_en example_board.v(278) " "Verilog HDL Implicit Net warning at example_board.v(278): created implicit net for \"txd1_ip_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 278 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    42. 

  42. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(180) " "Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 180 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    43. 

  43. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_int alta_sim.v(204) " "Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for \"ena_int\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 204 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    44. 

  44. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(205) " "Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 205 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    45. 

  45. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_h alta_sim.v(476) " "Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for \"outreg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 476 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    46. 

  46. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_l alta_sim.v(477) " "Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for \"outreg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 477 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    47. 

  47. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_h alta_sim.v(485) " "Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for \"oe_reg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 485 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    48. 

  48. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_l alta_sim.v(486) " "Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for \"oe_reg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 486 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    49. 

  49. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "dffOut alta_sim.v(2758) " "Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for \"dffOut\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2758 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516040 ""}
    50. 

  50. { "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "alta_bram_pulse_generator alta_sim.v(2428) " "Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module \"alta_bram_pulse_generator\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2428 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "Quartus II" 0 -1 1778307516047 ""}
    51. 

  51. { "Info" "ISGN_START_ELABORATION_TOP" "example_board " "Elaborating entity \"example_board\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1778307516119 ""}
    52. 

  52. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll:pll_inst " "Elaborating entity \"altpll\" for hierarchy \"altpll:pll_inst\"" {  } { { "example_board.v" "pll_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516163 ""}
    53. 

  53. { "Info" "ISGN_ELABORATION_HEADER" "altpll:pll_inst " "Elaborated megafunction instantiation \"altpll:pll_inst\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516168 ""}
    54. 

  54. { "Info" "ISGN_MEGAFN_PARAM_TOP" "altpll:pll_inst " "Instantiated megafunction \"altpll:pll_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 8 " "Parameter \"clk0_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 104 " "Parameter \"clk0_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 8 " "Parameter \"clk1_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 104 " "Parameter \"clk1_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 8 " "Parameter \"clk2_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 104 " "Parameter \"clk2_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_divide_by 8 " "Parameter \"clk3_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_multiply_by 104 " "Parameter \"clk3_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_phase_shift 0 " "Parameter \"clk3_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_divide_by 8 " "Parameter \"clk4_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_multiply_by 104 " "Parameter \"clk4_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_phase_shift 0 " "Parameter \"clk4_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 125000 " "Parameter \"inclk0_input_frequency\" = \"125000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_phasecounterselect 3 " "Parameter \"width_phasecounterselect\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516169 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1778307516169 ""}
    55. 

  55. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_6o32.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_6o32.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_6o32 " "Found entity 1: altpll_6o32" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516229 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516229 ""}
    56. 

  56. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_6o32 altpll:pll_inst\|altpll_6o32:auto_generated " "Elaborating entity \"altpll_6o32\" for hierarchy \"altpll:pll_inst\|altpll_6o32:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516232 ""}
    57. 

  57. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_gclksw alta_gclksw:gclksw_inst " "Elaborating entity \"alta_gclksw\" for hierarchy \"alta_gclksw:gclksw_inst\"" {  } { { "example_board.v" "gclksw_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516239 ""}
    58. 

  58. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "analog_ip analog_ip:macro_inst " "Elaborating entity \"analog_ip\" for hierarchy \"analog_ip:macro_inst\"" {  } { { "example_board.v" "macro_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516244 ""}
    59. 

  59. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 analog_ip.v(136) " "Verilog HDL assignment warning at analog_ip.v(136): truncated value with size 32 to match size of target (4)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516247 "|example_board|analog_ip:macro_inst"}
    60. 

  60. { "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "analog_ip.v(475) " "Verilog HDL Case Statement information at analog_ip.v(475): all case item expressions in this case statement are onehot" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 475 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Quartus II" 0 -1 1778307516247 "|example_board|analog_ip:macro_inst"}
    61. 

  61. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb2apb analog_ip:macro_inst\|ahb2apb:ahb2apb_inst " "Elaborating entity \"ahb2apb\" for hierarchy \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\"" {  } { { "analog_ip.v" "ahb2apb_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 131 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516249 ""}
    62. 

  62. { "Warning" "WVRFX_VERI_2086_UNCONVERTED" "ahb2apb.v(52) " "Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 52 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Quartus II" 0 -1 1778307516250 "|example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst"}
    63. 

  63. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ahb2apb.v(52) " "Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4)" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516251 "|example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst"}
    64. 

  64. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "cfg_reg analog_ip:macro_inst\|cfg_reg:cfg_reg_inst " "Elaborating entity \"cfg_reg\" for hierarchy \"analog_ip:macro_inst\|cfg_reg:cfg_reg_inst\"" {  } { { "analog_ip.v" "cfg_reg_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516252 ""}
    65. 

  65. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb_adc analog_ip:macro_inst\|apb_adc:apb_adc0_inst " "Elaborating entity \"apb_adc\" for hierarchy \"analog_ip:macro_inst\|apb_adc:apb_adc0_inst\"" {  } { { "analog_ip.v" "apb_adc0_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 240 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516258 ""}
    66. 

  66. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_adc analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Elaborating entity \"alta_adc\" for hierarchy \"analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst\"" {  } { { "analog_ip.v" "adc_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 584 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516261 ""}
    67. 

  67. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "trig_ctrl analog_ip:macro_inst\|trig_ctrl:trig_ctrl_inst " "Elaborating entity \"trig_ctrl\" for hierarchy \"analog_ip:macro_inst\|trig_ctrl:trig_ctrl_inst\"" {  } { { "analog_ip.v" "trig_ctrl_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 288 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516265 ""}
    68. 

  68. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 trig_ctrl.v(163) " "Verilog HDL assignment warning at trig_ctrl.v(163): truncated value with size 32 to match size of target (10)" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516266 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
    69. 

  69. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 trig_ctrl.v(359) " "Verilog HDL assignment warning at trig_ctrl.v(359): truncated value with size 32 to match size of target (10)" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 359 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516268 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
    70. 

  70. { "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "trig_ctrl.v(345) " "Verilog HDL Case Statement information at trig_ctrl.v(345): all case item expressions in this case statement are onehot" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 345 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Quartus II" 0 -1 1778307516268 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
    71. 

  71. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb_dac analog_ip:macro_inst\|apb_dac:apb_dac0_inst " "Elaborating entity \"apb_dac\" for hierarchy \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\"" {  } { { "analog_ip.v" "apb_dac0_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516270 ""}
    72. 

  72. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1) " "Verilog HDL assignment warning at sine.hex(1): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516274 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    73. 

  73. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(2) " "Verilog HDL assignment warning at sine.hex(2): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 2 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516274 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    74. 

  74. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(3) " "Verilog HDL assignment warning at sine.hex(3): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 3 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516274 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    75. 

  75. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(4) " "Verilog HDL assignment warning at sine.hex(4): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 4 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516274 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    76. 

  76. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(5) " "Verilog HDL assignment warning at sine.hex(5): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 5 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    77. 

  77. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(6) " "Verilog HDL assignment warning at sine.hex(6): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 6 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    78. 

  78. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(7) " "Verilog HDL assignment warning at sine.hex(7): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    79. 

  79. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(8) " "Verilog HDL assignment warning at sine.hex(8): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    80. 

  80. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(9) " "Verilog HDL assignment warning at sine.hex(9): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    81. 

  81. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(10) " "Verilog HDL assignment warning at sine.hex(10): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    82. 

  82. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(11) " "Verilog HDL assignment warning at sine.hex(11): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    83. 

  83. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(12) " "Verilog HDL assignment warning at sine.hex(12): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    84. 

  84. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(13) " "Verilog HDL assignment warning at sine.hex(13): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    85. 

  85. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(14) " "Verilog HDL assignment warning at sine.hex(14): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    86. 

  86. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(15) " "Verilog HDL assignment warning at sine.hex(15): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    87. 

  87. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(16) " "Verilog HDL assignment warning at sine.hex(16): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    88. 

  88. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(17) " "Verilog HDL assignment warning at sine.hex(17): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    89. 

  89. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(18) " "Verilog HDL assignment warning at sine.hex(18): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    90. 

  90. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(19) " "Verilog HDL assignment warning at sine.hex(19): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    91. 

  91. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(20) " "Verilog HDL assignment warning at sine.hex(20): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    92. 

  92. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(21) " "Verilog HDL assignment warning at sine.hex(21): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    93. 

  93. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(22) " "Verilog HDL assignment warning at sine.hex(22): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    94. 

  94. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(23) " "Verilog HDL assignment warning at sine.hex(23): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    95. 

  95. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(24) " "Verilog HDL assignment warning at sine.hex(24): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    96. 

  96. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(25) " "Verilog HDL assignment warning at sine.hex(25): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    97. 

  97. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(26) " "Verilog HDL assignment warning at sine.hex(26): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    98. 

  98. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(27) " "Verilog HDL assignment warning at sine.hex(27): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516275 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    99. 

  99. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(28) " "Verilog HDL assignment warning at sine.hex(28): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    100. 

  100. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(29) " "Verilog HDL assignment warning at sine.hex(29): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    101. 

  101. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(30) " "Verilog HDL assignment warning at sine.hex(30): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    102. 

  102. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(31) " "Verilog HDL assignment warning at sine.hex(31): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    103. 

  103. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(32) " "Verilog HDL assignment warning at sine.hex(32): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    104. 

  104. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(33) " "Verilog HDL assignment warning at sine.hex(33): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    105. 

  105. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(34) " "Verilog HDL assignment warning at sine.hex(34): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    106. 

  106. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(35) " "Verilog HDL assignment warning at sine.hex(35): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516276 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    107. 

  107. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(36) " "Verilog HDL assignment warning at sine.hex(36): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    108. 

  108. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(37) " "Verilog HDL assignment warning at sine.hex(37): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    109. 

  109. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(38) " "Verilog HDL assignment warning at sine.hex(38): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    110. 

  110. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(39) " "Verilog HDL assignment warning at sine.hex(39): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    111. 

  111. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(40) " "Verilog HDL assignment warning at sine.hex(40): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    112. 

  112. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(41) " "Verilog HDL assignment warning at sine.hex(41): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    113. 

  113. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(42) " "Verilog HDL assignment warning at sine.hex(42): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    114. 

  114. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(43) " "Verilog HDL assignment warning at sine.hex(43): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    115. 

  115. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(44) " "Verilog HDL assignment warning at sine.hex(44): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    116. 

  116. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(45) " "Verilog HDL assignment warning at sine.hex(45): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    117. 

  117. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(46) " "Verilog HDL assignment warning at sine.hex(46): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    118. 

  118. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(47) " "Verilog HDL assignment warning at sine.hex(47): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    119. 

  119. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(48) " "Verilog HDL assignment warning at sine.hex(48): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    120. 

  120. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(49) " "Verilog HDL assignment warning at sine.hex(49): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    121. 

  121. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(50) " "Verilog HDL assignment warning at sine.hex(50): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516277 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    122. 

  122. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(51) " "Verilog HDL assignment warning at sine.hex(51): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    123. 

  123. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(52) " "Verilog HDL assignment warning at sine.hex(52): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    124. 

  124. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(53) " "Verilog HDL assignment warning at sine.hex(53): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    125. 

  125. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(54) " "Verilog HDL assignment warning at sine.hex(54): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    126. 

  126. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(55) " "Verilog HDL assignment warning at sine.hex(55): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    127. 

  127. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(56) " "Verilog HDL assignment warning at sine.hex(56): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    128. 

  128. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(57) " "Verilog HDL assignment warning at sine.hex(57): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    129. 

  129. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(58) " "Verilog HDL assignment warning at sine.hex(58): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    130. 

  130. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(59) " "Verilog HDL assignment warning at sine.hex(59): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    131. 

  131. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(60) " "Verilog HDL assignment warning at sine.hex(60): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    132. 

  132. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(61) " "Verilog HDL assignment warning at sine.hex(61): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    133. 

  133. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(62) " "Verilog HDL assignment warning at sine.hex(62): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    134. 

  134. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(63) " "Verilog HDL assignment warning at sine.hex(63): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 63 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    135. 

  135. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(64) " "Verilog HDL assignment warning at sine.hex(64): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516278 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    136. 

  136. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(65) " "Verilog HDL assignment warning at sine.hex(65): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    137. 

  137. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(66) " "Verilog HDL assignment warning at sine.hex(66): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    138. 

  138. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(67) " "Verilog HDL assignment warning at sine.hex(67): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    139. 

  139. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(68) " "Verilog HDL assignment warning at sine.hex(68): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    140. 

  140. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(69) " "Verilog HDL assignment warning at sine.hex(69): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    141. 

  141. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(70) " "Verilog HDL assignment warning at sine.hex(70): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    142. 

  142. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(71) " "Verilog HDL assignment warning at sine.hex(71): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    143. 

  143. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(72) " "Verilog HDL assignment warning at sine.hex(72): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    144. 

  144. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(73) " "Verilog HDL assignment warning at sine.hex(73): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    145. 

  145. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(74) " "Verilog HDL assignment warning at sine.hex(74): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    146. 

  146. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(75) " "Verilog HDL assignment warning at sine.hex(75): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    147. 

  147. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(76) " "Verilog HDL assignment warning at sine.hex(76): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    148. 

  148. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(77) " "Verilog HDL assignment warning at sine.hex(77): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    149. 

  149. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(78) " "Verilog HDL assignment warning at sine.hex(78): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    150. 

  150. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(79) " "Verilog HDL assignment warning at sine.hex(79): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    151. 

  151. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(80) " "Verilog HDL assignment warning at sine.hex(80): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    152. 

  152. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(81) " "Verilog HDL assignment warning at sine.hex(81): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 81 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    153. 

  153. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(82) " "Verilog HDL assignment warning at sine.hex(82): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    154. 

  154. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(83) " "Verilog HDL assignment warning at sine.hex(83): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    155. 

  155. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(84) " "Verilog HDL assignment warning at sine.hex(84): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    156. 

  156. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(85) " "Verilog HDL assignment warning at sine.hex(85): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    157. 

  157. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(86) " "Verilog HDL assignment warning at sine.hex(86): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 86 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    158. 

  158. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(87) " "Verilog HDL assignment warning at sine.hex(87): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 87 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    159. 

  159. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(88) " "Verilog HDL assignment warning at sine.hex(88): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    160. 

  160. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(89) " "Verilog HDL assignment warning at sine.hex(89): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    161. 

  161. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(90) " "Verilog HDL assignment warning at sine.hex(90): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    162. 

  162. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(91) " "Verilog HDL assignment warning at sine.hex(91): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 91 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    163. 

  163. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(92) " "Verilog HDL assignment warning at sine.hex(92): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 92 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    164. 

  164. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(93) " "Verilog HDL assignment warning at sine.hex(93): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516279 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    165. 

  165. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(94) " "Verilog HDL assignment warning at sine.hex(94): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 94 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    166. 

  166. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(95) " "Verilog HDL assignment warning at sine.hex(95): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    167. 

  167. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(96) " "Verilog HDL assignment warning at sine.hex(96): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    168. 

  168. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(97) " "Verilog HDL assignment warning at sine.hex(97): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 97 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    169. 

  169. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(98) " "Verilog HDL assignment warning at sine.hex(98): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    170. 

  170. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(99) " "Verilog HDL assignment warning at sine.hex(99): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    171. 

  171. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(100) " "Verilog HDL assignment warning at sine.hex(100): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    172. 

  172. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(101) " "Verilog HDL assignment warning at sine.hex(101): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    173. 

  173. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(102) " "Verilog HDL assignment warning at sine.hex(102): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    174. 

  174. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(103) " "Verilog HDL assignment warning at sine.hex(103): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    175. 

  175. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(104) " "Verilog HDL assignment warning at sine.hex(104): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    176. 

  176. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(105) " "Verilog HDL assignment warning at sine.hex(105): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    177. 

  177. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(106) " "Verilog HDL assignment warning at sine.hex(106): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    178. 

  178. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(107) " "Verilog HDL assignment warning at sine.hex(107): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    179. 

  179. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(108) " "Verilog HDL assignment warning at sine.hex(108): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    180. 

  180. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(109) " "Verilog HDL assignment warning at sine.hex(109): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    181. 

  181. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(110) " "Verilog HDL assignment warning at sine.hex(110): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    182. 

  182. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(111) " "Verilog HDL assignment warning at sine.hex(111): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    183. 

  183. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(112) " "Verilog HDL assignment warning at sine.hex(112): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 112 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    184. 

  184. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(113) " "Verilog HDL assignment warning at sine.hex(113): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    185. 

  185. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(114) " "Verilog HDL assignment warning at sine.hex(114): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    186. 

  186. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(115) " "Verilog HDL assignment warning at sine.hex(115): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    187. 

  187. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(116) " "Verilog HDL assignment warning at sine.hex(116): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 116 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    188. 

  188. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(117) " "Verilog HDL assignment warning at sine.hex(117): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    189. 

  189. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(118) " "Verilog HDL assignment warning at sine.hex(118): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    190. 

  190. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(119) " "Verilog HDL assignment warning at sine.hex(119): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    191. 

  191. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(120) " "Verilog HDL assignment warning at sine.hex(120): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    192. 

  192. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(121) " "Verilog HDL assignment warning at sine.hex(121): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    193. 

  193. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(122) " "Verilog HDL assignment warning at sine.hex(122): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    194. 

  194. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(123) " "Verilog HDL assignment warning at sine.hex(123): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    195. 

  195. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(124) " "Verilog HDL assignment warning at sine.hex(124): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    196. 

  196. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(125) " "Verilog HDL assignment warning at sine.hex(125): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    197. 

  197. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(126) " "Verilog HDL assignment warning at sine.hex(126): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    198. 

  198. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(127) " "Verilog HDL assignment warning at sine.hex(127): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    199. 

  199. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(128) " "Verilog HDL assignment warning at sine.hex(128): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    200. 

  200. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(129) " "Verilog HDL assignment warning at sine.hex(129): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    201. 

  201. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(130) " "Verilog HDL assignment warning at sine.hex(130): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    202. 

  202. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(131) " "Verilog HDL assignment warning at sine.hex(131): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 131 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516280 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    203. 

  203. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(132) " "Verilog HDL assignment warning at sine.hex(132): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    204. 

  204. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(133) " "Verilog HDL assignment warning at sine.hex(133): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    205. 

  205. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(134) " "Verilog HDL assignment warning at sine.hex(134): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    206. 

  206. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(135) " "Verilog HDL assignment warning at sine.hex(135): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 135 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    207. 

  207. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(136) " "Verilog HDL assignment warning at sine.hex(136): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    208. 

  208. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(137) " "Verilog HDL assignment warning at sine.hex(137): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    209. 

  209. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(138) " "Verilog HDL assignment warning at sine.hex(138): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    210. 

  210. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(139) " "Verilog HDL assignment warning at sine.hex(139): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 139 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    211. 

  211. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(140) " "Verilog HDL assignment warning at sine.hex(140): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 140 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    212. 

  212. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(141) " "Verilog HDL assignment warning at sine.hex(141): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 141 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    213. 

  213. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(142) " "Verilog HDL assignment warning at sine.hex(142): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    214. 

  214. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(143) " "Verilog HDL assignment warning at sine.hex(143): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    215. 

  215. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(144) " "Verilog HDL assignment warning at sine.hex(144): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 144 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    216. 

  216. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(145) " "Verilog HDL assignment warning at sine.hex(145): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 145 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    217. 

  217. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(146) " "Verilog HDL assignment warning at sine.hex(146): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    218. 

  218. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(147) " "Verilog HDL assignment warning at sine.hex(147): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 147 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    219. 

  219. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(148) " "Verilog HDL assignment warning at sine.hex(148): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 148 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    220. 

  220. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(149) " "Verilog HDL assignment warning at sine.hex(149): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    221. 

  221. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(150) " "Verilog HDL assignment warning at sine.hex(150): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    222. 

  222. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(151) " "Verilog HDL assignment warning at sine.hex(151): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 151 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    223. 

  223. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(152) " "Verilog HDL assignment warning at sine.hex(152): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 152 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    224. 

  224. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(153) " "Verilog HDL assignment warning at sine.hex(153): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 153 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    225. 

  225. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(154) " "Verilog HDL assignment warning at sine.hex(154): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    226. 

  226. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(155) " "Verilog HDL assignment warning at sine.hex(155): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 155 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    227. 

  227. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(156) " "Verilog HDL assignment warning at sine.hex(156): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 156 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    228. 

  228. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(157) " "Verilog HDL assignment warning at sine.hex(157): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    229. 

  229. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(158) " "Verilog HDL assignment warning at sine.hex(158): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516282 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    230. 

  230. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(159) " "Verilog HDL assignment warning at sine.hex(159): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    231. 

  231. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(160) " "Verilog HDL assignment warning at sine.hex(160): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    232. 

  232. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(161) " "Verilog HDL assignment warning at sine.hex(161): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    233. 

  233. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(162) " "Verilog HDL assignment warning at sine.hex(162): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    234. 

  234. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(163) " "Verilog HDL assignment warning at sine.hex(163): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    235. 

  235. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(164) " "Verilog HDL assignment warning at sine.hex(164): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 164 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    236. 

  236. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(165) " "Verilog HDL assignment warning at sine.hex(165): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    237. 

  237. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(166) " "Verilog HDL assignment warning at sine.hex(166): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    238. 

  238. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(167) " "Verilog HDL assignment warning at sine.hex(167): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    239. 

  239. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(168) " "Verilog HDL assignment warning at sine.hex(168): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    240. 

  240. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(169) " "Verilog HDL assignment warning at sine.hex(169): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 169 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    241. 

  241. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(170) " "Verilog HDL assignment warning at sine.hex(170): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 170 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    242. 

  242. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(171) " "Verilog HDL assignment warning at sine.hex(171): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 171 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    243. 

  243. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(172) " "Verilog HDL assignment warning at sine.hex(172): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 172 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    244. 

  244. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(173) " "Verilog HDL assignment warning at sine.hex(173): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 173 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    245. 

  245. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(174) " "Verilog HDL assignment warning at sine.hex(174): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    246. 

  246. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(175) " "Verilog HDL assignment warning at sine.hex(175): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 175 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    247. 

  247. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(176) " "Verilog HDL assignment warning at sine.hex(176): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    248. 

  248. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(177) " "Verilog HDL assignment warning at sine.hex(177): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 177 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    249. 

  249. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(178) " "Verilog HDL assignment warning at sine.hex(178): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    250. 

  250. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(179) " "Verilog HDL assignment warning at sine.hex(179): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 179 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    251. 

  251. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(180) " "Verilog HDL assignment warning at sine.hex(180): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 180 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    252. 

  252. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(181) " "Verilog HDL assignment warning at sine.hex(181): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    253. 

  253. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(182) " "Verilog HDL assignment warning at sine.hex(182): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 182 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    254. 

  254. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(183) " "Verilog HDL assignment warning at sine.hex(183): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    255. 

  255. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(184) " "Verilog HDL assignment warning at sine.hex(184): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 184 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    256. 

  256. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(185) " "Verilog HDL assignment warning at sine.hex(185): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 185 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516283 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    257. 

  257. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(186) " "Verilog HDL assignment warning at sine.hex(186): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    258. 

  258. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(187) " "Verilog HDL assignment warning at sine.hex(187): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 187 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    259. 

  259. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(188) " "Verilog HDL assignment warning at sine.hex(188): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    260. 

  260. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(189) " "Verilog HDL assignment warning at sine.hex(189): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 189 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    261. 

  261. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(190) " "Verilog HDL assignment warning at sine.hex(190): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    262. 

  262. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(191) " "Verilog HDL assignment warning at sine.hex(191): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 191 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    263. 

  263. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(192) " "Verilog HDL assignment warning at sine.hex(192): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    264. 

  264. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(193) " "Verilog HDL assignment warning at sine.hex(193): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 193 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    265. 

  265. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(194) " "Verilog HDL assignment warning at sine.hex(194): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 194 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    266. 

  266. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(195) " "Verilog HDL assignment warning at sine.hex(195): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    267. 

  267. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(196) " "Verilog HDL assignment warning at sine.hex(196): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 196 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    268. 

  268. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(197) " "Verilog HDL assignment warning at sine.hex(197): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    269. 

  269. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(198) " "Verilog HDL assignment warning at sine.hex(198): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 198 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    270. 

  270. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(199) " "Verilog HDL assignment warning at sine.hex(199): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 199 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    271. 

  271. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(200) " "Verilog HDL assignment warning at sine.hex(200): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 200 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    272. 

  272. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(201) " "Verilog HDL assignment warning at sine.hex(201): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    273. 

  273. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(202) " "Verilog HDL assignment warning at sine.hex(202): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    274. 

  274. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(203) " "Verilog HDL assignment warning at sine.hex(203): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 203 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    275. 

  275. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(204) " "Verilog HDL assignment warning at sine.hex(204): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 204 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    276. 

  276. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(205) " "Verilog HDL assignment warning at sine.hex(205): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 205 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    277. 

  277. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(206) " "Verilog HDL assignment warning at sine.hex(206): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 206 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    278. 

  278. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(207) " "Verilog HDL assignment warning at sine.hex(207): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516284 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    279. 

  279. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(208) " "Verilog HDL assignment warning at sine.hex(208): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    280. 

  280. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(209) " "Verilog HDL assignment warning at sine.hex(209): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 209 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    281. 

  281. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(210) " "Verilog HDL assignment warning at sine.hex(210): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 210 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    282. 

  282. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(211) " "Verilog HDL assignment warning at sine.hex(211): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 211 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    283. 

  283. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(212) " "Verilog HDL assignment warning at sine.hex(212): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 212 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    284. 

  284. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(213) " "Verilog HDL assignment warning at sine.hex(213): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 213 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    285. 

  285. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(214) " "Verilog HDL assignment warning at sine.hex(214): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    286. 

  286. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(215) " "Verilog HDL assignment warning at sine.hex(215): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 215 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    287. 

  287. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(216) " "Verilog HDL assignment warning at sine.hex(216): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 216 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    288. 

  288. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(217) " "Verilog HDL assignment warning at sine.hex(217): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 217 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    289. 

  289. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(218) " "Verilog HDL assignment warning at sine.hex(218): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 218 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    290. 

  290. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(219) " "Verilog HDL assignment warning at sine.hex(219): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 219 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    291. 

  291. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(220) " "Verilog HDL assignment warning at sine.hex(220): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 220 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    292. 

  292. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(221) " "Verilog HDL assignment warning at sine.hex(221): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 221 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    293. 

  293. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(222) " "Verilog HDL assignment warning at sine.hex(222): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 222 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    294. 

  294. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(223) " "Verilog HDL assignment warning at sine.hex(223): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 223 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    295. 

  295. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(224) " "Verilog HDL assignment warning at sine.hex(224): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 224 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    296. 

  296. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(225) " "Verilog HDL assignment warning at sine.hex(225): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    297. 

  297. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(226) " "Verilog HDL assignment warning at sine.hex(226): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 226 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    298. 

  298. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(227) " "Verilog HDL assignment warning at sine.hex(227): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 227 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    299. 

  299. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(228) " "Verilog HDL assignment warning at sine.hex(228): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 228 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    300. 

  300. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(229) " "Verilog HDL assignment warning at sine.hex(229): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    301. 

  301. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(230) " "Verilog HDL assignment warning at sine.hex(230): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 230 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    302. 

  302. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(231) " "Verilog HDL assignment warning at sine.hex(231): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 231 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    303. 

  303. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(232) " "Verilog HDL assignment warning at sine.hex(232): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 232 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    304. 

  304. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(233) " "Verilog HDL assignment warning at sine.hex(233): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 233 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    305. 

  305. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(234) " "Verilog HDL assignment warning at sine.hex(234): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 234 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    306. 

  306. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(235) " "Verilog HDL assignment warning at sine.hex(235): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 235 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    307. 

  307. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(236) " "Verilog HDL assignment warning at sine.hex(236): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 236 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    308. 

  308. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(237) " "Verilog HDL assignment warning at sine.hex(237): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 237 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    309. 

  309. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(238) " "Verilog HDL assignment warning at sine.hex(238): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 238 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    310. 

  310. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(239) " "Verilog HDL assignment warning at sine.hex(239): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 239 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    311. 

  311. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(240) " "Verilog HDL assignment warning at sine.hex(240): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    312. 

  312. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(241) " "Verilog HDL assignment warning at sine.hex(241): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 241 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    313. 

  313. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(242) " "Verilog HDL assignment warning at sine.hex(242): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 242 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    314. 

  314. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(243) " "Verilog HDL assignment warning at sine.hex(243): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 243 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    315. 

  315. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(244) " "Verilog HDL assignment warning at sine.hex(244): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 244 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    316. 

  316. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(245) " "Verilog HDL assignment warning at sine.hex(245): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    317. 

  317. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(246) " "Verilog HDL assignment warning at sine.hex(246): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 246 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    318. 

  318. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(247) " "Verilog HDL assignment warning at sine.hex(247): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 247 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    319. 

  319. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(248) " "Verilog HDL assignment warning at sine.hex(248): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 248 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516285 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    320. 

  320. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(249) " "Verilog HDL assignment warning at sine.hex(249): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 249 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    321. 

  321. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(250) " "Verilog HDL assignment warning at sine.hex(250): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 250 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    322. 

  322. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(251) " "Verilog HDL assignment warning at sine.hex(251): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 251 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    323. 

  323. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(252) " "Verilog HDL assignment warning at sine.hex(252): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 252 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    324. 

  324. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(253) " "Verilog HDL assignment warning at sine.hex(253): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 253 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    325. 

  325. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(254) " "Verilog HDL assignment warning at sine.hex(254): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 254 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    326. 

  326. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(255) " "Verilog HDL assignment warning at sine.hex(255): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 255 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    327. 

  327. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(256) " "Verilog HDL assignment warning at sine.hex(256): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 256 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    328. 

  328. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(257) " "Verilog HDL assignment warning at sine.hex(257): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 257 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    329. 

  329. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(258) " "Verilog HDL assignment warning at sine.hex(258): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 258 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    330. 

  330. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(259) " "Verilog HDL assignment warning at sine.hex(259): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 259 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    331. 

  331. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(260) " "Verilog HDL assignment warning at sine.hex(260): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 260 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    332. 

  332. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(261) " "Verilog HDL assignment warning at sine.hex(261): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 261 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    333. 

  333. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(262) " "Verilog HDL assignment warning at sine.hex(262): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 262 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    334. 

  334. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(263) " "Verilog HDL assignment warning at sine.hex(263): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 263 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    335. 

  335. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(264) " "Verilog HDL assignment warning at sine.hex(264): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 264 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    336. 

  336. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(265) " "Verilog HDL assignment warning at sine.hex(265): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 265 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    337. 

  337. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(266) " "Verilog HDL assignment warning at sine.hex(266): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 266 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    338. 

  338. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(267) " "Verilog HDL assignment warning at sine.hex(267): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 267 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    339. 

  339. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(268) " "Verilog HDL assignment warning at sine.hex(268): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 268 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    340. 

  340. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(269) " "Verilog HDL assignment warning at sine.hex(269): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 269 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    341. 

  341. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(270) " "Verilog HDL assignment warning at sine.hex(270): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 270 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    342. 

  342. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(271) " "Verilog HDL assignment warning at sine.hex(271): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 271 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    343. 

  343. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(272) " "Verilog HDL assignment warning at sine.hex(272): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 272 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    344. 

  344. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(273) " "Verilog HDL assignment warning at sine.hex(273): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 273 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    345. 

  345. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(274) " "Verilog HDL assignment warning at sine.hex(274): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 274 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    346. 

  346. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(275) " "Verilog HDL assignment warning at sine.hex(275): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 275 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    347. 

  347. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(276) " "Verilog HDL assignment warning at sine.hex(276): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 276 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    348. 

  348. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(277) " "Verilog HDL assignment warning at sine.hex(277): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 277 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    349. 

  349. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(278) " "Verilog HDL assignment warning at sine.hex(278): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 278 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    350. 

  350. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(279) " "Verilog HDL assignment warning at sine.hex(279): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 279 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    351. 

  351. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(280) " "Verilog HDL assignment warning at sine.hex(280): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 280 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    352. 

  352. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(281) " "Verilog HDL assignment warning at sine.hex(281): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 281 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    353. 

  353. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(282) " "Verilog HDL assignment warning at sine.hex(282): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 282 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    354. 

  354. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(283) " "Verilog HDL assignment warning at sine.hex(283): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 283 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    355. 

  355. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(284) " "Verilog HDL assignment warning at sine.hex(284): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 284 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    356. 

  356. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(285) " "Verilog HDL assignment warning at sine.hex(285): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 285 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516287 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    357. 

  357. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(286) " "Verilog HDL assignment warning at sine.hex(286): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    358. 

  358. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(287) " "Verilog HDL assignment warning at sine.hex(287): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 287 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    359. 

  359. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(288) " "Verilog HDL assignment warning at sine.hex(288): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 288 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    360. 

  360. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(289) " "Verilog HDL assignment warning at sine.hex(289): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 289 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    361. 

  361. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(290) " "Verilog HDL assignment warning at sine.hex(290): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 290 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    362. 

  362. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(291) " "Verilog HDL assignment warning at sine.hex(291): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 291 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    363. 

  363. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(292) " "Verilog HDL assignment warning at sine.hex(292): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 292 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    364. 

  364. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(293) " "Verilog HDL assignment warning at sine.hex(293): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 293 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    365. 

  365. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(294) " "Verilog HDL assignment warning at sine.hex(294): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 294 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    366. 

  366. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(295) " "Verilog HDL assignment warning at sine.hex(295): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 295 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    367. 

  367. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(296) " "Verilog HDL assignment warning at sine.hex(296): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 296 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    368. 

  368. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(297) " "Verilog HDL assignment warning at sine.hex(297): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 297 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516288 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    369. 

  369. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(298) " "Verilog HDL assignment warning at sine.hex(298): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 298 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    370. 

  370. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(299) " "Verilog HDL assignment warning at sine.hex(299): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 299 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    371. 

  371. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(300) " "Verilog HDL assignment warning at sine.hex(300): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 300 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    372. 

  372. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(301) " "Verilog HDL assignment warning at sine.hex(301): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 301 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    373. 

  373. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(302) " "Verilog HDL assignment warning at sine.hex(302): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 302 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    374. 

  374. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(303) " "Verilog HDL assignment warning at sine.hex(303): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 303 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    375. 

  375. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(304) " "Verilog HDL assignment warning at sine.hex(304): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 304 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    376. 

  376. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(305) " "Verilog HDL assignment warning at sine.hex(305): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 305 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    377. 

  377. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(306) " "Verilog HDL assignment warning at sine.hex(306): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 306 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    378. 

  378. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(307) " "Verilog HDL assignment warning at sine.hex(307): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    379. 

  379. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(308) " "Verilog HDL assignment warning at sine.hex(308): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 308 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    380. 

  380. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(309) " "Verilog HDL assignment warning at sine.hex(309): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 309 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    381. 

  381. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(310) " "Verilog HDL assignment warning at sine.hex(310): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 310 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    382. 

  382. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(311) " "Verilog HDL assignment warning at sine.hex(311): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 311 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    383. 

  383. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(312) " "Verilog HDL assignment warning at sine.hex(312): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 312 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    384. 

  384. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(313) " "Verilog HDL assignment warning at sine.hex(313): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 313 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    385. 

  385. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(314) " "Verilog HDL assignment warning at sine.hex(314): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 314 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    386. 

  386. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(315) " "Verilog HDL assignment warning at sine.hex(315): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 315 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    387. 

  387. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(316) " "Verilog HDL assignment warning at sine.hex(316): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 316 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516289 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    388. 

  388. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(317) " "Verilog HDL assignment warning at sine.hex(317): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 317 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    389. 

  389. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(318) " "Verilog HDL assignment warning at sine.hex(318): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 318 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    390. 

  390. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(319) " "Verilog HDL assignment warning at sine.hex(319): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 319 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    391. 

  391. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(320) " "Verilog HDL assignment warning at sine.hex(320): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 320 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    392. 

  392. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(321) " "Verilog HDL assignment warning at sine.hex(321): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 321 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    393. 

  393. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(322) " "Verilog HDL assignment warning at sine.hex(322): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 322 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    394. 

  394. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(323) " "Verilog HDL assignment warning at sine.hex(323): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 323 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    395. 

  395. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(324) " "Verilog HDL assignment warning at sine.hex(324): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 324 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    396. 

  396. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(325) " "Verilog HDL assignment warning at sine.hex(325): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 325 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    397. 

  397. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(326) " "Verilog HDL assignment warning at sine.hex(326): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 326 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    398. 

  398. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(327) " "Verilog HDL assignment warning at sine.hex(327): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 327 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    399. 

  399. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(328) " "Verilog HDL assignment warning at sine.hex(328): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 328 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    400. 

  400. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(329) " "Verilog HDL assignment warning at sine.hex(329): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 329 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    401. 

  401. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(330) " "Verilog HDL assignment warning at sine.hex(330): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 330 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    402. 

  402. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(331) " "Verilog HDL assignment warning at sine.hex(331): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 331 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    403. 

  403. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(332) " "Verilog HDL assignment warning at sine.hex(332): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 332 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    404. 

  404. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(333) " "Verilog HDL assignment warning at sine.hex(333): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 333 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    405. 

  405. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(334) " "Verilog HDL assignment warning at sine.hex(334): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 334 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    406. 

  406. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(335) " "Verilog HDL assignment warning at sine.hex(335): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 335 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    407. 

  407. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(336) " "Verilog HDL assignment warning at sine.hex(336): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 336 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    408. 

  408. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(337) " "Verilog HDL assignment warning at sine.hex(337): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 337 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    409. 

  409. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(338) " "Verilog HDL assignment warning at sine.hex(338): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 338 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    410. 

  410. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(339) " "Verilog HDL assignment warning at sine.hex(339): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 339 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    411. 

  411. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(340) " "Verilog HDL assignment warning at sine.hex(340): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 340 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516290 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    412. 

  412. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(341) " "Verilog HDL assignment warning at sine.hex(341): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 341 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    413. 

  413. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(342) " "Verilog HDL assignment warning at sine.hex(342): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 342 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    414. 

  414. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(343) " "Verilog HDL assignment warning at sine.hex(343): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 343 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    415. 

  415. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(344) " "Verilog HDL assignment warning at sine.hex(344): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 344 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    416. 

  416. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(345) " "Verilog HDL assignment warning at sine.hex(345): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 345 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    417. 

  417. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(346) " "Verilog HDL assignment warning at sine.hex(346): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 346 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    418. 

  418. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(347) " "Verilog HDL assignment warning at sine.hex(347): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 347 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    419. 

  419. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(348) " "Verilog HDL assignment warning at sine.hex(348): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 348 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    420. 

  420. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(349) " "Verilog HDL assignment warning at sine.hex(349): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 349 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    421. 

  421. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(350) " "Verilog HDL assignment warning at sine.hex(350): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 350 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    422. 

  422. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(351) " "Verilog HDL assignment warning at sine.hex(351): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 351 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    423. 

  423. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(352) " "Verilog HDL assignment warning at sine.hex(352): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 352 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    424. 

  424. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(353) " "Verilog HDL assignment warning at sine.hex(353): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 353 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    425. 

  425. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(354) " "Verilog HDL assignment warning at sine.hex(354): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 354 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    426. 

  426. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(355) " "Verilog HDL assignment warning at sine.hex(355): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 355 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    427. 

  427. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(356) " "Verilog HDL assignment warning at sine.hex(356): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 356 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    428. 

  428. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(357) " "Verilog HDL assignment warning at sine.hex(357): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 357 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    429. 

  429. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(358) " "Verilog HDL assignment warning at sine.hex(358): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 358 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    430. 

  430. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(359) " "Verilog HDL assignment warning at sine.hex(359): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 359 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    431. 

  431. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(360) " "Verilog HDL assignment warning at sine.hex(360): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 360 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    432. 

  432. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(361) " "Verilog HDL assignment warning at sine.hex(361): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 361 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    433. 

  433. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(362) " "Verilog HDL assignment warning at sine.hex(362): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 362 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    434. 

  434. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(363) " "Verilog HDL assignment warning at sine.hex(363): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 363 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    435. 

  435. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(364) " "Verilog HDL assignment warning at sine.hex(364): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 364 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    436. 

  436. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(365) " "Verilog HDL assignment warning at sine.hex(365): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 365 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    437. 

  437. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(366) " "Verilog HDL assignment warning at sine.hex(366): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 366 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    438. 

  438. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(367) " "Verilog HDL assignment warning at sine.hex(367): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 367 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516291 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    439. 

  439. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(368) " "Verilog HDL assignment warning at sine.hex(368): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 368 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    440. 

  440. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(369) " "Verilog HDL assignment warning at sine.hex(369): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 369 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    441. 

  441. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(370) " "Verilog HDL assignment warning at sine.hex(370): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 370 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    442. 

  442. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(371) " "Verilog HDL assignment warning at sine.hex(371): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 371 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    443. 

  443. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(372) " "Verilog HDL assignment warning at sine.hex(372): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 372 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    444. 

  444. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(373) " "Verilog HDL assignment warning at sine.hex(373): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 373 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    445. 

  445. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(374) " "Verilog HDL assignment warning at sine.hex(374): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 374 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    446. 

  446. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(375) " "Verilog HDL assignment warning at sine.hex(375): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 375 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    447. 

  447. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(376) " "Verilog HDL assignment warning at sine.hex(376): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 376 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    448. 

  448. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(377) " "Verilog HDL assignment warning at sine.hex(377): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 377 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    449. 

  449. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(378) " "Verilog HDL assignment warning at sine.hex(378): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 378 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    450. 

  450. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(379) " "Verilog HDL assignment warning at sine.hex(379): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 379 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    451. 

  451. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(380) " "Verilog HDL assignment warning at sine.hex(380): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 380 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    452. 

  452. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(381) " "Verilog HDL assignment warning at sine.hex(381): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 381 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    453. 

  453. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(382) " "Verilog HDL assignment warning at sine.hex(382): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 382 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    454. 

  454. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(383) " "Verilog HDL assignment warning at sine.hex(383): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 383 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    455. 

  455. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(384) " "Verilog HDL assignment warning at sine.hex(384): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 384 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    456. 

  456. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(385) " "Verilog HDL assignment warning at sine.hex(385): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    457. 

  457. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(386) " "Verilog HDL assignment warning at sine.hex(386): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 386 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    458. 

  458. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(387) " "Verilog HDL assignment warning at sine.hex(387): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 387 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    459. 

  459. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(388) " "Verilog HDL assignment warning at sine.hex(388): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 388 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    460. 

  460. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(389) " "Verilog HDL assignment warning at sine.hex(389): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 389 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    461. 

  461. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(390) " "Verilog HDL assignment warning at sine.hex(390): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 390 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    462. 

  462. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(391) " "Verilog HDL assignment warning at sine.hex(391): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 391 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    463. 

  463. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(392) " "Verilog HDL assignment warning at sine.hex(392): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 392 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    464. 

  464. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(393) " "Verilog HDL assignment warning at sine.hex(393): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 393 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    465. 

  465. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(394) " "Verilog HDL assignment warning at sine.hex(394): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 394 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    466. 

  466. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(395) " "Verilog HDL assignment warning at sine.hex(395): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 395 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    467. 

  467. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(396) " "Verilog HDL assignment warning at sine.hex(396): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 396 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    468. 

  468. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(397) " "Verilog HDL assignment warning at sine.hex(397): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 397 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    469. 

  469. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(398) " "Verilog HDL assignment warning at sine.hex(398): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 398 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516292 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    470. 

  470. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(399) " "Verilog HDL assignment warning at sine.hex(399): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 399 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    471. 

  471. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(400) " "Verilog HDL assignment warning at sine.hex(400): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 400 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    472. 

  472. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(401) " "Verilog HDL assignment warning at sine.hex(401): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 401 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    473. 

  473. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(402) " "Verilog HDL assignment warning at sine.hex(402): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 402 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    474. 

  474. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(403) " "Verilog HDL assignment warning at sine.hex(403): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 403 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    475. 

  475. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(404) " "Verilog HDL assignment warning at sine.hex(404): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 404 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    476. 

  476. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(405) " "Verilog HDL assignment warning at sine.hex(405): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 405 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    477. 

  477. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(406) " "Verilog HDL assignment warning at sine.hex(406): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 406 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    478. 

  478. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(407) " "Verilog HDL assignment warning at sine.hex(407): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 407 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    479. 

  479. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(408) " "Verilog HDL assignment warning at sine.hex(408): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 408 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    480. 

  480. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(409) " "Verilog HDL assignment warning at sine.hex(409): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 409 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    481. 

  481. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(410) " "Verilog HDL assignment warning at sine.hex(410): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 410 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    482. 

  482. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(411) " "Verilog HDL assignment warning at sine.hex(411): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 411 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    483. 

  483. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(412) " "Verilog HDL assignment warning at sine.hex(412): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 412 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516294 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    484. 

  484. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(413) " "Verilog HDL assignment warning at sine.hex(413): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 413 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    485. 

  485. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(414) " "Verilog HDL assignment warning at sine.hex(414): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 414 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    486. 

  486. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(415) " "Verilog HDL assignment warning at sine.hex(415): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 415 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    487. 

  487. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(416) " "Verilog HDL assignment warning at sine.hex(416): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 416 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    488. 

  488. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(417) " "Verilog HDL assignment warning at sine.hex(417): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 417 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    489. 

  489. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(418) " "Verilog HDL assignment warning at sine.hex(418): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 418 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    490. 

  490. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(419) " "Verilog HDL assignment warning at sine.hex(419): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 419 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    491. 

  491. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(420) " "Verilog HDL assignment warning at sine.hex(420): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 420 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    492. 

  492. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(421) " "Verilog HDL assignment warning at sine.hex(421): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 421 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    493. 

  493. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(422) " "Verilog HDL assignment warning at sine.hex(422): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 422 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    494. 

  494. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(423) " "Verilog HDL assignment warning at sine.hex(423): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 423 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    495. 

  495. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(424) " "Verilog HDL assignment warning at sine.hex(424): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 424 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    496. 

  496. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(425) " "Verilog HDL assignment warning at sine.hex(425): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 425 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    497. 

  497. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(426) " "Verilog HDL assignment warning at sine.hex(426): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 426 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    498. 

  498. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(427) " "Verilog HDL assignment warning at sine.hex(427): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 427 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    499. 

  499. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(428) " "Verilog HDL assignment warning at sine.hex(428): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 428 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    500. 

  500. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(429) " "Verilog HDL assignment warning at sine.hex(429): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 429 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    501. 

  501. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(430) " "Verilog HDL assignment warning at sine.hex(430): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 430 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    502. 

  502. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(431) " "Verilog HDL assignment warning at sine.hex(431): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    503. 

  503. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(432) " "Verilog HDL assignment warning at sine.hex(432): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    504. 

  504. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(433) " "Verilog HDL assignment warning at sine.hex(433): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    505. 

  505. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(434) " "Verilog HDL assignment warning at sine.hex(434): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    506. 

  506. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(435) " "Verilog HDL assignment warning at sine.hex(435): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 435 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    507. 

  507. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(436) " "Verilog HDL assignment warning at sine.hex(436): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 436 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    508. 

  508. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(437) " "Verilog HDL assignment warning at sine.hex(437): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 437 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    509. 

  509. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(438) " "Verilog HDL assignment warning at sine.hex(438): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 438 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516295 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    510. 

  510. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(439) " "Verilog HDL assignment warning at sine.hex(439): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 439 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    511. 

  511. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(440) " "Verilog HDL assignment warning at sine.hex(440): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 440 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    512. 

  512. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(441) " "Verilog HDL assignment warning at sine.hex(441): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 441 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    513. 

  513. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(442) " "Verilog HDL assignment warning at sine.hex(442): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 442 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    514. 

  514. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(443) " "Verilog HDL assignment warning at sine.hex(443): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 443 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    515. 

  515. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(444) " "Verilog HDL assignment warning at sine.hex(444): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 444 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    516. 

  516. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(445) " "Verilog HDL assignment warning at sine.hex(445): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 445 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    517. 

  517. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(446) " "Verilog HDL assignment warning at sine.hex(446): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 446 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    518. 

  518. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(447) " "Verilog HDL assignment warning at sine.hex(447): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 447 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    519. 

  519. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(448) " "Verilog HDL assignment warning at sine.hex(448): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 448 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    520. 

  520. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(449) " "Verilog HDL assignment warning at sine.hex(449): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 449 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    521. 

  521. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(450) " "Verilog HDL assignment warning at sine.hex(450): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 450 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    522. 

  522. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(451) " "Verilog HDL assignment warning at sine.hex(451): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 451 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    523. 

  523. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(452) " "Verilog HDL assignment warning at sine.hex(452): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 452 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    524. 

  524. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(453) " "Verilog HDL assignment warning at sine.hex(453): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 453 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    525. 

  525. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(454) " "Verilog HDL assignment warning at sine.hex(454): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 454 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    526. 

  526. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(455) " "Verilog HDL assignment warning at sine.hex(455): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 455 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    527. 

  527. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(456) " "Verilog HDL assignment warning at sine.hex(456): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 456 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    528. 

  528. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(457) " "Verilog HDL assignment warning at sine.hex(457): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 457 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    529. 

  529. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(458) " "Verilog HDL assignment warning at sine.hex(458): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 458 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    530. 

  530. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(459) " "Verilog HDL assignment warning at sine.hex(459): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 459 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    531. 

  531. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(460) " "Verilog HDL assignment warning at sine.hex(460): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 460 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    532. 

  532. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(461) " "Verilog HDL assignment warning at sine.hex(461): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 461 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    533. 

  533. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(462) " "Verilog HDL assignment warning at sine.hex(462): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 462 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    534. 

  534. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(463) " "Verilog HDL assignment warning at sine.hex(463): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 463 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    535. 

  535. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(464) " "Verilog HDL assignment warning at sine.hex(464): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 464 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    536. 

  536. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(465) " "Verilog HDL assignment warning at sine.hex(465): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 465 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    537. 

  537. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(466) " "Verilog HDL assignment warning at sine.hex(466): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 466 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    538. 

  538. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(467) " "Verilog HDL assignment warning at sine.hex(467): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 467 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    539. 

  539. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(468) " "Verilog HDL assignment warning at sine.hex(468): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 468 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    540. 

  540. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(469) " "Verilog HDL assignment warning at sine.hex(469): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 469 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    541. 

  541. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(470) " "Verilog HDL assignment warning at sine.hex(470): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 470 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    542. 

  542. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(471) " "Verilog HDL assignment warning at sine.hex(471): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 471 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    543. 

  543. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(472) " "Verilog HDL assignment warning at sine.hex(472): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 472 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    544. 

  544. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(473) " "Verilog HDL assignment warning at sine.hex(473): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 473 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    545. 

  545. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(474) " "Verilog HDL assignment warning at sine.hex(474): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 474 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    546. 

  546. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(475) " "Verilog HDL assignment warning at sine.hex(475): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 475 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    547. 

  547. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(476) " "Verilog HDL assignment warning at sine.hex(476): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 476 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516296 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    548. 

  548. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(477) " "Verilog HDL assignment warning at sine.hex(477): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 477 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    549. 

  549. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(478) " "Verilog HDL assignment warning at sine.hex(478): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 478 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    550. 

  550. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(479) " "Verilog HDL assignment warning at sine.hex(479): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 479 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    551. 

  551. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(480) " "Verilog HDL assignment warning at sine.hex(480): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 480 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    552. 

  552. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(481) " "Verilog HDL assignment warning at sine.hex(481): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 481 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    553. 

  553. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(482) " "Verilog HDL assignment warning at sine.hex(482): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 482 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    554. 

  554. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(483) " "Verilog HDL assignment warning at sine.hex(483): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 483 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    555. 

  555. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(484) " "Verilog HDL assignment warning at sine.hex(484): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 484 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    556. 

  556. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(485) " "Verilog HDL assignment warning at sine.hex(485): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 485 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    557. 

  557. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(486) " "Verilog HDL assignment warning at sine.hex(486): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 486 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    558. 

  558. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(487) " "Verilog HDL assignment warning at sine.hex(487): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 487 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    559. 

  559. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(488) " "Verilog HDL assignment warning at sine.hex(488): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 488 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    560. 

  560. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(489) " "Verilog HDL assignment warning at sine.hex(489): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 489 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    561. 

  561. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(490) " "Verilog HDL assignment warning at sine.hex(490): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 490 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    562. 

  562. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(491) " "Verilog HDL assignment warning at sine.hex(491): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 491 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516297 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    563. 

  563. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(492) " "Verilog HDL assignment warning at sine.hex(492): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 492 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    564. 

  564. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(493) " "Verilog HDL assignment warning at sine.hex(493): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 493 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    565. 

  565. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(494) " "Verilog HDL assignment warning at sine.hex(494): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 494 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    566. 

  566. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(495) " "Verilog HDL assignment warning at sine.hex(495): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 495 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    567. 

  567. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(496) " "Verilog HDL assignment warning at sine.hex(496): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 496 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    568. 

  568. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(497) " "Verilog HDL assignment warning at sine.hex(497): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 497 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    569. 

  569. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(498) " "Verilog HDL assignment warning at sine.hex(498): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 498 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    570. 

  570. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(499) " "Verilog HDL assignment warning at sine.hex(499): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 499 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    571. 

  571. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(500) " "Verilog HDL assignment warning at sine.hex(500): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 500 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    572. 

  572. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(501) " "Verilog HDL assignment warning at sine.hex(501): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 501 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    573. 

  573. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(502) " "Verilog HDL assignment warning at sine.hex(502): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 502 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    574. 

  574. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(503) " "Verilog HDL assignment warning at sine.hex(503): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 503 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    575. 

  575. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(504) " "Verilog HDL assignment warning at sine.hex(504): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 504 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    576. 

  576. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(505) " "Verilog HDL assignment warning at sine.hex(505): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 505 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    577. 

  577. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(506) " "Verilog HDL assignment warning at sine.hex(506): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 506 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    578. 

  578. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(507) " "Verilog HDL assignment warning at sine.hex(507): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 507 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    579. 

  579. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(508) " "Verilog HDL assignment warning at sine.hex(508): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 508 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    580. 

  580. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(509) " "Verilog HDL assignment warning at sine.hex(509): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 509 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    581. 

  581. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(510) " "Verilog HDL assignment warning at sine.hex(510): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 510 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    582. 

  582. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(511) " "Verilog HDL assignment warning at sine.hex(511): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 511 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    583. 

  583. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(512) " "Verilog HDL assignment warning at sine.hex(512): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 512 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    584. 

  584. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(513) " "Verilog HDL assignment warning at sine.hex(513): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 513 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    585. 

  585. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(514) " "Verilog HDL assignment warning at sine.hex(514): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 514 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    586. 

  586. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(515) " "Verilog HDL assignment warning at sine.hex(515): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 515 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    587. 

  587. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(516) " "Verilog HDL assignment warning at sine.hex(516): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 516 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    588. 

  588. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(517) " "Verilog HDL assignment warning at sine.hex(517): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 517 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    589. 

  589. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(518) " "Verilog HDL assignment warning at sine.hex(518): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 518 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    590. 

  590. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(519) " "Verilog HDL assignment warning at sine.hex(519): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 519 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516298 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    591. 

  591. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(520) " "Verilog HDL assignment warning at sine.hex(520): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 520 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    592. 

  592. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(521) " "Verilog HDL assignment warning at sine.hex(521): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 521 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    593. 

  593. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(522) " "Verilog HDL assignment warning at sine.hex(522): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 522 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    594. 

  594. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(523) " "Verilog HDL assignment warning at sine.hex(523): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 523 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    595. 

  595. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(524) " "Verilog HDL assignment warning at sine.hex(524): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 524 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    596. 

  596. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(525) " "Verilog HDL assignment warning at sine.hex(525): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 525 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    597. 

  597. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(526) " "Verilog HDL assignment warning at sine.hex(526): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 526 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    598. 

  598. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(527) " "Verilog HDL assignment warning at sine.hex(527): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 527 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    599. 

  599. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(528) " "Verilog HDL assignment warning at sine.hex(528): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 528 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    600. 

  600. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(529) " "Verilog HDL assignment warning at sine.hex(529): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 529 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    601. 

  601. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(530) " "Verilog HDL assignment warning at sine.hex(530): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 530 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    602. 

  602. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(531) " "Verilog HDL assignment warning at sine.hex(531): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 531 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    603. 

  603. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(532) " "Verilog HDL assignment warning at sine.hex(532): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 532 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    604. 

  604. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(533) " "Verilog HDL assignment warning at sine.hex(533): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 533 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    605. 

  605. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(534) " "Verilog HDL assignment warning at sine.hex(534): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 534 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    606. 

  606. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(535) " "Verilog HDL assignment warning at sine.hex(535): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 535 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    607. 

  607. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(536) " "Verilog HDL assignment warning at sine.hex(536): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 536 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    608. 

  608. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(537) " "Verilog HDL assignment warning at sine.hex(537): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 537 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    609. 

  609. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(538) " "Verilog HDL assignment warning at sine.hex(538): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 538 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    610. 

  610. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(539) " "Verilog HDL assignment warning at sine.hex(539): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 539 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    611. 

  611. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(540) " "Verilog HDL assignment warning at sine.hex(540): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 540 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    612. 

  612. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(541) " "Verilog HDL assignment warning at sine.hex(541): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 541 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    613. 

  613. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(542) " "Verilog HDL assignment warning at sine.hex(542): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 542 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    614. 

  614. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(543) " "Verilog HDL assignment warning at sine.hex(543): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 543 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    615. 

  615. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(544) " "Verilog HDL assignment warning at sine.hex(544): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 544 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    616. 

  616. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(545) " "Verilog HDL assignment warning at sine.hex(545): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 545 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    617. 

  617. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(546) " "Verilog HDL assignment warning at sine.hex(546): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 546 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    618. 

  618. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(547) " "Verilog HDL assignment warning at sine.hex(547): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 547 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    619. 

  619. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(548) " "Verilog HDL assignment warning at sine.hex(548): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 548 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    620. 

  620. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(549) " "Verilog HDL assignment warning at sine.hex(549): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 549 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    621. 

  621. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(550) " "Verilog HDL assignment warning at sine.hex(550): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 550 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    622. 

  622. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(551) " "Verilog HDL assignment warning at sine.hex(551): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 551 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    623. 

  623. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(552) " "Verilog HDL assignment warning at sine.hex(552): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 552 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    624. 

  624. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(553) " "Verilog HDL assignment warning at sine.hex(553): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 553 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    625. 

  625. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(554) " "Verilog HDL assignment warning at sine.hex(554): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 554 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    626. 

  626. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(555) " "Verilog HDL assignment warning at sine.hex(555): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 555 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    627. 

  627. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(556) " "Verilog HDL assignment warning at sine.hex(556): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 556 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    628. 

  628. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(557) " "Verilog HDL assignment warning at sine.hex(557): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 557 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    629. 

  629. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(558) " "Verilog HDL assignment warning at sine.hex(558): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 558 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    630. 

  630. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(559) " "Verilog HDL assignment warning at sine.hex(559): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 559 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    631. 

  631. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(560) " "Verilog HDL assignment warning at sine.hex(560): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 560 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    632. 

  632. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(561) " "Verilog HDL assignment warning at sine.hex(561): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 561 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516299 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    633. 

  633. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(562) " "Verilog HDL assignment warning at sine.hex(562): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 562 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    634. 

  634. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(563) " "Verilog HDL assignment warning at sine.hex(563): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 563 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    635. 

  635. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(564) " "Verilog HDL assignment warning at sine.hex(564): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 564 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    636. 

  636. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(565) " "Verilog HDL assignment warning at sine.hex(565): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 565 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    637. 

  637. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(566) " "Verilog HDL assignment warning at sine.hex(566): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 566 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    638. 

  638. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(567) " "Verilog HDL assignment warning at sine.hex(567): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 567 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    639. 

  639. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(568) " "Verilog HDL assignment warning at sine.hex(568): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 568 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    640. 

  640. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(569) " "Verilog HDL assignment warning at sine.hex(569): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 569 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    641. 

  641. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(570) " "Verilog HDL assignment warning at sine.hex(570): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 570 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    642. 

  642. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(571) " "Verilog HDL assignment warning at sine.hex(571): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 571 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    643. 

  643. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(572) " "Verilog HDL assignment warning at sine.hex(572): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 572 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    644. 

  644. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(573) " "Verilog HDL assignment warning at sine.hex(573): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 573 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    645. 

  645. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(574) " "Verilog HDL assignment warning at sine.hex(574): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 574 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    646. 

  646. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(575) " "Verilog HDL assignment warning at sine.hex(575): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 575 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    647. 

  647. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(576) " "Verilog HDL assignment warning at sine.hex(576): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 576 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    648. 

  648. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(577) " "Verilog HDL assignment warning at sine.hex(577): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 577 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    649. 

  649. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(578) " "Verilog HDL assignment warning at sine.hex(578): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 578 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    650. 

  650. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(579) " "Verilog HDL assignment warning at sine.hex(579): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 579 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    651. 

  651. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(580) " "Verilog HDL assignment warning at sine.hex(580): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 580 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    652. 

  652. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(581) " "Verilog HDL assignment warning at sine.hex(581): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 581 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    653. 

  653. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(582) " "Verilog HDL assignment warning at sine.hex(582): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 582 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    654. 

  654. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(583) " "Verilog HDL assignment warning at sine.hex(583): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 583 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    655. 

  655. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(584) " "Verilog HDL assignment warning at sine.hex(584): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 584 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    656. 

  656. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(585) " "Verilog HDL assignment warning at sine.hex(585): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 585 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    657. 

  657. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(586) " "Verilog HDL assignment warning at sine.hex(586): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 586 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    658. 

  658. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(587) " "Verilog HDL assignment warning at sine.hex(587): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 587 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    659. 

  659. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(588) " "Verilog HDL assignment warning at sine.hex(588): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 588 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516300 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    660. 

  660. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(589) " "Verilog HDL assignment warning at sine.hex(589): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 589 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    661. 

  661. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(590) " "Verilog HDL assignment warning at sine.hex(590): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 590 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    662. 

  662. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(591) " "Verilog HDL assignment warning at sine.hex(591): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 591 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    663. 

  663. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(592) " "Verilog HDL assignment warning at sine.hex(592): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 592 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    664. 

  664. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(593) " "Verilog HDL assignment warning at sine.hex(593): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 593 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    665. 

  665. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(594) " "Verilog HDL assignment warning at sine.hex(594): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 594 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    666. 

  666. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(595) " "Verilog HDL assignment warning at sine.hex(595): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 595 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    667. 

  667. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(596) " "Verilog HDL assignment warning at sine.hex(596): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 596 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    668. 

  668. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(597) " "Verilog HDL assignment warning at sine.hex(597): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 597 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    669. 

  669. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(598) " "Verilog HDL assignment warning at sine.hex(598): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 598 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    670. 

  670. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(599) " "Verilog HDL assignment warning at sine.hex(599): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 599 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    671. 

  671. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(600) " "Verilog HDL assignment warning at sine.hex(600): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 600 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    672. 

  672. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(601) " "Verilog HDL assignment warning at sine.hex(601): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 601 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    673. 

  673. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(602) " "Verilog HDL assignment warning at sine.hex(602): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 602 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    674. 

  674. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(603) " "Verilog HDL assignment warning at sine.hex(603): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 603 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    675. 

  675. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(604) " "Verilog HDL assignment warning at sine.hex(604): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 604 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    676. 

  676. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(605) " "Verilog HDL assignment warning at sine.hex(605): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 605 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    677. 

  677. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(606) " "Verilog HDL assignment warning at sine.hex(606): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 606 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    678. 

  678. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(607) " "Verilog HDL assignment warning at sine.hex(607): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 607 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    679. 

  679. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(608) " "Verilog HDL assignment warning at sine.hex(608): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 608 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    680. 

  680. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(609) " "Verilog HDL assignment warning at sine.hex(609): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 609 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    681. 

  681. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(610) " "Verilog HDL assignment warning at sine.hex(610): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 610 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    682. 

  682. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(611) " "Verilog HDL assignment warning at sine.hex(611): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 611 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    683. 

  683. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(612) " "Verilog HDL assignment warning at sine.hex(612): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 612 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    684. 

  684. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(613) " "Verilog HDL assignment warning at sine.hex(613): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 613 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    685. 

  685. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(614) " "Verilog HDL assignment warning at sine.hex(614): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 614 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516301 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    686. 

  686. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(615) " "Verilog HDL assignment warning at sine.hex(615): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 615 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    687. 

  687. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(616) " "Verilog HDL assignment warning at sine.hex(616): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 616 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    688. 

  688. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(617) " "Verilog HDL assignment warning at sine.hex(617): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 617 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    689. 

  689. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(618) " "Verilog HDL assignment warning at sine.hex(618): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 618 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    690. 

  690. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(619) " "Verilog HDL assignment warning at sine.hex(619): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 619 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    691. 

  691. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(620) " "Verilog HDL assignment warning at sine.hex(620): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 620 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    692. 

  692. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(621) " "Verilog HDL assignment warning at sine.hex(621): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 621 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    693. 

  693. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(622) " "Verilog HDL assignment warning at sine.hex(622): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 622 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    694. 

  694. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(623) " "Verilog HDL assignment warning at sine.hex(623): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 623 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    695. 

  695. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(624) " "Verilog HDL assignment warning at sine.hex(624): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 624 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    696. 

  696. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(625) " "Verilog HDL assignment warning at sine.hex(625): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 625 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    697. 

  697. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(626) " "Verilog HDL assignment warning at sine.hex(626): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 626 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    698. 

  698. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(627) " "Verilog HDL assignment warning at sine.hex(627): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 627 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    699. 

  699. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(628) " "Verilog HDL assignment warning at sine.hex(628): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 628 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    700. 

  700. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(629) " "Verilog HDL assignment warning at sine.hex(629): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 629 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    701. 

  701. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(630) " "Verilog HDL assignment warning at sine.hex(630): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 630 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    702. 

  702. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(631) " "Verilog HDL assignment warning at sine.hex(631): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 631 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    703. 

  703. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(632) " "Verilog HDL assignment warning at sine.hex(632): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 632 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    704. 

  704. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(633) " "Verilog HDL assignment warning at sine.hex(633): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 633 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    705. 

  705. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(634) " "Verilog HDL assignment warning at sine.hex(634): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 634 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    706. 

  706. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(635) " "Verilog HDL assignment warning at sine.hex(635): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 635 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    707. 

  707. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(636) " "Verilog HDL assignment warning at sine.hex(636): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 636 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    708. 

  708. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(637) " "Verilog HDL assignment warning at sine.hex(637): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 637 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    709. 

  709. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(638) " "Verilog HDL assignment warning at sine.hex(638): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 638 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    710. 

  710. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(639) " "Verilog HDL assignment warning at sine.hex(639): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 639 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    711. 

  711. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(640) " "Verilog HDL assignment warning at sine.hex(640): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 640 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    712. 

  712. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(641) " "Verilog HDL assignment warning at sine.hex(641): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 641 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    713. 

  713. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(642) " "Verilog HDL assignment warning at sine.hex(642): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 642 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    714. 

  714. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(643) " "Verilog HDL assignment warning at sine.hex(643): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 643 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    715. 

  715. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(644) " "Verilog HDL assignment warning at sine.hex(644): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 644 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516302 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    716. 

  716. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(645) " "Verilog HDL assignment warning at sine.hex(645): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 645 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    717. 

  717. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(646) " "Verilog HDL assignment warning at sine.hex(646): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 646 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    718. 

  718. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(647) " "Verilog HDL assignment warning at sine.hex(647): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 647 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    719. 

  719. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(648) " "Verilog HDL assignment warning at sine.hex(648): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 648 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    720. 

  720. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(649) " "Verilog HDL assignment warning at sine.hex(649): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 649 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    721. 

  721. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(650) " "Verilog HDL assignment warning at sine.hex(650): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 650 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    722. 

  722. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(651) " "Verilog HDL assignment warning at sine.hex(651): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 651 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    723. 

  723. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(652) " "Verilog HDL assignment warning at sine.hex(652): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 652 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    724. 

  724. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(653) " "Verilog HDL assignment warning at sine.hex(653): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 653 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    725. 

  725. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(654) " "Verilog HDL assignment warning at sine.hex(654): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 654 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    726. 

  726. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(655) " "Verilog HDL assignment warning at sine.hex(655): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 655 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    727. 

  727. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(656) " "Verilog HDL assignment warning at sine.hex(656): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 656 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    728. 

  728. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(657) " "Verilog HDL assignment warning at sine.hex(657): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 657 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    729. 

  729. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(658) " "Verilog HDL assignment warning at sine.hex(658): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 658 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    730. 

  730. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(659) " "Verilog HDL assignment warning at sine.hex(659): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 659 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    731. 

  731. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(660) " "Verilog HDL assignment warning at sine.hex(660): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 660 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    732. 

  732. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(661) " "Verilog HDL assignment warning at sine.hex(661): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 661 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    733. 

  733. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(662) " "Verilog HDL assignment warning at sine.hex(662): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 662 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    734. 

  734. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(663) " "Verilog HDL assignment warning at sine.hex(663): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 663 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    735. 

  735. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(664) " "Verilog HDL assignment warning at sine.hex(664): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 664 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    736. 

  736. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(665) " "Verilog HDL assignment warning at sine.hex(665): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 665 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    737. 

  737. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(666) " "Verilog HDL assignment warning at sine.hex(666): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 666 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    738. 

  738. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(667) " "Verilog HDL assignment warning at sine.hex(667): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 667 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    739. 

  739. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(668) " "Verilog HDL assignment warning at sine.hex(668): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 668 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    740. 

  740. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(669) " "Verilog HDL assignment warning at sine.hex(669): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 669 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    741. 

  741. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(670) " "Verilog HDL assignment warning at sine.hex(670): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 670 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    742. 

  742. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(671) " "Verilog HDL assignment warning at sine.hex(671): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 671 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    743. 

  743. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(672) " "Verilog HDL assignment warning at sine.hex(672): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 672 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516303 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    744. 

  744. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(673) " "Verilog HDL assignment warning at sine.hex(673): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 673 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    745. 

  745. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(674) " "Verilog HDL assignment warning at sine.hex(674): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 674 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    746. 

  746. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(675) " "Verilog HDL assignment warning at sine.hex(675): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 675 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    747. 

  747. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(676) " "Verilog HDL assignment warning at sine.hex(676): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 676 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    748. 

  748. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(677) " "Verilog HDL assignment warning at sine.hex(677): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 677 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    749. 

  749. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(678) " "Verilog HDL assignment warning at sine.hex(678): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 678 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    750. 

  750. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(679) " "Verilog HDL assignment warning at sine.hex(679): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 679 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    751. 

  751. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(680) " "Verilog HDL assignment warning at sine.hex(680): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 680 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    752. 

  752. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(681) " "Verilog HDL assignment warning at sine.hex(681): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 681 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    753. 

  753. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(682) " "Verilog HDL assignment warning at sine.hex(682): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 682 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    754. 

  754. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(683) " "Verilog HDL assignment warning at sine.hex(683): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 683 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    755. 

  755. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(684) " "Verilog HDL assignment warning at sine.hex(684): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 684 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    756. 

  756. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(685) " "Verilog HDL assignment warning at sine.hex(685): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 685 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    757. 

  757. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(686) " "Verilog HDL assignment warning at sine.hex(686): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 686 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    758. 

  758. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(687) " "Verilog HDL assignment warning at sine.hex(687): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 687 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    759. 

  759. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(688) " "Verilog HDL assignment warning at sine.hex(688): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 688 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    760. 

  760. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(689) " "Verilog HDL assignment warning at sine.hex(689): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 689 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    761. 

  761. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(690) " "Verilog HDL assignment warning at sine.hex(690): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 690 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    762. 

  762. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(691) " "Verilog HDL assignment warning at sine.hex(691): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 691 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    763. 

  763. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(692) " "Verilog HDL assignment warning at sine.hex(692): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 692 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    764. 

  764. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(693) " "Verilog HDL assignment warning at sine.hex(693): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 693 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    765. 

  765. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(694) " "Verilog HDL assignment warning at sine.hex(694): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 694 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    766. 

  766. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(695) " "Verilog HDL assignment warning at sine.hex(695): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 695 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    767. 

  767. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(696) " "Verilog HDL assignment warning at sine.hex(696): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 696 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    768. 

  768. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(697) " "Verilog HDL assignment warning at sine.hex(697): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 697 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    769. 

  769. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(698) " "Verilog HDL assignment warning at sine.hex(698): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 698 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    770. 

  770. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(699) " "Verilog HDL assignment warning at sine.hex(699): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 699 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516304 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    771. 

  771. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(700) " "Verilog HDL assignment warning at sine.hex(700): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 700 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    772. 

  772. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(701) " "Verilog HDL assignment warning at sine.hex(701): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 701 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    773. 

  773. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(702) " "Verilog HDL assignment warning at sine.hex(702): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 702 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    774. 

  774. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(703) " "Verilog HDL assignment warning at sine.hex(703): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 703 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    775. 

  775. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(704) " "Verilog HDL assignment warning at sine.hex(704): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 704 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    776. 

  776. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(705) " "Verilog HDL assignment warning at sine.hex(705): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 705 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    777. 

  777. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(706) " "Verilog HDL assignment warning at sine.hex(706): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 706 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    778. 

  778. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(707) " "Verilog HDL assignment warning at sine.hex(707): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 707 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    779. 

  779. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(708) " "Verilog HDL assignment warning at sine.hex(708): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 708 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    780. 

  780. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(709) " "Verilog HDL assignment warning at sine.hex(709): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 709 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    781. 

  781. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(710) " "Verilog HDL assignment warning at sine.hex(710): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 710 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    782. 

  782. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(711) " "Verilog HDL assignment warning at sine.hex(711): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 711 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    783. 

  783. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(712) " "Verilog HDL assignment warning at sine.hex(712): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 712 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    784. 

  784. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(713) " "Verilog HDL assignment warning at sine.hex(713): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 713 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    785. 

  785. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(714) " "Verilog HDL assignment warning at sine.hex(714): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 714 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    786. 

  786. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(715) " "Verilog HDL assignment warning at sine.hex(715): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 715 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    787. 

  787. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(716) " "Verilog HDL assignment warning at sine.hex(716): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 716 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    788. 

  788. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(717) " "Verilog HDL assignment warning at sine.hex(717): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 717 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    789. 

  789. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(718) " "Verilog HDL assignment warning at sine.hex(718): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 718 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    790. 

  790. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(719) " "Verilog HDL assignment warning at sine.hex(719): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 719 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    791. 

  791. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(720) " "Verilog HDL assignment warning at sine.hex(720): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 720 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    792. 

  792. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(721) " "Verilog HDL assignment warning at sine.hex(721): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 721 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    793. 

  793. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(722) " "Verilog HDL assignment warning at sine.hex(722): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 722 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    794. 

  794. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(723) " "Verilog HDL assignment warning at sine.hex(723): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 723 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    795. 

  795. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(724) " "Verilog HDL assignment warning at sine.hex(724): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 724 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    796. 

  796. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(725) " "Verilog HDL assignment warning at sine.hex(725): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 725 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    797. 

  797. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(726) " "Verilog HDL assignment warning at sine.hex(726): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 726 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    798. 

  798. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(727) " "Verilog HDL assignment warning at sine.hex(727): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 727 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516306 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    799. 

  799. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(728) " "Verilog HDL assignment warning at sine.hex(728): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 728 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    800. 

  800. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(729) " "Verilog HDL assignment warning at sine.hex(729): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 729 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    801. 

  801. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(730) " "Verilog HDL assignment warning at sine.hex(730): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 730 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    802. 

  802. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(731) " "Verilog HDL assignment warning at sine.hex(731): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 731 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    803. 

  803. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(732) " "Verilog HDL assignment warning at sine.hex(732): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 732 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    804. 

  804. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(733) " "Verilog HDL assignment warning at sine.hex(733): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 733 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    805. 

  805. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(734) " "Verilog HDL assignment warning at sine.hex(734): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 734 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    806. 

  806. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(735) " "Verilog HDL assignment warning at sine.hex(735): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 735 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    807. 

  807. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(736) " "Verilog HDL assignment warning at sine.hex(736): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 736 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    808. 

  808. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(737) " "Verilog HDL assignment warning at sine.hex(737): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 737 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    809. 

  809. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(738) " "Verilog HDL assignment warning at sine.hex(738): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 738 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    810. 

  810. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(739) " "Verilog HDL assignment warning at sine.hex(739): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 739 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    811. 

  811. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(740) " "Verilog HDL assignment warning at sine.hex(740): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 740 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    812. 

  812. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(741) " "Verilog HDL assignment warning at sine.hex(741): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 741 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    813. 

  813. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(742) " "Verilog HDL assignment warning at sine.hex(742): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 742 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    814. 

  814. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(743) " "Verilog HDL assignment warning at sine.hex(743): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 743 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    815. 

  815. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(744) " "Verilog HDL assignment warning at sine.hex(744): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 744 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    816. 

  816. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(745) " "Verilog HDL assignment warning at sine.hex(745): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 745 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    817. 

  817. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(746) " "Verilog HDL assignment warning at sine.hex(746): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 746 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    818. 

  818. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(747) " "Verilog HDL assignment warning at sine.hex(747): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 747 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    819. 

  819. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(748) " "Verilog HDL assignment warning at sine.hex(748): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 748 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    820. 

  820. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(749) " "Verilog HDL assignment warning at sine.hex(749): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 749 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    821. 

  821. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(750) " "Verilog HDL assignment warning at sine.hex(750): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 750 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    822. 

  822. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(751) " "Verilog HDL assignment warning at sine.hex(751): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 751 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    823. 

  823. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(752) " "Verilog HDL assignment warning at sine.hex(752): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 752 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    824. 

  824. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(753) " "Verilog HDL assignment warning at sine.hex(753): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 753 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    825. 

  825. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(754) " "Verilog HDL assignment warning at sine.hex(754): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 754 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516307 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    826. 

  826. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(755) " "Verilog HDL assignment warning at sine.hex(755): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 755 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    827. 

  827. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(756) " "Verilog HDL assignment warning at sine.hex(756): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 756 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    828. 

  828. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(757) " "Verilog HDL assignment warning at sine.hex(757): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 757 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    829. 

  829. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(758) " "Verilog HDL assignment warning at sine.hex(758): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 758 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    830. 

  830. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(759) " "Verilog HDL assignment warning at sine.hex(759): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 759 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    831. 

  831. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(760) " "Verilog HDL assignment warning at sine.hex(760): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 760 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    832. 

  832. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(761) " "Verilog HDL assignment warning at sine.hex(761): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 761 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    833. 

  833. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(762) " "Verilog HDL assignment warning at sine.hex(762): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 762 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    834. 

  834. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(763) " "Verilog HDL assignment warning at sine.hex(763): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 763 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    835. 

  835. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(764) " "Verilog HDL assignment warning at sine.hex(764): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 764 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    836. 

  836. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(765) " "Verilog HDL assignment warning at sine.hex(765): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 765 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    837. 

  837. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(766) " "Verilog HDL assignment warning at sine.hex(766): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 766 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    838. 

  838. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(767) " "Verilog HDL assignment warning at sine.hex(767): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 767 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    839. 

  839. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(768) " "Verilog HDL assignment warning at sine.hex(768): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 768 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    840. 

  840. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(769) " "Verilog HDL assignment warning at sine.hex(769): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 769 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    841. 

  841. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(770) " "Verilog HDL assignment warning at sine.hex(770): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 770 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    842. 

  842. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(771) " "Verilog HDL assignment warning at sine.hex(771): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 771 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    843. 

  843. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(772) " "Verilog HDL assignment warning at sine.hex(772): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 772 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    844. 

  844. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(773) " "Verilog HDL assignment warning at sine.hex(773): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 773 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    845. 

  845. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(774) " "Verilog HDL assignment warning at sine.hex(774): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 774 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    846. 

  846. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(775) " "Verilog HDL assignment warning at sine.hex(775): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 775 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    847. 

  847. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(776) " "Verilog HDL assignment warning at sine.hex(776): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 776 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    848. 

  848. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(777) " "Verilog HDL assignment warning at sine.hex(777): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 777 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    849. 

  849. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(778) " "Verilog HDL assignment warning at sine.hex(778): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 778 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    850. 

  850. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(779) " "Verilog HDL assignment warning at sine.hex(779): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 779 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516308 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    851. 

  851. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(780) " "Verilog HDL assignment warning at sine.hex(780): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 780 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    852. 

  852. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(781) " "Verilog HDL assignment warning at sine.hex(781): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 781 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    853. 

  853. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(782) " "Verilog HDL assignment warning at sine.hex(782): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 782 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    854. 

  854. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(783) " "Verilog HDL assignment warning at sine.hex(783): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 783 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    855. 

  855. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(784) " "Verilog HDL assignment warning at sine.hex(784): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 784 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    856. 

  856. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(785) " "Verilog HDL assignment warning at sine.hex(785): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 785 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    857. 

  857. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(786) " "Verilog HDL assignment warning at sine.hex(786): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 786 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    858. 

  858. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(787) " "Verilog HDL assignment warning at sine.hex(787): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 787 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    859. 

  859. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(788) " "Verilog HDL assignment warning at sine.hex(788): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 788 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    860. 

  860. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(789) " "Verilog HDL assignment warning at sine.hex(789): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 789 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    861. 

  861. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(790) " "Verilog HDL assignment warning at sine.hex(790): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 790 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    862. 

  862. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(791) " "Verilog HDL assignment warning at sine.hex(791): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 791 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    863. 

  863. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(792) " "Verilog HDL assignment warning at sine.hex(792): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 792 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    864. 

  864. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(793) " "Verilog HDL assignment warning at sine.hex(793): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 793 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    865. 

  865. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(794) " "Verilog HDL assignment warning at sine.hex(794): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 794 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    866. 

  866. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(795) " "Verilog HDL assignment warning at sine.hex(795): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 795 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    867. 

  867. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(796) " "Verilog HDL assignment warning at sine.hex(796): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 796 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    868. 

  868. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(797) " "Verilog HDL assignment warning at sine.hex(797): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 797 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    869. 

  869. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(798) " "Verilog HDL assignment warning at sine.hex(798): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 798 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    870. 

  870. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(799) " "Verilog HDL assignment warning at sine.hex(799): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 799 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    871. 

  871. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(800) " "Verilog HDL assignment warning at sine.hex(800): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 800 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    872. 

  872. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(801) " "Verilog HDL assignment warning at sine.hex(801): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 801 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    873. 

  873. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(802) " "Verilog HDL assignment warning at sine.hex(802): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 802 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    874. 

  874. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(803) " "Verilog HDL assignment warning at sine.hex(803): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 803 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    875. 

  875. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(804) " "Verilog HDL assignment warning at sine.hex(804): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 804 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    876. 

  876. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(805) " "Verilog HDL assignment warning at sine.hex(805): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 805 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    877. 

  877. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(806) " "Verilog HDL assignment warning at sine.hex(806): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 806 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    878. 

  878. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(807) " "Verilog HDL assignment warning at sine.hex(807): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 807 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    879. 

  879. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(808) " "Verilog HDL assignment warning at sine.hex(808): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 808 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    880. 

  880. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(809) " "Verilog HDL assignment warning at sine.hex(809): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 809 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    881. 

  881. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(810) " "Verilog HDL assignment warning at sine.hex(810): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 810 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    882. 

  882. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(811) " "Verilog HDL assignment warning at sine.hex(811): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 811 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    883. 

  883. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(812) " "Verilog HDL assignment warning at sine.hex(812): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 812 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    884. 

  884. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(813) " "Verilog HDL assignment warning at sine.hex(813): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 813 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    885. 

  885. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(814) " "Verilog HDL assignment warning at sine.hex(814): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 814 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    886. 

  886. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(815) " "Verilog HDL assignment warning at sine.hex(815): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 815 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    887. 

  887. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(816) " "Verilog HDL assignment warning at sine.hex(816): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 816 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    888. 

  888. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(817) " "Verilog HDL assignment warning at sine.hex(817): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 817 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    889. 

  889. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(818) " "Verilog HDL assignment warning at sine.hex(818): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 818 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    890. 

  890. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(819) " "Verilog HDL assignment warning at sine.hex(819): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 819 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    891. 

  891. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(820) " "Verilog HDL assignment warning at sine.hex(820): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 820 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516309 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    892. 

  892. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(821) " "Verilog HDL assignment warning at sine.hex(821): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 821 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    893. 

  893. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(822) " "Verilog HDL assignment warning at sine.hex(822): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 822 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    894. 

  894. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(823) " "Verilog HDL assignment warning at sine.hex(823): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 823 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    895. 

  895. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(824) " "Verilog HDL assignment warning at sine.hex(824): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 824 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    896. 

  896. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(825) " "Verilog HDL assignment warning at sine.hex(825): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 825 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    897. 

  897. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(826) " "Verilog HDL assignment warning at sine.hex(826): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 826 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    898. 

  898. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(827) " "Verilog HDL assignment warning at sine.hex(827): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 827 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    899. 

  899. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(828) " "Verilog HDL assignment warning at sine.hex(828): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 828 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    900. 

  900. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(829) " "Verilog HDL assignment warning at sine.hex(829): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 829 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    901. 

  901. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(830) " "Verilog HDL assignment warning at sine.hex(830): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 830 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    902. 

  902. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(831) " "Verilog HDL assignment warning at sine.hex(831): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 831 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    903. 

  903. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(832) " "Verilog HDL assignment warning at sine.hex(832): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 832 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    904. 

  904. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(833) " "Verilog HDL assignment warning at sine.hex(833): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 833 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    905. 

  905. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(834) " "Verilog HDL assignment warning at sine.hex(834): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 834 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    906. 

  906. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(835) " "Verilog HDL assignment warning at sine.hex(835): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 835 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    907. 

  907. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(836) " "Verilog HDL assignment warning at sine.hex(836): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 836 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    908. 

  908. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(837) " "Verilog HDL assignment warning at sine.hex(837): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 837 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    909. 

  909. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(838) " "Verilog HDL assignment warning at sine.hex(838): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 838 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    910. 

  910. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(839) " "Verilog HDL assignment warning at sine.hex(839): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 839 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516310 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    911. 

  911. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(840) " "Verilog HDL assignment warning at sine.hex(840): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 840 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    912. 

  912. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(841) " "Verilog HDL assignment warning at sine.hex(841): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 841 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    913. 

  913. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(842) " "Verilog HDL assignment warning at sine.hex(842): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 842 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    914. 

  914. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(843) " "Verilog HDL assignment warning at sine.hex(843): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 843 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    915. 

  915. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(844) " "Verilog HDL assignment warning at sine.hex(844): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 844 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    916. 

  916. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(845) " "Verilog HDL assignment warning at sine.hex(845): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 845 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    917. 

  917. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(846) " "Verilog HDL assignment warning at sine.hex(846): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 846 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    918. 

  918. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(847) " "Verilog HDL assignment warning at sine.hex(847): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 847 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    919. 

  919. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(848) " "Verilog HDL assignment warning at sine.hex(848): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 848 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    920. 

  920. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(849) " "Verilog HDL assignment warning at sine.hex(849): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 849 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    921. 

  921. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(850) " "Verilog HDL assignment warning at sine.hex(850): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 850 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    922. 

  922. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(851) " "Verilog HDL assignment warning at sine.hex(851): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 851 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    923. 

  923. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(852) " "Verilog HDL assignment warning at sine.hex(852): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 852 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    924. 

  924. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(853) " "Verilog HDL assignment warning at sine.hex(853): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 853 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    925. 

  925. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(854) " "Verilog HDL assignment warning at sine.hex(854): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 854 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    926. 

  926. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(855) " "Verilog HDL assignment warning at sine.hex(855): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 855 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    927. 

  927. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(856) " "Verilog HDL assignment warning at sine.hex(856): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 856 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    928. 

  928. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(857) " "Verilog HDL assignment warning at sine.hex(857): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 857 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    929. 

  929. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(858) " "Verilog HDL assignment warning at sine.hex(858): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 858 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516311 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    930. 

  930. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(859) " "Verilog HDL assignment warning at sine.hex(859): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 859 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    931. 

  931. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(860) " "Verilog HDL assignment warning at sine.hex(860): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 860 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    932. 

  932. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(861) " "Verilog HDL assignment warning at sine.hex(861): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 861 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    933. 

  933. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(862) " "Verilog HDL assignment warning at sine.hex(862): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 862 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    934. 

  934. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(863) " "Verilog HDL assignment warning at sine.hex(863): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 863 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    935. 

  935. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(864) " "Verilog HDL assignment warning at sine.hex(864): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 864 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    936. 

  936. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(865) " "Verilog HDL assignment warning at sine.hex(865): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 865 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    937. 

  937. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(866) " "Verilog HDL assignment warning at sine.hex(866): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 866 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    938. 

  938. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(867) " "Verilog HDL assignment warning at sine.hex(867): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 867 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    939. 

  939. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(868) " "Verilog HDL assignment warning at sine.hex(868): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 868 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516312 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    940. 

  940. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(869) " "Verilog HDL assignment warning at sine.hex(869): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 869 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    941. 

  941. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(870) " "Verilog HDL assignment warning at sine.hex(870): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 870 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    942. 

  942. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(871) " "Verilog HDL assignment warning at sine.hex(871): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 871 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    943. 

  943. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(872) " "Verilog HDL assignment warning at sine.hex(872): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 872 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    944. 

  944. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(873) " "Verilog HDL assignment warning at sine.hex(873): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 873 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    945. 

  945. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(874) " "Verilog HDL assignment warning at sine.hex(874): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 874 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    946. 

  946. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(875) " "Verilog HDL assignment warning at sine.hex(875): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 875 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    947. 

  947. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(876) " "Verilog HDL assignment warning at sine.hex(876): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 876 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    948. 

  948. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(877) " "Verilog HDL assignment warning at sine.hex(877): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 877 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    949. 

  949. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(878) " "Verilog HDL assignment warning at sine.hex(878): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 878 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    950. 

  950. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(879) " "Verilog HDL assignment warning at sine.hex(879): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 879 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    951. 

  951. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(880) " "Verilog HDL assignment warning at sine.hex(880): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 880 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    952. 

  952. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(881) " "Verilog HDL assignment warning at sine.hex(881): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 881 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    953. 

  953. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(882) " "Verilog HDL assignment warning at sine.hex(882): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 882 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    954. 

  954. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(883) " "Verilog HDL assignment warning at sine.hex(883): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 883 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    955. 

  955. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(884) " "Verilog HDL assignment warning at sine.hex(884): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 884 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    956. 

  956. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(885) " "Verilog HDL assignment warning at sine.hex(885): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 885 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    957. 

  957. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(886) " "Verilog HDL assignment warning at sine.hex(886): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 886 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    958. 

  958. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(887) " "Verilog HDL assignment warning at sine.hex(887): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 887 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    959. 

  959. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(888) " "Verilog HDL assignment warning at sine.hex(888): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 888 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    960. 

  960. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(889) " "Verilog HDL assignment warning at sine.hex(889): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 889 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516313 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    961. 

  961. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(890) " "Verilog HDL assignment warning at sine.hex(890): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 890 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    962. 

  962. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(891) " "Verilog HDL assignment warning at sine.hex(891): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 891 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    963. 

  963. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(892) " "Verilog HDL assignment warning at sine.hex(892): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 892 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    964. 

  964. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(893) " "Verilog HDL assignment warning at sine.hex(893): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 893 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    965. 

  965. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(894) " "Verilog HDL assignment warning at sine.hex(894): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 894 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    966. 

  966. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(895) " "Verilog HDL assignment warning at sine.hex(895): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 895 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    967. 

  967. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(896) " "Verilog HDL assignment warning at sine.hex(896): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 896 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    968. 

  968. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(897) " "Verilog HDL assignment warning at sine.hex(897): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 897 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    969. 

  969. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(898) " "Verilog HDL assignment warning at sine.hex(898): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 898 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    970. 

  970. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(899) " "Verilog HDL assignment warning at sine.hex(899): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 899 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    971. 

  971. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(900) " "Verilog HDL assignment warning at sine.hex(900): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 900 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    972. 

  972. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(901) " "Verilog HDL assignment warning at sine.hex(901): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 901 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    973. 

  973. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(902) " "Verilog HDL assignment warning at sine.hex(902): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 902 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    974. 

  974. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(903) " "Verilog HDL assignment warning at sine.hex(903): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 903 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    975. 

  975. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(904) " "Verilog HDL assignment warning at sine.hex(904): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 904 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    976. 

  976. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(905) " "Verilog HDL assignment warning at sine.hex(905): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 905 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    977. 

  977. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(906) " "Verilog HDL assignment warning at sine.hex(906): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 906 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    978. 

  978. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(907) " "Verilog HDL assignment warning at sine.hex(907): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 907 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    979. 

  979. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(908) " "Verilog HDL assignment warning at sine.hex(908): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 908 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    980. 

  980. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(909) " "Verilog HDL assignment warning at sine.hex(909): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 909 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    981. 

  981. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(910) " "Verilog HDL assignment warning at sine.hex(910): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 910 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    982. 

  982. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(911) " "Verilog HDL assignment warning at sine.hex(911): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 911 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    983. 

  983. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(912) " "Verilog HDL assignment warning at sine.hex(912): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 912 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    984. 

  984. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(913) " "Verilog HDL assignment warning at sine.hex(913): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 913 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    985. 

  985. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(914) " "Verilog HDL assignment warning at sine.hex(914): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 914 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    986. 

  986. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(915) " "Verilog HDL assignment warning at sine.hex(915): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 915 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    987. 

  987. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(916) " "Verilog HDL assignment warning at sine.hex(916): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 916 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516314 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    988. 

  988. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(917) " "Verilog HDL assignment warning at sine.hex(917): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 917 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    989. 

  989. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(918) " "Verilog HDL assignment warning at sine.hex(918): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 918 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    990. 

  990. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(919) " "Verilog HDL assignment warning at sine.hex(919): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 919 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    991. 

  991. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(920) " "Verilog HDL assignment warning at sine.hex(920): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 920 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    992. 

  992. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(921) " "Verilog HDL assignment warning at sine.hex(921): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 921 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    993. 

  993. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(922) " "Verilog HDL assignment warning at sine.hex(922): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 922 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    994. 

  994. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(923) " "Verilog HDL assignment warning at sine.hex(923): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 923 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    995. 

  995. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(924) " "Verilog HDL assignment warning at sine.hex(924): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 924 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    996. 

  996. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(925) " "Verilog HDL assignment warning at sine.hex(925): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 925 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    997. 

  997. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(926) " "Verilog HDL assignment warning at sine.hex(926): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 926 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    998. 

  998. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(927) " "Verilog HDL assignment warning at sine.hex(927): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 927 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    999. 

  999. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(928) " "Verilog HDL assignment warning at sine.hex(928): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 928 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1000. 

  1000. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(929) " "Verilog HDL assignment warning at sine.hex(929): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 929 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1001. 

  1001. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(930) " "Verilog HDL assignment warning at sine.hex(930): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 930 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1002. 

  1002. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(931) " "Verilog HDL assignment warning at sine.hex(931): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 931 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1003. 

  1003. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(932) " "Verilog HDL assignment warning at sine.hex(932): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 932 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1004. 

  1004. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(933) " "Verilog HDL assignment warning at sine.hex(933): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 933 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1005. 

  1005. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(934) " "Verilog HDL assignment warning at sine.hex(934): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 934 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1006. 

  1006. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(935) " "Verilog HDL assignment warning at sine.hex(935): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 935 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1007. 

  1007. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(936) " "Verilog HDL assignment warning at sine.hex(936): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 936 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1008. 

  1008. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(937) " "Verilog HDL assignment warning at sine.hex(937): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 937 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1009. 

  1009. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(938) " "Verilog HDL assignment warning at sine.hex(938): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 938 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1010. 

  1010. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(939) " "Verilog HDL assignment warning at sine.hex(939): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 939 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1011. 

  1011. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(940) " "Verilog HDL assignment warning at sine.hex(940): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 940 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1012. 

  1012. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(941) " "Verilog HDL assignment warning at sine.hex(941): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 941 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1013. 

  1013. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(942) " "Verilog HDL assignment warning at sine.hex(942): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 942 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516315 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1014. 

  1014. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(943) " "Verilog HDL assignment warning at sine.hex(943): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 943 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1015. 

  1015. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(944) " "Verilog HDL assignment warning at sine.hex(944): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 944 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1016. 

  1016. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(945) " "Verilog HDL assignment warning at sine.hex(945): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 945 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1017. 

  1017. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(946) " "Verilog HDL assignment warning at sine.hex(946): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 946 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1018. 

  1018. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(947) " "Verilog HDL assignment warning at sine.hex(947): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 947 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1019. 

  1019. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(948) " "Verilog HDL assignment warning at sine.hex(948): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 948 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1020. 

  1020. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(949) " "Verilog HDL assignment warning at sine.hex(949): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 949 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1021. 

  1021. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(950) " "Verilog HDL assignment warning at sine.hex(950): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 950 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1022. 

  1022. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(951) " "Verilog HDL assignment warning at sine.hex(951): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 951 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1023. 

  1023. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(952) " "Verilog HDL assignment warning at sine.hex(952): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 952 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1024. 

  1024. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(953) " "Verilog HDL assignment warning at sine.hex(953): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 953 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1025. 

  1025. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(954) " "Verilog HDL assignment warning at sine.hex(954): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 954 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1026. 

  1026. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(955) " "Verilog HDL assignment warning at sine.hex(955): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 955 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1027. 

  1027. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(956) " "Verilog HDL assignment warning at sine.hex(956): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 956 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1028. 

  1028. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(957) " "Verilog HDL assignment warning at sine.hex(957): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 957 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1029. 

  1029. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(958) " "Verilog HDL assignment warning at sine.hex(958): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 958 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1030. 

  1030. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(959) " "Verilog HDL assignment warning at sine.hex(959): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 959 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1031. 

  1031. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(960) " "Verilog HDL assignment warning at sine.hex(960): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 960 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1032. 

  1032. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(961) " "Verilog HDL assignment warning at sine.hex(961): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 961 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1033. 

  1033. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(962) " "Verilog HDL assignment warning at sine.hex(962): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 962 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1034. 

  1034. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(963) " "Verilog HDL assignment warning at sine.hex(963): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 963 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1035. 

  1035. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(964) " "Verilog HDL assignment warning at sine.hex(964): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 964 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1036. 

  1036. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(965) " "Verilog HDL assignment warning at sine.hex(965): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 965 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1037. 

  1037. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(966) " "Verilog HDL assignment warning at sine.hex(966): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 966 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1038. 

  1038. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(967) " "Verilog HDL assignment warning at sine.hex(967): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 967 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1039. 

  1039. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(968) " "Verilog HDL assignment warning at sine.hex(968): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 968 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1040. 

  1040. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(969) " "Verilog HDL assignment warning at sine.hex(969): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 969 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1041. 

  1041. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(970) " "Verilog HDL assignment warning at sine.hex(970): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 970 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516316 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1042. 

  1042. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(971) " "Verilog HDL assignment warning at sine.hex(971): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 971 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1043. 

  1043. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(972) " "Verilog HDL assignment warning at sine.hex(972): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 972 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1044. 

  1044. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(973) " "Verilog HDL assignment warning at sine.hex(973): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 973 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1045. 

  1045. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(974) " "Verilog HDL assignment warning at sine.hex(974): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 974 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1046. 

  1046. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(975) " "Verilog HDL assignment warning at sine.hex(975): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 975 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1047. 

  1047. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(976) " "Verilog HDL assignment warning at sine.hex(976): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 976 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1048. 

  1048. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(977) " "Verilog HDL assignment warning at sine.hex(977): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 977 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1049. 

  1049. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(978) " "Verilog HDL assignment warning at sine.hex(978): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 978 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1050. 

  1050. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(979) " "Verilog HDL assignment warning at sine.hex(979): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 979 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1051. 

  1051. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(980) " "Verilog HDL assignment warning at sine.hex(980): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 980 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1052. 

  1052. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(981) " "Verilog HDL assignment warning at sine.hex(981): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 981 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1053. 

  1053. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(982) " "Verilog HDL assignment warning at sine.hex(982): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 982 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1054. 

  1054. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(983) " "Verilog HDL assignment warning at sine.hex(983): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 983 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1055. 

  1055. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(984) " "Verilog HDL assignment warning at sine.hex(984): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 984 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1056. 

  1056. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(985) " "Verilog HDL assignment warning at sine.hex(985): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 985 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1057. 

  1057. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(986) " "Verilog HDL assignment warning at sine.hex(986): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 986 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1058. 

  1058. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(987) " "Verilog HDL assignment warning at sine.hex(987): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 987 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1059. 

  1059. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(988) " "Verilog HDL assignment warning at sine.hex(988): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 988 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1060. 

  1060. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(989) " "Verilog HDL assignment warning at sine.hex(989): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 989 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1061. 

  1061. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(990) " "Verilog HDL assignment warning at sine.hex(990): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 990 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1062. 

  1062. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(991) " "Verilog HDL assignment warning at sine.hex(991): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 991 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1063. 

  1063. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(992) " "Verilog HDL assignment warning at sine.hex(992): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 992 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1064. 

  1064. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(993) " "Verilog HDL assignment warning at sine.hex(993): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 993 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1065. 

  1065. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(994) " "Verilog HDL assignment warning at sine.hex(994): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 994 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1066. 

  1066. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(995) " "Verilog HDL assignment warning at sine.hex(995): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 995 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1067. 

  1067. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(996) " "Verilog HDL assignment warning at sine.hex(996): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 996 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1068. 

  1068. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(997) " "Verilog HDL assignment warning at sine.hex(997): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 997 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1069. 

  1069. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(998) " "Verilog HDL assignment warning at sine.hex(998): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 998 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516317 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1070. 

  1070. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(999) " "Verilog HDL assignment warning at sine.hex(999): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 999 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1071. 

  1071. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1000) " "Verilog HDL assignment warning at sine.hex(1000): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1000 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1072. 

  1072. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1001) " "Verilog HDL assignment warning at sine.hex(1001): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1001 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1073. 

  1073. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1002) " "Verilog HDL assignment warning at sine.hex(1002): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1002 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1074. 

  1074. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1003) " "Verilog HDL assignment warning at sine.hex(1003): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1003 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1075. 

  1075. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1004) " "Verilog HDL assignment warning at sine.hex(1004): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1004 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1076. 

  1076. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1005) " "Verilog HDL assignment warning at sine.hex(1005): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1005 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1077. 

  1077. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1006) " "Verilog HDL assignment warning at sine.hex(1006): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1006 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1078. 

  1078. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1007) " "Verilog HDL assignment warning at sine.hex(1007): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1007 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1079. 

  1079. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1008) " "Verilog HDL assignment warning at sine.hex(1008): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1008 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1080. 

  1080. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1009) " "Verilog HDL assignment warning at sine.hex(1009): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1009 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1081. 

  1081. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1010) " "Verilog HDL assignment warning at sine.hex(1010): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1010 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1082. 

  1082. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1011) " "Verilog HDL assignment warning at sine.hex(1011): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1011 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1083. 

  1083. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1012) " "Verilog HDL assignment warning at sine.hex(1012): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1012 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1084. 

  1084. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1013) " "Verilog HDL assignment warning at sine.hex(1013): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1013 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1085. 

  1085. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1014) " "Verilog HDL assignment warning at sine.hex(1014): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1014 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1086. 

  1086. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1015) " "Verilog HDL assignment warning at sine.hex(1015): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1015 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1087. 

  1087. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1016) " "Verilog HDL assignment warning at sine.hex(1016): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1016 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1088. 

  1088. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1017) " "Verilog HDL assignment warning at sine.hex(1017): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1017 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1089. 

  1089. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1018) " "Verilog HDL assignment warning at sine.hex(1018): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1018 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1090. 

  1090. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1019) " "Verilog HDL assignment warning at sine.hex(1019): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1019 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1091. 

  1091. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1020) " "Verilog HDL assignment warning at sine.hex(1020): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1020 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516318 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1092. 

  1092. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1021) " "Verilog HDL assignment warning at sine.hex(1021): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1021 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1093. 

  1093. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1022) " "Verilog HDL assignment warning at sine.hex(1022): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1022 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1094. 

  1094. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1023) " "Verilog HDL assignment warning at sine.hex(1023): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1023 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1095. 

  1095. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1024) " "Verilog HDL assignment warning at sine.hex(1024): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1024 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1096. 

  1096. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(678) " "Verilog HDL assignment warning at analog_ip.v(678): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 678 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1097. 

  1097. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(686) " "Verilog HDL assignment warning at analog_ip.v(686): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 686 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1098. 

  1098. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(691) " "Verilog HDL assignment warning at analog_ip.v(691): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 691 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1099. 

  1099. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(699) " "Verilog HDL assignment warning at analog_ip.v(699): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 699 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1100. 

  1100. { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "mult analog_ip.v(669) " "Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable \"mult\", which holds its previous value in one or more paths through the always construct" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 669 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1101. 

  1101. { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "step analog_ip.v(669) " "Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable \"step\", which holds its previous value in one or more paths through the always construct" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 669 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1102. 

  1102. { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.data_a 0 analog_ip.v(635) " "Net \"sine_rom.data_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1103. 

  1103. { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.waddr_a 0 analog_ip.v(635) " "Net \"sine_rom.waddr_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1104. 

  1104. { "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.we_a 0 analog_ip.v(635) " "Net \"sine_rom.we_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778307516319 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
    1105. 

  1105. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_dac analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Elaborating entity \"alta_dac\" for hierarchy \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst\"" {  } { { "analog_ip.v" "dac_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 718 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516321 ""}
    1106. 

  1106. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud_detect analog_ip:macro_inst\|baud_detect:u_baud_detect " "Elaborating entity \"baud_detect\" for hierarchy \"analog_ip:macro_inst\|baud_detect:u_baud_detect\"" {  } { { "analog_ip.v" "u_baud_detect" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 327 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516325 ""}
    1107. 

  1107. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(33) " "Verilog HDL assignment warning at baud_detect.v(33): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516329 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
    1108. 

  1108. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(35) " "Verilog HDL assignment warning at baud_detect.v(35): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516329 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
    1109. 

  1109. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 baud_detect.v(40) " "Verilog HDL assignment warning at baud_detect.v(40): truncated value with size 32 to match size of target (4)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516329 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
    1110. 

  1110. { "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "min_time baud_detect.v(28) " "Verilog HDL Always Construct warning at baud_detect.v(28): inferring latch(es) for variable \"min_time\", which holds its previous value in one or more paths through the always construct" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 28 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778307516329 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
    1111. 

  1111. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(50) " "Verilog HDL assignment warning at baud_detect.v(50): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516329 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
    1112. 

  1112. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Elaborating entity \"altsyncram\" for hierarchy \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\"" {  } { { "analog_ip.v" "u_dual_port_ram" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516369 ""}
    1113. 

  1113. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""}
    1114. 

  1114. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Instantiated megafunction \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 2 " "Parameter \"width_byteena_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 2 " "Parameter \"width_byteena_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516372 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1778307516372 ""}
    1115. 

  1115. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sgu1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sgu1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sgu1 " "Found entity 1: altsyncram_sgu1" {  } { { "db/altsyncram_sgu1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altsyncram_sgu1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778307516450 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778307516450 ""}
    1116. 

  1116. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sgu1 analog_ip:macro_inst\|altsyncram:u_dual_port_ram\|altsyncram_sgu1:auto_generated " "Elaborating entity \"altsyncram_sgu1\" for hierarchy \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\|altsyncram_sgu1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516453 ""}
    1117. 

  1117. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb2ram analog_ip:macro_inst\|apb2ram:u_apb2ram " "Elaborating entity \"apb2ram\" for hierarchy \"analog_ip:macro_inst\|apb2ram:u_apb2ram\"" {  } { { "analog_ip.v" "u_apb2ram" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 456 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516457 ""}
    1118. 

  1118. { "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "15 10 apb2ram.v(26) " "Verilog HDL assignment warning at apb2ram.v(26): truncated value with size 15 to match size of target (10)" {  } { { "apb2ram.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778307516457 "|example_board|analog_ip:macro_inst|apb2ram:u_apb2ram"}
    1119. 

  1119. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_rv32 alta_rv32:rv32 " "Elaborating entity \"alta_rv32\" for hierarchy \"alta_rv32:rv32\"" {  } { { "example_board.v" "rv32" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 451 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778307516460 ""}
    1120. 

  1120. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_data alta_sim.v(3739) " "Output port \"gpio0_io_out_data\" at alta_sim.v(3739) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1121. 

  1121. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_en alta_sim.v(3740) " "Output port \"gpio0_io_out_en\" at alta_sim.v(3740) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1122. 

  1122. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_data alta_sim.v(3742) " "Output port \"gpio1_io_out_data\" at alta_sim.v(3742) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1123. 

  1123. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_en alta_sim.v(3743) " "Output port \"gpio1_io_out_en\" at alta_sim.v(3743) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1124. 

  1124. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_data alta_sim.v(3753) " "Output port \"gpio2_io_out_data\" at alta_sim.v(3753) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1125. 

  1125. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_en alta_sim.v(3754) " "Output port \"gpio2_io_out_en\" at alta_sim.v(3754) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1126. 

  1126. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_data alta_sim.v(3756) " "Output port \"gpio3_io_out_data\" at alta_sim.v(3756) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1127. 

  1127. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_en alta_sim.v(3757) " "Output port \"gpio3_io_out_en\" at alta_sim.v(3757) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1128. 

  1128. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_data alta_sim.v(3759) " "Output port \"gpio4_io_out_data\" at alta_sim.v(3759) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516462 "|example_board|alta_rv32:rv32"}
    1129. 

  1129. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_en alta_sim.v(3760) " "Output port \"gpio4_io_out_en\" at alta_sim.v(3760) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1130. 

  1130. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_data alta_sim.v(3762) " "Output port \"gpio5_io_out_data\" at alta_sim.v(3762) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1131. 

  1131. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_en alta_sim.v(3763) " "Output port \"gpio5_io_out_en\" at alta_sim.v(3763) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1132. 

  1132. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_data alta_sim.v(3765) " "Output port \"gpio6_io_out_data\" at alta_sim.v(3765) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1133. 

  1133. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_en alta_sim.v(3766) " "Output port \"gpio6_io_out_en\" at alta_sim.v(3766) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1134. 

  1134. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_data alta_sim.v(3768) " "Output port \"gpio7_io_out_data\" at alta_sim.v(3768) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1135. 

  1135. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_en alta_sim.v(3769) " "Output port \"gpio7_io_out_en\" at alta_sim.v(3769) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1136. 

  1136. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_data alta_sim.v(3771) " "Output port \"gpio8_io_out_data\" at alta_sim.v(3771) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1137. 

  1137. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_en alta_sim.v(3772) " "Output port \"gpio8_io_out_en\" at alta_sim.v(3772) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1138. 

  1138. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_data alta_sim.v(3774) " "Output port \"gpio9_io_out_data\" at alta_sim.v(3774) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1139. 

  1139. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_en alta_sim.v(3775) " "Output port \"gpio9_io_out_en\" at alta_sim.v(3775) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1140. 

  1140. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGSTATE alta_sim.v(3780) " "Output port \"swj_JTAGSTATE\" at alta_sim.v(3780) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516463 "|example_board|alta_rv32:rv32"}
    1141. 

  1141. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGIR alta_sim.v(3781) " "Output port \"swj_JTAGIR\" at alta_sim.v(3781) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516465 "|example_board|alta_rv32:rv32"}
    1142. 

  1142. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "dmactive alta_sim.v(3778) " "Output port \"dmactive\" at alta_sim.v(3778) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3778 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516465 "|example_board|alta_rv32:rv32"}
    1143. 

  1143. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGNSW alta_sim.v(3779) " "Output port \"swj_JTAGNSW\" at alta_sim.v(3779) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3779 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778307516465 "|example_board|alta_rv32:rv32"}
    1144. 

  1144. { "Info" "ISGN_QIC_SYNTHESIS_TOP_SEVERAL" "4 " "4 design partitions require synthesis" { { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "Top " "Partition \"Top\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778307516632 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "macro_inst_apb_adc0_inst_adc_inst " "Partition \"macro_inst_apb_adc0_inst_adc_inst\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778307516632 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "macro_inst_apb_dac0_inst_dac_inst " "Partition \"macro_inst_apb_dac0_inst_dac_inst\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778307516632 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "rv32 " "Partition \"rv32\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778307516632 ""}  } {  } 0 12206 "%1!d! design partitions require synthesis" 0 0 "Quartus II" 0 -1 1778307516632 ""}
    1145. 

  1145. { "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ZERO" "" "No design partitions will skip synthesis in the current incremental compilation" {  } {  } 0 12209 "No design partitions will skip synthesis in the current incremental compilation" 0 0 "Quartus II" 0 -1 1778307516632 ""}
    1146. 

  1146. { "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1778307516968 ""}
    1147. 

  1147. { "Info" "IQSYN_PARALLEL_SYNTHESIS" "4 4 " "Using 4 processors to synthesize 4 partitions in parallel" {  } {  } 0 281037 "Using %1!d! processors to synthesize %2!d! partitions in parallel" 0 0 "Quartus II" 0 -1 1778307516979 ""}
    1148. 

  1148. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 0 1778307517449 ""}
    1149. 

  1149. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 0 1778307517449 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:18:37 2026 " "Processing started: Sat May 09 14:18:37 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 0 1778307517449 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 0 1778307517449 ""}
    1150. 

  1150. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board " "Command: quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 0 1778307517449 ""}
    1151. 

  1151. { "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult0\"" {  } { { "analog_ip.v" "Mult0" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519197 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult2\"" {  } { { "analog_ip.v" "Mult2" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519197 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult3\"" {  } { { "analog_ip.v" "Mult3" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519197 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 0 1778307519197 ""}
    1152. 

  1152. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""}
    1153. 

  1153. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 10 " "Parameter \"LPM_WIDTHB\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519279 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307519279 ""}
    1154. 

  1154. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_oct.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_oct.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_oct " "Found entity 1: mult_oct" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307519340 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307519340 ""}
    1155. 

  1155. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""}
    1156. 

  1156. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519356 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307519356 ""}
    1157. 

  1157. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_pbt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_pbt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_pbt " "Found entity 1: mult_pbt" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307519433 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307519433 ""}
    1158. 

  1158. { "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition Top " "Limiting DSP block usage to 0 DSP block(s) for the partition Top" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778307519662 ""}
    1159. 

  1159. { "Info" "IBAL_BAL_CONVERTED_DSP_SLICES" "3 " "Converted 3 DSP block slices" { { "Info" "IBAL_BAL_OVERALL_DSP_USAGE" "before 3 " "Used 3 DSP blocks before DSP block balancing" { { "Info" "IBAL_BAL_DSP_MODE_USAGE" "Simple Multiplier (18-bit) 3 3 " "Used 3 DSP block slices in \"Simple Multiplier (18-bit)\" mode implemented in approximately 3 DSP blocks" {  } {  } 0 270003 "Used %2!d! DSP block slices in \"%1!s!\" mode implemented in approximately %3!d! DSP blocks" 0 0 "Quartus II" 0 0 1778307519662 ""}  } {  } 0 270002 "Used %2!d! DSP blocks %1!s! DSP block balancing" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_CONVERTED_DSP_SLICES_TO_LE" "3 " "Converted the following 3 DSP block slices to logic elements" { { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_mult1\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519662 ""}  } {  } 0 270013 "Converted the following %1!d! DSP block slices to logic elements" 0 0 "Quartus II" 0 0 1778307519662 ""} { "Info" "IBAL_BAL_OVERALL_DSP_USAGE" "after 0 " "Used 0 DSP blocks after DSP block balancing" {  } {  } 0 270002 "Used %2!d! DSP blocks %1!s! DSP block balancing" 0 0 "Quartus II" 0 0 1778307519662 ""}  } {  } 0 270001 "Converted %1!d! DSP block slices" 0 0 "Quartus II" 0 0 1778307519662 ""}
    1160. 

  1160. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778307519679 ""}
    1161. 

  1161. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778307519679 ""}
    1162. 

  1162. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""}
    1163. 

  1163. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_A UNSIGNED " "Parameter \"MULT_REPRESENTATION_A\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_B UNSIGNED " "Parameter \"MULT_REPRESENTATION_B\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_PIPELINE 0 " "Parameter \"MULT_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLOCK NONE " "Parameter \"MULT_CLOCK\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLEAR NONE " "Parameter \"MULT_CLEAR\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_A_IS_CONSTANT NO " "Parameter \"MULT_INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_B_IS_CONSTANT NO " "Parameter \"MULT_INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 10 " "Parameter \"dataa_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 10 " "Parameter \"datab_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 20 " "Parameter \"output_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clock NONE " "Parameter \"dataa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clock NONE " "Parameter \"datab_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clear NONE " "Parameter \"dataa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clear NONE " "Parameter \"datab_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519728 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307519728 ""}
    1164. 

  1164. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_mult_iug1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_mult_iug1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_mult_iug1 " "Found entity 1: mac_mult_iug1" {  } { { "db/mac_mult_iug1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_mult_iug1.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307519775 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307519775 ""}
    1165. 

  1165. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_aql.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_aql.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_aql " "Found entity 1: mult_aql" {  } { { "db/mult_aql.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_aql.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307519833 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307519833 ""}
    1166. 

  1166. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""}
    1167. 

  1167. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE OUTPUT_ONLY " "Parameter \"OPERATION_MODE\" = \"OUTPUT_ONLY\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 20 " "Parameter \"dataa_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 0 " "Parameter \"datab_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datac_width 0 " "Parameter \"datac_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datad_width 0 " "Parameter \"datad_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 20 " "Parameter \"output_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clock NONE " "Parameter \"addnsub0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clock NONE " "Parameter \"addnsub1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clock NONE " "Parameter \"zeroacc_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clock NONE " "Parameter \"first_adder0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clock NONE " "Parameter \"first_adder1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clear NONE " "Parameter \"addnsub0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clear NONE " "Parameter \"addnsub1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clear NONE " "Parameter \"zeroacc_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clear NONE " "Parameter \"first_adder0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clear NONE " "Parameter \"first_adder1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clock NONE " "Parameter \"signa_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clock NONE " "Parameter \"signb_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clock NONE " "Parameter \"addnsub0_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clock NONE " "Parameter \"addnsub1_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clock NONE " "Parameter \"zeroacc_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clear NONE " "Parameter \"signa_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clear NONE " "Parameter \"signb_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clear NONE " "Parameter \"addnsub0_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clear NONE " "Parameter \"addnsub1_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clear NONE " "Parameter \"zeroacc_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519892 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307519892 ""}
    1168. 

  1168. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_out_lr82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_out_lr82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_out_lr82 " "Found entity 1: mac_out_lr82" {  } { { "db/mac_out_lr82.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_out_lr82.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307519941 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307519941 ""}
    1169. 

  1169. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""}
    1170. 

  1170. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_A UNSIGNED " "Parameter \"MULT_REPRESENTATION_A\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_B UNSIGNED " "Parameter \"MULT_REPRESENTATION_B\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_PIPELINE 0 " "Parameter \"MULT_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLOCK NONE " "Parameter \"MULT_CLOCK\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLEAR NONE " "Parameter \"MULT_CLEAR\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_A_IS_CONSTANT NO " "Parameter \"MULT_INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_B_IS_CONSTANT NO " "Parameter \"MULT_INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 10 " "Parameter \"dataa_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 9 " "Parameter \"datab_width\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 19 " "Parameter \"output_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clock NONE " "Parameter \"dataa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clock NONE " "Parameter \"datab_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clear NONE " "Parameter \"dataa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clear NONE " "Parameter \"datab_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307519951 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307519951 ""}
    1171. 

  1171. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_mult_jtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_mult_jtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_mult_jtg1 " "Found entity 1: mac_mult_jtg1" {  } { { "db/mac_mult_jtg1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_mult_jtg1.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307520000 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307520000 ""}
    1172. 

  1172. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_bpl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_bpl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_bpl " "Found entity 1: mult_bpl" {  } { { "db/mult_bpl.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_bpl.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307520059 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307520059 ""}
    1173. 

  1173. { "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""}
    1174. 

  1174. { "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE OUTPUT_ONLY " "Parameter \"OPERATION_MODE\" = \"OUTPUT_ONLY\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 19 " "Parameter \"dataa_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 0 " "Parameter \"datab_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datac_width 0 " "Parameter \"datac_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datad_width 0 " "Parameter \"datad_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 19 " "Parameter \"output_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clock NONE " "Parameter \"addnsub0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clock NONE " "Parameter \"addnsub1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clock NONE " "Parameter \"zeroacc_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clock NONE " "Parameter \"first_adder0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clock NONE " "Parameter \"first_adder1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clear NONE " "Parameter \"addnsub0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clear NONE " "Parameter \"addnsub1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clear NONE " "Parameter \"zeroacc_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clear NONE " "Parameter \"first_adder0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clear NONE " "Parameter \"first_adder1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clock NONE " "Parameter \"signa_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clock NONE " "Parameter \"signb_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clock NONE " "Parameter \"addnsub0_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clock NONE " "Parameter \"addnsub1_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clock NONE " "Parameter \"zeroacc_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clear NONE " "Parameter \"signa_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clear NONE " "Parameter \"signb_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clear NONE " "Parameter \"addnsub0_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clear NONE " "Parameter \"addnsub1_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clear NONE " "Parameter \"zeroacc_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778307520096 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778307520096 ""}
    1175. 

  1175. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_out_5s82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_out_5s82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_out_5s82 " "Found entity 1: mac_out_5s82" {  } { { "db/mac_out_5s82.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_out_5s82.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778307520159 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778307520159 ""}
    1176. 

  1176. { "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" {  } {  } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Quartus II" 0 0 1778307520366 ""}
    1177. 

  1177. { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 0 1778307520368 ""}
    1178. 

  1178. { "Info" "IMLS_MLS_IGNORED_SUMMARY" "585 " "Ignored 585 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "30 " "Ignored 30 CARRY_SUM buffer(s)" {  } {  } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Quartus II" 0 0 1778307520374 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "555 " "Ignored 555 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 0 1778307520374 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 0 1778307520374 ""}
    1179. 

  1179. { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "BAUD_RATE " "Bidir \"BAUD_RATE\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778307520381 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "TEST_SINGLE " "Bidir \"TEST_SINGLE\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778307520381 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "UART1_RX " "Bidir \"UART1_RX\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778307520381 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "so_io1 " "Bidir \"so_io1\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778307520381 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 0 1778307520381 ""}
    1180. 

  1180. { "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 62 -1 0 } } { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 81 -1 0 } } { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 51 -1 0 } } { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 49 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 0 1778307520400 ""}
    1181. 

  1181. { "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 0 1778307520400 ""}
    1182. 

  1182. { "Warning" "WMLS_MLS_DISABLED_OE" "" "TRI or OPNDRN buffers permanently disabled" { { "Warning" "WMLS_MLS_NODE_NAME" "BAUD_RATE~synth " "Node \"BAUD_RATE~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307520912 ""} { "Warning" "WMLS_MLS_NODE_NAME" "TEST_SINGLE~synth " "Node \"TEST_SINGLE~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307520912 ""} { "Warning" "WMLS_MLS_NODE_NAME" "UART1_RX~synth " "Node \"UART1_RX~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307520912 ""} { "Warning" "WMLS_MLS_NODE_NAME" "so_io1~synth " "Node \"so_io1~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307520912 ""}  } {  } 0 13008 "TRI or OPNDRN buffers permanently disabled" 0 0 "Quartus II" 0 0 1778307520912 ""}
    1183. 

  1183. { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307521092 ""}
    1184. 

  1184. { "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 0 1778307525019 ""}
    1185. 

  1185. { "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_stop " "Logic cell \"sys_ctrl_stop\"" {  } { { "example_board.v" "sys_ctrl_stop" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 88 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_in\[0\] " "Logic cell \"gpio0_io_in\[0\]\"" {  } { { "example_board.v" "gpio0_io_in\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 319 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_in\[1\] " "Logic cell \"gpio4_io_in\[1\]\"" {  } { { "example_board.v" "gpio4_io_in\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 347 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_in\[2\] " "Logic cell \"gpio4_io_in\[2\]\"" {  } { { "example_board.v" "gpio4_io_in\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 347 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_in\[1\] " "Logic cell \"gpio6_io_in\[1\]\"" {  } { { "example_board.v" "gpio6_io_in\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 355 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_in\[3\] " "Logic cell \"gpio6_io_in\[3\]\"" {  } { { "example_board.v" "gpio6_io_in\[3\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 355 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[6\] " "Logic cell \"gpio4_io_out_data\[6\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[6\] " "Logic cell \"gpio4_io_out_en\[6\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[5\] " "Logic cell \"gpio4_io_out_data\[5\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[5\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[5\] " "Logic cell \"gpio4_io_out_en\[5\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[5\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio7_io_out_data\[6\] " "Logic cell \"gpio7_io_out_data\[6\]\"" {  } { { "example_board.v" "gpio7_io_out_data\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 357 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio7_io_out_en\[6\] " "Logic cell \"gpio7_io_out_en\[6\]\"" {  } { { "example_board.v" "gpio7_io_out_en\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 358 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_resetn " "Logic cell \"sys_resetn\"" {  } { { "example_board.v" "sys_resetn" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 87 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[0\] " "Logic cell \"sys_ctrl_clkSource\[0\]\"" {  } { { "example_board.v" "sys_ctrl_clkSource\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 89 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[1\] " "Logic cell \"sys_ctrl_clkSource\[1\]\"" {  } { { "example_board.v" "sys_ctrl_clkSource\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 89 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[1\] " "Logic cell \"gpio4_io_out_data\[1\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[1\] " "Logic cell \"gpio4_io_out_en\[1\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[2\] " "Logic cell \"gpio4_io_out_data\[2\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[2\] " "Logic cell \"gpio4_io_out_en\[2\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_out_data\[0\] " "Logic cell \"gpio0_io_out_data\[0\]\"" {  } { { "example_board.v" "gpio0_io_out_data\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 313 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_out_en\[0\] " "Logic cell \"gpio0_io_out_en\[0\]\"" {  } { { "example_board.v" "gpio0_io_out_en\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 314 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio8_io_out_data\[0\] " "Logic cell \"gpio8_io_out_data\[0\]\"" {  } { { "example_board.v" "gpio8_io_out_data\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 363 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio8_io_out_en\[0\] " "Logic cell \"gpio8_io_out_en\[0\]\"" {  } { { "example_board.v" "gpio8_io_out_en\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 364 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""} { "Info" "ISCL_SCL_CELL_NAME" "PLL_ENABLE " "Logic cell \"PLL_ENABLE\"" {  } { { "example_board.v" "PLL_ENABLE" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 85 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778307525032 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 0 1778307525032 ""}
    1186. 

  1186. { "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 0 1778307525208 ""}
    1187. 

  1187. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 0 1778307525223 ""}
    1188. 

  1188. { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 0 1778307525777 ""}
    1189. 

  1189. { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000      PIN_HSE " " 125.000      PIN_HSE" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778307525777 ""}
    1190. 

  1190. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 0 1778307525826 ""}
    1191. 

  1191. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 0 1778307525885 ""}
    1192. 

  1192. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 0 1778307525887 ""}
    1193. 

  1193. { "Info" "ICUT_CUT_TM_SUMMARY" "1764 " "Implemented 1764 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1728 " "Implemented 1728 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 0 1778307525957 ""} { "Info" "ICUT_CUT_TM_BLACKBOX" "3 " "Implemented 3 partitions" {  } {  } 0 21071 "Implemented %1!d! partitions" 0 0 "Quartus II" 0 0 1778307525957 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 0 1778307525957 ""}
    1194. 

  1194. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 0 1778307526034 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:18:46 2026 " "Processing ended: Sat May 09 14:18:46 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 0 1778307526034 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 0 1778307526034 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:15 " "Total CPU time (on all processors): 00:00:15" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 0 1778307526034 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 0 1778307526034 ""}
    1195. 

  1195. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 1 1778307517440 ""}
    1196. 

  1196. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 1 1778307517440 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:18:37 2026 " "Processing started: Sat May 09 14:18:37 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 1 1778307517440 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 1 1778307517440 ""}
    1197. 

  1197. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board " "Command: quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 1 1778307517440 ""}
    1198. 

  1198. { "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778307518044 ""}
    1199. 

  1199. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778307518065 ""}
    1200. 

  1200. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778307518065 ""}
    1201. 

  1201. { "Info" "IQSYN_SYNTHESIZE_PARTITION" "macro_inst_apb_adc0_inst_adc_inst " "Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_adc0_inst_adc_inst" {  } { { "analog_ip.v" "adc_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 584 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 1 1778307518174 ""}
    1202. 

  1202. { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 1 1778307518175 ""}
    1203. 

  1203. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 1 1778307518880 ""}
    1204. 

  1204. { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 1 1778307519365 ""}
    1205. 

  1205. { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778307519365 ""}
    1206. 

  1206. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 1 1778307519375 ""}
    1207. 

  1207. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 1 1778307519414 ""}
    1208. 

  1208. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 1 1778307519414 ""}
    1209. 

  1209. { "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 1 1778307519484 ""} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Implemented 13 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 1 1778307519484 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 1 1778307519484 ""}
    1210. 

  1210. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 1 1778307519511 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:18:39 2026 " "Processing ended: Sat May 09 14:18:39 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 1 1778307519511 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 1 1778307519511 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 1 1778307519511 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 1 1778307519511 ""}
    1211. 

  1211. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 2 1778307517442 ""}
    1212. 

  1212. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 2 1778307517442 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:18:37 2026 " "Processing started: Sat May 09 14:18:37 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 2 1778307517442 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 2 1778307517442 ""}
    1213. 

  1213. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board " "Command: quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 2 1778307517442 ""}
    1214. 

  1214. { "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778307518042 ""}
    1215. 

  1215. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778307518063 ""}
    1216. 

  1216. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778307518064 ""}
    1217. 

  1217. { "Info" "IQSYN_SYNTHESIZE_PARTITION" "macro_inst_apb_dac0_inst_dac_inst " "Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_dac0_inst_dac_inst" {  } { { "analog_ip.v" "dac_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 718 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 2 1778307518167 ""}
    1218. 

  1218. { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 2 1778307518168 ""}
    1219. 

  1219. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 2 1778307518833 ""}
    1220. 

  1220. { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 2 1778307519305 ""}
    1221. 

  1221. { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778307519305 ""}
    1222. 

  1222. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 2 1778307519316 ""}
    1223. 

  1223. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 2 1778307519345 ""}
    1224. 

  1224. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 2 1778307519345 ""}
    1225. 

  1225. { "Info" "ICUT_CUT_TM_SUMMARY" "14 " "Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 2 1778307519390 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 2 1778307519390 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 2 1778307519390 ""}
    1226. 

  1226. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 2 1778307519419 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:18:39 2026 " "Processing ended: Sat May 09 14:18:39 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 2 1778307519419 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 2 1778307519419 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 2 1778307519419 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 2 1778307519419 ""}
    1227. 

  1227. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 3 1778307517420 ""}
    1228. 

  1228. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 3 1778307517420 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:18:37 2026 " "Processing started: Sat May 09 14:18:37 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 3 1778307517420 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 3 1778307517420 ""}
    1229. 

  1229. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board " "Command: quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 3 1778307517420 ""}
    1230. 

  1230. { "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition alta_rv32:rv32 " "Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778307517973 ""}
    1231. 

  1231. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 alta_rv32:rv32 " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778307517996 ""}
    1232. 

  1232. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 alta_rv32:rv32 " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778307517996 ""}
    1233. 

  1233. { "Info" "IQSYN_SYNTHESIZE_PARTITION" "rv32 " "Starting Logic Optimization and Technology Mapping for Partition rv32" {  } { { "example_board.v" "rv32" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 451 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 3 1778307518102 ""}
    1234. 

  1234. { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 3 1778307518103 ""}
    1235. 

  1235. { "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio0_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio1_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio2_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio3_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio4_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio5_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio6_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio7_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio8_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|gpio9_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|dmactive GND " "Pin \"alta_rv32:rv32\|dmactive\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3778 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|dmactive"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGNSW GND " "Pin \"alta_rv32:rv32\|swj_JTAGNSW\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3779 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGNSW"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[0\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[1\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[2\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[3\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[0\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGIR[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[1\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGIR[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[2\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGIR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[3\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778307518486 "|example_board|alta_rv32:rv32|swj_JTAGIR[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 3 1778307518486 ""}
    1236. 

  1236. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 3 1778307518777 ""}
    1237. 

  1237. { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 3 1778307519435 ""}
    1238. 

  1238. { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778307519435 ""}
    1239. 

  1239. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 3 1778307519453 ""}
    1240. 

  1240. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 3 1778307519511 ""}
    1241. 

  1241. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 3 1778307519511 ""}
    1242. 

  1242. { "Info" "ICUT_CUT_TM_SUMMARY" "520 " "Implemented 520 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "224 " "Implemented 224 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 3 1778307519587 ""} { "Info" "ICUT_CUT_TM_OPINS" "295 " "Implemented 295 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 3 1778307519587 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 3 1778307519587 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 3 1778307519587 ""}
    1243. 

  1243. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 171 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 3 1778307519627 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:18:39 2026 " "Processing ended: Sat May 09 14:18:39 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 3 1778307519627 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 3 1778307519627 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 3 1778307519627 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 3 1778307519627 ""}
    1244. 

  1244. { "Info" "IQSYN_PARALLEL_SYNTHESIS_SUCCESS" "" "Finished parallel synthesis of all partitions" {  } {  } 0 281038 "Finished parallel synthesis of all partitions" 0 0 "Quartus II" 0 -1 1778307526643 ""}
    1245. 

  1245. { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg " "Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1778307526791 ""}
    1246. 

  1246. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1282 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1282 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4640 " "Peak virtual memory: 4640 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778307526915 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:18:46 2026 " "Processing ended: Sat May 09 14:18:46 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778307526915 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778307526915 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:18 " "Total CPU time (on all processors): 00:00:18" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778307526915 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778307526915 ""}
    1247.