9102_APP/logic/analog_ip.v

`timescale 1ns/1ps

module analog_ip (
  inout              BAUD_RATE,
  inout              TEST_SINGLE,
  inout              UART1_RX,
  inout              UART1_TX,
  inout              so_io1,
  input              csn_out_data,
  input              csn_out_en,
  output tri0        rxd1_ip_in,
  input              sck_out_data,
  input              sck_out_en,
  output tri0        so_io1_in,
  input              so_io1_out_data,
  input              so_io1_out_en,
  input              txd1_ip_out_data,
  input              txd1_ip_out_en,
  input              sys_clock,
  input              bus_clock,
  input              resetn,
  input              stop,
  input       [1:0]  mem_ahb_htrans,
  input              mem_ahb_hready,
  input              mem_ahb_hwrite,
  input       [31:0] mem_ahb_haddr,
  input       [2:0]  mem_ahb_hsize,
  input       [2:0]  mem_ahb_hburst,
  input       [31:0] mem_ahb_hwdata,
  output tri1        mem_ahb_hreadyout,
  output tri0        mem_ahb_hresp,
  output tri0 [31:0] mem_ahb_hrdata,
  output tri0        slave_ahb_hsel,
  output tri1        slave_ahb_hready,
  input              slave_ahb_hreadyout,
  output tri0 [1:0]  slave_ahb_htrans,
  output tri0 [2:0]  slave_ahb_hsize,
  output tri0 [2:0]  slave_ahb_hburst,
  output tri0        slave_ahb_hwrite,
  output tri0 [31:0] slave_ahb_haddr,
  output tri0 [31:0] slave_ahb_hwdata,
  input              slave_ahb_hresp,
  input       [31:0] slave_ahb_hrdata,
  output tri0 [3:0]  ext_dma_DMACBREQ,
  output tri0 [3:0]  ext_dma_DMACLBREQ,
  output tri0 [3:0]  ext_dma_DMACSREQ,
  output tri0 [3:0]  ext_dma_DMACLSREQ,
  input       [3:0]  ext_dma_DMACCLR,
  input       [3:0]  ext_dma_DMACTC,
  output tri0 [3:0]  local_int
);

assign UART1_TX = txd1_ip_out_en ? txd1_ip_out_data : 1'bz;
assign rxd1_ip_in = UART1_RX;

assign slave_ahb_hsel    = 1'b0;
assign slave_ahb_hready  = 1'b1;
assign slave_ahb_htrans  = 2'b00; 
assign slave_ahb_hsize   = 3'b000;
assign slave_ahb_hburst  = 3'b000;
assign slave_ahb_hwrite  = 1'b0;
assign slave_ahb_haddr   = 32'b0;
assign slave_ahb_hwdata  = 32'b0;

assign ext_dma_DMACBREQ  = 4'b0000;   // 禁用DMA
assign ext_dma_DMACLBREQ = 4'b0000;
assign ext_dma_DMACSREQ  = 4'b0000;
assign ext_dma_DMACLSREQ = 4'b0000;
assign local_int         = 4'b0000;   // 禁用中断

// ==============================================
// 核心RAM参数定义
// ==============================================
parameter RAM_SIZE      = 2048;    // 总容量：1024*16bit = 2048字节
parameter RAM_DEPTH     = 1024;    // 数据深度：1024个
parameter RAM_WIDTH     = 16;      // 数据位宽：16bit
parameter ADDR_BITS     = 16;
parameter DATA_BITS     = 32;
parameter PER_BITS      = 12;
parameter PER_CNT       = 4;        // APB外设：ADC0(0)、DAC0(1),这里设置4是为了兼容3000地址的DAC0

// 前四个地址用作说明 未实际使用对应变量
// parameter ADC0_ADDR     = 'h0000;   // ADC0地址
// parameter CFG_REG_ADDR  = 'h1000;   // 配置参数模块偏移地址
// parameter TRIG_CTRL_ADDR= 'h2000;   // 触发模块偏移地址
// parameter DAC0_ADDR     = 'h3000;   // DAC0地址
parameter RAM_BASE_ADDR = 'h6000;   // 双口RAM APB地址 实际应用

// ==============================================
// AHB2APB 桥
// ==============================================
wire                 apb_psel;
wire                 apb_penable;
wire                 apb_pwrite;
wire [ADDR_BITS-1:0] apb_paddr;
wire [DATA_BITS-1:0] apb_pwdata;
wire [3:0]           apb_pstrb;
wire [2:0]           apb_pprot;
wire                 apb_pready  = 1'b1;
wire                 apb_pslverr = 1'b0;
reg  [DATA_BITS-1:0] apb_prdata;

wire apb_clock = bus_clock;
ahb2apb #(ADDR_BITS, DATA_BITS) ahb2apb_inst(
  .reset        (!resetn                     ),
  .ahb_clock    (sys_clock                   ),
  .ahb_hmastlock(1'b0                        ),
  .ahb_htrans   (mem_ahb_htrans              ),
  .ahb_hsel     (1'b1                        ),
  .ahb_hready   (mem_ahb_hready              ),
  .ahb_hwrite   (mem_ahb_hwrite              ),
  .ahb_haddr    (mem_ahb_haddr[ADDR_BITS-1:0]),
  .ahb_hsize    (mem_ahb_hsize               ),
  .ahb_hburst   (mem_ahb_hburst              ),
  .ahb_hprot    (4'b0011                     ),
  .ahb_hwdata   (mem_ahb_hwdata              ),
  .ahb_hrdata   (mem_ahb_hrdata              ),
  .ahb_hreadyout(mem_ahb_hreadyout           ),
  .ahb_hresp    (mem_ahb_hresp               ),
  .apb_clock    (apb_clock                   ),
  .apb_psel     (apb_psel                    ),
  .apb_penable  (apb_penable                 ),
  .apb_pwrite   (apb_pwrite                  ),
  .apb_paddr    (apb_paddr                   ),
  .apb_pwdata   (apb_pwdata                  ),
  .apb_pstrb    (apb_pstrb                   ),
  .apb_pprot    (apb_pprot                   ),
  .apb_pready   (apb_pready                  ),
  .apb_pslverr  (apb_pslverr                 ),
  .apb_prdata   (apb_prdata                  )
);

// ==============================================
// APB 外设选择
// ==============================================
wire [PER_CNT-1:0] select = 1 << (apb_paddr[ADDR_BITS-1:PER_BITS]);

wire                 per_psel[PER_CNT];
wire                 per_penable[PER_CNT];
wire                 per_pwrite[PER_CNT];
wire [PER_BITS-1:0]  per_paddr[PER_CNT];
wire [DATA_BITS-1:0] per_pwdata[PER_CNT];
wire [DATA_BITS-1:0] per_prdata[PER_CNT];

genvar i;
generate
  for (i = 0; i < PER_CNT; i = i + 1) begin : gen_per
    assign per_psel[i]    = apb_psel    & select[i];
    assign per_penable[i] = apb_penable & select[i];
    assign per_pwrite[i]  = apb_pwrite;
    assign per_paddr[i]   = apb_paddr[PER_BITS-1:0];
    assign per_pwdata[i]  = apb_pwdata;
  end
endgenerate

// ==============================================
// 实例化 cfg_reg
// ==============================================
wire                cfg_adc_en;
wire [7:0]          cfg_adc_clk_div;
wire [3:0]          cfg_adc_chnl_sel;
wire [11:0]         cfg_trig_threshold;
wire [15:0]         cfg_trig_pulse_width;
wire [1:0]          cfg_trig_edge;
wire [1:0]          cfg_trig_mode;
wire [4:0]          cfg_trig_time_slot;
wire [15:0]         cfg_trig_auto_timeout;
wire                cfg_adc_run;
wire                cfg_adc_restart;

// 新增：DAC 配置信号 
wire                cfg_dac_en;
wire                cfg_dac_run;
wire [1:0]          cfg_wave_type;
wire [9:0]          cfg_max_vol;
wire [9:0]          cfg_min_vol;
wire [31:0]         cfg_frequency;
wire [7:0]          cfg_duty_cycle;

cfg_reg cfg_reg_inst(
  .pclk               (apb_clock),
  .presetn            (resetn),
  .paddr              (per_paddr[1]),
  .pwrite             (per_pwrite[1]),
  .pwdata             (per_pwdata[1]),
  .prdata             (per_prdata[1]),
  .psel               (per_psel[1]),
  .penable            (per_penable[1]),
  .adc_en             (cfg_adc_en),
  .adc_clk_div        (cfg_adc_clk_div),
  .adc_chnl_sel       (cfg_adc_chnl_sel),
  .trig_threshold     (cfg_trig_threshold),
  .trig_pulse_width   (cfg_trig_pulse_width),
  .trig_edge          (cfg_trig_edge),
  .trig_mode          (cfg_trig_mode),
  .trig_time_slot     (cfg_trig_time_slot),
  .trig_auto_timeout  (cfg_trig_auto_timeout),
  .adc_run            (cfg_adc_run),
  .adc_restart        (cfg_adc_restart),


  // ********************** 新增：DAC 输出 **********************
  .dac_en             (cfg_dac_en),
  .dac_run            (cfg_dac_run),
  .wave_type          (cfg_wave_type),
  .max_vol            (cfg_max_vol),
  .min_vol            (cfg_min_vol),
  .frequency          (cfg_frequency),
  .duty_cycle         (cfg_duty_cycle)
);


// ==============================================
// 实例化 ADC0
// ==============================================
wire        adc0_eoc;
wire [11:0] adc0_data;
apb_adc #(
  .SCLK_BIT(16)
) apb_adc0_inst(
  // APB接口