9102_APP/logic/alta_logs/run.log

> alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
Cmd : C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/bin/af.exe 2025.06.b0(3f05be1c)
> alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
Args : -X "set QUARTUS_SDC true" -X "set FITTING Auto" -X "set FITTER full" -X "set EFFORT high" -X "set HOLDX default" -X "set SKEW   basic" -X "set MODE QUARTUS" -X "set FLOW ALL" -F ./af_run.tcl
> 
> set_seed_rand $SEED
> set ar_timing_derate ${TIMING_DERATE}
> 
> date_time
Sat May 09 14:19:31 2026
> if { [file exists [file join . ${DESIGN}.pre.asf]] } {
  alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
  source [file join . ${DESIGN}.pre.asf]
}
Using pre-ASF file example_board.pre.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> set BOARD_PLL_CLKIN PIN_OSC
> set db_io_name_priority False
> set ip_pll_vco_lowpower true
> set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "ON"
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> 
> set LOAD_DB    false
> set LOAD_PLACE false
> set LOAD_ROUTE false
> set LOAD_PACK false
> if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
  set LOAD_ROUTE true
} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
} elseif { $FLOW == "PR" || $FLOW == "PLACE_AND_ROUTE" } {
  set LOAD_DB    false
  set LOAD_PACK  true
}
> 
> set ORIGINAL_QSF "./example_board.qsf"
> set ORIGINAL_PIN ""
> 
> #################################################################################
> 
> # The default SDC file is ${DESIGN}.sdc 
> set sdc_file $SDC_FILE
> if { $sdc_file == "" } {
  set sdc_file [file join . ${DESIGN}.adc]
  if { ! [file exists $sdc_file] } { set sdc_file [file join . ${DESIGN}.sdc]; }
}
> # No default VE file is not specified
> set ve_file $VEX_FILE
> 
> while (1) {

if { $FLOW == "SKIP" } { break }

if { [info exists CORNER] } { set_mode -corner $CORNER; }

eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
foreach ip_file $IP_FILES { read_ip $ip_file; }


if { $FLOW == "GEN" } {
  if { ! [info exists CONFIG_BITS] } {
    set CONFIG_BITS [file join ${RESULT_DIR} ${DESIGN}.bin]
  }
  if { [llength $CONFIG_BITS] > 1 } {
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY [file join ${RESULT_DIR} ${DESIGN}_boot.bin]
    }
    if { ! [info exists CONFIG_ADDRESSES] } {
      set CONFIG_ADDRESSES ""
    }
    generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
  } else {
    set CONFIG_ROOT   [file rootname [lindex $CONFIG_BITS 0]]
    set SLAVE_RBF     "${CONFIG_ROOT}_slave.rbf"
    set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
    if { [file exists [lindex $CONFIG_BITS 0]] } {
      generate_binary -slave  $SLAVE_RBF     -inputs [lindex $CONFIG_BITS 0] -reverse
      generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
    }
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY $MASTER_BINARY
    }
  }
  set PRG_FILE [file rootname $BOOT_BINARY].prg
  set AS_FILE  [file rootname $BOOT_BINARY]_as.prg
  generate_programming_file $BOOT_BINARY -erase $ERASE \
                            -program $PROGRAM -verify $VERIFY -offset $OFFSET \
                            -prg $PRG_FILE -as $AS_FILE
  break
}

if { $LOAD_DB } {
  load_db -top ${TOP_MODULE}
  if { [file exists $sdc_file] } { read_sdc $sdc_file; }

} elseif { $MODE == "QUARTUS" } {
  set verilog ${DESIGN}.vo
  set is_migrated false
  if { ! [file exists $verilog] } {
    set verilog [file join . simulation modelsim ${DESIGN}.vo]
    set is_migrated true
  }
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }
  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $ve_file != "" && ! [file exists $ve_file] } {
    alta::tcl_warn "Can not find design VE file $ve_file"
    set ve_file ""
  } else {
    alta::tcl_highlight "Using design VE file $ve_file.\n"
  }
  set ret [read_design -top ${TOP_MODULE} -ve $ve_file -qsf $ORIGINAL_QSF $verilog -hierachy 1]
  if { !$ret } { exit -1; }

  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    alta::tcl_highlight "Using design SDC file $sdc_file.\n"
    read_sdc $sdc_file
  }

} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
  set_hierarchy_separator .
  set db_gclk_assignment_level 2
  set verilog ${DESIGN}.vqm
  set is_migrated false
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }

  if { $VEX_FILE != "" } {
    if { $VEX_FILE == "-" } {
      set VEX_FILE ""
    } elseif { ! [file exists $VEX_FILE] } {
      error "Can not find design VE file $VEX_FILE"
    }
  }
  if { $AGF_FILE != "" } {
    if { $AGF_FILE == "-" } {
      set AGF_FILE ""
    } elseif { ! [file exists $AGF_FILE] } {
      error "Can not find design AGF file $AGF_FILE"
    }
  }

  set alta0_asf [file join $::alta_work alta0.asf]
  set alta0_apf [file join $::alta_work alta0.apf]
  file delete -force $alta0_asf
  file delete -force $alta0_apf
  if { $AGF_FILE != "" || $VEX_FILE != "" } {
    alta::convert_pio_settings_cmd $VEX_FILE $AGF_FILE $alta0_asf $alta0_apf
  }

  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    a