TimeQuest Timing Analyzer report for example_board Sat May 09 14:19:24 2026 Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. TimeQuest Timing Analyzer Summary 3. Parallel Compilation 4. SDC File List 5. Clocks 6. Slow 1200mV 85C Model Fmax Summary 7. Timing Closure Recommendations 8. Slow 1200mV 85C Model Setup Summary 9. Slow 1200mV 85C Model Hold Summary 10. Slow 1200mV 85C Model Recovery Summary 11. Slow 1200mV 85C Model Removal Summary 12. Slow 1200mV 85C Model Minimum Pulse Width Summary 13. Slow 1200mV 85C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' 14. Slow 1200mV 85C Model Setup: 'PIN_HSI' 15. Slow 1200mV 85C Model Hold: 'PIN_HSI' 16. Slow 1200mV 85C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' 17. Slow 1200mV 85C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' 18. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI' 19. Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN' 20. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE' 21. Clock to Output Times 22. Minimum Clock to Output Times 23. Slow 1200mV 85C Model Metastability Report 24. Slow 1200mV 0C Model Fmax Summary 25. Slow 1200mV 0C Model Setup Summary 26. Slow 1200mV 0C Model Hold Summary 27. Slow 1200mV 0C Model Recovery Summary 28. Slow 1200mV 0C Model Removal Summary 29. Slow 1200mV 0C Model Minimum Pulse Width Summary 30. Slow 1200mV 0C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' 31. Slow 1200mV 0C Model Setup: 'PIN_HSI' 32. Slow 1200mV 0C Model Hold: 'PIN_HSI' 33. Slow 1200mV 0C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' 34. Slow 1200mV 0C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' 35. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' 36. Slow 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' 37. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' 38. Clock to Output Times 39. Minimum Clock to Output Times 40. Slow 1200mV 0C Model Metastability Report 41. Fast 1200mV 0C Model Setup Summary 42. Fast 1200mV 0C Model Hold Summary 43. Fast 1200mV 0C Model Recovery Summary 44. Fast 1200mV 0C Model Removal Summary 45. Fast 1200mV 0C Model Minimum Pulse Width Summary 46. Fast 1200mV 0C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' 47. Fast 1200mV 0C Model Setup: 'PIN_HSI' 48. Fast 1200mV 0C Model Hold: 'PIN_HSI' 49. Fast 1200mV 0C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' 50. Fast 1200mV 0C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' 51. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' 52. Fast 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' 53. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' 54. Clock to Output Times 55. Minimum Clock to Output Times 56. Fast 1200mV 0C Model Metastability Report 57. Multicorner Timing Analysis Summary 58. Clock to Output Times 59. Minimum Clock to Output Times 60. Board Trace Model Assignments 61. Input Transition Times 62. Signal Integrity Metrics (Slow 1200mv 0c Model) 63. Signal Integrity Metrics (Slow 1200mv 85c Model) 64. Signal Integrity Metrics (Fast 1200mv 0c Model) 65. Setup Transfers 66. Hold Transfers 67. Report TCCS 68. Report RSKM 69. Unconstrained Paths 70. TimeQuest Timing Analyzer Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +--------------------------------------------------------------------------+ ; TimeQuest Timing Analyzer Summary ; +--------------------+-----------------------------------------------------+ ; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Full Version ; ; Revision Name ; example_board ; ; Device Family ; Cyclone IV E ; ; Device Name ; EP4CE75F29C8 ; ; Timing Models ; Final ; ; Delay Model ; Combined ; ; Rise/Fall Delays ; Enabled ; +--------------------+-----------------------------------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 4 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processors 2-4 ; < 0.1% ; ; Processors 5-8 ; 0.0% ; +----------------------------+-------------+ +-------------------------------------------------------+ ; SDC File List ; +-------------------+--------+--------------------------+ ; SDC File Path ; Status ; Read at ; +-------------------+--------+--------------------------+ ; example_board.sdc ; OK ; Sat May 09 14:19:22 2026 ; +-------------------+--------+--------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Clocks ; +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+ ; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+ ; PIN_HSE ; Base ; 125.000 ; 8.0 MHz ; 0.000 ; 62.500 ; ; ; ; ; ; ; ; ; ; ; { PIN_HSE } ; ; PIN_HSI ; Base ; 100.000 ; 10.0 MHz ; 0.000 ; 50.000 ; ; ; ; ; ; ; ; ; ; ; { PIN_HSI } ; ; PLL_CLKIN ; Base ; 125.000 ; 8.0 MHz ; 0.000 ; 62.500 ; ; ; ; ; ; ; ; ; ; ; { PLL_CLKIN } ; ; pll_inst|auto_generated|pll1|clk[0] ; Generated ; 9.615 ; 104.0 MHz ; 0.000 ; 4.807 ; 50.00 ; 1 ; 13 ; ; ; ; ; false ; PLL_CLKIN ; pll_inst|auto_generated|pll1|inclk[0] ; { pll_inst|auto_generated|pll1|clk[0] } ; +-------------------------------------+-----------+---------+-----------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-----------+---------------------------------------+-----------------------------------------+ +---------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Fmax Summary ; +------------+-----------------+-------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+-------------------------------------+------+ ; 132.75 MHz ; 132.75 MHz ; PIN_HSI ; ; ; 132.75 MHz ; 132.75 MHz ; pll_inst|auto_generated|pll1|clk[0] ; ; +------------+-----------------+-------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. ---------------------------------- ; Timing Closure Recommendations ; ---------------------------------- HTML report is unavailable in plain text report export. +--------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup Summary ; +-------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+--------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 2.082 ; 0.000 ; ; PIN_HSI ; 92.467 ; 0.000 ; +-------------------------------------+--------+---------------+ +-------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold Summary ; +-------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+-------+---------------+ ; PIN_HSI ; 0.264 ; 0.000 ; ; pll_inst|auto_generated|pll1|clk[0] ; 0.264 ; 0.000 ; +-------------------------------------+-------+---------------+ ------------------------------------------ ; Slow 1200mV 85C Model Recovery Summary ; ------------------------------------------ No paths to report. ----------------------------------------- ; Slow 1200mV 85C Model Removal Summary ; ----------------------------------------- No paths to report. +---------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width Summary ; +-------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+---------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 4.458 ; 0.000 ; ; PIN_HSI ; 49.635 ; 0.000 ; ; PLL_CLKIN ; 62.371 ; 0.000 ; ; PIN_HSE ; 121.000 ; 0.000 ; +-------------------------------------+---------+---------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 2.082 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.089 ; 7.465 ; ; 2.099 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.450 ; ; 2.200 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.349 ; ; 2.223 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.326 ; ; 2.277 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 7.267 ; ; 2.289 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.089 ; 7.258 ; ; 2.332 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.089 ; 7.215 ; ; 2.339 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.210 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.345 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.203 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.362 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.188 ; ; 2.364 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.093 ; 7.179 ; ; 2.368 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 7.176 ; ; 2.369 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 7.179 ; ; 2.381 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.093 ; 7.162 ; ; 2.408 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 7.136 ; ; 2.419 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.130 ; ; 2.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.089 ; 7.124 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.457 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.093 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.463 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.086 ; 7.087 ; ; 2.482 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 7.062 ; ; 2.486 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.093 ; 7.057 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.494 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 7.051 ; ; 2.501 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 7.048 ; ; 2.514 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.089 ; 7.033 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.552 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.996 ; ; 2.556 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.087 ; 6.993 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.963 ; ; 2.581 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.094 ; 6.961 ; ; 2.584 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.092 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.585 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.091 ; 6.960 ; ; 2.590 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.093 ; 6.953 ; ; 2.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.953 ; ; 2.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.953 ; ; 2.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.953 ; ; 2.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.953 ; ; 2.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.088 ; 6.953 ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Setup: 'PIN_HSI' ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 92.467 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.089 ; 7.465 ; ; 92.484 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.450 ; ; 92.585 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.349 ; ; 92.608 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.326 ; ; 92.662 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 7.267 ; ; 92.674 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.089 ; 7.258 ; ; 92.717 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.089 ; 7.215 ; ; 92.724 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.210 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.730 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.203 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.747 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.188 ; ; 92.749 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.093 ; 7.179 ; ; 92.753 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 7.176 ; ; 92.754 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 7.179 ; ; 92.766 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.093 ; 7.162 ; ; 92.793 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 7.136 ; ; 92.804 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.130 ; ; 92.808 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.089 ; 7.124 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.842 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.093 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.848 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.086 ; 7.087 ; ; 92.867 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 7.062 ; ; 92.871 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.093 ; 7.057 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.879 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 7.051 ; ; 92.886 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 7.048 ; ; 92.899 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.089 ; 7.033 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.937 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.996 ; ; 92.941 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.087 ; 6.993 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.963 ; ; 92.966 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.094 ; 6.961 ; ; 92.969 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.092 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.970 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.091 ; 6.960 ; ; 92.975 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.093 ; 6.953 ; ; 92.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.953 ; ; 92.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.953 ; ; 92.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.953 ; ; 92.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.953 ; ; 92.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.088 ; 6.953 ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'PIN_HSI' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.264 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.586 ; 1.062 ; ; 0.265 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.550 ; 1.027 ; ; 0.335 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.591 ; 1.138 ; ; 0.378 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.591 ; 1.181 ; ; 0.405 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.149 ; ; 0.407 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.151 ; ; 0.408 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.152 ; ; 0.408 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.152 ; ; 0.427 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.106 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.106 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.172 ; ; 0.429 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.173 ; ; 0.437 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.492 ; 1.183 ; ; 0.437 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.147 ; 0.796 ; ; 0.443 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.187 ; ; 0.445 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.492 ; 1.191 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.192 ; ; 0.454 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.492 ; 1.200 ; ; 0.455 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.490 ; 1.199 ; ; 0.458 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.579 ; 1.249 ; ; 0.460 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.758 ; ; 0.460 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.758 ; ; 0.483 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 0.802 ; ; 0.483 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 0.802 ; ; 0.488 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.786 ; ; 0.490 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.788 ; ; 0.494 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.793 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.794 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.794 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.793 ; ; 0.496 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.795 ; ; 0.496 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.795 ; ; 0.497 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.796 ; ; 0.497 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.796 ; ; 0.505 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.803 ; ; 0.505 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.550 ; 1.267 ; ; 0.506 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.805 ; ; 0.507 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.088 ; 0.807 ; ; 0.513 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.811 ; ; 0.513 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.811 ; ; 0.517 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.815 ; ; 0.520 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.819 ; ; 0.520 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.819 ; ; 0.520 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.818 ; ; 0.521 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.820 ; ; 0.522 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.820 ; ; 0.539 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.837 ; ; 0.546 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.845 ; ; 0.576 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.147 ; 0.935 ; ; 0.577 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.147 ; 0.936 ; ; 0.643 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.942 ; ; 0.643 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.591 ; 1.446 ; ; 0.650 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.591 ; 1.453 ; ; 0.661 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.961 ; ; 0.663 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.961 ; ; 0.682 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.980 ; ; 0.683 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wren_b ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.484 ; 1.421 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.991 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.990 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.990 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.991 ; ; 0.695 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.994 ; ; 0.695 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.994 ; ; 0.699 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.087 ; 0.998 ; ; 0.699 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 0.997 ; ; 0.703 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.579 ; 1.494 ; ; 0.704 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.579 ; 1.495 ; ; 0.705 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.086 ; 1.003 ; ; 0.706 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.088 ; 1.006 ; ; 0.713 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.088 ; 1.013 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.037 ; ; 0.719 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.038 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.107 ; 1.040 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 0.264 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.586 ; 1.062 ; ; 0.265 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.550 ; 1.027 ; ; 0.335 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.591 ; 1.138 ; ; 0.378 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.591 ; 1.181 ; ; 0.405 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.149 ; ; 0.407 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.151 ; ; 0.408 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.152 ; ; 0.408 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.152 ; ; 0.427 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.106 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.106 ; 0.746 ; ; 0.428 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.172 ; ; 0.429 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.173 ; ; 0.437 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.492 ; 1.183 ; ; 0.437 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.147 ; 0.796 ; ; 0.443 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.187 ; ; 0.445 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.492 ; 1.191 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.746 ; ; 0.447 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.746 ; ; 0.448 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.192 ; ; 0.454 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.492 ; 1.200 ; ; 0.455 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.490 ; 1.199 ; ; 0.458 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.579 ; 1.249 ; ; 0.460 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.758 ; ; 0.460 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.758 ; ; 0.483 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 0.802 ; ; 0.483 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 0.802 ; ; 0.488 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.786 ; ; 0.490 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.788 ; ; 0.494 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.793 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.794 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.794 ; ; 0.495 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.793 ; ; 0.496 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.795 ; ; 0.496 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.795 ; ; 0.497 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.796 ; ; 0.497 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.796 ; ; 0.505 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.803 ; ; 0.505 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.550 ; 1.267 ; ; 0.506 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.805 ; ; 0.507 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 0.807 ; ; 0.513 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.811 ; ; 0.513 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.811 ; ; 0.517 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.815 ; ; 0.520 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.819 ; ; 0.520 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.819 ; ; 0.520 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.818 ; ; 0.521 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.820 ; ; 0.522 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.820 ; ; 0.539 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.837 ; ; 0.546 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.845 ; ; 0.576 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.147 ; 0.935 ; ; 0.577 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.147 ; 0.936 ; ; 0.643 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.942 ; ; 0.643 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.591 ; 1.446 ; ; 0.650 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.591 ; 1.453 ; ; 0.661 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.960 ; ; 0.662 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.961 ; ; 0.663 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.961 ; ; 0.682 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.980 ; ; 0.683 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wren_b ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.484 ; 1.421 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.991 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.990 ; ; 0.692 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.990 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.992 ; ; 0.693 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.991 ; ; 0.695 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.994 ; ; 0.695 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.994 ; ; 0.699 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.087 ; 0.998 ; ; 0.699 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 0.997 ; ; 0.703 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.579 ; 1.494 ; ; 0.704 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.579 ; 1.495 ; ; 0.705 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.086 ; 1.003 ; ; 0.706 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 1.006 ; ; 0.713 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.088 ; 1.013 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.037 ; ; 0.718 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.037 ; ; 0.719 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.038 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.040 ; ; 0.721 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.107 ; 1.040 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ ; 4.458 ; 4.678 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_eoc_sync2 ; ; 4.458 ; 4.678 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; ; 4.458 ; 4.678 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; ; 4.458 ; 4.678 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|single_shot_lock ; ; 4.458 ; 4.678 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|write_strobe ; ; 4.459 ; 4.679 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[0] ; ; 4.459 ; 4.679 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[1] ; ; 4.459 ; 4.679 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[2] ; ; 4.460 ; 4.680 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[3] ; ; 4.460 ; 4.680 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[4] ; ; 4.460 ; 4.680 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[8] ; ; 4.462 ; 4.682 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; ; 4.462 ; 4.682 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; ; 4.462 ; 4.682 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; ; 4.463 ; 4.683 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_hit_reg ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[12] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[13] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[14] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[15] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[2] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[9] ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_active ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; ; 4.467 ; 4.687 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_trigger ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[2] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[3] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[0] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[1] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[6] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[0] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[1] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[0] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[4] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[0] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[10] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[11] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[12] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[13] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[14] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[15] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[1] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[2] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[3] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[4] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[5] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[6] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[7] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8] ; ; 4.468 ; 4.688 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[9] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[10] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[11] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[13] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; ; 4.471 ; 4.691 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; ; 4.475 ; 4.695 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[0] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[8] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[9] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[0] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[10] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[11] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[12] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[13] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[14] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[15] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[1] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[2] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[3] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[4] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[5] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[6] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[7] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[8] ; ; 4.476 ; 4.696 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[9] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[0] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[4] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; ; 4.477 ; 4.697 ; 0.220 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI' ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; 49.635 ; 49.870 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_address_reg0 ; ; 49.635 ; 49.870 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_we_reg ; ; 49.635 ; 49.870 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_address_reg0 ; ; 49.635 ; 49.870 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_re_reg ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_we_reg ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_address_reg0 ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_re_reg ; ; 49.636 ; 49.871 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_we_reg ; ; 49.638 ; 49.873 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_datain_reg0 ; ; 49.638 ; 49.873 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; ; 49.638 ; 49.873 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_datain_reg0 ; ; 49.638 ; 49.873 ; 0.235 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[0] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[10] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[11] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[12] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[13] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[14] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[15] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[1] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[6] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[8] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[9] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[0] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[1] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_chnl_sel[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_clk_div[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_clk_div[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_clk_div[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_clk_div[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_clk_div[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|adc_restart ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|dac_en ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|dac_run ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[0] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[1] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[6] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|duty_cycle[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[14] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[1] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[6] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[9] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[3] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[14] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[19] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[20] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[23] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[4] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[5] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[7] ; ; 49.775 ; 49.963 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[8] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[14] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[3] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[4] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; ; 49.776 ; 49.964 ; 0.188 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'PLL_CLKIN' ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; 62.371 ; 62.371 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 62.371 ; 62.371 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 62.391 ; 62.391 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 62.419 ; 62.419 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 62.580 ; 62.580 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 62.609 ; 62.609 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 62.627 ; 62.627 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 62.627 ; 62.627 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE' ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ; +---------+--------------+----------------+-----------+---------+------------+---------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Clock to Output Times ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.999 ; 3.062 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.999 ; 3.062 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.188 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.119 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.911 ; 2.975 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.911 ; 2.975 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.317 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.383 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ---------------------------------------------- ; Slow 1200mV 85C Model Metastability Report ; ---------------------------------------------- No synchronizer chains to report. +---------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Fmax Summary ; +------------+-----------------+-------------------------------------+------+ ; Fmax ; Restricted Fmax ; Clock Name ; Note ; +------------+-----------------+-------------------------------------+------+ ; 144.13 MHz ; 144.13 MHz ; PIN_HSI ; ; ; 144.13 MHz ; 144.13 MHz ; pll_inst|auto_generated|pll1|clk[0] ; ; +------------+-----------------+-------------------------------------+------+ This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. +--------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup Summary ; +-------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+--------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 2.677 ; 0.000 ; ; PIN_HSI ; 93.062 ; 0.000 ; +-------------------------------------+--------+---------------+ +-------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold Summary ; +-------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+-------+---------------+ ; PIN_HSI ; 0.208 ; 0.000 ; ; pll_inst|auto_generated|pll1|clk[0] ; 0.208 ; 0.000 ; +-------------------------------------+-------+---------------+ ----------------------------------------- ; Slow 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Slow 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +---------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width Summary ; +-------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+---------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 4.447 ; 0.000 ; ; PIN_HSI ; 49.631 ; 0.000 ; ; PLL_CLKIN ; 62.365 ; 0.000 ; ; PIN_HSE ; 121.000 ; 0.000 ; +-------------------------------------+---------+---------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+-----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+-----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 2.677 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.883 ; ; 2.717 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.079 ; 6.841 ; ; 2.757 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.803 ; ; 2.776 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.784 ; ; 2.832 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.722 ; ; 2.843 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.084 ; 6.710 ; ; 2.871 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.079 ; 6.687 ; ; 2.875 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.685 ; ; 2.925 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.084 ; 6.628 ; ; 2.930 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.624 ; ; 2.932 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.079 ; 6.626 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.939 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.622 ; ; 2.958 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.596 ; ; 2.963 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.596 ; ; 2.978 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.582 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.979 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.580 ; ; 2.987 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.079 ; 6.571 ; ; 3.003 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.551 ; ; 3.018 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.019 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.542 ; ; 3.026 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.084 ; 6.527 ; ; 3.037 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.518 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.038 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.523 ; ; 3.058 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.496 ; ; 3.065 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.084 ; 6.488 ; ; 3.068 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.084 ; 6.485 ; ; 3.083 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.471 ; ; 3.089 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.079 ; 6.469 ; ; 3.091 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.463 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.094 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.082 ; 6.461 ; ; 3.101 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.077 ; 6.459 ; ; 3.102 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.452 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.105 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.449 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.107 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.078 ; 6.452 ; ; 3.118 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.436 ; ; 3.121 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.085 ; 6.431 ; ; 3.122 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.083 ; 6.432 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; ; 3.137 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.076 ; 6.424 ; +-------+-----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Setup: 'PIN_HSI' ; +--------+-----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+-----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 93.062 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.883 ; ; 93.102 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.079 ; 6.841 ; ; 93.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.803 ; ; 93.161 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.784 ; ; 93.217 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.722 ; ; 93.228 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.084 ; 6.710 ; ; 93.256 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.079 ; 6.687 ; ; 93.260 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.685 ; ; 93.310 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.084 ; 6.628 ; ; 93.315 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.624 ; ; 93.317 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.079 ; 6.626 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.324 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.622 ; ; 93.343 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.596 ; ; 93.348 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.596 ; ; 93.363 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.582 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.364 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.580 ; ; 93.372 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.079 ; 6.571 ; ; 93.388 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.551 ; ; 93.403 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.404 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.542 ; ; 93.411 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.084 ; 6.527 ; ; 93.422 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.518 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.423 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.523 ; ; 93.443 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.496 ; ; 93.450 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.084 ; 6.488 ; ; 93.453 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.084 ; 6.485 ; ; 93.468 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.471 ; ; 93.474 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.079 ; 6.469 ; ; 93.476 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.463 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.479 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.082 ; 6.461 ; ; 93.486 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.077 ; 6.459 ; ; 93.487 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.452 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.490 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.449 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.492 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.078 ; 6.452 ; ; 93.503 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.436 ; ; 93.506 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.085 ; 6.431 ; ; 93.507 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.083 ; 6.432 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; ; 93.522 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.076 ; 6.424 ; +--------+-----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'PIN_HSI' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.208 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.549 ; 0.952 ; ; 0.217 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.508 ; 0.920 ; ; 0.307 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.053 ; ; 0.332 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.078 ; ; 0.378 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.096 ; 0.669 ; ; 0.379 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.095 ; 0.669 ; ; 0.379 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.095 ; 0.669 ; ; 0.389 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.051 ; ; 0.390 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.052 ; ; 0.391 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.053 ; ; 0.391 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.053 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.669 ; ; 0.407 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.069 ; ; 0.408 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.137 ; 0.740 ; ; 0.411 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.073 ; ; 0.412 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.684 ; ; 0.412 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.684 ; ; 0.414 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.434 ; 1.078 ; ; 0.419 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.434 ; 1.083 ; ; 0.421 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.540 ; 1.156 ; ; 0.424 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.086 ; ; 0.426 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.088 ; ; 0.427 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.434 ; 1.091 ; ; 0.431 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.432 ; 1.093 ; ; 0.445 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.097 ; 0.737 ; ; 0.446 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.096 ; 0.737 ; ; 0.451 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.723 ; ; 0.453 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.725 ; ; 0.457 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.729 ; ; 0.465 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.738 ; ; 0.465 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.737 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.738 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.738 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.738 ; ; 0.467 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.739 ; ; 0.467 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.739 ; ; 0.467 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.740 ; ; 0.468 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.740 ; ; 0.469 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.742 ; ; 0.478 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.508 ; 1.181 ; ; 0.480 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.752 ; ; 0.480 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.752 ; ; 0.486 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.759 ; ; 0.486 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.758 ; ; 0.487 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.760 ; ; 0.487 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.759 ; ; 0.488 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.760 ; ; 0.489 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.761 ; ; 0.502 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.774 ; ; 0.508 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.781 ; ; 0.535 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.137 ; 0.867 ; ; 0.535 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.137 ; 0.867 ; ; 0.552 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.298 ; ; 0.553 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.299 ; ; 0.594 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.866 ; ; 0.613 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.359 ; ; 0.613 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.885 ; ; 0.613 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.885 ; ; 0.614 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.886 ; ; 0.615 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.888 ; ; 0.616 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.889 ; ; 0.621 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.893 ; ; 0.621 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.894 ; ; 0.622 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.540 ; 1.357 ; ; 0.623 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.896 ; ; 0.625 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.540 ; 1.360 ; ; 0.626 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.898 ; ; 0.631 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.904 ; ; 0.635 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wren_b ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.426 ; 1.291 ; ; 0.635 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.907 ; ; 0.638 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.911 ; ; 0.639 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.551 ; 1.385 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.913 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.914 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.914 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.914 ; ; 0.643 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.915 ; ; 0.645 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[19] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[19] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.078 ; 0.918 ; ; 0.645 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.077 ; 0.917 ; ; 0.668 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.097 ; 0.960 ; ; 0.668 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.097 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.096 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.096 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.097 ; 0.961 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.097 ; 0.961 ; ; 0.670 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.096 ; 0.961 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 0.208 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.549 ; 0.952 ; ; 0.217 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.508 ; 0.920 ; ; 0.307 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.053 ; ; 0.332 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.078 ; ; 0.378 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.096 ; 0.669 ; ; 0.379 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.095 ; 0.669 ; ; 0.379 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.095 ; 0.669 ; ; 0.389 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.051 ; ; 0.390 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.052 ; ; 0.391 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.053 ; ; 0.391 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.053 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.669 ; ; 0.396 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.669 ; ; 0.397 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.669 ; ; 0.407 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.069 ; ; 0.408 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.137 ; 0.740 ; ; 0.411 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.073 ; ; 0.412 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.684 ; ; 0.412 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.684 ; ; 0.414 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.434 ; 1.078 ; ; 0.419 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.434 ; 1.083 ; ; 0.421 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.540 ; 1.156 ; ; 0.424 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.086 ; ; 0.426 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.088 ; ; 0.427 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.434 ; 1.091 ; ; 0.431 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.432 ; 1.093 ; ; 0.445 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.097 ; 0.737 ; ; 0.446 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.096 ; 0.737 ; ; 0.451 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.723 ; ; 0.453 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.725 ; ; 0.457 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.729 ; ; 0.465 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.738 ; ; 0.465 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.737 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.738 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.738 ; ; 0.466 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.738 ; ; 0.467 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.739 ; ; 0.467 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.739 ; ; 0.467 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.740 ; ; 0.468 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.740 ; ; 0.469 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.742 ; ; 0.478 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.508 ; 1.181 ; ; 0.480 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.752 ; ; 0.480 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.752 ; ; 0.486 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.759 ; ; 0.486 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.758 ; ; 0.487 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.760 ; ; 0.487 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.759 ; ; 0.488 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.760 ; ; 0.489 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.761 ; ; 0.502 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.774 ; ; 0.508 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.781 ; ; 0.535 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.137 ; 0.867 ; ; 0.535 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.137 ; 0.867 ; ; 0.552 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.298 ; ; 0.553 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.299 ; ; 0.594 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.866 ; ; 0.613 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.359 ; ; 0.613 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.885 ; ; 0.613 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.885 ; ; 0.614 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.887 ; ; 0.614 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.886 ; ; 0.615 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.888 ; ; 0.616 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.889 ; ; 0.621 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.893 ; ; 0.621 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.894 ; ; 0.622 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.540 ; 1.357 ; ; 0.623 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.896 ; ; 0.625 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.540 ; 1.360 ; ; 0.626 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.898 ; ; 0.631 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.904 ; ; 0.635 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wren_b ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.426 ; 1.291 ; ; 0.635 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.907 ; ; 0.638 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.911 ; ; 0.639 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.551 ; 1.385 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.913 ; ; 0.641 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.913 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.914 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.914 ; ; 0.642 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.914 ; ; 0.643 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.915 ; ; 0.645 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[19] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[19] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.078 ; 0.918 ; ; 0.645 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.077 ; 0.917 ; ; 0.668 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.097 ; 0.960 ; ; 0.668 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.097 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.096 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.096 ; 0.960 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.097 ; 0.961 ; ; 0.669 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.097 ; 0.961 ; ; 0.670 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.096 ; 0.961 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ ; 4.447 ; 4.663 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_eoc_sync2 ; ; 4.447 ; 4.663 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; ; 4.447 ; 4.663 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; ; 4.447 ; 4.663 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|single_shot_lock ; ; 4.447 ; 4.663 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|write_strobe ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[12] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[13] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[14] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[15] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[2] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[3] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[4] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[8] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[9] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[0] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[1] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[2] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[0] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[10] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[11] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[12] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[13] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[14] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[15] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[1] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[2] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[3] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[4] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[5] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[6] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[7] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[9] ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_active ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; ; 4.449 ; 4.665 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_trigger ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[10] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[11] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[13] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; ; 4.450 ; 4.666 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[2] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[3] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[0] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[1] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[6] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[0] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[1] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[0] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[4] ; ; 4.451 ; 4.667 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[0] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[4] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[7] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[8] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[0] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[8] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[9] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[0] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[10] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[11] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[12] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[13] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[14] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[15] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[1] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[2] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[3] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[4] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[5] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[6] ; ; 4.452 ; 4.668 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[7] ; +-------+--------------+----------------+------------------+-------------------------------------+------------+-------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' ; +--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; 49.631 ; 49.861 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_address_reg0 ; ; 49.631 ; 49.861 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_we_reg ; ; 49.632 ; 49.862 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_address_reg0 ; ; 49.632 ; 49.862 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; ; 49.633 ; 49.863 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 49.633 ; 49.863 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_re_reg ; ; 49.633 ; 49.863 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_we_reg ; ; 49.634 ; 49.864 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_address_reg0 ; ; 49.634 ; 49.864 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_re_reg ; ; 49.634 ; 49.864 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_we_reg ; ; 49.635 ; 49.865 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_datain_reg0 ; ; 49.635 ; 49.865 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; ; 49.636 ; 49.866 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_datain_reg0 ; ; 49.636 ; 49.866 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; ; 49.764 ; 49.980 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_eoc_sync2 ; ; 49.764 ; 49.980 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; ; 49.764 ; 49.980 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; ; 49.764 ; 49.980 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|single_shot_lock ; ; 49.764 ; 49.980 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|write_strobe ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[12] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[13] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[14] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[15] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[2] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[3] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[4] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[8] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[9] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[0] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_edge[1] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[2] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[0] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[10] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[11] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[12] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[13] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[14] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[15] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[1] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[2] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[3] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[4] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[5] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[6] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[7] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[9] ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_active ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; ; 49.766 ; 49.982 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_trigger ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[10] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[11] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[13] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; ; 49.767 ; 49.983 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[2] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[3] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[0] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[1] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[6] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[0] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[1] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[0] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[4] ; ; 49.768 ; 49.984 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[0] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[4] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[7] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[8] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[0] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[8] ; ; 49.769 ; 49.985 ; 0.216 ; High Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[9] ; +--------+--------------+----------------+------------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; 62.365 ; 62.365 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 62.365 ; 62.365 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 62.404 ; 62.404 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 62.423 ; 62.423 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 62.576 ; 62.576 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 62.596 ; 62.596 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 62.635 ; 62.635 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 62.635 ; 62.635 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ; +---------+--------------+----------------+-----------+---------+------------+---------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Clock to Output Times ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.743 ; 2.779 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.743 ; 2.779 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.308 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.220 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.664 ; 2.703 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.664 ; 2.703 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.135 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.219 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ --------------------------------------------- ; Slow 1200mV 0C Model Metastability Report ; --------------------------------------------- No synchronizer chains to report. +--------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup Summary ; +-------------------------------------+--------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+--------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 6.421 ; 0.000 ; ; PIN_HSI ; 96.806 ; 0.000 ; +-------------------------------------+--------+---------------+ +-------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold Summary ; +-------------------------------------+-------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+-------+---------------+ ; PIN_HSI ; 0.084 ; 0.000 ; ; pll_inst|auto_generated|pll1|clk[0] ; 0.084 ; 0.000 ; +-------------------------------------+-------+---------------+ ----------------------------------------- ; Fast 1200mV 0C Model Recovery Summary ; ----------------------------------------- No paths to report. ---------------------------------------- ; Fast 1200mV 0C Model Removal Summary ; ---------------------------------------- No paths to report. +---------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width Summary ; +-------------------------------------+---------+---------------+ ; Clock ; Slack ; End Point TNS ; +-------------------------------------+---------+---------------+ ; pll_inst|auto_generated|pll1|clk[0] ; 4.559 ; 0.000 ; ; PIN_HSI ; 49.208 ; 0.000 ; ; PLL_CLKIN ; 61.901 ; 0.000 ; ; PIN_HSE ; 121.000 ; 0.000 ; +-------------------------------------+---------+---------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 6.421 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.156 ; ; 6.427 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.041 ; 3.154 ; ; 6.447 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.046 ; 3.129 ; ; 6.455 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 3.128 ; ; 6.461 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.116 ; ; 6.491 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 3.092 ; ; 6.491 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.046 ; 3.085 ; ; 6.504 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.046 ; 3.072 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.049 ; ; 6.529 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.041 ; 3.052 ; ; 6.532 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.045 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.535 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.047 ; ; 6.542 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 3.041 ; ; 6.545 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.041 ; 3.036 ; ; 6.546 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 3.037 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.555 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.022 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 3.019 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.563 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 3.021 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.008 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.569 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.044 ; 3.009 ; ; 6.573 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 3.004 ; ; 6.580 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.046 ; 2.996 ; ; 6.589 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.988 ; ; 6.590 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.041 ; 2.991 ; ; 6.595 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.982 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.038 ; 2.985 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.599 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.978 ; ; 6.607 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 2.976 ; ; 6.607 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.047 ; 2.968 ; ; 6.612 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.039 ; 2.971 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.612 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.965 ; ; 6.619 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.045 ; 2.958 ; ; 6.619 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.046 ; 2.957 ; ; 6.629 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.041 ; 2.952 ; ; 6.635 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; 0.148 ; 3.135 ; ; 6.637 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 9.615 ; -0.040 ; 2.945 ; +-------+----------------------------------------------------------------+--------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Setup: 'PIN_HSI' ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 96.806 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.156 ; ; 96.812 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.041 ; 3.154 ; ; 96.832 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.046 ; 3.129 ; ; 96.840 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 3.128 ; ; 96.846 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.116 ; ; 96.876 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 3.092 ; ; 96.876 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.046 ; 3.085 ; ; 96.889 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.046 ; 3.072 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.049 ; ; 96.914 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.041 ; 3.052 ; ; 96.917 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.045 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.920 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.047 ; ; 96.927 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 3.041 ; ; 96.930 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.041 ; 3.036 ; ; 96.931 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 3.037 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.940 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.022 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 3.019 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.948 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 3.021 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.008 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.954 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.044 ; 3.009 ; ; 96.958 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 3.004 ; ; 96.965 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.046 ; 2.996 ; ; 96.974 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.988 ; ; 96.975 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.041 ; 2.991 ; ; 96.980 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_data_prev[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.982 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.038 ; 2.985 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.984 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.978 ; ; 96.992 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 2.976 ; ; 96.992 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|apb_db[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.047 ; 2.968 ; ; 96.997 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[4] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.039 ; 2.971 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[0] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[3] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[4] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|last_trig_end_addr_edge[9] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 96.997 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[5] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.965 ; ; 97.004 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.045 ; 2.958 ; ; 97.004 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.046 ; 2.957 ; ; 97.014 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[2] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.041 ; 2.952 ; ; 97.020 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_threshold[0] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; PIN_HSI ; PIN_HSI ; 100.000 ; 0.148 ; 3.135 ; ; 97.022 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[7] ; PIN_HSI ; PIN_HSI ; 100.000 ; -0.040 ; 2.945 ; +--------+----------------------------------------------------------------+--------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'PIN_HSI' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ ; 0.084 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.229 ; 0.397 ; ; 0.085 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.242 ; 0.411 ; ; 0.115 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.244 ; 0.443 ; ; 0.127 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.244 ; 0.455 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.472 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.472 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.228 ; 0.474 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.478 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.478 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.228 ; 0.480 ; ; 0.149 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.479 ; ; 0.149 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.228 ; 0.481 ; ; 0.150 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.480 ; ; 0.158 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.488 ; ; 0.159 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.238 ; 0.481 ; ; 0.159 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.489 ; ; 0.161 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.226 ; 0.491 ; ; 0.170 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.062 ; 0.316 ; ; 0.175 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.307 ; ; 0.175 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.307 ; ; 0.176 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.047 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.307 ; ; 0.184 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.307 ; ; 0.184 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.229 ; 0.497 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.307 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.314 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.314 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.313 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.314 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.314 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.314 ; ; 0.193 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.316 ; ; 0.193 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.325 ; ; 0.193 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.316 ; ; 0.193 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.316 ; ; 0.194 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.047 ; 0.325 ; ; 0.199 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.321 ; ; 0.199 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.321 ; ; 0.200 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.322 ; ; 0.201 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.323 ; ; 0.202 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.324 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.324 ; ; 0.203 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.326 ; ; 0.204 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.328 ; ; 0.206 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.329 ; ; 0.207 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.329 ; ; 0.209 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.332 ; ; 0.212 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.334 ; ; 0.213 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.337 ; ; 0.228 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.062 ; 0.374 ; ; 0.229 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.062 ; 0.375 ; ; 0.235 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.244 ; 0.563 ; ; 0.238 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.244 ; 0.566 ; ; 0.258 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.238 ; 0.580 ; ; 0.258 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.238 ; 0.580 ; ; 0.259 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.382 ; ; 0.261 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.384 ; ; 0.261 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.384 ; ; 0.262 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.384 ; ; 0.262 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.385 ; ; 0.262 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.386 ; ; 0.263 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.387 ; ; 0.263 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.386 ; ; 0.263 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.386 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.387 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.386 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.386 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.387 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.388 ; ; 0.266 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.388 ; ; 0.266 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.390 ; ; 0.267 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.390 ; ; 0.268 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.390 ; ; 0.271 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.395 ; ; 0.271 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.393 ; ; 0.272 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[19] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[19] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.040 ; 0.396 ; ; 0.273 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.395 ; ; 0.278 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.244 ; 0.606 ; ; 0.279 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[31] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.038 ; 0.401 ; ; 0.284 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[1] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_pulse_width[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.039 ; 0.407 ; ; 0.285 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.417 ; ; 0.286 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.418 ; ; 0.286 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.047 ; 0.417 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.047 ; 0.418 ; ; 0.288 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; PIN_HSI ; PIN_HSI ; 0.000 ; 0.048 ; 0.420 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Hold: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ ; 0.084 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[29] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.229 ; 0.397 ; ; 0.085 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[8] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.242 ; 0.411 ; ; 0.115 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[21] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.244 ; 0.443 ; ; 0.127 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.244 ; 0.455 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[2] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.472 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[5] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.472 ; ; 0.142 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[11] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.228 ; 0.474 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[0] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.478 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[6] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.478 ; ; 0.148 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[10] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.228 ; 0.480 ; ; 0.149 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[7] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.479 ; ; 0.149 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[9] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.228 ; 0.481 ; ; 0.150 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[1] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.480 ; ; 0.158 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[4] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.488 ; ; 0.159 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.238 ; 0.481 ; ; 0.159 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[3] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.489 ; ; 0.161 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_data_b[8] ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.226 ; 0.491 ; ; 0.170 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[29] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.316 ; ; 0.175 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.PRE_FILL ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.307 ; ; 0.175 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.SAMPLING ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.307 ; ; 0.176 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_level ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.IDLE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.POST_TRIG ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.307 ; ; 0.183 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|curr_state.DONE ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.307 ; ; 0.184 ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.307 ; ; 0.184 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[30] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.229 ; 0.497 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.307 ; ; 0.185 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.307 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[2] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.314 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[6] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.314 ; ; 0.191 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.313 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.314 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.314 ; ; 0.192 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.314 ; ; 0.193 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|prdata[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.316 ; ; 0.193 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.325 ; ; 0.193 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[1] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.316 ; ; 0.193 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[8] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.316 ; ; 0.194 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 0.325 ; ; 0.199 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.321 ; ; 0.199 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.321 ; ; 0.200 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.322 ; ; 0.201 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.323 ; ; 0.202 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.324 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.325 ; ; 0.202 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.324 ; ; 0.203 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.326 ; ; 0.204 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|ram_wr_addr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.328 ; ; 0.206 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.329 ; ; 0.207 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.329 ; ; 0.209 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[8] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.332 ; ; 0.212 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.334 ; ; 0.213 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|adc_rst_sync3 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trig_done ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.337 ; ; 0.228 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[26] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.374 ; ; 0.229 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[30] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.062 ; 0.375 ; ; 0.235 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.244 ; 0.563 ; ; 0.238 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[31] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.244 ; 0.566 ; ; 0.258 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.238 ; 0.580 ; ; 0.258 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.238 ; 0.580 ; ; 0.259 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[2] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.382 ; ; 0.261 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.384 ; ; 0.261 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[27] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[27] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.384 ; ; 0.262 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.384 ; ; 0.262 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.385 ; ; 0.262 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[25] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.386 ; ; 0.263 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[18] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.387 ; ; 0.263 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.386 ; ; 0.263 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[28] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[28] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.386 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[0] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.387 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[8] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.386 ; ; 0.264 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[24] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.386 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.387 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[5] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[10] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[10] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[9] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.388 ; ; 0.265 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[11] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[11] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.388 ; ; 0.266 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.388 ; ; 0.266 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.390 ; ; 0.267 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[7] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.390 ; ; 0.268 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[9] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.390 ; ; 0.271 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|wave_type[0] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.395 ; ; 0.271 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|min_vol[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.393 ; ; 0.272 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[19] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[19] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.040 ; 0.396 ; ; 0.273 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.395 ; ; 0.278 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|prdata[12] ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.244 ; 0.606 ; ; 0.279 ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[31] ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[31] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.038 ; 0.401 ; ; 0.284 ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[1] ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_pulse_width[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.039 ; 0.407 ; ; 0.285 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.417 ; ; 0.286 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.418 ; ; 0.286 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 0.417 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.419 ; ; 0.287 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.047 ; 0.418 ; ; 0.288 ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.048 ; 0.420 ; +-------+--------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+-------------------------------------+-------------------------------------+--------------+------------+------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'pll_inst|auto_generated|pll1|clk[0]' ; +-------+--------------+----------------+------------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +-------+--------------+----------------+------------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+ ; 4.559 ; 4.789 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_address_reg0 ; ; 4.559 ; 4.789 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_re_reg ; ; 4.559 ; 4.789 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_we_reg ; ; 4.560 ; 4.790 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 4.560 ; 4.790 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_re_reg ; ; 4.560 ; 4.790 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_we_reg ; ; 4.560 ; 4.790 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_address_reg0 ; ; 4.560 ; 4.790 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; ; 4.561 ; 4.791 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_address_reg0 ; ; 4.561 ; 4.791 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_we_reg ; ; 4.561 ; 4.791 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_datain_reg0 ; ; 4.562 ; 4.792 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_datain_reg0 ; ; 4.562 ; 4.792 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; ; 4.563 ; 4.793 ; 0.230 ; Low Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbIdle ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|apbState.apbSetup ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[12] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[13] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|haddr[15] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hdone ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hreadyout ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|hwrite ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[12] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[13] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[14] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|paddr[15] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pdone ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|penable ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[16] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[18] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[19] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[20] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[23] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[25] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[2] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[3] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[7] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[9] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|psel ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pvalid ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|pwrite ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[0] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[3] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[4] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[6] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[5] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_r[6] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[12] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[16] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[18] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[23] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[25] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|frequency[9] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|pr_select[0] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|pr_select[1] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|pr_select[2] ; ; 4.588 ; 4.804 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|pr_select[3] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[0] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[17] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[1] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[22] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[24] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[4] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[5] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[6] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[8] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[0] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[10] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[11] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[12] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[13] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[14] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[15] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[1] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[2] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[3] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[4] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[5] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[6] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[7] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[8] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_adc:apb_adc0_inst|sclk_counter[9] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[1] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[2] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[5] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[7] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[8] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|max_vol_r[9] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[0] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[1] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[2] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[3] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[4] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[5] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[6] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[7] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[8] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|min_vol_r[9] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[0] ; ; 4.589 ; 4.805 ; 0.216 ; High Pulse Width ; pll_inst|auto_generated|pll1|clk[0] ; Rise ; analog_ip:macro_inst|apb_dac:apb_dac0_inst|phase_acc[10] ; +-------+--------------+----------------+------------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI' ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ ; 49.208 ; 49.438 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_address_reg0 ; ; 49.208 ; 49.438 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_re_reg ; ; 49.208 ; 49.438 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_we_reg ; ; 49.209 ; 49.439 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_address_reg0 ; ; 49.209 ; 49.439 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_re_reg ; ; 49.209 ; 49.439 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_we_reg ; ; 49.209 ; 49.439 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_address_reg0 ; ; 49.209 ; 49.439 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_we_reg ; ; 49.210 ; 49.440 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_address_reg0 ; ; 49.210 ; 49.440 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_we_reg ; ; 49.210 ; 49.440 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~porta_datain_reg0 ; ; 49.211 ; 49.441 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~porta_datain_reg0 ; ; 49.211 ; 49.441 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a9~portb_datain_reg0 ; ; 49.212 ; 49.442 ; 0.230 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|altsyncram:u_dual_port_ram|altsyncram_sgu1:auto_generated|ram_block1a0~portb_datain_reg0 ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[0] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[10] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[1] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[2] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[3] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[4] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[5] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[6] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[7] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[8] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|gap_cnt_auto[9] ; ; 49.244 ; 49.428 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|trigger_ptr[8] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[0] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[10] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[11] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[12] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[13] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[14] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[15] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[1] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[2] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[3] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[4] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[5] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[6] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[7] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[8] ; ; 49.245 ; 49.429 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_cnt[9] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[0] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[1] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[2] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[3] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[4] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[5] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[6] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[7] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[8] ; ; 49.246 ; 49.430 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|auto_wait_cnt[9] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[10] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[11] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[12] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[13] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[14] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[15] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[21] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[26] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[27] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[28] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[29] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[30] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|ahb2apb:ahb2apb_inst|prdata[31] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[0] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[10] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[11] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[12] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[13] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[14] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[15] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[1] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[2] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[3] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[4] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[5] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[6] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[7] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[8] ; ; 49.248 ; 49.432 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|eoc_cnt[9] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[12] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[13] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[14] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[15] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[2] ; ; 49.249 ; 49.433 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[9] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[0] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[2] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[3] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[4] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|max_vol[6] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[0] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[1] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_auto_timeout[6] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[0] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_mode[1] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[0] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|cfg_reg:cfg_reg_inst|trig_time_slot[4] ; ; 49.250 ; 49.434 ; 0.184 ; Low Pulse Width ; PIN_HSI ; Rise ; analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst|pulse_active ; +--------+--------------+----------------+-----------------+---------+------------+----------------------------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'PLL_CLKIN' ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ ; 61.901 ; 61.901 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 61.901 ; 61.901 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 61.948 ; 61.948 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 61.952 ; 61.952 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 62.500 ; 62.500 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 62.500 ; 62.500 ; 0.000 ; Low Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|i ; ; 63.048 ; 63.048 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|inclk[0] ; ; 63.052 ; 63.052 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; PLL_CLKIN~input|o ; ; 63.095 ; 63.095 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; 63.095 ; 63.095 ; 0.000 ; High Pulse Width ; PLL_CLKIN ; Rise ; pll_inst|auto_generated|pll1|observablevcoout ; ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PLL_CLKIN ; Rise ; PLL_CLKIN ; +---------+--------------+----------------+------------------+-----------+------------+-----------------------------------------------+ +--------------------------------------------------------------------------------------+ ; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE' ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; +---------+--------------+----------------+-----------+---------+------------+---------+ ; 121.000 ; 125.000 ; 4.000 ; Port Rate ; PIN_HSE ; Rise ; PIN_HSE ; +---------+--------------+----------------+-----------+---------+------------+---------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Clock to Output Times ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.343 ; 1.909 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.343 ; 1.909 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.087 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.064 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.300 ; 1.866 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.300 ; 1.866 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.334 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.311 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ --------------------------------------------- ; Fast 1200mV 0C Model Metastability Report ; --------------------------------------------- No synchronizer chains to report. +--------------------------------------------------------------------------------------------------+ ; Multicorner Timing Analysis Summary ; +--------------------------------------+--------+-------+----------+---------+---------------------+ ; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; +--------------------------------------+--------+-------+----------+---------+---------------------+ ; Worst-case Slack ; 2.082 ; 0.084 ; N/A ; N/A ; 4.447 ; ; PIN_HSE ; N/A ; N/A ; N/A ; N/A ; 121.000 ; ; PIN_HSI ; 92.467 ; 0.084 ; N/A ; N/A ; 49.208 ; ; PLL_CLKIN ; N/A ; N/A ; N/A ; N/A ; 61.901 ; ; pll_inst|auto_generated|pll1|clk[0] ; 2.082 ; 0.084 ; N/A ; N/A ; 4.447 ; ; Design-wide TNS ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; 0.0 ; ; PIN_HSE ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; PIN_HSI ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; ; PLL_CLKIN ; N/A ; N/A ; N/A ; N/A ; 0.000 ; ; pll_inst|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; N/A ; N/A ; 0.000 ; +--------------------------------------+--------+-------+----------+---------+---------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Clock to Output Times ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.999 ; 3.062 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 2.999 ; 3.062 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; 0.308 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; 0.220 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+-------+-------+------------+-------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Minimum Clock to Output Times ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.300 ; 1.866 ; Rise ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI ; 1.300 ; 1.866 ; Fall ; PIN_HSI ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; -0.334 ; ; Rise ; pll_inst|auto_generated|pll1|clk[0] ; ; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PLL_CLKIN ; ; -0.383 ; Fall ; pll_inst|auto_generated|pll1|clk[0] ; +------------------------------------------+------------+--------+--------+------------+-------------------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Board Trace Model Assignments ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ ; SPI0_CSN ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; SPI0_SCK ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; BAUD_RATE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO4_1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; GPIO4_2 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; TEST_SINGLE ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; UART1_RX ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; UART1_TX ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; so_io1 ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ; +---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+ +----------------------------------------------------------------------------+ ; Input Transition Times ; +-------------------------+--------------+-----------------+-----------------+ ; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ; +-------------------------+--------------+-----------------+-----------------+ ; PIN_HSE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; BAUD_RATE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO4_1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; GPIO4_2 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; TEST_SINGLE ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; UART1_RX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; UART1_TX ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; so_io1 ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; UART0_UARTRXD ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; PIN_HSI ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; PLL_CLKIN ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_ASDO_DATA1~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; ; ~ALTERA_DATA0~ ; 3.3-V LVTTL ; 2640 ps ; 2640 ps ; +-------------------------+--------------+-----------------+-----------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 0c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ; 3.08 V ; 8.89e-09 V ; 3.09 V ; -0.011 V ; 0.196 V ; 0.301 V ; 4.93e-09 s ; 3.56e-09 s ; Yes ; Yes ; ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; 3.08 V ; 8.89e-09 V ; 3.12 V ; -0.11 V ; 0.153 V ; 0.272 V ; 6.41e-10 s ; 4.57e-10 s ; No ; Yes ; ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ; 3.08 V ; 3.51e-09 V ; 3.18 V ; -0.157 V ; 0.147 V ; 0.259 V ; 2.81e-10 s ; 2.53e-10 s ; Yes ; Yes ; ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; 3.08 V ; 6.38e-09 V ; 3.12 V ; -0.0818 V ; 0.205 V ; 0.244 V ; 8.86e-10 s ; 6.56e-10 s ; No ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Slow 1200mv 85c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.08 V ; -0.00457 V ; 0.185 V ; 0.21 V ; 5.8e-09 s ; 4.46e-09 s ; Yes ; Yes ; ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; 3.08 V ; 7.5e-07 V ; 3.11 V ; -0.0503 V ; 0.122 V ; 0.172 V ; 7.08e-10 s ; 6.43e-10 s ; Yes ; Yes ; ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ; 3.08 V ; 2.6e-07 V ; 3.13 V ; -0.103 V ; 0.164 V ; 0.134 V ; 3.14e-10 s ; 4.05e-10 s ; Yes ; No ; ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; 3.08 V ; 5.04e-07 V ; 3.11 V ; -0.0469 V ; 0.191 V ; 0.215 V ; 1.08e-09 s ; 8.62e-10 s ; Yes ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Signal Integrity Metrics (Fast 1200mv 0c Model) ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ ; SPI0_CSN ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; SPI0_SCK ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; UART0_UARTTXD ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; BAUD_RATE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; GPIO4_1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; GPIO4_2 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.48 V ; -0.0173 V ; 0.356 V ; 0.324 V ; 3.89e-09 s ; 3.06e-09 s ; No ; No ; ; SPI0_SI_IO0 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; TEST_SINGLE ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; UART1_RX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; UART1_TX ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; 3.46 V ; 1.85e-07 V ; 3.57 V ; -0.141 V ; 0.301 V ; 0.239 V ; 4.61e-10 s ; 4.2e-10 s ; No ; No ; ; so_io1 ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; ; ~ALTERA_DCLK~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; 3.46 V ; 6.54e-08 V ; 3.66 V ; -0.26 V ; 0.41 V ; 0.32 V ; 1.57e-10 s ; 2.15e-10 s ; No ; Yes ; ; ~ALTERA_nCEO~ ; 3.3-V LVTTL ; 0 s ; 0 s ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; 3.46 V ; 1.25e-07 V ; 3.57 V ; -0.0855 V ; 0.315 V ; 0.175 V ; 6.79e-10 s ; 6.15e-10 s ; No ; No ; +---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+ +-------------------------------------------------------------------------------------------------------------------------+ ; Setup Transfers ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ ; PIN_HSI ; PIN_HSI ; 32929 ; 0 ; 0 ; 0 ; ; pll_inst|auto_generated|pll1|clk[0] ; PIN_HSI ; false path ; 0 ; 0 ; 0 ; ; PIN_HSI ; pll_inst|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 32929 ; 0 ; 0 ; 0 ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. +-------------------------------------------------------------------------------------------------------------------------+ ; Hold Transfers ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ ; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ ; PIN_HSI ; PIN_HSI ; 32929 ; 0 ; 0 ; 0 ; ; pll_inst|auto_generated|pll1|clk[0] ; PIN_HSI ; false path ; 0 ; 0 ; 0 ; ; PIN_HSI ; pll_inst|auto_generated|pll1|clk[0] ; false path ; 0 ; 0 ; 0 ; ; pll_inst|auto_generated|pll1|clk[0] ; pll_inst|auto_generated|pll1|clk[0] ; 32929 ; 0 ; 0 ; 0 ; +-------------------------------------+-------------------------------------+------------+----------+----------+----------+ Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. --------------- ; Report TCCS ; --------------- No dedicated SERDES Transmitter circuitry present in device or used in design --------------- ; Report RSKM ; --------------- No dedicated SERDES Receiver circuitry present in device or used in design +------------------------------------------------+ ; Unconstrained Paths ; +---------------------------------+-------+------+ ; Property ; Setup ; Hold ; +---------------------------------+-------+------+ ; Illegal Clocks ; 0 ; 0 ; ; Unconstrained Clocks ; 0 ; 0 ; ; Unconstrained Input Ports ; 1 ; 1 ; ; Unconstrained Input Port Paths ; 1 ; 1 ; ; Unconstrained Output Ports ; 1 ; 1 ; ; Unconstrained Output Port Paths ; 3 ; 3 ; +---------------------------------+-------+------+ +------------------------------------+ ; TimeQuest Timing Analyzer Messages ; +------------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version Info: Processing started: Sat May 09 14:19:21 2026 Info: Command: quartus_sta example_board -c example_board Info: qsta_default_script.tcl version: #1 Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. Info (21077): Low junction temperature is 0 degrees C Info (21077): High junction temperature is 85 degrees C Info (332104): Reading SDC File: 'example_board.sdc' Info (332110): Deriving PLL clocks Info (332110): create_clock -period 125.000 -waveform {0.000 62.500} -name PLL_CLKIN PLL_CLKIN Info (332110): create_generated_clock -source {pll_inst|auto_generated|pll1|inclk[0]} -multiply_by 13 -duty_cycle 50.00 -name {pll_inst|auto_generated|pll1|clk[0]} {pll_inst|auto_generated|pll1|clk[0]} Warning (332174): Ignored filter at example_board.sdc(13): rv32|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition Warning (332049): Ignored set_false_path at example_board.sdc(13): Argument is not an object ID Info (332050): set_false_path -from rv32|resetn_out Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold) Critical Warning (332169): From pll_inst|auto_generated|pll1|clk[0] (Rise) to pll_inst|auto_generated|pll1|clk[0] (Rise) (setup and hold) Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info: Analyzing Slow 1200mV 85C Model Info (332146): Worst-case setup slack is 2.082 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 2.082 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 92.467 0.000 PIN_HSI Info (332146): Worst-case hold slack is 0.264 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 0.264 0.000 PIN_HSI Info (332119): 0.264 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 4.458 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 4.458 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 49.635 0.000 PIN_HSI Info (332119): 62.371 0.000 PLL_CLKIN Info (332119): 121.000 0.000 PIN_HSE Info: Analyzing Slow 1200mV 0C Model Info (334003): Started post-fitting delay annotation Info (334004): Delay annotation completed successfully Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold) Critical Warning (332169): From pll_inst|auto_generated|pll1|clk[0] (Rise) to pll_inst|auto_generated|pll1|clk[0] (Rise) (setup and hold) Info (332146): Worst-case setup slack is 2.677 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 2.677 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 93.062 0.000 PIN_HSI Info (332146): Worst-case hold slack is 0.208 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 0.208 0.000 PIN_HSI Info (332119): 0.208 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 4.447 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 4.447 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 49.631 0.000 PIN_HSI Info (332119): 62.365 0.000 PLL_CLKIN Info (332119): 121.000 0.000 PIN_HSE Info: Analyzing Fast 1200mV 0C Model Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command. Critical Warning (332169): From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold) Critical Warning (332169): From pll_inst|auto_generated|pll1|clk[0] (Rise) to pll_inst|auto_generated|pll1|clk[0] (Rise) (setup and hold) Info (332146): Worst-case setup slack is 6.421 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 6.421 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 96.806 0.000 PIN_HSI Info (332146): Worst-case hold slack is 0.084 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 0.084 0.000 PIN_HSI Info (332119): 0.084 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332140): No Recovery paths to report Info (332140): No Removal paths to report Info (332146): Worst-case minimum pulse width slack is 4.559 Info (332119): Slack End Point TNS Clock Info (332119): ========= ============= ===================== Info (332119): 4.559 0.000 pll_inst|auto_generated|pll1|clk[0] Info (332119): 49.208 0.000 PIN_HSI Info (332119): 61.901 0.000 PLL_CLKIN Info (332119): 121.000 0.000 PIN_HSE Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 11 warnings Info: Peak virtual memory: 4712 megabytes Info: Processing ended: Sat May 09 14:19:24 2026 Info: Elapsed time: 00:00:03 Info: Total CPU time (on all processors): 00:00:03