--lpm_divide DEVICE_FAMILY="Cyclone IV E" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=32 LPM_WIDTHN=28 OPTIMIZE_FOR_SPEED=5 denom numer quotient CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 IGNORE_CARRY_BUFFERS="OFF" --VERSION_BEGIN 13.0 cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_abs 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_divide 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION sign_div_unsign_9nh (denominator[31..0], numerator[31..0]) RETURNS ( quotient[31..0], remainder[31..0]); --synthesis_resources = lut 555 SUBDESIGN lpm_divide_mkm ( denom[31..0] : input; numer[27..0] : input; quotient[27..0] : output; remain[31..0] : output; ) VARIABLE divider : sign_div_unsign_9nh; gnd_wire : WIRE; num_padder[3..0] : WIRE; numer_tmp[31..0] : WIRE; BEGIN divider.denominator[] = denom[]; divider.numerator[] = numer_tmp[]; gnd_wire = B"0"; num_padder[] = ( gnd_wire, gnd_wire, gnd_wire, gnd_wire); numer_tmp[] = ( num_padder[], numer[]); quotient[27..0] = divider.quotient[27..0]; remain[] = divider.remainder[]; END; --VALID FILE