--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INDATA_ACLR_A="NONE" INIT_FILE="db/example_board.ram0_apb_dac_21e6ff89.hdl.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=1024 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" WIDTH_A=10 WIDTHAD_A=10 WRCONTROL_ACLR_A="NONE" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 --VERSION_BEGIN 13.0 cbx_altsyncram 2013:04:24:18:08:47:SJ cbx_cycloneii 2013:04:24:18:08:47:SJ cbx_lpm_add_sub 2013:04:24:18:08:47:SJ cbx_lpm_compare 2013:04:24:18:08:47:SJ cbx_lpm_decode 2013:04:24:18:08:47:SJ cbx_lpm_mux 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ cbx_stratix 2013:04:24:18:08:47:SJ cbx_stratixii 2013:04:24:18:08:47:SJ cbx_stratixiii 2013:04:24:18:08:47:SJ cbx_stratixv 2013:04:24:18:08:47:SJ cbx_util_mgl 2013:04:24:18:08:47:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe) WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS) RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); --synthesis_resources = M9K 2 OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; SUBDESIGN altsyncram_ak71 ( address_a[9..0] : input; clock0 : input; q_a[9..0] : output; ) VARIABLE ram_block1a0 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 0, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a1 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 1, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a2 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 2, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a3 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 3, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a4 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 4, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a5 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 5, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a6 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 6, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a7 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 7, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a8 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 8, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); ram_block1a9 : cycloneive_ram_block WITH ( CLK0_CORE_CLOCK_ENABLE = "none", CLK0_INPUT_CLOCK_ENABLE = "none", CONNECTIVITY_CHECKING = "OFF", INIT_FILE = "db/example_board.ram0_apb_dac_21e6ff89.hdl.mif", INIT_FILE_LAYOUT = "port_a", LOGICAL_RAM_NAME = "ALTSYNCRAM", OPERATION_MODE = "rom", PORT_A_ADDRESS_CLEAR = "none", PORT_A_ADDRESS_WIDTH = 10, PORT_A_DATA_OUT_CLEAR = "none", PORT_A_DATA_OUT_CLOCK = "none", PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS = 0, PORT_A_FIRST_BIT_NUMBER = 9, PORT_A_LAST_ADDRESS = 1023, PORT_A_LOGICAL_RAM_DEPTH = 1024, PORT_A_LOGICAL_RAM_WIDTH = 10, RAM_BLOCK_TYPE = "AUTO" ); address_a_wire[9..0] : WIRE; BEGIN ram_block1a[9..0].clk0 = clock0; ram_block1a[9..0].portaaddr[] = ( address_a_wire[9..0]); ram_block1a[9..0].portare = B"1111111111"; address_a_wire[] = address_a[]; q_a[] = ( ram_block1a[9..0].portadataout[0..0]); END; --VALID FILE