=== User constraints ===

Clock transfer report:
  Worst  hold:   0.543, with clock PIN_HSE
  Worst  hold:   0.543, with clock PIN_HSI
  Worst  hold:   0.543, with clock pll_inst|auto_generated|pll1|clk[0]

=== Auto constraints ===
Coverage report
  User constraints covered 3450 connections out of 6471 total, coverage: 53.3%
  Auto constraints covered 3450 connections out of 6471 total, coverage: 53.3%


Hold from macro_inst|trig_ctrl_inst|ram_wr_data_b[7] to macro_inst|u_dual_port_ram|auto_generated|ram_block1a0, clock PIN_HSI, constraint 0.000, skew -0.118, data 0.809
  Slack:   0.543
    Arrival Time:    4.422
        0.000    0.000   R                         Launch Clock Edge
      Launch Clock Path:
        0.000    0.000   RR                    example_board|PIN_HSI =>                      PIN_HSI~input|padio 
        1.309    1.309   RR                      PIN_HSI~input|padio =>                    PIN_HSI~input|combout 
        1.309    0.000   RR                    PIN_HSI~input|combout => gclksw_inst|gclk_switch__alta_gclksw|clkin0 
        1.711    0.402   RR gclksw_inst|gclk_switch__alta_gclksw|clkin0 => gclksw_inst|gclk_switch__alta_gclksw|clkout 
        1.824    0.113   RR gclksw_inst|gclk_switch__alta_gclksw|clkout =>            gclksw_inst|gclk_switch|inclk 
        1.824    0.000   RR            gclksw_inst|gclk_switch|inclk =>           gclksw_inst|gclk_switch|outclk 
        3.334    1.510   RR           gclksw_inst|gclk_switch|outclk =>               clken_ctrl_X54_Y4_N0|ClkIn 
        3.482    0.148   RR               clken_ctrl_X54_Y4_N0|ClkIn =>              clken_ctrl_X54_Y4_N0|ClkOut 
        3.613    0.131   RR              clken_ctrl_X54_Y4_N0|ClkOut => macro_inst|trig_ctrl_inst|ram_wr_data_b[7]|Clk 
      Data Path:
        3.828    0.215   RR macro_inst|trig_ctrl_inst|ram_wr_data_b[7]|Clk => macro_inst|trig_ctrl_inst|ram_wr_data_b[7]|Q D
        4.422    0.594   RR macro_inst|trig_ctrl_inst|ram_wr_data_b[7]|Q => macro_inst|u_dual_port_ram|auto_generated|ram_block1a0|DataInB[16] E
    Required Time:   3.879
        0.000    0.000   R                          Latch Clock Edge
      Latch Clock Path:
        0.000    0.000   RR                    example_board|PIN_HSI =>                      PIN_HSI~input|padio 
        1.309    1.309   RR                      PIN_HSI~input|padio =>                    PIN_HSI~input|combout 
        1.309    0.000   RR                    PIN_HSI~input|combout => gclksw_inst|gclk_switch__alta_gclksw|clkin0 
        1.711    0.402   RR gclksw_inst|gclk_switch__alta_gclksw|clkin0 => gclksw_inst|gclk_switch__alta_gclksw|clkout 
        1.824    0.113   RR gclksw_inst|gclk_switch__alta_gclksw|clkout =>            gclksw_inst|gclk_switch|inclk 
        1.824    0.000   RR            gclksw_inst|gclk_switch|inclk =>           gclksw_inst|gclk_switch|outclk 
        3.495    1.671   RR           gclksw_inst|gclk_switch|outclk => macro_inst|u_dual_port_ram|auto_generated|ram_block1a0|Clk0 
        3.879    0.384   R                                      Hold