{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778306608096 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306608096 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:27 2026 " "Processing started: Sat May 09 14:03:27 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306608096 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778306608096 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board " "Command: quartus_map --read_settings_files=on --write_settings_files=off example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778306608097 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1778306608503 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "POST_TRIG_CNT post_trig_cnt trig_ctrl.v(26) " "Verilog HDL Declaration information at trig_ctrl.v(26): object \"POST_TRIG_CNT\" differs only in case from object \"post_trig_cnt\" in the same scope" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 26 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778306608554 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "trig_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file trig_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 trig_ctrl " "Found entity 1: trig_ctrl" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608554 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608554 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "cfg_reg.v(121) " "Verilog HDL information at cfg_reg.v(121): always construct contains both blocking and non-blocking assignments" {  } { { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 121 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1778306608557 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cfg_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file cfg_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 cfg_reg " "Found entity 1: cfg_reg" {  } { { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608557 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608557 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "apb2ram.v 1 1 " "Found 1 design units, including 1 entities, in source file apb2ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 apb2ram " "Found entity 1: apb2ram" {  } { { "apb2ram.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608559 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608559 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "baud_detect.v(49) " "Verilog HDL information at baud_detect.v(49): always construct contains both blocking and non-blocking assignments" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 49 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Quartus II" 0 -1 1778306608562 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "baud_detect.v 1 1 " "Found 1 design units, including 1 entities, in source file baud_detect.v" { { "Info" "ISGN_ENTITY_NAME" "1 baud_detect " "Found entity 1: baud_detect" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608562 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608562 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ahb2apb.v 1 1 " "Found 1 design units, including 1 entities, in source file ahb2apb.v" { { "Info" "ISGN_ENTITY_NAME" "1 ahb2apb " "Found entity 1: ahb2apb" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608564 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608564 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "example_board.v 1 1 " "Found 1 design units, including 1 entities, in source file example_board.v" { { "Info" "ISGN_ENTITY_NAME" "1 example_board " "Found entity 1: example_board" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608568 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608568 ""}
{ "Warning" "WVRFX_L2_VERI_INGORE_DANGLING_COMMA" "analog_ip.v(314) " "Verilog HDL Module Instantiation warning at analog_ip.v(314): ignored dangling comma in List of Port Connections" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0 "Quartus II" 0 -1 1778306608571 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "BAUD_RATE baud_rate analog_ip.v(4) " "Verilog HDL Declaration information at analog_ip.v(4): object \"BAUD_RATE\" differs only in case from object \"baud_rate\" in the same scope" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 4 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778306608571 ""}
{ "Warning" "WVRFX_INVALID_ATTRIBUTE_TYPE" "ram_style analog_ip.v(634) " "Unrecognized synthesis attribute \"ram_style\" at analog_ip.v(634)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 634 0 0 } }  } 0 10335 "Unrecognized synthesis attribute \"%1!s!\" at %2!s!" 0 0 "Quartus II" 0 -1 1778306608572 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "analog_ip.v 3 3 " "Found 3 design units, including 3 entities, in source file analog_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 analog_ip " "Found entity 1: analog_ip" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 3 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608572 ""} { "Info" "ISGN_ENTITY_NAME" "2 apb_adc " "Found entity 2: apb_adc" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 497 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608572 ""} { "Info" "ISGN_ENTITY_NAME" "3 apb_dac " "Found entity 3: apb_dac" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 591 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608572 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608572 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4171) " "Verilog HDL Declaration information at alta_sim.v(4171): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4171 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778306608578 ""}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "alta_sim.v(4325) " "Verilog HDL warning at alta_sim.v(4325): extended using \"x\" or \"z\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4325 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1778306608579 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4376) " "Verilog HDL Declaration information at alta_sim.v(4376): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4376 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1778306608579 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v 57 57 " "Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" { { "Info" "ISGN_ENTITY_NAME" "1 alta_slice " "Found entity 1: alta_slice" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "2 alta_clkenctrl_rst " "Found entity 2: alta_clkenctrl_rst" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 85 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "3 alta_clkenctrl " "Found entity 3: alta_clkenctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "4 alta_asyncctrl " "Found entity 4: alta_asyncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 118 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "5 alta_syncctrl " "Found entity 5: alta_syncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 132 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "6 alta_io_gclk " "Found entity 6: alta_io_gclk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 146 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "7 alta_gclksel " "Found entity 7: alta_gclksel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 159 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "8 alta_gclkgen " "Found entity 8: alta_gclkgen" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 171 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "9 alta_gclkgen0 " "Found entity 9: alta_gclkgen0" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 184 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "10 alta_gclkgen2 " "Found entity 10: alta_gclkgen2" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "11 alta_io " "Found entity 11: alta_io" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 209 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "12 alta_rio " "Found entity 12: alta_rio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 275 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "13 alta_srff " "Found entity 13: alta_srff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 343 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "14 alta_dff " "Found entity 14: alta_dff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 366 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "15 alta_ufm_gddd " "Found entity 15: alta_ufm_gddd" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 373 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "16 alta_dff_stall " "Found entity 16: alta_dff_stall" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 377 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "17 alta_srlat " "Found entity 17: alta_srlat" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "18 alta_dio " "Found entity 18: alta_dio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 402 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "19 alta_indel " "Found entity 19: alta_indel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "20 alta_dpclkdel " "Found entity 20: alta_dpclkdel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 509 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "21 alta_ufms " "Found entity 21: alta_ufms" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 520 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "22 alta_ufms_sim " "Found entity 22: alta_ufms_sim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 546 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "23 alta_pll " "Found entity 23: alta_pll" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 902 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "24 alta_pllx " "Found entity 24: alta_pllx" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 960 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "25 pll_clk_trim " "Found entity 25: pll_clk_trim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "26 alta_pllv " "Found entity 26: alta_pllv" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1999 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "27 alta_pllve " "Found entity 27: alta_pllve" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "28 alta_sram " "Found entity 28: alta_sram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2310 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "29 alta_dpram16x4 " "Found entity 29: alta_dpram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2349 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "30 alta_spram16x4 " "Found entity 30: alta_spram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2367 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "31 alta_wram " "Found entity 31: alta_wram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "32 alta_bram_pulse_generator " "Found entity 32: alta_bram_pulse_generator" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2423 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "33 alta_bram " "Found entity 33: alta_bram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2440 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "34 alta_boot " "Found entity 34: alta_boot" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2611 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "35 alta_osc " "Found entity 35: alta_osc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2625 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "36 alta_ufml " "Found entity 36: alta_ufml" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2640 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "37 alta_jtag " "Found entity 37: alta_jtag" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2649 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "38 alta_mult " "Found entity 38: alta_mult" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2682 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "39 alta_dff_en " "Found entity 39: alta_dff_en" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2754 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "40 alta_multm_add " "Found entity 40: alta_multm_add" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2762 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "41 alta_multm " "Found entity 41: alta_multm" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2785 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "42 alta_i2c " "Found entity 42: alta_i2c" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3020 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "43 alta_spi " "Found entity 43: alta_spi" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3057 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "44 alta_irda " "Found entity 44: alta_irda" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3104 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "45 alta_bram9k " "Found entity 45: alta_bram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3124 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "46 alta_mcu " "Found entity 46: alta_mcu" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3365 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "47 alta_mcu_m3 " "Found entity 47: alta_mcu_m3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3494 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "48 alta_remote " "Found entity 48: alta_remote" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3657 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "49 alta_saradc " "Found entity 49: alta_saradc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3668 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "50 alta_gclksw " "Found entity 50: alta_gclksw" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3683 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "51 alta_rv32 " "Found entity 51: alta_rv32" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3715 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "52 alta_mipi_clk " "Found entity 52: alta_mipi_clk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3906 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "53 alta_adc " "Found entity 53: alta_adc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3922 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "54 alta_dac " "Found entity 54: alta_dac" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "55 alta_cmp " "Found entity 55: alta_cmp" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4006 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "56 alta_ram4k " "Found entity 56: alta_ram4k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4062 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""} { "Info" "ISGN_ENTITY_NAME" "57 alta_ram9k " "Found entity 57: alta_ram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4241 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608581 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_10_in example_board.v(39) " "Verilog HDL Implicit Net warning at example_board.v(39): created implicit net for \"PIN_10_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 39 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608583 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_21_in example_board.v(55) " "Verilog HDL Implicit Net warning at example_board.v(55): created implicit net for \"PIN_21_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 55 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_29_in example_board.v(58) " "Verilog HDL Implicit Net warning at example_board.v(58): created implicit net for \"PIN_29_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 58 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_31_in example_board.v(69) " "Verilog HDL Implicit Net warning at example_board.v(69): created implicit net for \"PIN_31_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 69 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSE_in example_board.v(75) " "Verilog HDL Implicit Net warning at example_board.v(75): created implicit net for \"PIN_HSE_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 75 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSI_in example_board.v(78) " "Verilog HDL Implicit Net warning at example_board.v(78): created implicit net for \"PIN_HSI_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 78 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_OSC_in example_board.v(81) " "Verilog HDL Implicit Net warning at example_board.v(81): created implicit net for \"PIN_OSC_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 81 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "usb0_xcvr_clk example_board.v(204) " "Verilog HDL Implicit Net warning at example_board.v(204): created implicit net for \"usb0_xcvr_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 204 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "bus_clk example_board.v(205) " "Verilog HDL Implicit Net warning at example_board.v(205): created implicit net for \"bus_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 205 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sys_clk example_board.v(216) " "Verilog HDL Implicit Net warning at example_board.v(216): created implicit net for \"sys_clk\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 216 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "csn_out_data example_board.v(269) " "Verilog HDL Implicit Net warning at example_board.v(269): created implicit net for \"csn_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 269 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "csn_out_en example_board.v(270) " "Verilog HDL Implicit Net warning at example_board.v(270): created implicit net for \"csn_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 270 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd1_ip_in example_board.v(271) " "Verilog HDL Implicit Net warning at example_board.v(271): created implicit net for \"rxd1_ip_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 271 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sck_out_data example_board.v(272) " "Verilog HDL Implicit Net warning at example_board.v(272): created implicit net for \"sck_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 272 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sck_out_en example_board.v(273) " "Verilog HDL Implicit Net warning at example_board.v(273): created implicit net for \"sck_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 273 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_in example_board.v(274) " "Verilog HDL Implicit Net warning at example_board.v(274): created implicit net for \"so_io1_in\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 274 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_out_data example_board.v(275) " "Verilog HDL Implicit Net warning at example_board.v(275): created implicit net for \"so_io1_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 275 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "so_io1_out_en example_board.v(276) " "Verilog HDL Implicit Net warning at example_board.v(276): created implicit net for \"so_io1_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 276 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd1_ip_out_data example_board.v(277) " "Verilog HDL Implicit Net warning at example_board.v(277): created implicit net for \"txd1_ip_out_data\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 277 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd1_ip_out_en example_board.v(278) " "Verilog HDL Implicit Net warning at example_board.v(278): created implicit net for \"txd1_ip_out_en\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 278 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(180) " "Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 180 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_int alta_sim.v(204) " "Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for \"ena_int\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 204 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(205) " "Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 205 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_h alta_sim.v(476) " "Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for \"outreg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 476 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_l alta_sim.v(477) " "Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for \"outreg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 477 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_h alta_sim.v(485) " "Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for \"oe_reg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 485 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_l alta_sim.v(486) " "Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for \"oe_reg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 486 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "dffOut alta_sim.v(2758) " "Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for \"dffOut\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2758 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608584 ""}
{ "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "alta_bram_pulse_generator alta_sim.v(2428) " "Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module \"alta_bram_pulse_generator\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2428 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "Quartus II" 0 -1 1778306608592 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "example_board " "Elaborating entity \"example_board\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1778306608671 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll:pll_inst " "Elaborating entity \"altpll\" for hierarchy \"altpll:pll_inst\"" {  } { { "example_board.v" "pll_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608716 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "altpll:pll_inst " "Elaborated megafunction instantiation \"altpll:pll_inst\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altpll:pll_inst " "Instantiated megafunction \"altpll:pll_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 8 " "Parameter \"clk0_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 104 " "Parameter \"clk0_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 8 " "Parameter \"clk1_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 104 " "Parameter \"clk1_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 8 " "Parameter \"clk2_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 104 " "Parameter \"clk2_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_divide_by 8 " "Parameter \"clk3_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_multiply_by 104 " "Parameter \"clk3_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_phase_shift 0 " "Parameter \"clk3_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_divide_by 8 " "Parameter \"clk4_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_multiply_by 104 " "Parameter \"clk4_multiply_by\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_phase_shift 0 " "Parameter \"clk4_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 125000 " "Parameter \"inclk0_input_frequency\" = \"125000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_UNUSED " "Parameter \"port_clk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_phasecounterselect 3 " "Parameter \"width_phasecounterselect\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608721 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1778306608721 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_6o32.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_6o32.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_6o32 " "Found entity 1: altpll_6o32" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608781 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608781 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_6o32 altpll:pll_inst\|altpll_6o32:auto_generated " "Elaborating entity \"altpll_6o32\" for hierarchy \"altpll:pll_inst\|altpll_6o32:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608783 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_gclksw alta_gclksw:gclksw_inst " "Elaborating entity \"alta_gclksw\" for hierarchy \"alta_gclksw:gclksw_inst\"" {  } { { "example_board.v" "gclksw_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 216 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608787 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "analog_ip analog_ip:macro_inst " "Elaborating entity \"analog_ip\" for hierarchy \"analog_ip:macro_inst\"" {  } { { "example_board.v" "macro_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608791 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 analog_ip.v(136) " "Verilog HDL assignment warning at analog_ip.v(136): truncated value with size 32 to match size of target (4)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608793 "|example_board|analog_ip:macro_inst"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "analog_ip.v(475) " "Verilog HDL Case Statement information at analog_ip.v(475): all case item expressions in this case statement are onehot" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 475 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Quartus II" 0 -1 1778306608793 "|example_board|analog_ip:macro_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb2apb analog_ip:macro_inst\|ahb2apb:ahb2apb_inst " "Elaborating entity \"ahb2apb\" for hierarchy \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\"" {  } { { "analog_ip.v" "ahb2apb_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 131 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608794 ""}
{ "Warning" "WVRFX_VERI_2086_UNCONVERTED" "ahb2apb.v(52) " "Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 52 0 0 } }  } 0 10764 "Verilog HDL warning at %1!s!: converting signed shift amount to unsigned" 0 0 "Quartus II" 0 -1 1778306608796 "|example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 ahb2apb.v(52) " "Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4)" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608796 "|example_board|analog_ip:macro_inst|ahb2apb:ahb2apb_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cfg_reg analog_ip:macro_inst\|cfg_reg:cfg_reg_inst " "Elaborating entity \"cfg_reg\" for hierarchy \"analog_ip:macro_inst\|cfg_reg:cfg_reg_inst\"" {  } { { "analog_ip.v" "cfg_reg_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 210 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608798 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb_adc analog_ip:macro_inst\|apb_adc:apb_adc0_inst " "Elaborating entity \"apb_adc\" for hierarchy \"analog_ip:macro_inst\|apb_adc:apb_adc0_inst\"" {  } { { "analog_ip.v" "apb_adc0_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 240 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608801 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_adc analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Elaborating entity \"alta_adc\" for hierarchy \"analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst\"" {  } { { "analog_ip.v" "adc_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 584 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608804 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trig_ctrl analog_ip:macro_inst\|trig_ctrl:trig_ctrl_inst " "Elaborating entity \"trig_ctrl\" for hierarchy \"analog_ip:macro_inst\|trig_ctrl:trig_ctrl_inst\"" {  } { { "analog_ip.v" "trig_ctrl_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 288 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608807 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 trig_ctrl.v(163) " "Verilog HDL assignment warning at trig_ctrl.v(163): truncated value with size 32 to match size of target (10)" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608810 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 trig_ctrl.v(359) " "Verilog HDL assignment warning at trig_ctrl.v(359): truncated value with size 32 to match size of target (10)" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 359 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608810 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "trig_ctrl.v(345) " "Verilog HDL Case Statement information at trig_ctrl.v(345): all case item expressions in this case statement are onehot" {  } { { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 345 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Quartus II" 0 -1 1778306608810 "|example_board|analog_ip:macro_inst|trig_ctrl:trig_ctrl_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb_dac analog_ip:macro_inst\|apb_dac:apb_dac0_inst " "Elaborating entity \"apb_dac\" for hierarchy \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\"" {  } { { "analog_ip.v" "apb_dac0_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608811 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1) " "Verilog HDL assignment warning at sine.hex(1): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(2) " "Verilog HDL assignment warning at sine.hex(2): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 2 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(3) " "Verilog HDL assignment warning at sine.hex(3): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 3 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(4) " "Verilog HDL assignment warning at sine.hex(4): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 4 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(5) " "Verilog HDL assignment warning at sine.hex(5): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 5 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(6) " "Verilog HDL assignment warning at sine.hex(6): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 6 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(7) " "Verilog HDL assignment warning at sine.hex(7): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 7 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608814 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(8) " "Verilog HDL assignment warning at sine.hex(8): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 8 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(9) " "Verilog HDL assignment warning at sine.hex(9): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 9 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(10) " "Verilog HDL assignment warning at sine.hex(10): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(11) " "Verilog HDL assignment warning at sine.hex(11): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(12) " "Verilog HDL assignment warning at sine.hex(12): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(13) " "Verilog HDL assignment warning at sine.hex(13): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 13 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(14) " "Verilog HDL assignment warning at sine.hex(14): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 14 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(15) " "Verilog HDL assignment warning at sine.hex(15): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 15 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(16) " "Verilog HDL assignment warning at sine.hex(16): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 16 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(17) " "Verilog HDL assignment warning at sine.hex(17): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 17 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(18) " "Verilog HDL assignment warning at sine.hex(18): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 18 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(19) " "Verilog HDL assignment warning at sine.hex(19): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(20) " "Verilog HDL assignment warning at sine.hex(20): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 20 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(21) " "Verilog HDL assignment warning at sine.hex(21): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 21 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(22) " "Verilog HDL assignment warning at sine.hex(22): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 22 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(23) " "Verilog HDL assignment warning at sine.hex(23): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(24) " "Verilog HDL assignment warning at sine.hex(24): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 24 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(25) " "Verilog HDL assignment warning at sine.hex(25): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608815 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(26) " "Verilog HDL assignment warning at sine.hex(26): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(27) " "Verilog HDL assignment warning at sine.hex(27): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 27 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(28) " "Verilog HDL assignment warning at sine.hex(28): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 28 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(29) " "Verilog HDL assignment warning at sine.hex(29): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 29 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(30) " "Verilog HDL assignment warning at sine.hex(30): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 30 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(31) " "Verilog HDL assignment warning at sine.hex(31): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(32) " "Verilog HDL assignment warning at sine.hex(32): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 32 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(33) " "Verilog HDL assignment warning at sine.hex(33): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(34) " "Verilog HDL assignment warning at sine.hex(34): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 34 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(35) " "Verilog HDL assignment warning at sine.hex(35): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(36) " "Verilog HDL assignment warning at sine.hex(36): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 36 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(37) " "Verilog HDL assignment warning at sine.hex(37): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(38) " "Verilog HDL assignment warning at sine.hex(38): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 38 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(39) " "Verilog HDL assignment warning at sine.hex(39): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(40) " "Verilog HDL assignment warning at sine.hex(40): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608816 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(41) " "Verilog HDL assignment warning at sine.hex(41): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 41 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(42) " "Verilog HDL assignment warning at sine.hex(42): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 42 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(43) " "Verilog HDL assignment warning at sine.hex(43): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 43 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(44) " "Verilog HDL assignment warning at sine.hex(44): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 44 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(45) " "Verilog HDL assignment warning at sine.hex(45): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 45 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(46) " "Verilog HDL assignment warning at sine.hex(46): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(47) " "Verilog HDL assignment warning at sine.hex(47): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 47 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(48) " "Verilog HDL assignment warning at sine.hex(48): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 48 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(49) " "Verilog HDL assignment warning at sine.hex(49): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 49 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(50) " "Verilog HDL assignment warning at sine.hex(50): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(51) " "Verilog HDL assignment warning at sine.hex(51): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(52) " "Verilog HDL assignment warning at sine.hex(52): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(53) " "Verilog HDL assignment warning at sine.hex(53): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 53 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(54) " "Verilog HDL assignment warning at sine.hex(54): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 54 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(55) " "Verilog HDL assignment warning at sine.hex(55): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(56) " "Verilog HDL assignment warning at sine.hex(56): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 56 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(57) " "Verilog HDL assignment warning at sine.hex(57): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(58) " "Verilog HDL assignment warning at sine.hex(58): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 58 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(59) " "Verilog HDL assignment warning at sine.hex(59): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 59 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(60) " "Verilog HDL assignment warning at sine.hex(60): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(61) " "Verilog HDL assignment warning at sine.hex(61): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 61 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(62) " "Verilog HDL assignment warning at sine.hex(62): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(63) " "Verilog HDL assignment warning at sine.hex(63): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 63 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(64) " "Verilog HDL assignment warning at sine.hex(64): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 64 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(65) " "Verilog HDL assignment warning at sine.hex(65): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(66) " "Verilog HDL assignment warning at sine.hex(66): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(67) " "Verilog HDL assignment warning at sine.hex(67): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 67 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(68) " "Verilog HDL assignment warning at sine.hex(68): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 68 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608817 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(69) " "Verilog HDL assignment warning at sine.hex(69): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 69 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(70) " "Verilog HDL assignment warning at sine.hex(70): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 70 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(71) " "Verilog HDL assignment warning at sine.hex(71): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 71 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(72) " "Verilog HDL assignment warning at sine.hex(72): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(73) " "Verilog HDL assignment warning at sine.hex(73): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 73 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(74) " "Verilog HDL assignment warning at sine.hex(74): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 74 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(75) " "Verilog HDL assignment warning at sine.hex(75): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 75 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(76) " "Verilog HDL assignment warning at sine.hex(76): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(77) " "Verilog HDL assignment warning at sine.hex(77): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608818 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(78) " "Verilog HDL assignment warning at sine.hex(78): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(79) " "Verilog HDL assignment warning at sine.hex(79): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 79 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(80) " "Verilog HDL assignment warning at sine.hex(80): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 80 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(81) " "Verilog HDL assignment warning at sine.hex(81): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 81 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(82) " "Verilog HDL assignment warning at sine.hex(82): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(83) " "Verilog HDL assignment warning at sine.hex(83): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(84) " "Verilog HDL assignment warning at sine.hex(84): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 84 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(85) " "Verilog HDL assignment warning at sine.hex(85): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 85 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(86) " "Verilog HDL assignment warning at sine.hex(86): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 86 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(87) " "Verilog HDL assignment warning at sine.hex(87): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 87 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(88) " "Verilog HDL assignment warning at sine.hex(88): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 88 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(89) " "Verilog HDL assignment warning at sine.hex(89): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 89 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(90) " "Verilog HDL assignment warning at sine.hex(90): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(91) " "Verilog HDL assignment warning at sine.hex(91): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 91 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(92) " "Verilog HDL assignment warning at sine.hex(92): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 92 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(93) " "Verilog HDL assignment warning at sine.hex(93): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 93 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(94) " "Verilog HDL assignment warning at sine.hex(94): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 94 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(95) " "Verilog HDL assignment warning at sine.hex(95): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(96) " "Verilog HDL assignment warning at sine.hex(96): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608819 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(97) " "Verilog HDL assignment warning at sine.hex(97): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 97 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(98) " "Verilog HDL assignment warning at sine.hex(98): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(99) " "Verilog HDL assignment warning at sine.hex(99): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(100) " "Verilog HDL assignment warning at sine.hex(100): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 100 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(101) " "Verilog HDL assignment warning at sine.hex(101): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 101 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(102) " "Verilog HDL assignment warning at sine.hex(102): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(103) " "Verilog HDL assignment warning at sine.hex(103): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 103 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(104) " "Verilog HDL assignment warning at sine.hex(104): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(105) " "Verilog HDL assignment warning at sine.hex(105): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 105 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(106) " "Verilog HDL assignment warning at sine.hex(106): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 106 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(107) " "Verilog HDL assignment warning at sine.hex(107): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 107 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(108) " "Verilog HDL assignment warning at sine.hex(108): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 108 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(109) " "Verilog HDL assignment warning at sine.hex(109): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 109 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(110) " "Verilog HDL assignment warning at sine.hex(110): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 110 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(111) " "Verilog HDL assignment warning at sine.hex(111): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 111 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(112) " "Verilog HDL assignment warning at sine.hex(112): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 112 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(113) " "Verilog HDL assignment warning at sine.hex(113): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 113 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(114) " "Verilog HDL assignment warning at sine.hex(114): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 114 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(115) " "Verilog HDL assignment warning at sine.hex(115): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 115 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(116) " "Verilog HDL assignment warning at sine.hex(116): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 116 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(117) " "Verilog HDL assignment warning at sine.hex(117): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 117 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(118) " "Verilog HDL assignment warning at sine.hex(118): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 118 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(119) " "Verilog HDL assignment warning at sine.hex(119): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 119 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(120) " "Verilog HDL assignment warning at sine.hex(120): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 120 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(121) " "Verilog HDL assignment warning at sine.hex(121): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(122) " "Verilog HDL assignment warning at sine.hex(122): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(123) " "Verilog HDL assignment warning at sine.hex(123): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(124) " "Verilog HDL assignment warning at sine.hex(124): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(125) " "Verilog HDL assignment warning at sine.hex(125): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 125 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(126) " "Verilog HDL assignment warning at sine.hex(126): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 126 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608820 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(127) " "Verilog HDL assignment warning at sine.hex(127): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 127 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(128) " "Verilog HDL assignment warning at sine.hex(128): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 128 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(129) " "Verilog HDL assignment warning at sine.hex(129): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 129 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(130) " "Verilog HDL assignment warning at sine.hex(130): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(131) " "Verilog HDL assignment warning at sine.hex(131): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 131 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(132) " "Verilog HDL assignment warning at sine.hex(132): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 132 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(133) " "Verilog HDL assignment warning at sine.hex(133): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 133 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(134) " "Verilog HDL assignment warning at sine.hex(134): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 134 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(135) " "Verilog HDL assignment warning at sine.hex(135): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 135 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(136) " "Verilog HDL assignment warning at sine.hex(136): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 136 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(137) " "Verilog HDL assignment warning at sine.hex(137): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(138) " "Verilog HDL assignment warning at sine.hex(138): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(139) " "Verilog HDL assignment warning at sine.hex(139): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 139 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(140) " "Verilog HDL assignment warning at sine.hex(140): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 140 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(141) " "Verilog HDL assignment warning at sine.hex(141): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 141 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(142) " "Verilog HDL assignment warning at sine.hex(142): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 142 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(143) " "Verilog HDL assignment warning at sine.hex(143): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 143 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(144) " "Verilog HDL assignment warning at sine.hex(144): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 144 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(145) " "Verilog HDL assignment warning at sine.hex(145): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 145 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(146) " "Verilog HDL assignment warning at sine.hex(146): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 146 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(147) " "Verilog HDL assignment warning at sine.hex(147): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 147 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(148) " "Verilog HDL assignment warning at sine.hex(148): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 148 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(149) " "Verilog HDL assignment warning at sine.hex(149): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 149 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(150) " "Verilog HDL assignment warning at sine.hex(150): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 150 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(151) " "Verilog HDL assignment warning at sine.hex(151): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 151 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(152) " "Verilog HDL assignment warning at sine.hex(152): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 152 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(153) " "Verilog HDL assignment warning at sine.hex(153): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 153 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(154) " "Verilog HDL assignment warning at sine.hex(154): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 154 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608821 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(155) " "Verilog HDL assignment warning at sine.hex(155): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 155 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(156) " "Verilog HDL assignment warning at sine.hex(156): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 156 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(157) " "Verilog HDL assignment warning at sine.hex(157): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 157 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(158) " "Verilog HDL assignment warning at sine.hex(158): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 158 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(159) " "Verilog HDL assignment warning at sine.hex(159): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 159 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(160) " "Verilog HDL assignment warning at sine.hex(160): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 160 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(161) " "Verilog HDL assignment warning at sine.hex(161): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(162) " "Verilog HDL assignment warning at sine.hex(162): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 162 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(163) " "Verilog HDL assignment warning at sine.hex(163): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 163 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(164) " "Verilog HDL assignment warning at sine.hex(164): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 164 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(165) " "Verilog HDL assignment warning at sine.hex(165): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(166) " "Verilog HDL assignment warning at sine.hex(166): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(167) " "Verilog HDL assignment warning at sine.hex(167): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 167 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(168) " "Verilog HDL assignment warning at sine.hex(168): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 168 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(169) " "Verilog HDL assignment warning at sine.hex(169): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 169 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(170) " "Verilog HDL assignment warning at sine.hex(170): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 170 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(171) " "Verilog HDL assignment warning at sine.hex(171): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 171 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(172) " "Verilog HDL assignment warning at sine.hex(172): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 172 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(173) " "Verilog HDL assignment warning at sine.hex(173): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 173 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(174) " "Verilog HDL assignment warning at sine.hex(174): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 174 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(175) " "Verilog HDL assignment warning at sine.hex(175): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 175 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(176) " "Verilog HDL assignment warning at sine.hex(176): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 176 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(177) " "Verilog HDL assignment warning at sine.hex(177): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 177 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(178) " "Verilog HDL assignment warning at sine.hex(178): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 178 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(179) " "Verilog HDL assignment warning at sine.hex(179): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 179 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(180) " "Verilog HDL assignment warning at sine.hex(180): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 180 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(181) " "Verilog HDL assignment warning at sine.hex(181): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(182) " "Verilog HDL assignment warning at sine.hex(182): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 182 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608822 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(183) " "Verilog HDL assignment warning at sine.hex(183): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 183 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(184) " "Verilog HDL assignment warning at sine.hex(184): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 184 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(185) " "Verilog HDL assignment warning at sine.hex(185): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 185 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(186) " "Verilog HDL assignment warning at sine.hex(186): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 186 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(187) " "Verilog HDL assignment warning at sine.hex(187): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 187 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(188) " "Verilog HDL assignment warning at sine.hex(188): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(189) " "Verilog HDL assignment warning at sine.hex(189): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 189 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(190) " "Verilog HDL assignment warning at sine.hex(190): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 190 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(191) " "Verilog HDL assignment warning at sine.hex(191): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 191 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(192) " "Verilog HDL assignment warning at sine.hex(192): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 192 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(193) " "Verilog HDL assignment warning at sine.hex(193): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 193 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(194) " "Verilog HDL assignment warning at sine.hex(194): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 194 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(195) " "Verilog HDL assignment warning at sine.hex(195): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 195 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(196) " "Verilog HDL assignment warning at sine.hex(196): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 196 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(197) " "Verilog HDL assignment warning at sine.hex(197): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(198) " "Verilog HDL assignment warning at sine.hex(198): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 198 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(199) " "Verilog HDL assignment warning at sine.hex(199): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 199 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608823 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(200) " "Verilog HDL assignment warning at sine.hex(200): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 200 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(201) " "Verilog HDL assignment warning at sine.hex(201): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 201 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(202) " "Verilog HDL assignment warning at sine.hex(202): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 202 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(203) " "Verilog HDL assignment warning at sine.hex(203): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 203 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(204) " "Verilog HDL assignment warning at sine.hex(204): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 204 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(205) " "Verilog HDL assignment warning at sine.hex(205): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 205 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(206) " "Verilog HDL assignment warning at sine.hex(206): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 206 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(207) " "Verilog HDL assignment warning at sine.hex(207): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 207 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(208) " "Verilog HDL assignment warning at sine.hex(208): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 208 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(209) " "Verilog HDL assignment warning at sine.hex(209): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 209 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(210) " "Verilog HDL assignment warning at sine.hex(210): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 210 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(211) " "Verilog HDL assignment warning at sine.hex(211): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 211 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(212) " "Verilog HDL assignment warning at sine.hex(212): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 212 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(213) " "Verilog HDL assignment warning at sine.hex(213): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 213 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(214) " "Verilog HDL assignment warning at sine.hex(214): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 214 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(215) " "Verilog HDL assignment warning at sine.hex(215): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 215 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(216) " "Verilog HDL assignment warning at sine.hex(216): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 216 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(217) " "Verilog HDL assignment warning at sine.hex(217): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 217 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(218) " "Verilog HDL assignment warning at sine.hex(218): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 218 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(219) " "Verilog HDL assignment warning at sine.hex(219): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 219 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(220) " "Verilog HDL assignment warning at sine.hex(220): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 220 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(221) " "Verilog HDL assignment warning at sine.hex(221): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 221 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(222) " "Verilog HDL assignment warning at sine.hex(222): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 222 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(223) " "Verilog HDL assignment warning at sine.hex(223): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 223 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(224) " "Verilog HDL assignment warning at sine.hex(224): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 224 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(225) " "Verilog HDL assignment warning at sine.hex(225): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 225 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(226) " "Verilog HDL assignment warning at sine.hex(226): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 226 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(227) " "Verilog HDL assignment warning at sine.hex(227): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 227 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(228) " "Verilog HDL assignment warning at sine.hex(228): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 228 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608824 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(229) " "Verilog HDL assignment warning at sine.hex(229): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 229 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(230) " "Verilog HDL assignment warning at sine.hex(230): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 230 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(231) " "Verilog HDL assignment warning at sine.hex(231): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 231 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(232) " "Verilog HDL assignment warning at sine.hex(232): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 232 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(233) " "Verilog HDL assignment warning at sine.hex(233): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 233 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(234) " "Verilog HDL assignment warning at sine.hex(234): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 234 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(235) " "Verilog HDL assignment warning at sine.hex(235): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 235 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(236) " "Verilog HDL assignment warning at sine.hex(236): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 236 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(237) " "Verilog HDL assignment warning at sine.hex(237): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 237 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(238) " "Verilog HDL assignment warning at sine.hex(238): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 238 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(239) " "Verilog HDL assignment warning at sine.hex(239): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 239 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(240) " "Verilog HDL assignment warning at sine.hex(240): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 240 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(241) " "Verilog HDL assignment warning at sine.hex(241): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 241 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(242) " "Verilog HDL assignment warning at sine.hex(242): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 242 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(243) " "Verilog HDL assignment warning at sine.hex(243): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 243 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(244) " "Verilog HDL assignment warning at sine.hex(244): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 244 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(245) " "Verilog HDL assignment warning at sine.hex(245): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 245 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(246) " "Verilog HDL assignment warning at sine.hex(246): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 246 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(247) " "Verilog HDL assignment warning at sine.hex(247): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 247 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(248) " "Verilog HDL assignment warning at sine.hex(248): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 248 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(249) " "Verilog HDL assignment warning at sine.hex(249): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 249 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(250) " "Verilog HDL assignment warning at sine.hex(250): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 250 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(251) " "Verilog HDL assignment warning at sine.hex(251): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 251 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(252) " "Verilog HDL assignment warning at sine.hex(252): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 252 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(253) " "Verilog HDL assignment warning at sine.hex(253): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 253 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(254) " "Verilog HDL assignment warning at sine.hex(254): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 254 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(255) " "Verilog HDL assignment warning at sine.hex(255): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 255 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(256) " "Verilog HDL assignment warning at sine.hex(256): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 256 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(257) " "Verilog HDL assignment warning at sine.hex(257): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 257 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(258) " "Verilog HDL assignment warning at sine.hex(258): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 258 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608825 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(259) " "Verilog HDL assignment warning at sine.hex(259): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 259 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(260) " "Verilog HDL assignment warning at sine.hex(260): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 260 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(261) " "Verilog HDL assignment warning at sine.hex(261): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 261 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(262) " "Verilog HDL assignment warning at sine.hex(262): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 262 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(263) " "Verilog HDL assignment warning at sine.hex(263): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 263 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(264) " "Verilog HDL assignment warning at sine.hex(264): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 264 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(265) " "Verilog HDL assignment warning at sine.hex(265): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 265 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(266) " "Verilog HDL assignment warning at sine.hex(266): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 266 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(267) " "Verilog HDL assignment warning at sine.hex(267): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 267 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(268) " "Verilog HDL assignment warning at sine.hex(268): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 268 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(269) " "Verilog HDL assignment warning at sine.hex(269): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 269 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(270) " "Verilog HDL assignment warning at sine.hex(270): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 270 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(271) " "Verilog HDL assignment warning at sine.hex(271): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 271 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(272) " "Verilog HDL assignment warning at sine.hex(272): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 272 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(273) " "Verilog HDL assignment warning at sine.hex(273): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 273 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(274) " "Verilog HDL assignment warning at sine.hex(274): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 274 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(275) " "Verilog HDL assignment warning at sine.hex(275): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 275 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(276) " "Verilog HDL assignment warning at sine.hex(276): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 276 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(277) " "Verilog HDL assignment warning at sine.hex(277): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 277 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(278) " "Verilog HDL assignment warning at sine.hex(278): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 278 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(279) " "Verilog HDL assignment warning at sine.hex(279): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 279 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(280) " "Verilog HDL assignment warning at sine.hex(280): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 280 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(281) " "Verilog HDL assignment warning at sine.hex(281): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 281 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(282) " "Verilog HDL assignment warning at sine.hex(282): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 282 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(283) " "Verilog HDL assignment warning at sine.hex(283): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 283 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(284) " "Verilog HDL assignment warning at sine.hex(284): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 284 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(285) " "Verilog HDL assignment warning at sine.hex(285): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 285 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(286) " "Verilog HDL assignment warning at sine.hex(286): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 286 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(287) " "Verilog HDL assignment warning at sine.hex(287): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 287 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(288) " "Verilog HDL assignment warning at sine.hex(288): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 288 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(289) " "Verilog HDL assignment warning at sine.hex(289): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 289 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(290) " "Verilog HDL assignment warning at sine.hex(290): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 290 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(291) " "Verilog HDL assignment warning at sine.hex(291): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 291 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(292) " "Verilog HDL assignment warning at sine.hex(292): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 292 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(293) " "Verilog HDL assignment warning at sine.hex(293): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 293 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(294) " "Verilog HDL assignment warning at sine.hex(294): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 294 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(295) " "Verilog HDL assignment warning at sine.hex(295): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 295 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(296) " "Verilog HDL assignment warning at sine.hex(296): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 296 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(297) " "Verilog HDL assignment warning at sine.hex(297): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 297 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(298) " "Verilog HDL assignment warning at sine.hex(298): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 298 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(299) " "Verilog HDL assignment warning at sine.hex(299): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 299 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(300) " "Verilog HDL assignment warning at sine.hex(300): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 300 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(301) " "Verilog HDL assignment warning at sine.hex(301): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 301 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(302) " "Verilog HDL assignment warning at sine.hex(302): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 302 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(303) " "Verilog HDL assignment warning at sine.hex(303): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 303 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608826 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(304) " "Verilog HDL assignment warning at sine.hex(304): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 304 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(305) " "Verilog HDL assignment warning at sine.hex(305): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 305 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(306) " "Verilog HDL assignment warning at sine.hex(306): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 306 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(307) " "Verilog HDL assignment warning at sine.hex(307): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 307 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(308) " "Verilog HDL assignment warning at sine.hex(308): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 308 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(309) " "Verilog HDL assignment warning at sine.hex(309): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 309 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(310) " "Verilog HDL assignment warning at sine.hex(310): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 310 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(311) " "Verilog HDL assignment warning at sine.hex(311): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 311 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(312) " "Verilog HDL assignment warning at sine.hex(312): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 312 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(313) " "Verilog HDL assignment warning at sine.hex(313): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 313 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(314) " "Verilog HDL assignment warning at sine.hex(314): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 314 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(315) " "Verilog HDL assignment warning at sine.hex(315): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 315 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(316) " "Verilog HDL assignment warning at sine.hex(316): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 316 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(317) " "Verilog HDL assignment warning at sine.hex(317): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 317 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(318) " "Verilog HDL assignment warning at sine.hex(318): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 318 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(319) " "Verilog HDL assignment warning at sine.hex(319): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 319 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(320) " "Verilog HDL assignment warning at sine.hex(320): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 320 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(321) " "Verilog HDL assignment warning at sine.hex(321): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 321 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(322) " "Verilog HDL assignment warning at sine.hex(322): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 322 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(323) " "Verilog HDL assignment warning at sine.hex(323): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 323 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(324) " "Verilog HDL assignment warning at sine.hex(324): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 324 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(325) " "Verilog HDL assignment warning at sine.hex(325): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 325 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(326) " "Verilog HDL assignment warning at sine.hex(326): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 326 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(327) " "Verilog HDL assignment warning at sine.hex(327): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 327 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(328) " "Verilog HDL assignment warning at sine.hex(328): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 328 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(329) " "Verilog HDL assignment warning at sine.hex(329): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 329 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(330) " "Verilog HDL assignment warning at sine.hex(330): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 330 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(331) " "Verilog HDL assignment warning at sine.hex(331): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 331 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(332) " "Verilog HDL assignment warning at sine.hex(332): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 332 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(333) " "Verilog HDL assignment warning at sine.hex(333): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 333 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(334) " "Verilog HDL assignment warning at sine.hex(334): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 334 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(335) " "Verilog HDL assignment warning at sine.hex(335): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 335 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(336) " "Verilog HDL assignment warning at sine.hex(336): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 336 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(337) " "Verilog HDL assignment warning at sine.hex(337): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 337 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608828 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(338) " "Verilog HDL assignment warning at sine.hex(338): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 338 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(339) " "Verilog HDL assignment warning at sine.hex(339): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 339 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(340) " "Verilog HDL assignment warning at sine.hex(340): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 340 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(341) " "Verilog HDL assignment warning at sine.hex(341): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 341 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(342) " "Verilog HDL assignment warning at sine.hex(342): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 342 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(343) " "Verilog HDL assignment warning at sine.hex(343): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 343 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(344) " "Verilog HDL assignment warning at sine.hex(344): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 344 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(345) " "Verilog HDL assignment warning at sine.hex(345): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 345 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(346) " "Verilog HDL assignment warning at sine.hex(346): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 346 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(347) " "Verilog HDL assignment warning at sine.hex(347): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 347 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(348) " "Verilog HDL assignment warning at sine.hex(348): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 348 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(349) " "Verilog HDL assignment warning at sine.hex(349): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 349 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(350) " "Verilog HDL assignment warning at sine.hex(350): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 350 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(351) " "Verilog HDL assignment warning at sine.hex(351): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 351 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(352) " "Verilog HDL assignment warning at sine.hex(352): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 352 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(353) " "Verilog HDL assignment warning at sine.hex(353): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 353 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(354) " "Verilog HDL assignment warning at sine.hex(354): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 354 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(355) " "Verilog HDL assignment warning at sine.hex(355): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 355 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(356) " "Verilog HDL assignment warning at sine.hex(356): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 356 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(357) " "Verilog HDL assignment warning at sine.hex(357): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 357 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(358) " "Verilog HDL assignment warning at sine.hex(358): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 358 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(359) " "Verilog HDL assignment warning at sine.hex(359): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 359 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(360) " "Verilog HDL assignment warning at sine.hex(360): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 360 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(361) " "Verilog HDL assignment warning at sine.hex(361): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 361 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(362) " "Verilog HDL assignment warning at sine.hex(362): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 362 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(363) " "Verilog HDL assignment warning at sine.hex(363): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 363 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(364) " "Verilog HDL assignment warning at sine.hex(364): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 364 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(365) " "Verilog HDL assignment warning at sine.hex(365): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 365 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(366) " "Verilog HDL assignment warning at sine.hex(366): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 366 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(367) " "Verilog HDL assignment warning at sine.hex(367): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 367 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(368) " "Verilog HDL assignment warning at sine.hex(368): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 368 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(369) " "Verilog HDL assignment warning at sine.hex(369): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 369 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608829 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(370) " "Verilog HDL assignment warning at sine.hex(370): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 370 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(371) " "Verilog HDL assignment warning at sine.hex(371): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 371 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(372) " "Verilog HDL assignment warning at sine.hex(372): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 372 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(373) " "Verilog HDL assignment warning at sine.hex(373): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 373 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(374) " "Verilog HDL assignment warning at sine.hex(374): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 374 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(375) " "Verilog HDL assignment warning at sine.hex(375): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 375 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(376) " "Verilog HDL assignment warning at sine.hex(376): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 376 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(377) " "Verilog HDL assignment warning at sine.hex(377): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 377 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(378) " "Verilog HDL assignment warning at sine.hex(378): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 378 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608830 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(379) " "Verilog HDL assignment warning at sine.hex(379): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 379 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(380) " "Verilog HDL assignment warning at sine.hex(380): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 380 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(381) " "Verilog HDL assignment warning at sine.hex(381): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 381 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(382) " "Verilog HDL assignment warning at sine.hex(382): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 382 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(383) " "Verilog HDL assignment warning at sine.hex(383): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 383 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(384) " "Verilog HDL assignment warning at sine.hex(384): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 384 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(385) " "Verilog HDL assignment warning at sine.hex(385): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 385 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(386) " "Verilog HDL assignment warning at sine.hex(386): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 386 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(387) " "Verilog HDL assignment warning at sine.hex(387): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 387 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(388) " "Verilog HDL assignment warning at sine.hex(388): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 388 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(389) " "Verilog HDL assignment warning at sine.hex(389): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 389 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(390) " "Verilog HDL assignment warning at sine.hex(390): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 390 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608831 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(391) " "Verilog HDL assignment warning at sine.hex(391): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 391 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(392) " "Verilog HDL assignment warning at sine.hex(392): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 392 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(393) " "Verilog HDL assignment warning at sine.hex(393): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 393 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(394) " "Verilog HDL assignment warning at sine.hex(394): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 394 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(395) " "Verilog HDL assignment warning at sine.hex(395): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 395 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(396) " "Verilog HDL assignment warning at sine.hex(396): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 396 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(397) " "Verilog HDL assignment warning at sine.hex(397): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 397 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(398) " "Verilog HDL assignment warning at sine.hex(398): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 398 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(399) " "Verilog HDL assignment warning at sine.hex(399): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 399 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(400) " "Verilog HDL assignment warning at sine.hex(400): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 400 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(401) " "Verilog HDL assignment warning at sine.hex(401): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 401 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(402) " "Verilog HDL assignment warning at sine.hex(402): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 402 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(403) " "Verilog HDL assignment warning at sine.hex(403): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 403 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(404) " "Verilog HDL assignment warning at sine.hex(404): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 404 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(405) " "Verilog HDL assignment warning at sine.hex(405): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 405 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(406) " "Verilog HDL assignment warning at sine.hex(406): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 406 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(407) " "Verilog HDL assignment warning at sine.hex(407): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 407 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(408) " "Verilog HDL assignment warning at sine.hex(408): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 408 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(409) " "Verilog HDL assignment warning at sine.hex(409): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 409 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(410) " "Verilog HDL assignment warning at sine.hex(410): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 410 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(411) " "Verilog HDL assignment warning at sine.hex(411): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 411 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(412) " "Verilog HDL assignment warning at sine.hex(412): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 412 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(413) " "Verilog HDL assignment warning at sine.hex(413): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 413 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(414) " "Verilog HDL assignment warning at sine.hex(414): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 414 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(415) " "Verilog HDL assignment warning at sine.hex(415): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 415 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(416) " "Verilog HDL assignment warning at sine.hex(416): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 416 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(417) " "Verilog HDL assignment warning at sine.hex(417): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 417 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608832 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(418) " "Verilog HDL assignment warning at sine.hex(418): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 418 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(419) " "Verilog HDL assignment warning at sine.hex(419): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 419 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(420) " "Verilog HDL assignment warning at sine.hex(420): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 420 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(421) " "Verilog HDL assignment warning at sine.hex(421): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 421 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(422) " "Verilog HDL assignment warning at sine.hex(422): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 422 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(423) " "Verilog HDL assignment warning at sine.hex(423): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 423 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(424) " "Verilog HDL assignment warning at sine.hex(424): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 424 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(425) " "Verilog HDL assignment warning at sine.hex(425): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 425 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(426) " "Verilog HDL assignment warning at sine.hex(426): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 426 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608833 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(427) " "Verilog HDL assignment warning at sine.hex(427): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 427 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(428) " "Verilog HDL assignment warning at sine.hex(428): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 428 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(429) " "Verilog HDL assignment warning at sine.hex(429): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 429 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(430) " "Verilog HDL assignment warning at sine.hex(430): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 430 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(431) " "Verilog HDL assignment warning at sine.hex(431): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 431 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(432) " "Verilog HDL assignment warning at sine.hex(432): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 432 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(433) " "Verilog HDL assignment warning at sine.hex(433): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 433 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(434) " "Verilog HDL assignment warning at sine.hex(434): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 434 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(435) " "Verilog HDL assignment warning at sine.hex(435): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 435 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(436) " "Verilog HDL assignment warning at sine.hex(436): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 436 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(437) " "Verilog HDL assignment warning at sine.hex(437): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 437 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(438) " "Verilog HDL assignment warning at sine.hex(438): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 438 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(439) " "Verilog HDL assignment warning at sine.hex(439): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 439 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(440) " "Verilog HDL assignment warning at sine.hex(440): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 440 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(441) " "Verilog HDL assignment warning at sine.hex(441): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 441 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608834 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(442) " "Verilog HDL assignment warning at sine.hex(442): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 442 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(443) " "Verilog HDL assignment warning at sine.hex(443): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 443 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(444) " "Verilog HDL assignment warning at sine.hex(444): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 444 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(445) " "Verilog HDL assignment warning at sine.hex(445): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 445 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(446) " "Verilog HDL assignment warning at sine.hex(446): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 446 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(447) " "Verilog HDL assignment warning at sine.hex(447): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 447 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(448) " "Verilog HDL assignment warning at sine.hex(448): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 448 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(449) " "Verilog HDL assignment warning at sine.hex(449): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 449 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(450) " "Verilog HDL assignment warning at sine.hex(450): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 450 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(451) " "Verilog HDL assignment warning at sine.hex(451): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 451 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(452) " "Verilog HDL assignment warning at sine.hex(452): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 452 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(453) " "Verilog HDL assignment warning at sine.hex(453): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 453 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(454) " "Verilog HDL assignment warning at sine.hex(454): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 454 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(455) " "Verilog HDL assignment warning at sine.hex(455): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 455 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(456) " "Verilog HDL assignment warning at sine.hex(456): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 456 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608835 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(457) " "Verilog HDL assignment warning at sine.hex(457): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 457 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(458) " "Verilog HDL assignment warning at sine.hex(458): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 458 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(459) " "Verilog HDL assignment warning at sine.hex(459): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 459 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(460) " "Verilog HDL assignment warning at sine.hex(460): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 460 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(461) " "Verilog HDL assignment warning at sine.hex(461): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 461 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(462) " "Verilog HDL assignment warning at sine.hex(462): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 462 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(463) " "Verilog HDL assignment warning at sine.hex(463): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 463 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(464) " "Verilog HDL assignment warning at sine.hex(464): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 464 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(465) " "Verilog HDL assignment warning at sine.hex(465): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 465 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(466) " "Verilog HDL assignment warning at sine.hex(466): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 466 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(467) " "Verilog HDL assignment warning at sine.hex(467): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 467 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(468) " "Verilog HDL assignment warning at sine.hex(468): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 468 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(469) " "Verilog HDL assignment warning at sine.hex(469): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 469 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(470) " "Verilog HDL assignment warning at sine.hex(470): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 470 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(471) " "Verilog HDL assignment warning at sine.hex(471): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 471 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(472) " "Verilog HDL assignment warning at sine.hex(472): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 472 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(473) " "Verilog HDL assignment warning at sine.hex(473): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 473 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(474) " "Verilog HDL assignment warning at sine.hex(474): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 474 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(475) " "Verilog HDL assignment warning at sine.hex(475): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 475 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(476) " "Verilog HDL assignment warning at sine.hex(476): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 476 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(477) " "Verilog HDL assignment warning at sine.hex(477): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 477 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(478) " "Verilog HDL assignment warning at sine.hex(478): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 478 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(479) " "Verilog HDL assignment warning at sine.hex(479): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 479 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(480) " "Verilog HDL assignment warning at sine.hex(480): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 480 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608836 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(481) " "Verilog HDL assignment warning at sine.hex(481): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 481 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(482) " "Verilog HDL assignment warning at sine.hex(482): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 482 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(483) " "Verilog HDL assignment warning at sine.hex(483): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 483 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(484) " "Verilog HDL assignment warning at sine.hex(484): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 484 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(485) " "Verilog HDL assignment warning at sine.hex(485): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 485 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(486) " "Verilog HDL assignment warning at sine.hex(486): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 486 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(487) " "Verilog HDL assignment warning at sine.hex(487): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 487 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(488) " "Verilog HDL assignment warning at sine.hex(488): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 488 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(489) " "Verilog HDL assignment warning at sine.hex(489): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 489 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(490) " "Verilog HDL assignment warning at sine.hex(490): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 490 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(491) " "Verilog HDL assignment warning at sine.hex(491): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 491 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(492) " "Verilog HDL assignment warning at sine.hex(492): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 492 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(493) " "Verilog HDL assignment warning at sine.hex(493): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 493 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(494) " "Verilog HDL assignment warning at sine.hex(494): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 494 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(495) " "Verilog HDL assignment warning at sine.hex(495): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 495 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(496) " "Verilog HDL assignment warning at sine.hex(496): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 496 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(497) " "Verilog HDL assignment warning at sine.hex(497): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 497 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(498) " "Verilog HDL assignment warning at sine.hex(498): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 498 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(499) " "Verilog HDL assignment warning at sine.hex(499): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 499 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(500) " "Verilog HDL assignment warning at sine.hex(500): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 500 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(501) " "Verilog HDL assignment warning at sine.hex(501): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 501 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(502) " "Verilog HDL assignment warning at sine.hex(502): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 502 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(503) " "Verilog HDL assignment warning at sine.hex(503): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 503 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(504) " "Verilog HDL assignment warning at sine.hex(504): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 504 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(505) " "Verilog HDL assignment warning at sine.hex(505): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 505 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(506) " "Verilog HDL assignment warning at sine.hex(506): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 506 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608838 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(507) " "Verilog HDL assignment warning at sine.hex(507): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 507 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(508) " "Verilog HDL assignment warning at sine.hex(508): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 508 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(509) " "Verilog HDL assignment warning at sine.hex(509): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 509 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(510) " "Verilog HDL assignment warning at sine.hex(510): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 510 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(511) " "Verilog HDL assignment warning at sine.hex(511): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 511 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(512) " "Verilog HDL assignment warning at sine.hex(512): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 512 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(513) " "Verilog HDL assignment warning at sine.hex(513): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 513 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(514) " "Verilog HDL assignment warning at sine.hex(514): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 514 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(515) " "Verilog HDL assignment warning at sine.hex(515): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 515 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(516) " "Verilog HDL assignment warning at sine.hex(516): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 516 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(517) " "Verilog HDL assignment warning at sine.hex(517): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 517 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(518) " "Verilog HDL assignment warning at sine.hex(518): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 518 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(519) " "Verilog HDL assignment warning at sine.hex(519): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 519 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(520) " "Verilog HDL assignment warning at sine.hex(520): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 520 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(521) " "Verilog HDL assignment warning at sine.hex(521): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 521 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(522) " "Verilog HDL assignment warning at sine.hex(522): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 522 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(523) " "Verilog HDL assignment warning at sine.hex(523): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 523 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(524) " "Verilog HDL assignment warning at sine.hex(524): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 524 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(525) " "Verilog HDL assignment warning at sine.hex(525): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 525 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(526) " "Verilog HDL assignment warning at sine.hex(526): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 526 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(527) " "Verilog HDL assignment warning at sine.hex(527): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 527 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(528) " "Verilog HDL assignment warning at sine.hex(528): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 528 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(529) " "Verilog HDL assignment warning at sine.hex(529): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 529 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(530) " "Verilog HDL assignment warning at sine.hex(530): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 530 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(531) " "Verilog HDL assignment warning at sine.hex(531): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 531 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(532) " "Verilog HDL assignment warning at sine.hex(532): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 532 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(533) " "Verilog HDL assignment warning at sine.hex(533): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 533 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608839 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(534) " "Verilog HDL assignment warning at sine.hex(534): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 534 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(535) " "Verilog HDL assignment warning at sine.hex(535): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 535 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(536) " "Verilog HDL assignment warning at sine.hex(536): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 536 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(537) " "Verilog HDL assignment warning at sine.hex(537): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 537 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(538) " "Verilog HDL assignment warning at sine.hex(538): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 538 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(539) " "Verilog HDL assignment warning at sine.hex(539): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 539 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(540) " "Verilog HDL assignment warning at sine.hex(540): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 540 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(541) " "Verilog HDL assignment warning at sine.hex(541): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 541 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(542) " "Verilog HDL assignment warning at sine.hex(542): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 542 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(543) " "Verilog HDL assignment warning at sine.hex(543): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 543 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(544) " "Verilog HDL assignment warning at sine.hex(544): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 544 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(545) " "Verilog HDL assignment warning at sine.hex(545): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 545 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(546) " "Verilog HDL assignment warning at sine.hex(546): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 546 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(547) " "Verilog HDL assignment warning at sine.hex(547): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 547 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(548) " "Verilog HDL assignment warning at sine.hex(548): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 548 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(549) " "Verilog HDL assignment warning at sine.hex(549): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 549 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(550) " "Verilog HDL assignment warning at sine.hex(550): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 550 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(551) " "Verilog HDL assignment warning at sine.hex(551): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 551 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(552) " "Verilog HDL assignment warning at sine.hex(552): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 552 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(553) " "Verilog HDL assignment warning at sine.hex(553): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 553 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(554) " "Verilog HDL assignment warning at sine.hex(554): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 554 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(555) " "Verilog HDL assignment warning at sine.hex(555): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 555 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(556) " "Verilog HDL assignment warning at sine.hex(556): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 556 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(557) " "Verilog HDL assignment warning at sine.hex(557): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 557 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(558) " "Verilog HDL assignment warning at sine.hex(558): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 558 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(559) " "Verilog HDL assignment warning at sine.hex(559): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 559 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(560) " "Verilog HDL assignment warning at sine.hex(560): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 560 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(561) " "Verilog HDL assignment warning at sine.hex(561): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 561 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(562) " "Verilog HDL assignment warning at sine.hex(562): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 562 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(563) " "Verilog HDL assignment warning at sine.hex(563): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 563 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(564) " "Verilog HDL assignment warning at sine.hex(564): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 564 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(565) " "Verilog HDL assignment warning at sine.hex(565): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 565 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(566) " "Verilog HDL assignment warning at sine.hex(566): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 566 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(567) " "Verilog HDL assignment warning at sine.hex(567): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 567 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(568) " "Verilog HDL assignment warning at sine.hex(568): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 568 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(569) " "Verilog HDL assignment warning at sine.hex(569): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 569 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(570) " "Verilog HDL assignment warning at sine.hex(570): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 570 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(571) " "Verilog HDL assignment warning at sine.hex(571): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 571 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(572) " "Verilog HDL assignment warning at sine.hex(572): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 572 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(573) " "Verilog HDL assignment warning at sine.hex(573): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 573 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608840 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(574) " "Verilog HDL assignment warning at sine.hex(574): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 574 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(575) " "Verilog HDL assignment warning at sine.hex(575): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 575 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(576) " "Verilog HDL assignment warning at sine.hex(576): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 576 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(577) " "Verilog HDL assignment warning at sine.hex(577): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 577 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(578) " "Verilog HDL assignment warning at sine.hex(578): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 578 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(579) " "Verilog HDL assignment warning at sine.hex(579): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 579 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(580) " "Verilog HDL assignment warning at sine.hex(580): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 580 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(581) " "Verilog HDL assignment warning at sine.hex(581): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 581 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(582) " "Verilog HDL assignment warning at sine.hex(582): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 582 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(583) " "Verilog HDL assignment warning at sine.hex(583): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 583 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(584) " "Verilog HDL assignment warning at sine.hex(584): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 584 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(585) " "Verilog HDL assignment warning at sine.hex(585): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 585 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(586) " "Verilog HDL assignment warning at sine.hex(586): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 586 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(587) " "Verilog HDL assignment warning at sine.hex(587): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 587 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(588) " "Verilog HDL assignment warning at sine.hex(588): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 588 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(589) " "Verilog HDL assignment warning at sine.hex(589): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 589 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(590) " "Verilog HDL assignment warning at sine.hex(590): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 590 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(591) " "Verilog HDL assignment warning at sine.hex(591): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 591 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(592) " "Verilog HDL assignment warning at sine.hex(592): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 592 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(593) " "Verilog HDL assignment warning at sine.hex(593): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 593 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(594) " "Verilog HDL assignment warning at sine.hex(594): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 594 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(595) " "Verilog HDL assignment warning at sine.hex(595): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 595 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(596) " "Verilog HDL assignment warning at sine.hex(596): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 596 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(597) " "Verilog HDL assignment warning at sine.hex(597): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 597 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(598) " "Verilog HDL assignment warning at sine.hex(598): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 598 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(599) " "Verilog HDL assignment warning at sine.hex(599): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 599 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(600) " "Verilog HDL assignment warning at sine.hex(600): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 600 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(601) " "Verilog HDL assignment warning at sine.hex(601): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 601 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608841 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(602) " "Verilog HDL assignment warning at sine.hex(602): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 602 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(603) " "Verilog HDL assignment warning at sine.hex(603): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 603 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(604) " "Verilog HDL assignment warning at sine.hex(604): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 604 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(605) " "Verilog HDL assignment warning at sine.hex(605): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 605 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(606) " "Verilog HDL assignment warning at sine.hex(606): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 606 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(607) " "Verilog HDL assignment warning at sine.hex(607): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 607 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(608) " "Verilog HDL assignment warning at sine.hex(608): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 608 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(609) " "Verilog HDL assignment warning at sine.hex(609): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 609 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(610) " "Verilog HDL assignment warning at sine.hex(610): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 610 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(611) " "Verilog HDL assignment warning at sine.hex(611): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 611 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(612) " "Verilog HDL assignment warning at sine.hex(612): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 612 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(613) " "Verilog HDL assignment warning at sine.hex(613): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 613 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(614) " "Verilog HDL assignment warning at sine.hex(614): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 614 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(615) " "Verilog HDL assignment warning at sine.hex(615): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 615 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(616) " "Verilog HDL assignment warning at sine.hex(616): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 616 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(617) " "Verilog HDL assignment warning at sine.hex(617): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 617 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(618) " "Verilog HDL assignment warning at sine.hex(618): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 618 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(619) " "Verilog HDL assignment warning at sine.hex(619): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 619 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(620) " "Verilog HDL assignment warning at sine.hex(620): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 620 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(621) " "Verilog HDL assignment warning at sine.hex(621): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 621 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(622) " "Verilog HDL assignment warning at sine.hex(622): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 622 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(623) " "Verilog HDL assignment warning at sine.hex(623): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 623 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(624) " "Verilog HDL assignment warning at sine.hex(624): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 624 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(625) " "Verilog HDL assignment warning at sine.hex(625): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 625 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(626) " "Verilog HDL assignment warning at sine.hex(626): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 626 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(627) " "Verilog HDL assignment warning at sine.hex(627): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 627 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(628) " "Verilog HDL assignment warning at sine.hex(628): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 628 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(629) " "Verilog HDL assignment warning at sine.hex(629): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 629 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(630) " "Verilog HDL assignment warning at sine.hex(630): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 630 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(631) " "Verilog HDL assignment warning at sine.hex(631): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 631 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(632) " "Verilog HDL assignment warning at sine.hex(632): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 632 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(633) " "Verilog HDL assignment warning at sine.hex(633): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 633 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(634) " "Verilog HDL assignment warning at sine.hex(634): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 634 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(635) " "Verilog HDL assignment warning at sine.hex(635): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 635 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(636) " "Verilog HDL assignment warning at sine.hex(636): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 636 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(637) " "Verilog HDL assignment warning at sine.hex(637): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 637 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(638) " "Verilog HDL assignment warning at sine.hex(638): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 638 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(639) " "Verilog HDL assignment warning at sine.hex(639): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 639 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(640) " "Verilog HDL assignment warning at sine.hex(640): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 640 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(641) " "Verilog HDL assignment warning at sine.hex(641): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 641 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(642) " "Verilog HDL assignment warning at sine.hex(642): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 642 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(643) " "Verilog HDL assignment warning at sine.hex(643): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 643 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(644) " "Verilog HDL assignment warning at sine.hex(644): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 644 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608842 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(645) " "Verilog HDL assignment warning at sine.hex(645): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 645 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(646) " "Verilog HDL assignment warning at sine.hex(646): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 646 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(647) " "Verilog HDL assignment warning at sine.hex(647): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 647 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(648) " "Verilog HDL assignment warning at sine.hex(648): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 648 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(649) " "Verilog HDL assignment warning at sine.hex(649): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 649 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(650) " "Verilog HDL assignment warning at sine.hex(650): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 650 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(651) " "Verilog HDL assignment warning at sine.hex(651): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 651 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(652) " "Verilog HDL assignment warning at sine.hex(652): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 652 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(653) " "Verilog HDL assignment warning at sine.hex(653): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 653 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(654) " "Verilog HDL assignment warning at sine.hex(654): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 654 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(655) " "Verilog HDL assignment warning at sine.hex(655): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 655 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(656) " "Verilog HDL assignment warning at sine.hex(656): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 656 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(657) " "Verilog HDL assignment warning at sine.hex(657): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 657 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(658) " "Verilog HDL assignment warning at sine.hex(658): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 658 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(659) " "Verilog HDL assignment warning at sine.hex(659): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 659 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(660) " "Verilog HDL assignment warning at sine.hex(660): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 660 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(661) " "Verilog HDL assignment warning at sine.hex(661): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 661 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(662) " "Verilog HDL assignment warning at sine.hex(662): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 662 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(663) " "Verilog HDL assignment warning at sine.hex(663): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 663 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(664) " "Verilog HDL assignment warning at sine.hex(664): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 664 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(665) " "Verilog HDL assignment warning at sine.hex(665): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 665 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(666) " "Verilog HDL assignment warning at sine.hex(666): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 666 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(667) " "Verilog HDL assignment warning at sine.hex(667): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 667 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(668) " "Verilog HDL assignment warning at sine.hex(668): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 668 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(669) " "Verilog HDL assignment warning at sine.hex(669): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 669 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(670) " "Verilog HDL assignment warning at sine.hex(670): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 670 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(671) " "Verilog HDL assignment warning at sine.hex(671): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 671 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(672) " "Verilog HDL assignment warning at sine.hex(672): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 672 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(673) " "Verilog HDL assignment warning at sine.hex(673): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 673 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(674) " "Verilog HDL assignment warning at sine.hex(674): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 674 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(675) " "Verilog HDL assignment warning at sine.hex(675): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 675 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(676) " "Verilog HDL assignment warning at sine.hex(676): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 676 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(677) " "Verilog HDL assignment warning at sine.hex(677): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 677 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(678) " "Verilog HDL assignment warning at sine.hex(678): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 678 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(679) " "Verilog HDL assignment warning at sine.hex(679): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 679 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(680) " "Verilog HDL assignment warning at sine.hex(680): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 680 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(681) " "Verilog HDL assignment warning at sine.hex(681): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 681 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(682) " "Verilog HDL assignment warning at sine.hex(682): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 682 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(683) " "Verilog HDL assignment warning at sine.hex(683): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 683 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(684) " "Verilog HDL assignment warning at sine.hex(684): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 684 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(685) " "Verilog HDL assignment warning at sine.hex(685): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 685 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(686) " "Verilog HDL assignment warning at sine.hex(686): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 686 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608844 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(687) " "Verilog HDL assignment warning at sine.hex(687): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 687 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(688) " "Verilog HDL assignment warning at sine.hex(688): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 688 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(689) " "Verilog HDL assignment warning at sine.hex(689): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 689 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(690) " "Verilog HDL assignment warning at sine.hex(690): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 690 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(691) " "Verilog HDL assignment warning at sine.hex(691): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 691 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(692) " "Verilog HDL assignment warning at sine.hex(692): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 692 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(693) " "Verilog HDL assignment warning at sine.hex(693): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 693 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(694) " "Verilog HDL assignment warning at sine.hex(694): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 694 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(695) " "Verilog HDL assignment warning at sine.hex(695): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 695 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(696) " "Verilog HDL assignment warning at sine.hex(696): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 696 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(697) " "Verilog HDL assignment warning at sine.hex(697): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 697 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(698) " "Verilog HDL assignment warning at sine.hex(698): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 698 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(699) " "Verilog HDL assignment warning at sine.hex(699): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 699 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(700) " "Verilog HDL assignment warning at sine.hex(700): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 700 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(701) " "Verilog HDL assignment warning at sine.hex(701): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 701 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(702) " "Verilog HDL assignment warning at sine.hex(702): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 702 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(703) " "Verilog HDL assignment warning at sine.hex(703): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 703 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(704) " "Verilog HDL assignment warning at sine.hex(704): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 704 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(705) " "Verilog HDL assignment warning at sine.hex(705): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 705 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(706) " "Verilog HDL assignment warning at sine.hex(706): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 706 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(707) " "Verilog HDL assignment warning at sine.hex(707): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 707 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(708) " "Verilog HDL assignment warning at sine.hex(708): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 708 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(709) " "Verilog HDL assignment warning at sine.hex(709): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 709 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(710) " "Verilog HDL assignment warning at sine.hex(710): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 710 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(711) " "Verilog HDL assignment warning at sine.hex(711): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 711 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(712) " "Verilog HDL assignment warning at sine.hex(712): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 712 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(713) " "Verilog HDL assignment warning at sine.hex(713): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 713 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(714) " "Verilog HDL assignment warning at sine.hex(714): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 714 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(715) " "Verilog HDL assignment warning at sine.hex(715): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 715 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608845 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(716) " "Verilog HDL assignment warning at sine.hex(716): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 716 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(717) " "Verilog HDL assignment warning at sine.hex(717): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 717 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(718) " "Verilog HDL assignment warning at sine.hex(718): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 718 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(719) " "Verilog HDL assignment warning at sine.hex(719): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 719 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(720) " "Verilog HDL assignment warning at sine.hex(720): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 720 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(721) " "Verilog HDL assignment warning at sine.hex(721): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 721 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(722) " "Verilog HDL assignment warning at sine.hex(722): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 722 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(723) " "Verilog HDL assignment warning at sine.hex(723): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 723 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(724) " "Verilog HDL assignment warning at sine.hex(724): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 724 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(725) " "Verilog HDL assignment warning at sine.hex(725): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 725 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608846 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(726) " "Verilog HDL assignment warning at sine.hex(726): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 726 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(727) " "Verilog HDL assignment warning at sine.hex(727): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 727 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(728) " "Verilog HDL assignment warning at sine.hex(728): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 728 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(729) " "Verilog HDL assignment warning at sine.hex(729): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 729 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(730) " "Verilog HDL assignment warning at sine.hex(730): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 730 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(731) " "Verilog HDL assignment warning at sine.hex(731): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 731 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(732) " "Verilog HDL assignment warning at sine.hex(732): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 732 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(733) " "Verilog HDL assignment warning at sine.hex(733): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 733 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(734) " "Verilog HDL assignment warning at sine.hex(734): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 734 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(735) " "Verilog HDL assignment warning at sine.hex(735): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 735 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(736) " "Verilog HDL assignment warning at sine.hex(736): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 736 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(737) " "Verilog HDL assignment warning at sine.hex(737): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 737 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(738) " "Verilog HDL assignment warning at sine.hex(738): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 738 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(739) " "Verilog HDL assignment warning at sine.hex(739): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 739 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(740) " "Verilog HDL assignment warning at sine.hex(740): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 740 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(741) " "Verilog HDL assignment warning at sine.hex(741): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 741 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(742) " "Verilog HDL assignment warning at sine.hex(742): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 742 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(743) " "Verilog HDL assignment warning at sine.hex(743): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 743 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(744) " "Verilog HDL assignment warning at sine.hex(744): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 744 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(745) " "Verilog HDL assignment warning at sine.hex(745): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 745 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(746) " "Verilog HDL assignment warning at sine.hex(746): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 746 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(747) " "Verilog HDL assignment warning at sine.hex(747): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 747 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(748) " "Verilog HDL assignment warning at sine.hex(748): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 748 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(749) " "Verilog HDL assignment warning at sine.hex(749): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 749 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(750) " "Verilog HDL assignment warning at sine.hex(750): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 750 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(751) " "Verilog HDL assignment warning at sine.hex(751): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 751 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(752) " "Verilog HDL assignment warning at sine.hex(752): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 752 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(753) " "Verilog HDL assignment warning at sine.hex(753): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 753 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(754) " "Verilog HDL assignment warning at sine.hex(754): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 754 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(755) " "Verilog HDL assignment warning at sine.hex(755): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 755 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(756) " "Verilog HDL assignment warning at sine.hex(756): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 756 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(757) " "Verilog HDL assignment warning at sine.hex(757): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 757 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(758) " "Verilog HDL assignment warning at sine.hex(758): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 758 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(759) " "Verilog HDL assignment warning at sine.hex(759): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 759 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(760) " "Verilog HDL assignment warning at sine.hex(760): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 760 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(761) " "Verilog HDL assignment warning at sine.hex(761): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 761 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(762) " "Verilog HDL assignment warning at sine.hex(762): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 762 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(763) " "Verilog HDL assignment warning at sine.hex(763): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 763 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(764) " "Verilog HDL assignment warning at sine.hex(764): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 764 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(765) " "Verilog HDL assignment warning at sine.hex(765): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 765 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608847 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(766) " "Verilog HDL assignment warning at sine.hex(766): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 766 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(767) " "Verilog HDL assignment warning at sine.hex(767): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 767 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(768) " "Verilog HDL assignment warning at sine.hex(768): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 768 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(769) " "Verilog HDL assignment warning at sine.hex(769): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 769 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(770) " "Verilog HDL assignment warning at sine.hex(770): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 770 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(771) " "Verilog HDL assignment warning at sine.hex(771): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 771 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(772) " "Verilog HDL assignment warning at sine.hex(772): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 772 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(773) " "Verilog HDL assignment warning at sine.hex(773): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 773 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(774) " "Verilog HDL assignment warning at sine.hex(774): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 774 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(775) " "Verilog HDL assignment warning at sine.hex(775): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 775 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(776) " "Verilog HDL assignment warning at sine.hex(776): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 776 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(777) " "Verilog HDL assignment warning at sine.hex(777): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 777 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(778) " "Verilog HDL assignment warning at sine.hex(778): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 778 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(779) " "Verilog HDL assignment warning at sine.hex(779): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 779 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(780) " "Verilog HDL assignment warning at sine.hex(780): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 780 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(781) " "Verilog HDL assignment warning at sine.hex(781): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 781 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608848 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(782) " "Verilog HDL assignment warning at sine.hex(782): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 782 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(783) " "Verilog HDL assignment warning at sine.hex(783): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 783 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(784) " "Verilog HDL assignment warning at sine.hex(784): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 784 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(785) " "Verilog HDL assignment warning at sine.hex(785): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 785 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(786) " "Verilog HDL assignment warning at sine.hex(786): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 786 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(787) " "Verilog HDL assignment warning at sine.hex(787): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 787 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(788) " "Verilog HDL assignment warning at sine.hex(788): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 788 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(789) " "Verilog HDL assignment warning at sine.hex(789): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 789 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(790) " "Verilog HDL assignment warning at sine.hex(790): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 790 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(791) " "Verilog HDL assignment warning at sine.hex(791): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 791 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(792) " "Verilog HDL assignment warning at sine.hex(792): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 792 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(793) " "Verilog HDL assignment warning at sine.hex(793): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 793 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(794) " "Verilog HDL assignment warning at sine.hex(794): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 794 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(795) " "Verilog HDL assignment warning at sine.hex(795): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 795 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(796) " "Verilog HDL assignment warning at sine.hex(796): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 796 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(797) " "Verilog HDL assignment warning at sine.hex(797): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 797 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(798) " "Verilog HDL assignment warning at sine.hex(798): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 798 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(799) " "Verilog HDL assignment warning at sine.hex(799): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 799 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(800) " "Verilog HDL assignment warning at sine.hex(800): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 800 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(801) " "Verilog HDL assignment warning at sine.hex(801): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 801 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(802) " "Verilog HDL assignment warning at sine.hex(802): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 802 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(803) " "Verilog HDL assignment warning at sine.hex(803): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 803 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(804) " "Verilog HDL assignment warning at sine.hex(804): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 804 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(805) " "Verilog HDL assignment warning at sine.hex(805): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 805 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(806) " "Verilog HDL assignment warning at sine.hex(806): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 806 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(807) " "Verilog HDL assignment warning at sine.hex(807): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 807 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608849 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(808) " "Verilog HDL assignment warning at sine.hex(808): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 808 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(809) " "Verilog HDL assignment warning at sine.hex(809): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 809 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(810) " "Verilog HDL assignment warning at sine.hex(810): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 810 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(811) " "Verilog HDL assignment warning at sine.hex(811): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 811 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(812) " "Verilog HDL assignment warning at sine.hex(812): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 812 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(813) " "Verilog HDL assignment warning at sine.hex(813): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 813 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(814) " "Verilog HDL assignment warning at sine.hex(814): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 814 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(815) " "Verilog HDL assignment warning at sine.hex(815): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 815 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(816) " "Verilog HDL assignment warning at sine.hex(816): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 816 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(817) " "Verilog HDL assignment warning at sine.hex(817): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 817 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(818) " "Verilog HDL assignment warning at sine.hex(818): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 818 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(819) " "Verilog HDL assignment warning at sine.hex(819): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 819 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(820) " "Verilog HDL assignment warning at sine.hex(820): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 820 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(821) " "Verilog HDL assignment warning at sine.hex(821): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 821 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(822) " "Verilog HDL assignment warning at sine.hex(822): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 822 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(823) " "Verilog HDL assignment warning at sine.hex(823): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 823 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(824) " "Verilog HDL assignment warning at sine.hex(824): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 824 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(825) " "Verilog HDL assignment warning at sine.hex(825): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 825 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(826) " "Verilog HDL assignment warning at sine.hex(826): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 826 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608850 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(827) " "Verilog HDL assignment warning at sine.hex(827): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 827 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(828) " "Verilog HDL assignment warning at sine.hex(828): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 828 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(829) " "Verilog HDL assignment warning at sine.hex(829): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 829 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(830) " "Verilog HDL assignment warning at sine.hex(830): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 830 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(831) " "Verilog HDL assignment warning at sine.hex(831): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 831 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(832) " "Verilog HDL assignment warning at sine.hex(832): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 832 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(833) " "Verilog HDL assignment warning at sine.hex(833): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 833 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(834) " "Verilog HDL assignment warning at sine.hex(834): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 834 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(835) " "Verilog HDL assignment warning at sine.hex(835): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 835 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(836) " "Verilog HDL assignment warning at sine.hex(836): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 836 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(837) " "Verilog HDL assignment warning at sine.hex(837): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 837 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(838) " "Verilog HDL assignment warning at sine.hex(838): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 838 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(839) " "Verilog HDL assignment warning at sine.hex(839): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 839 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(840) " "Verilog HDL assignment warning at sine.hex(840): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 840 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(841) " "Verilog HDL assignment warning at sine.hex(841): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 841 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(842) " "Verilog HDL assignment warning at sine.hex(842): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 842 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608851 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(843) " "Verilog HDL assignment warning at sine.hex(843): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 843 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(844) " "Verilog HDL assignment warning at sine.hex(844): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 844 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(845) " "Verilog HDL assignment warning at sine.hex(845): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 845 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(846) " "Verilog HDL assignment warning at sine.hex(846): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 846 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(847) " "Verilog HDL assignment warning at sine.hex(847): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 847 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(848) " "Verilog HDL assignment warning at sine.hex(848): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 848 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(849) " "Verilog HDL assignment warning at sine.hex(849): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 849 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(850) " "Verilog HDL assignment warning at sine.hex(850): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 850 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(851) " "Verilog HDL assignment warning at sine.hex(851): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 851 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(852) " "Verilog HDL assignment warning at sine.hex(852): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 852 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(853) " "Verilog HDL assignment warning at sine.hex(853): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 853 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(854) " "Verilog HDL assignment warning at sine.hex(854): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 854 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(855) " "Verilog HDL assignment warning at sine.hex(855): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 855 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(856) " "Verilog HDL assignment warning at sine.hex(856): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 856 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(857) " "Verilog HDL assignment warning at sine.hex(857): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 857 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(858) " "Verilog HDL assignment warning at sine.hex(858): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 858 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(859) " "Verilog HDL assignment warning at sine.hex(859): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 859 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(860) " "Verilog HDL assignment warning at sine.hex(860): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 860 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(861) " "Verilog HDL assignment warning at sine.hex(861): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 861 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(862) " "Verilog HDL assignment warning at sine.hex(862): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 862 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(863) " "Verilog HDL assignment warning at sine.hex(863): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 863 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(864) " "Verilog HDL assignment warning at sine.hex(864): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 864 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608852 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(865) " "Verilog HDL assignment warning at sine.hex(865): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 865 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(866) " "Verilog HDL assignment warning at sine.hex(866): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 866 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(867) " "Verilog HDL assignment warning at sine.hex(867): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 867 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(868) " "Verilog HDL assignment warning at sine.hex(868): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 868 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(869) " "Verilog HDL assignment warning at sine.hex(869): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 869 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(870) " "Verilog HDL assignment warning at sine.hex(870): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 870 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(871) " "Verilog HDL assignment warning at sine.hex(871): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 871 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(872) " "Verilog HDL assignment warning at sine.hex(872): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 872 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(873) " "Verilog HDL assignment warning at sine.hex(873): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 873 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(874) " "Verilog HDL assignment warning at sine.hex(874): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 874 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(875) " "Verilog HDL assignment warning at sine.hex(875): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 875 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(876) " "Verilog HDL assignment warning at sine.hex(876): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 876 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(877) " "Verilog HDL assignment warning at sine.hex(877): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 877 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(878) " "Verilog HDL assignment warning at sine.hex(878): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 878 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(879) " "Verilog HDL assignment warning at sine.hex(879): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 879 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(880) " "Verilog HDL assignment warning at sine.hex(880): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 880 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(881) " "Verilog HDL assignment warning at sine.hex(881): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 881 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(882) " "Verilog HDL assignment warning at sine.hex(882): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 882 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(883) " "Verilog HDL assignment warning at sine.hex(883): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 883 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(884) " "Verilog HDL assignment warning at sine.hex(884): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 884 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(885) " "Verilog HDL assignment warning at sine.hex(885): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 885 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(886) " "Verilog HDL assignment warning at sine.hex(886): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 886 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(887) " "Verilog HDL assignment warning at sine.hex(887): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 887 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(888) " "Verilog HDL assignment warning at sine.hex(888): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 888 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(889) " "Verilog HDL assignment warning at sine.hex(889): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 889 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(890) " "Verilog HDL assignment warning at sine.hex(890): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 890 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(891) " "Verilog HDL assignment warning at sine.hex(891): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 891 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(892) " "Verilog HDL assignment warning at sine.hex(892): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 892 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608853 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(893) " "Verilog HDL assignment warning at sine.hex(893): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 893 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(894) " "Verilog HDL assignment warning at sine.hex(894): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 894 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(895) " "Verilog HDL assignment warning at sine.hex(895): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 895 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(896) " "Verilog HDL assignment warning at sine.hex(896): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 896 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(897) " "Verilog HDL assignment warning at sine.hex(897): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 897 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(898) " "Verilog HDL assignment warning at sine.hex(898): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 898 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(899) " "Verilog HDL assignment warning at sine.hex(899): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 899 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(900) " "Verilog HDL assignment warning at sine.hex(900): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 900 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(901) " "Verilog HDL assignment warning at sine.hex(901): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 901 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(902) " "Verilog HDL assignment warning at sine.hex(902): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 902 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(903) " "Verilog HDL assignment warning at sine.hex(903): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 903 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(904) " "Verilog HDL assignment warning at sine.hex(904): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 904 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(905) " "Verilog HDL assignment warning at sine.hex(905): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 905 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(906) " "Verilog HDL assignment warning at sine.hex(906): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 906 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(907) " "Verilog HDL assignment warning at sine.hex(907): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 907 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(908) " "Verilog HDL assignment warning at sine.hex(908): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 908 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(909) " "Verilog HDL assignment warning at sine.hex(909): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 909 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(910) " "Verilog HDL assignment warning at sine.hex(910): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 910 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(911) " "Verilog HDL assignment warning at sine.hex(911): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 911 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(912) " "Verilog HDL assignment warning at sine.hex(912): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 912 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(913) " "Verilog HDL assignment warning at sine.hex(913): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 913 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(914) " "Verilog HDL assignment warning at sine.hex(914): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 914 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(915) " "Verilog HDL assignment warning at sine.hex(915): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 915 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(916) " "Verilog HDL assignment warning at sine.hex(916): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 916 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(917) " "Verilog HDL assignment warning at sine.hex(917): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 917 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(918) " "Verilog HDL assignment warning at sine.hex(918): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 918 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(919) " "Verilog HDL assignment warning at sine.hex(919): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 919 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(920) " "Verilog HDL assignment warning at sine.hex(920): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 920 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(921) " "Verilog HDL assignment warning at sine.hex(921): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 921 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(922) " "Verilog HDL assignment warning at sine.hex(922): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 922 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(923) " "Verilog HDL assignment warning at sine.hex(923): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 923 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(924) " "Verilog HDL assignment warning at sine.hex(924): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 924 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(925) " "Verilog HDL assignment warning at sine.hex(925): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 925 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(926) " "Verilog HDL assignment warning at sine.hex(926): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 926 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(927) " "Verilog HDL assignment warning at sine.hex(927): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 927 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(928) " "Verilog HDL assignment warning at sine.hex(928): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 928 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(929) " "Verilog HDL assignment warning at sine.hex(929): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 929 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(930) " "Verilog HDL assignment warning at sine.hex(930): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 930 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(931) " "Verilog HDL assignment warning at sine.hex(931): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 931 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608854 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(932) " "Verilog HDL assignment warning at sine.hex(932): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 932 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(933) " "Verilog HDL assignment warning at sine.hex(933): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 933 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(934) " "Verilog HDL assignment warning at sine.hex(934): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 934 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(935) " "Verilog HDL assignment warning at sine.hex(935): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 935 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(936) " "Verilog HDL assignment warning at sine.hex(936): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 936 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(937) " "Verilog HDL assignment warning at sine.hex(937): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 937 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(938) " "Verilog HDL assignment warning at sine.hex(938): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 938 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(939) " "Verilog HDL assignment warning at sine.hex(939): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 939 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(940) " "Verilog HDL assignment warning at sine.hex(940): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 940 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(941) " "Verilog HDL assignment warning at sine.hex(941): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 941 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(942) " "Verilog HDL assignment warning at sine.hex(942): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 942 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(943) " "Verilog HDL assignment warning at sine.hex(943): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 943 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(944) " "Verilog HDL assignment warning at sine.hex(944): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 944 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(945) " "Verilog HDL assignment warning at sine.hex(945): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 945 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(946) " "Verilog HDL assignment warning at sine.hex(946): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 946 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(947) " "Verilog HDL assignment warning at sine.hex(947): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 947 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(948) " "Verilog HDL assignment warning at sine.hex(948): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 948 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(949) " "Verilog HDL assignment warning at sine.hex(949): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 949 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(950) " "Verilog HDL assignment warning at sine.hex(950): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 950 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(951) " "Verilog HDL assignment warning at sine.hex(951): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 951 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(952) " "Verilog HDL assignment warning at sine.hex(952): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 952 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(953) " "Verilog HDL assignment warning at sine.hex(953): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 953 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(954) " "Verilog HDL assignment warning at sine.hex(954): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 954 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(955) " "Verilog HDL assignment warning at sine.hex(955): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 955 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(956) " "Verilog HDL assignment warning at sine.hex(956): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 956 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(957) " "Verilog HDL assignment warning at sine.hex(957): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 957 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(958) " "Verilog HDL assignment warning at sine.hex(958): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 958 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608856 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(959) " "Verilog HDL assignment warning at sine.hex(959): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 959 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(960) " "Verilog HDL assignment warning at sine.hex(960): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 960 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(961) " "Verilog HDL assignment warning at sine.hex(961): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 961 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(962) " "Verilog HDL assignment warning at sine.hex(962): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 962 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(963) " "Verilog HDL assignment warning at sine.hex(963): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 963 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(964) " "Verilog HDL assignment warning at sine.hex(964): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 964 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(965) " "Verilog HDL assignment warning at sine.hex(965): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 965 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(966) " "Verilog HDL assignment warning at sine.hex(966): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 966 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(967) " "Verilog HDL assignment warning at sine.hex(967): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 967 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(968) " "Verilog HDL assignment warning at sine.hex(968): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 968 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(969) " "Verilog HDL assignment warning at sine.hex(969): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 969 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(970) " "Verilog HDL assignment warning at sine.hex(970): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 970 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(971) " "Verilog HDL assignment warning at sine.hex(971): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 971 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(972) " "Verilog HDL assignment warning at sine.hex(972): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 972 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(973) " "Verilog HDL assignment warning at sine.hex(973): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 973 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(974) " "Verilog HDL assignment warning at sine.hex(974): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 974 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(975) " "Verilog HDL assignment warning at sine.hex(975): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 975 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(976) " "Verilog HDL assignment warning at sine.hex(976): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 976 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(977) " "Verilog HDL assignment warning at sine.hex(977): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 977 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(978) " "Verilog HDL assignment warning at sine.hex(978): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 978 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(979) " "Verilog HDL assignment warning at sine.hex(979): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 979 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(980) " "Verilog HDL assignment warning at sine.hex(980): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 980 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(981) " "Verilog HDL assignment warning at sine.hex(981): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 981 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(982) " "Verilog HDL assignment warning at sine.hex(982): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 982 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(983) " "Verilog HDL assignment warning at sine.hex(983): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 983 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(984) " "Verilog HDL assignment warning at sine.hex(984): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 984 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(985) " "Verilog HDL assignment warning at sine.hex(985): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 985 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(986) " "Verilog HDL assignment warning at sine.hex(986): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 986 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608857 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(987) " "Verilog HDL assignment warning at sine.hex(987): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 987 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(988) " "Verilog HDL assignment warning at sine.hex(988): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 988 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(989) " "Verilog HDL assignment warning at sine.hex(989): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 989 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(990) " "Verilog HDL assignment warning at sine.hex(990): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 990 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(991) " "Verilog HDL assignment warning at sine.hex(991): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 991 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(992) " "Verilog HDL assignment warning at sine.hex(992): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 992 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(993) " "Verilog HDL assignment warning at sine.hex(993): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 993 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(994) " "Verilog HDL assignment warning at sine.hex(994): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 994 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(995) " "Verilog HDL assignment warning at sine.hex(995): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 995 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(996) " "Verilog HDL assignment warning at sine.hex(996): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 996 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(997) " "Verilog HDL assignment warning at sine.hex(997): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 997 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(998) " "Verilog HDL assignment warning at sine.hex(998): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 998 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(999) " "Verilog HDL assignment warning at sine.hex(999): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 999 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1000) " "Verilog HDL assignment warning at sine.hex(1000): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1000 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1001) " "Verilog HDL assignment warning at sine.hex(1001): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1001 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1002) " "Verilog HDL assignment warning at sine.hex(1002): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1002 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1003) " "Verilog HDL assignment warning at sine.hex(1003): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1003 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1004) " "Verilog HDL assignment warning at sine.hex(1004): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1004 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1005) " "Verilog HDL assignment warning at sine.hex(1005): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1005 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1006) " "Verilog HDL assignment warning at sine.hex(1006): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1006 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1007) " "Verilog HDL assignment warning at sine.hex(1007): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1007 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1008) " "Verilog HDL assignment warning at sine.hex(1008): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1008 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1009) " "Verilog HDL assignment warning at sine.hex(1009): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1009 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1010) " "Verilog HDL assignment warning at sine.hex(1010): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1010 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1011) " "Verilog HDL assignment warning at sine.hex(1011): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1011 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1012) " "Verilog HDL assignment warning at sine.hex(1012): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1012 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1013) " "Verilog HDL assignment warning at sine.hex(1013): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1013 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1014) " "Verilog HDL assignment warning at sine.hex(1014): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1014 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608858 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1015) " "Verilog HDL assignment warning at sine.hex(1015): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1015 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1016) " "Verilog HDL assignment warning at sine.hex(1016): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1016 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1017) " "Verilog HDL assignment warning at sine.hex(1017): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1017 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1018) " "Verilog HDL assignment warning at sine.hex(1018): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1018 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1019) " "Verilog HDL assignment warning at sine.hex(1019): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1019 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1020) " "Verilog HDL assignment warning at sine.hex(1020): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1020 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1021) " "Verilog HDL assignment warning at sine.hex(1021): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1021 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1022) " "Verilog HDL assignment warning at sine.hex(1022): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1022 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1023) " "Verilog HDL assignment warning at sine.hex(1023): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1023 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "12 10 sine.hex(1024) " "Verilog HDL assignment warning at sine.hex(1024): truncated value with size 12 to match size of target (10)" {  } { { "sine.hex" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/sine.hex" 1024 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(678) " "Verilog HDL assignment warning at analog_ip.v(678): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 678 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(686) " "Verilog HDL assignment warning at analog_ip.v(686): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 686 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(691) " "Verilog HDL assignment warning at analog_ip.v(691): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 691 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "20 10 analog_ip.v(699) " "Verilog HDL assignment warning at analog_ip.v(699): truncated value with size 20 to match size of target (10)" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 699 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "mult analog_ip.v(669) " "Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable \"mult\", which holds its previous value in one or more paths through the always construct" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 669 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "step analog_ip.v(669) " "Verilog HDL Always Construct warning at analog_ip.v(669): inferring latch(es) for variable \"step\", which holds its previous value in one or more paths through the always construct" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 669 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.data_a 0 analog_ip.v(635) " "Net \"sine_rom.data_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.waddr_a 0 analog_ip.v(635) " "Net \"sine_rom.waddr_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "sine_rom.we_a 0 analog_ip.v(635) " "Net \"sine_rom.we_a\" at analog_ip.v(635) has no driver or initial value, using a default initial value '0'" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 635 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Quartus II" 0 -1 1778306608859 "|example_board|analog_ip:macro_inst|apb_dac:apb_dac0_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_dac analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Elaborating entity \"alta_dac\" for hierarchy \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst\"" {  } { { "analog_ip.v" "dac_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 718 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608861 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud_detect analog_ip:macro_inst\|baud_detect:u_baud_detect " "Elaborating entity \"baud_detect\" for hierarchy \"analog_ip:macro_inst\|baud_detect:u_baud_detect\"" {  } { { "analog_ip.v" "u_baud_detect" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 327 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608864 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(33) " "Verilog HDL assignment warning at baud_detect.v(33): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 33 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608868 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(35) " "Verilog HDL assignment warning at baud_detect.v(35): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 35 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608868 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 baud_detect.v(40) " "Verilog HDL assignment warning at baud_detect.v(40): truncated value with size 32 to match size of target (4)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 40 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608868 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "min_time baud_detect.v(28) " "Verilog HDL Always Construct warning at baud_detect.v(28): inferring latch(es) for variable \"min_time\", which holds its previous value in one or more paths through the always construct" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 28 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Quartus II" 0 -1 1778306608868 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 24 baud_detect.v(50) " "Verilog HDL assignment warning at baud_detect.v(50): truncated value with size 32 to match size of target (24)" {  } { { "baud_detect.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/baud_detect.v" 50 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608868 "|example_board|analog_ip:macro_inst|baud_detect:u_baud_detect"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Elaborating entity \"altsyncram\" for hierarchy \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\"" {  } { { "analog_ip.v" "u_dual_port_ram" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608904 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|altsyncram:u_dual_port_ram " "Instantiated megafunction \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "byte_size 8 " "Parameter \"byte_size\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_a BYPASS " "Parameter \"clock_enable_output_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode BIDIR_DUAL_PORT " "Parameter \"operation_mode\" = \"BIDIR_DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Parameter \"widthad_a\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 2 " "Parameter \"width_byteena_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a UNREGISTERED " "Parameter \"outdata_reg_a\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 1024 " "Parameter \"numwords_b\" = \"1024\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 10 " "Parameter \"widthad_b\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_b 2 " "Parameter \"width_byteena_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type M9K " "Parameter \"ram_block_type\" = \"M9K\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_port_a NEW_DATA_NO_NBE_READ " "Parameter \"read_during_write_mode_port_a\" = \"NEW_DATA_NO_NBE_READ\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608906 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 390 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1778306608906 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sgu1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sgu1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sgu1 " "Found entity 1: altsyncram_sgu1" {  } { { "db/altsyncram_sgu1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altsyncram_sgu1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1778306608965 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1778306608965 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_sgu1 analog_ip:macro_inst\|altsyncram:u_dual_port_ram\|altsyncram_sgu1:auto_generated " "Elaborating entity \"altsyncram_sgu1\" for hierarchy \"analog_ip:macro_inst\|altsyncram:u_dual_port_ram\|altsyncram_sgu1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608967 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "apb2ram analog_ip:macro_inst\|apb2ram:u_apb2ram " "Elaborating entity \"apb2ram\" for hierarchy \"analog_ip:macro_inst\|apb2ram:u_apb2ram\"" {  } { { "analog_ip.v" "u_apb2ram" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 456 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608972 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "15 10 apb2ram.v(26) " "Verilog HDL assignment warning at apb2ram.v(26): truncated value with size 15 to match size of target (10)" {  } { { "apb2ram.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/apb2ram.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Quartus II" 0 -1 1778306608973 "|example_board|analog_ip:macro_inst|apb2ram:u_apb2ram"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_rv32 alta_rv32:rv32 " "Elaborating entity \"alta_rv32\" for hierarchy \"alta_rv32:rv32\"" {  } { { "example_board.v" "rv32" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 451 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1778306608975 ""}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_data alta_sim.v(3739) " "Output port \"gpio0_io_out_data\" at alta_sim.v(3739) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608976 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_en alta_sim.v(3740) " "Output port \"gpio0_io_out_en\" at alta_sim.v(3740) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608976 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_data alta_sim.v(3742) " "Output port \"gpio1_io_out_data\" at alta_sim.v(3742) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608976 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_en alta_sim.v(3743) " "Output port \"gpio1_io_out_en\" at alta_sim.v(3743) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608976 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_data alta_sim.v(3753) " "Output port \"gpio2_io_out_data\" at alta_sim.v(3753) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_en alta_sim.v(3754) " "Output port \"gpio2_io_out_en\" at alta_sim.v(3754) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_data alta_sim.v(3756) " "Output port \"gpio3_io_out_data\" at alta_sim.v(3756) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_en alta_sim.v(3757) " "Output port \"gpio3_io_out_en\" at alta_sim.v(3757) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_data alta_sim.v(3759) " "Output port \"gpio4_io_out_data\" at alta_sim.v(3759) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_en alta_sim.v(3760) " "Output port \"gpio4_io_out_en\" at alta_sim.v(3760) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_data alta_sim.v(3762) " "Output port \"gpio5_io_out_data\" at alta_sim.v(3762) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_en alta_sim.v(3763) " "Output port \"gpio5_io_out_en\" at alta_sim.v(3763) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_data alta_sim.v(3765) " "Output port \"gpio6_io_out_data\" at alta_sim.v(3765) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_en alta_sim.v(3766) " "Output port \"gpio6_io_out_en\" at alta_sim.v(3766) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_data alta_sim.v(3768) " "Output port \"gpio7_io_out_data\" at alta_sim.v(3768) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_en alta_sim.v(3769) " "Output port \"gpio7_io_out_en\" at alta_sim.v(3769) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608977 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_data alta_sim.v(3771) " "Output port \"gpio8_io_out_data\" at alta_sim.v(3771) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_en alta_sim.v(3772) " "Output port \"gpio8_io_out_en\" at alta_sim.v(3772) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_data alta_sim.v(3774) " "Output port \"gpio9_io_out_data\" at alta_sim.v(3774) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_en alta_sim.v(3775) " "Output port \"gpio9_io_out_en\" at alta_sim.v(3775) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGSTATE alta_sim.v(3780) " "Output port \"swj_JTAGSTATE\" at alta_sim.v(3780) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGIR alta_sim.v(3781) " "Output port \"swj_JTAGIR\" at alta_sim.v(3781) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "dmactive alta_sim.v(3778) " "Output port \"dmactive\" at alta_sim.v(3778) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3778 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGNSW alta_sim.v(3779) " "Output port \"swj_JTAGNSW\" at alta_sim.v(3779) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3779 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1778306608978 "|example_board|alta_rv32:rv32"}
{ "Info" "ISGN_QIC_SYNTHESIS_TOP_SEVERAL" "4 " "4 design partitions require synthesis" { { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "Top " "Partition \"Top\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778306609139 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "macro_inst_apb_adc0_inst_adc_inst " "Partition \"macro_inst_apb_adc0_inst_adc_inst\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778306609139 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "macro_inst_apb_dac0_inst_dac_inst " "Partition \"macro_inst_apb_dac0_inst_dac_inst\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778306609139 ""} { "Info" "ISGN_QIC_SYNTHESIS_REASON_SOURCE" "rv32 " "Partition \"rv32\" requires synthesis because its netlist type is Source File" {  } {  } 0 12210 "Partition \"%1!s!\" requires synthesis because its netlist type is Source File" 0 0 "Quartus II" 0 -1 1778306609139 ""}  } {  } 0 12206 "%1!d! design partitions require synthesis" 0 0 "Quartus II" 0 -1 1778306609139 ""}
{ "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ZERO" "" "No design partitions will skip synthesis in the current incremental compilation" {  } {  } 0 12209 "No design partitions will skip synthesis in the current incremental compilation" 0 0 "Quartus II" 0 -1 1778306609139 ""}
{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "3 " "3 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1778306609462 ""}
{ "Info" "IQSYN_PARALLEL_SYNTHESIS" "4 4 " "Using 4 processors to synthesize 4 partitions in parallel" {  } {  } 0 281037 "Using %1!d! processors to synthesize %2!d! partitions in parallel" 0 0 "Quartus II" 0 -1 1778306609473 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 2 1778306609915 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 2 1778306609915 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:29 2026 " "Processing started: Sat May 09 14:03:29 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 2 1778306609915 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 2 1778306609915 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board " "Command: quartus_map --parallel=1 --helper=2 --partition=macro_inst_apb_dac0_inst_dac_inst example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 2 1778306609915 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 1 1778306609916 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 1 1778306609917 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:29 2026 " "Processing started: Sat May 09 14:03:29 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 1 1778306609917 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 1 1778306609917 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board " "Command: quartus_map --parallel=1 --helper=1 --partition=macro_inst_apb_adc0_inst_adc_inst example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 1 1778306609917 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 3 1778306609929 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 3 1778306609929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:29 2026 " "Processing started: Sat May 09 14:03:29 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 3 1778306609929 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 3 1778306609929 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board " "Command: quartus_map --parallel=1 --helper=3 --partition=rv32 example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 3 1778306609929 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 0 1778306609929 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 0 1778306609929 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:29 2026 " "Processing started: Sat May 09 14:03:29 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 0 1778306609929 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 0 1778306609929 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board " "Command: quartus_map --parallel=1 --helper=0 --partition=Top example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 0 1778306609929 ""}
{ "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778306610473 ""}
{ "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting DSP block usage to 0 DSP block(s) for the partition analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778306610473 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778306610487 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|alta_dac:dac_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 2 1778306610488 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778306610489 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 1 1778306610489 ""}
{ "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition alta_rv32:rv32 " "Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778306610490 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 alta_rv32:rv32 " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778306610505 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 alta_rv32:rv32 " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 3 1778306610507 ""}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "macro_inst_apb_adc0_inst_adc_inst " "Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_adc0_inst_adc_inst" {  } { { "analog_ip.v" "adc_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 584 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 1 1778306610582 ""}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 1 1778306610583 ""}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "macro_inst_apb_dac0_inst_dac_inst " "Starting Logic Optimization and Technology Mapping for Partition macro_inst_apb_dac0_inst_dac_inst" {  } { { "analog_ip.v" "dac_inst" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 718 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 2 1778306610585 ""}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 2 1778306610585 ""}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "rv32 " "Starting Logic Optimization and Technology Mapping for Partition rv32" {  } { { "example_board.v" "rv32" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 451 0 0 } }  } 0 281019 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "Quartus II" 0 3 1778306610600 ""}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 3 1778306610602 ""}
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio0_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio0_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio0_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio1_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio1_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio1_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio2_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio2_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio2_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio3_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio3_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio3_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio4_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio4_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio4_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio5_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio5_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio5_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio6_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio6_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio6_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio7_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio7_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio7_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio8_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio8_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio8_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[0\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[1\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[2\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[3\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[4\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[5\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[6\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_data\[7\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_data\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_data[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[0\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[1\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[2\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[3\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[4\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[4\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[5\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[5\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[6\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[6\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|gpio9_io_out_en\[7\] GND " "Pin \"alta_rv32:rv32\|gpio9_io_out_en\[7\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|gpio9_io_out_en[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|dmactive GND " "Pin \"alta_rv32:rv32\|dmactive\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3778 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|dmactive"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGNSW GND " "Pin \"alta_rv32:rv32\|swj_JTAGNSW\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3779 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGNSW"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[0\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[1\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[2\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGSTATE\[3\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGSTATE\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGSTATE[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[0\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[0\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGIR[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[1\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[1\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGIR[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[2\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[2\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGIR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "alta_rv32:rv32\|swj_JTAGIR\[3\] GND " "Pin \"alta_rv32:rv32\|swj_JTAGIR\[3\]\" is stuck at GND" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 -1 0 } }  } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 3 1778306610991 "|example_board|alta_rv32:rv32|swj_JTAGIR[3]"}  } {  } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 3 1778306610991 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 1 1778306611169 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 2 1778306611183 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 3 1778306611254 ""}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "3 " "Inferred 3 megafunctions from design logic" { { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult0 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult0\"" {  } { { "analog_ip.v" "Mult0" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306611541 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult2 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult2\"" {  } { { "analog_ip.v" "Mult2" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306611541 ""} { "Info" "ILPMS_LPM_MULT_INFERRED" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult3 lpm_mult " "Inferred multiplier megafunction (\"lpm_mult\") from the following logic: \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|Mult3\"" {  } { { "analog_ip.v" "Mult3" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } }  } 0 278003 "Inferred multiplier megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306611541 ""}  } {  } 0 278001 "Inferred %1!llu! megafunctions from design logic" 0 0 "Quartus II" 0 0 1778306611541 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 1 1778306611646 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 1 1778306611646 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 2 1778306611648 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 2 1778306611648 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 1 1778306611658 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 2 1778306611665 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 1 1778306611688 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 1 1778306611688 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 10 " "Parameter \"LPM_WIDTHB\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 20 " "Parameter \"LPM_WIDTHP\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 20 " "Parameter \"LPM_WIDTHR\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611695 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306611695 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 2 1778306611696 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 2 1778306611696 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "21 " "Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "8 " "Implemented 8 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 1 1778306611738 ""} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Implemented 13 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 1 1778306611738 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 1 1778306611738 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "14 " "Implemented 14 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "13 " "Implemented 13 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 2 1778306611752 ""} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Implemented 1 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 2 1778306611752 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 2 1778306611752 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 1 1778306611768 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:31 2026 " "Processing ended: Sat May 09 14:03:31 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 1 1778306611768 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 1 1778306611768 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 1 1778306611768 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 1 1778306611768 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 2 1778306611778 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:31 2026 " "Processing ended: Sat May 09 14:03:31 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 2 1778306611778 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 2 1778306611778 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 2 1778306611778 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 2 1778306611778 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_oct.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_oct.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_oct " "Found entity 1: mult_oct" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306611786 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306611786 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHA 10 " "Parameter \"LPM_WIDTHA\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHB 9 " "Parameter \"LPM_WIDTHB\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHP 19 " "Parameter \"LPM_WIDTHP\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHR 19 " "Parameter \"LPM_WIDTHR\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 1 " "Parameter \"LPM_WIDTHS\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_REPRESENTATION UNSIGNED " "Parameter \"LPM_REPRESENTATION\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_A_IS_CONSTANT NO " "Parameter \"INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INPUT_B_IS_CONSTANT NO " "Parameter \"INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MAXIMIZE_SPEED 6 " "Parameter \"MAXIMIZE_SPEED\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306611806 ""}  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306611806 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 3 1778306611861 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 3 1778306611861 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_pbt.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_pbt.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_pbt " "Found entity 1: mult_pbt" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306611873 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306611873 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 3 1778306611879 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 3 1778306611924 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 3 1778306611925 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "520 " "Implemented 520 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "224 " "Implemented 224 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 3 1778306611977 ""} { "Info" "ICUT_CUT_TM_OPINS" "295 " "Implemented 295 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 3 1778306611977 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1 " "Implemented 1 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 3 1778306611977 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 3 1778306611977 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 171 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4684 " "Peak virtual memory: 4684 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 3 1778306612008 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:32 2026 " "Processing ended: Sat May 09 14:03:32 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 3 1778306612008 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 3 1778306612008 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Total CPU time (on all processors): 00:00:08" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 3 1778306612008 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 3 1778306612008 ""}
{ "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition Top " "Limiting DSP block usage to 0 DSP block(s) for the partition Top" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778306612061 ""}
{ "Info" "IBAL_BAL_CONVERTED_DSP_SLICES" "3 " "Converted 3 DSP block slices" { { "Info" "IBAL_BAL_OVERALL_DSP_USAGE" "before 3 " "Used 3 DSP blocks before DSP block balancing" { { "Info" "IBAL_BAL_DSP_MODE_USAGE" "Simple Multiplier (18-bit) 3 3 " "Used 3 DSP block slices in \"Simple Multiplier (18-bit)\" mode implemented in approximately 3 DSP blocks" {  } {  } 0 270003 "Used %2!d! DSP block slices in \"%1!s!\" mode implemented in approximately %3!d! DSP blocks" 0 0 "Quartus II" 0 0 1778306612061 ""}  } {  } 0 270002 "Used %2!d! DSP blocks %1!s! DSP block balancing" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_CONVERTED_DSP_SLICES_TO_LE" "3 " "Converted the following 3 DSP block slices to logic elements" { { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 698 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_out2\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|mac_mult1\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 690 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_DSP_SLICE" "Simple Multiplier (18-bit) analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2 " "DSP block slice in \"Simple Multiplier (18-bit)\" mode with output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2\"" { { "Info" "IBAL_BAL_MAC_OUT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2 " "DSP block output node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270004 "DSP block output node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_MAC_MULT_NODE" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_mult1 " "DSP block multiplier node \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult0\|mult_oct:auto_generated\|mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270005 "DSP block multiplier node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } } { "lpm_mult.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/lpm_mult.tdf" 375 4 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 677 -1 0 } } { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 314 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 311 0 0 } }  } 0 270006 "DSP block slice in \"%1!s!\" mode with output node \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612061 ""}  } {  } 0 270013 "Converted the following %1!d! DSP block slices to logic elements" 0 0 "Quartus II" 0 0 1778306612061 ""} { "Info" "IBAL_BAL_OVERALL_DSP_USAGE" "after 0 " "Used 0 DSP blocks after DSP block balancing" {  } {  } 0 270002 "Used %2!d! DSP blocks %1!s! DSP block balancing" 0 0 "Quartus II" 0 0 1778306612061 ""}  } {  } 0 270001 "Converted %1!d! DSP block slices" 0 0 "Quartus II" 0 0 1778306612061 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778306612076 ""}
{ "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1778306612076 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_mult:mac_mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_A UNSIGNED " "Parameter \"MULT_REPRESENTATION_A\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_B UNSIGNED " "Parameter \"MULT_REPRESENTATION_B\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_PIPELINE 0 " "Parameter \"MULT_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLOCK NONE " "Parameter \"MULT_CLOCK\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLEAR NONE " "Parameter \"MULT_CLEAR\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_A_IS_CONSTANT NO " "Parameter \"MULT_INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_B_IS_CONSTANT NO " "Parameter \"MULT_INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 10 " "Parameter \"dataa_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 10 " "Parameter \"datab_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 20 " "Parameter \"output_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clock NONE " "Parameter \"dataa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clock NONE " "Parameter \"datab_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clear NONE " "Parameter \"dataa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clear NONE " "Parameter \"datab_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612164 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 35 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306612164 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_mult_iug1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_mult_iug1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_mult_iug1 " "Found entity 1: mac_mult_iug1" {  } { { "db/mac_mult_iug1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_mult_iug1.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612219 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612219 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_aql.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_aql.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_aql " "Found entity 1: mult_aql" {  } { { "db/mult_aql.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_aql.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612275 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612275 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2\"" {  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult3\|mult_oct:auto_generated\|alt_mac_out:mac_out2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE OUTPUT_ONLY " "Parameter \"OPERATION_MODE\" = \"OUTPUT_ONLY\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 20 " "Parameter \"dataa_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 0 " "Parameter \"datab_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datac_width 0 " "Parameter \"datac_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datad_width 0 " "Parameter \"datad_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 20 " "Parameter \"output_width\" = \"20\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clock NONE " "Parameter \"addnsub0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clock NONE " "Parameter \"addnsub1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clock NONE " "Parameter \"zeroacc_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clock NONE " "Parameter \"first_adder0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clock NONE " "Parameter \"first_adder1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clear NONE " "Parameter \"addnsub0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clear NONE " "Parameter \"addnsub1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clear NONE " "Parameter \"zeroacc_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clear NONE " "Parameter \"first_adder0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clear NONE " "Parameter \"first_adder1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clock NONE " "Parameter \"signa_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clock NONE " "Parameter \"signb_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clock NONE " "Parameter \"addnsub0_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clock NONE " "Parameter \"addnsub1_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clock NONE " "Parameter \"zeroacc_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clear NONE " "Parameter \"signa_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clear NONE " "Parameter \"signb_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clear NONE " "Parameter \"addnsub0_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clear NONE " "Parameter \"addnsub1_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clear NONE " "Parameter \"zeroacc_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612420 ""}  } { { "db/mult_oct.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_oct.tdf" 44 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306612420 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_out_lr82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_out_lr82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_out_lr82 " "Found entity 1: mac_out_lr82" {  } { { "db/mac_out_lr82.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_out_lr82.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612469 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612469 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_mult:mac_mult1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_A UNSIGNED " "Parameter \"MULT_REPRESENTATION_A\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_REPRESENTATION_B UNSIGNED " "Parameter \"MULT_REPRESENTATION_B\" = \"UNSIGNED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_PIPELINE 0 " "Parameter \"MULT_PIPELINE\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLOCK NONE " "Parameter \"MULT_CLOCK\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_CLEAR NONE " "Parameter \"MULT_CLEAR\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_A_IS_CONSTANT NO " "Parameter \"MULT_INPUT_A_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "MULT_INPUT_B_IS_CONSTANT NO " "Parameter \"MULT_INPUT_B_IS_CONSTANT\" = \"NO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 10 " "Parameter \"dataa_width\" = \"10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 9 " "Parameter \"datab_width\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 19 " "Parameter \"output_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clock NONE " "Parameter \"dataa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clock NONE " "Parameter \"datab_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_clear NONE " "Parameter \"dataa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_clear NONE " "Parameter \"datab_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612479 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 35 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306612479 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_mult_jtg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_mult_jtg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_mult_jtg1 " "Found entity 1: mac_mult_jtg1" {  } { { "db/mac_mult_jtg1.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_mult_jtg1.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612530 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612530 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mult_bpl.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mult_bpl.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mult_bpl " "Found entity 1: mult_bpl" {  } { { "db/mult_bpl.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_bpl.tdf" 28 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612586 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612586 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2 " "Elaborated megafunction instantiation \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2\"" {  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306612617 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2 " "Instantiated megafunction \"analog_ip:macro_inst\|apb_dac:apb_dac0_inst\|lpm_mult:Mult2\|mult_pbt:auto_generated\|alt_mac_out:mac_out2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE OUTPUT_ONLY " "Parameter \"OPERATION_MODE\" = \"OUTPUT_ONLY\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "dataa_width 19 " "Parameter \"dataa_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datab_width 0 " "Parameter \"datab_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datac_width 0 " "Parameter \"datac_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "datad_width 0 " "Parameter \"datad_width\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_width 19 " "Parameter \"output_width\" = \"19\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clock NONE " "Parameter \"signa_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clock NONE " "Parameter \"signb_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clock NONE " "Parameter \"addnsub0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clock NONE " "Parameter \"addnsub1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clock NONE " "Parameter \"zeroacc_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clock NONE " "Parameter \"first_adder0_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clock NONE " "Parameter \"first_adder1_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clock NONE " "Parameter \"output_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_clear NONE " "Parameter \"signa_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_clear NONE " "Parameter \"signb_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_clear NONE " "Parameter \"addnsub0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_clear NONE " "Parameter \"addnsub1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_clear NONE " "Parameter \"zeroacc_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder0_clear NONE " "Parameter \"first_adder0_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "first_adder1_clear NONE " "Parameter \"first_adder1_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "output_clear NONE " "Parameter \"output_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clock NONE " "Parameter \"signa_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clock NONE " "Parameter \"signb_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clock NONE " "Parameter \"addnsub0_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clock NONE " "Parameter \"addnsub1_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clock NONE " "Parameter \"zeroacc_pipeline_clock\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signa_pipeline_clear NONE " "Parameter \"signa_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "signb_pipeline_clear NONE " "Parameter \"signb_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub0_pipeline_clear NONE " "Parameter \"addnsub0_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "addnsub1_pipeline_clear NONE " "Parameter \"addnsub1_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "zeroacc_pipeline_clear NONE " "Parameter \"zeroacc_pipeline_clear\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 0 1778306612618 ""}  } { { "db/mult_pbt.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mult_pbt.tdf" 44 2 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 0 1778306612618 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mac_out_5s82.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mac_out_5s82.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mac_out_5s82 " "Found entity 1: mac_out_5s82" {  } { { "db/mac_out_5s82.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/mac_out_5s82.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 0 1778306612665 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 0 1778306612665 ""}
{ "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" {  } {  } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Quartus II" 0 0 1778306612863 ""}
{ "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 0 1778306612865 ""}
{ "Info" "IMLS_MLS_IGNORED_SUMMARY" "585 " "Ignored 585 buffer(s)" { { "Info" "IMLS_MLS_IGNORED_CARRY_SUM" "30 " "Ignored 30 CARRY_SUM buffer(s)" {  } {  } 0 13016 "Ignored %1!d! CARRY_SUM buffer(s)" 0 0 "Quartus II" 0 0 1778306612873 ""} { "Info" "IMLS_MLS_IGNORED_SOFT" "555 " "Ignored 555 SOFT buffer(s)" {  } {  } 0 13019 "Ignored %1!d! SOFT buffer(s)" 0 0 "Quartus II" 0 0 1778306612873 ""}  } {  } 0 13014 "Ignored %1!d! buffer(s)" 0 0 "Quartus II" 0 0 1778306612873 ""}
{ "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI_HDR" "" "The following bidir pins have no drivers" { { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "BAUD_RATE " "Bidir \"BAUD_RATE\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778306612879 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "TEST_SINGLE " "Bidir \"TEST_SINGLE\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778306612879 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "UART1_RX " "Bidir \"UART1_RX\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778306612879 ""} { "Warning" "WMLS_OPT_INSERTED_ALWAYS_DISABLED_TRI" "so_io1 " "Bidir \"so_io1\" has no driver" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 -1 0 } }  } 0 13040 "Bidir \"%1!s!\" has no driver" 0 0 "Quartus II" 0 0 1778306612879 ""}  } {  } 0 13039 "The following bidir pins have no drivers" 0 0 "Quartus II" 0 0 1778306612879 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 62 -1 0 } } { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 81 -1 0 } } { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 51 -1 0 } } { "trig_ctrl.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/trig_ctrl.v" 49 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Quartus II" 0 0 1778306612897 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Quartus II" 0 0 1778306612897 ""}
{ "Warning" "WMLS_MLS_DISABLED_OE" "" "TRI or OPNDRN buffers permanently disabled" { { "Warning" "WMLS_MLS_NODE_NAME" "BAUD_RATE~synth " "Node \"BAUD_RATE~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306613344 ""} { "Warning" "WMLS_MLS_NODE_NAME" "TEST_SINGLE~synth " "Node \"TEST_SINGLE~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306613344 ""} { "Warning" "WMLS_MLS_NODE_NAME" "UART1_RX~synth " "Node \"UART1_RX~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306613344 ""} { "Warning" "WMLS_MLS_NODE_NAME" "so_io1~synth " "Node \"so_io1~synth\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 -1 0 } }  } 0 13010 "Node \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306613344 ""}  } {  } 0 13008 "TRI or OPNDRN buffers permanently disabled" 0 0 "Quartus II" 0 0 1778306613344 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306613508 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "3 " "3 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Quartus II" 0 0 1778306617279 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_stop " "Logic cell \"sys_ctrl_stop\"" {  } { { "example_board.v" "sys_ctrl_stop" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 88 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_in\[0\] " "Logic cell \"gpio0_io_in\[0\]\"" {  } { { "example_board.v" "gpio0_io_in\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 319 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_in\[1\] " "Logic cell \"gpio4_io_in\[1\]\"" {  } { { "example_board.v" "gpio4_io_in\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 347 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_in\[2\] " "Logic cell \"gpio4_io_in\[2\]\"" {  } { { "example_board.v" "gpio4_io_in\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 347 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_in\[1\] " "Logic cell \"gpio6_io_in\[1\]\"" {  } { { "example_board.v" "gpio6_io_in\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 355 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_in\[3\] " "Logic cell \"gpio6_io_in\[3\]\"" {  } { { "example_board.v" "gpio6_io_in\[3\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 355 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[6\] " "Logic cell \"gpio4_io_out_data\[6\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[6\] " "Logic cell \"gpio4_io_out_en\[6\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[5\] " "Logic cell \"gpio4_io_out_data\[5\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[5\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[5\] " "Logic cell \"gpio4_io_out_en\[5\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[5\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio7_io_out_data\[6\] " "Logic cell \"gpio7_io_out_data\[6\]\"" {  } { { "example_board.v" "gpio7_io_out_data\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 357 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio7_io_out_en\[6\] " "Logic cell \"gpio7_io_out_en\[6\]\"" {  } { { "example_board.v" "gpio7_io_out_en\[6\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 358 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_resetn " "Logic cell \"sys_resetn\"" {  } { { "example_board.v" "sys_resetn" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 87 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[0\] " "Logic cell \"sys_ctrl_clkSource\[0\]\"" {  } { { "example_board.v" "sys_ctrl_clkSource\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 89 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[1\] " "Logic cell \"sys_ctrl_clkSource\[1\]\"" {  } { { "example_board.v" "sys_ctrl_clkSource\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 89 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[1\] " "Logic cell \"gpio4_io_out_data\[1\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[1\] " "Logic cell \"gpio4_io_out_en\[1\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[1\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_data\[2\] " "Logic cell \"gpio4_io_out_data\[2\]\"" {  } { { "example_board.v" "gpio4_io_out_data\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 333 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio4_io_out_en\[2\] " "Logic cell \"gpio4_io_out_en\[2\]\"" {  } { { "example_board.v" "gpio4_io_out_en\[2\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 334 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_out_data\[0\] " "Logic cell \"gpio0_io_out_data\[0\]\"" {  } { { "example_board.v" "gpio0_io_out_data\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 313 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio0_io_out_en\[0\] " "Logic cell \"gpio0_io_out_en\[0\]\"" {  } { { "example_board.v" "gpio0_io_out_en\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 314 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio8_io_out_data\[0\] " "Logic cell \"gpio8_io_out_data\[0\]\"" {  } { { "example_board.v" "gpio8_io_out_data\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 363 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio8_io_out_en\[0\] " "Logic cell \"gpio8_io_out_en\[0\]\"" {  } { { "example_board.v" "gpio8_io_out_en\[0\]" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 364 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""} { "Info" "ISCL_SCL_CELL_NAME" "PLL_ENABLE " "Logic cell \"PLL_ENABLE\"" {  } { { "example_board.v" "PLL_ENABLE" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 85 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1778306617288 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 0 1778306617288 ""}
{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 0 1778306617472 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 0 1778306617487 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 0 1778306618027 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000      PIN_HSE " " 125.000      PIN_HSE" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1778306618027 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 0 1778306618073 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 0 1778306618107 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 0 1778306618109 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1764 " "Implemented 1764 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1728 " "Implemented 1728 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 0 1778306618173 ""} { "Info" "ICUT_CUT_TM_BLACKBOX" "3 " "Implemented 3 partitions" {  } {  } 0 21071 "Implemented %1!d! partitions" 0 0 "Quartus II" 0 0 1778306618173 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 0 1778306618173 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4703 " "Peak virtual memory: 4703 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 0 1778306618242 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:38 2026 " "Processing ended: Sat May 09 14:03:38 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 0 1778306618242 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 0 1778306618242 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:14 " "Total CPU time (on all processors): 00:00:14" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 0 1778306618242 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 0 1778306618242 ""}
{ "Info" "IQSYN_PARALLEL_SYNTHESIS_SUCCESS" "" "Finished parallel synthesis of all partitions" {  } {  } 0 281038 "Finished parallel synthesis of all partitions" 0 0 "Quartus II" 0 -1 1778306618857 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg " "Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1778306618988 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1282 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1282 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4640 " "Peak virtual memory: 4640 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306619096 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:39 2026 " "Processing ended: Sat May 09 14:03:39 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306619096 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306619096 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:16 " "Total CPU time (on all processors): 00:00:16" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306619096 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778306619096 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778306620110 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus II 64-Bit " "Running Quartus II 64-Bit Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306620111 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:39 2026 " "Processing started: Sat May 09 14:03:39 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306620111 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778306620111 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=off --write_settings_files=off example_board -c example_board --merge=on " "Command: quartus_cdb --read_settings_files=off --write_settings_files=off example_board -c example_board --merge=on" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778306620111 ""}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "Top " "Using synthesis netlist for partition \"Top\"" {  } {  } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306620667 ""}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "macro_inst_apb_adc0_inst_adc_inst " "Using synthesis netlist for partition \"macro_inst_apb_adc0_inst_adc_inst\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 584 0 0 } }  } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306620744 ""}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "macro_inst_apb_dac0_inst_dac_inst " "Using synthesis netlist for partition \"macro_inst_apb_dac0_inst_dac_inst\"" {  } { { "analog_ip.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/analog_ip.v" 718 0 0 } }  } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306620781 ""}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "rv32 " "Using synthesis netlist for partition \"rv32\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 451 0 0 } }  } 0 35007 "Using synthesis netlist for partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306620819 ""}
{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "4 " "Resolved and merged 4 partition(s)" {  } {  } 0 35002 "Resolved and merged %1!d! partition(s)" 0 0 "Quartus II" 0 -1 1778306620876 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "2 0 1 0 0 " "Adding 2 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1778306620912 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306620912 ""}
{ "Info" "IAMERGE_QIC_ADVISOR_DRIVER_CONSTANT" "390 " "Found 390 ports with constant drivers. For more information, refer to the Partition Merger report" {  } {  } 0 35048 "Found %1!d! ports with constant drivers. For more information, refer to the Partition Merger report" 0 0 "Quartus II" 0 -1 1778306621053 ""}
{ "Info" "IAMERGE_QIC_ADVISOR_NO_FANOUT" "396 " "Found 396 ports with no fan-out. For more information, refer to the Partition Merger report" {  } {  } 0 35047 "Found %1!d! ports with no fan-out. For more information, refer to the Partition Merger report" 0 0 "Quartus II" 0 -1 1778306621053 ""}
{ "Warning" "WAMERGE_DANGLING_ATOM_TOP" "" "Found partition port(s) not driving logic, possibly wasting area" { { "Warning" "WAMERGE_DANGLING_ATOM" "alta_gclksw:gclksw_inst\|gclk_switch alta_rv32:rv32\|sys_clk " "Partition port \"alta_rv32:rv32\|sys_clk\", driven by node \"alta_gclksw:gclksw_inst\|gclk_switch\", does not drive logic" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } }  } 0 35017 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|sys_clk"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[16\] alta_rv32:rv32\|mem_ahb_haddr\[16\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[16\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[16\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[16]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[17\] alta_rv32:rv32\|mem_ahb_haddr\[17\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[17\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[17\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[17]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[18\] alta_rv32:rv32\|mem_ahb_haddr\[18\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[18\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[18\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[18]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[19\] alta_rv32:rv32\|mem_ahb_haddr\[19\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[19\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[19\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[19]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[20\] alta_rv32:rv32\|mem_ahb_haddr\[20\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[20\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[20\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[20]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[21\] alta_rv32:rv32\|mem_ahb_haddr\[21\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[21\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[21\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[21]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[22\] alta_rv32:rv32\|mem_ahb_haddr\[22\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[22\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[22\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[22]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[23\] alta_rv32:rv32\|mem_ahb_haddr\[23\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[23\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[23\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[23]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[24\] alta_rv32:rv32\|mem_ahb_haddr\[24\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[24\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[24\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[24]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[25\] alta_rv32:rv32\|mem_ahb_haddr\[25\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[25\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[25\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[25]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[26\] alta_rv32:rv32\|mem_ahb_haddr\[26\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[26\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[26\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[26]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[27\] alta_rv32:rv32\|mem_ahb_haddr\[27\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[27\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[27\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[27]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[28\] alta_rv32:rv32\|mem_ahb_haddr\[28\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[28\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[28\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[28]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[29\] alta_rv32:rv32\|mem_ahb_haddr\[29\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[29\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[29\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[29]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[30\] alta_rv32:rv32\|mem_ahb_haddr\[30\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[30\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[30\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[30]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[31\] alta_rv32:rv32\|mem_ahb_haddr\[31\] " "Partition port \"alta_rv32:rv32\|mem_ahb_haddr\[31\]\", driven by node \"analog_ip:macro_inst\|ahb2apb:ahb2apb_inst\|prdata\[31\]\", does not drive logic" {  } { { "ahb2apb.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/ahb2apb.v" 151 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|mem_ahb_haddr[31]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "analog_ip:macro_inst\|cfg_reg:cfg_reg_inst\|adc_chnl_sel\[1\] analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst\|insel\[1\] " "Partition port \"analog_ip:macro_inst\|apb_adc:apb_adc0_inst\|alta_adc:adc_inst\|insel\[1\]\", driven by node \"analog_ip:macro_inst\|cfg_reg:cfg_reg_inst\|adc_chnl_sel\[1\]\", does not drive logic" {  } { { "cfg_reg.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/cfg_reg.v" 81 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|analog_ip:macro_inst|apb_adc:apb_adc0_inst|alta_adc:adc_inst|insel[1]"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "PLL_LOCK alta_rv32:rv32\|sys_ctrl_standby " "Partition port \"alta_rv32:rv32\|sys_ctrl_standby\", driven by node \"PLL_LOCK\", does not drive logic" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 86 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|sys_ctrl_standby"} { "Warning" "WAMERGE_DANGLING_ATOM_NO_TIE_OFF" "PLL_LOCK alta_rv32:rv32\|sys_ctrl_sleep " "Partition port \"alta_rv32:rv32\|sys_ctrl_sleep\", driven by node \"PLL_LOCK\", does not drive logic" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 86 -1 0 } }  } 0 35018 "Partition port \"%2!s!\", driven by node \"%1!s!\", does not drive logic" 0 0 "Quartus II" 0 -1 1778306621056 "|example_board|alta_rv32:rv32|sys_ctrl_sleep"} { "Warning" "WAMERGE_DANGLING_PORT_FOOTER" "20 " "Only the first 20 ports are reported. For a full list of ports, refer to the Partition Warnings panel in the Partition Merge report" {  } {  } 0 35039 "Only the first %1!d! ports are reported. For a full list of ports, refer to the Partition Warnings panel in the Partition Merge report" 0 0 "Quartus II" 0 -1 1778306621056 ""}  } {  } 0 35016 "Found partition port(s) not driving logic, possibly wasting area" 0 0 "Quartus II" 0 -1 1778306621056 ""}
{ "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 0 0 } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 170 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 -1 1778306621066 ""}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "PIN_HSE " "No output dependent on input pin \"PIN_HSE\"" {  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 25 0 0 } }  } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Quartus II" 0 -1 1778306621085 "|example_board|PIN_HSE"}  } {  } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Quartus II" 0 -1 1778306621085 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "1763 " "Implemented 1763 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1778306621087 ""} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Implemented 3 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1778306621087 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "8 " "Implemented 8 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 -1 1778306621087 ""} { "Info" "ICUT_CUT_TM_LCELLS" "1730 " "Implemented 1730 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1778306621087 ""} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Implemented 16 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Quartus II" 0 -1 1778306621087 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 -1 1778306621087 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1778306621087 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 25 s Quartus II 64-Bit " "Quartus II 64-Bit Partition Merge was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4641 " "Peak virtual memory: 4641 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306621194 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:41 2026 " "Processing ended: Sat May 09 14:03:41 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306621194 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306621194 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306621194 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778306621194 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778306622316 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306622317 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:41 2026 " "Processing started: Sat May 09 14:03:41 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306622317 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1778306622317 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off example_board -c example_board --check_ios " "Command: quartus_fit --read_settings_files=off --write_settings_files=off example_board -c example_board --check_ios" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1778306622317 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #3" {  } {  } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1778306622460 ""}
{ "Info" "0" "" "Project  = example_board" {  } {  } 0 0 "Project  = example_board" 0 0 "Fitter" 0 0 1778306622462 ""}
{ "Info" "0" "" "Revision = example_board" {  } {  } 0 0 "Revision = example_board" 0 0 "Fitter" 0 0 1778306622462 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1778306622551 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "example_board EP4CE75F29C8 " "Selected device EP4CE75F29C8 for design \"example_board\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1778306622576 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778306622624 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778306622624 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] 13 1 0 0 " "Implementing clock multiplication of 13, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] port" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1778306622815 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1778306622815 ""}
{ "Warning" "WFITCC_FITCC_WARNING_DANGEROUS_HOLD_TIMING_SCENARIO" "" "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" {  } {  } 0 171002 "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" 0 0 "Fitter" 0 -1 1778306622912 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C8 " "Device EP4CE40F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306623316 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C8 " "Device EP4CE30F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306623316 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C8 " "Device EP4CE55F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306623316 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29C8 " "Device EP4CE115F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306623316 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1778306623316 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4579 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306623326 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4581 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306623326 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4583 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306623326 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4585 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306623326 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4587 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306623326 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1778306623326 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1778306623329 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "15 15 " "No exact pin location assignment(s) for 15 pins of 15 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSE " "Pin PIN_HSE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 25 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_CSN " "Pin SPI0_CSN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_CSN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 28 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_CSN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SCK " "Pin SPI0_SCK not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SCK } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 29 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTTXD " "Pin UART0_UARTTXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTTXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 33 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTTXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BAUD_RATE " "Pin BAUD_RATE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_1 " "Pin GPIO4_1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 23 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_2 " "Pin GPIO4_2 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_2 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 24 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SI_IO0 " "Pin SPI0_SI_IO0 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SI_IO0 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 30 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SI_IO0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TEST_SINGLE " "Pin TEST_SINGLE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_RX " "Pin UART1_RX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_TX " "Pin UART1_TX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_TX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 35 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_TX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "so_io1 " "Pin so_io1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTRXD " "Pin UART0_UARTRXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTRXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 32 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTRXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSI " "Pin PIN_HSI not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSI } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PLL_CLKIN " "Pin PLL_CLKIN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PLL_CLKIN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 27 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_CLKIN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306624339 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1778306624339 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1) " "Promoted node altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "alta_gclksw:gclksw_inst\|gclk_switch Global Clock CLKCTRL_G3 " "Automatically promoted alta_gclksw:gclksw_inst\|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { alta_gclksw:gclksw_inst|clkout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1175 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306624411 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 36 2 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altpll:pll_inst|altpll_6o32:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306624411 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Promoted node PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "alta_gclksw:gclksw_inst\|gclk_switch Global Clock CLKCTRL_G3 " "Automatically promoted alta_gclksw:gclksw_inst\|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { alta_gclksw:gclksw_inst|clkout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1175 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306624412 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4563 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306624412 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "sys_resetn  " "Promoted node sys_resetn " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306624412 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 87 0 0 } } { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_resetn" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sys_resetn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 227 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306624412 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL_ENABLE  " "Automatically promoted node PLL_ENABLE " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306624412 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 85 -1 0 } } { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PLL_ENABLE" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_ENABLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1334 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306624412 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 3.3V 2 3 8 " "Number of I/O pins in group: 13 (unused VREF, 3.3V VCCIO, 2 input, 3 output, 8 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1778306624462 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1778306624462 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1778306624462 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 40 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  40 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 59 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 58 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 52 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 47 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 59 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 57 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  57 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306624463 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1778306624463 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1778306624463 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dmactive " "Node \"dmactive\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "dmactive" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[0\] " "Node \"ext_dma_DMACBREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[1\] " "Node \"ext_dma_DMACBREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[2\] " "Node \"ext_dma_DMACBREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[3\] " "Node \"ext_dma_DMACBREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[0\] " "Node \"ext_dma_DMACCLR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[1\] " "Node \"ext_dma_DMACCLR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[2\] " "Node \"ext_dma_DMACCLR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[3\] " "Node \"ext_dma_DMACCLR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[0\] " "Node \"ext_dma_DMACLBREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[1\] " "Node \"ext_dma_DMACLBREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[2\] " "Node \"ext_dma_DMACLBREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[3\] " "Node \"ext_dma_DMACLBREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[0\] " "Node \"ext_dma_DMACLSREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[1\] " "Node \"ext_dma_DMACLSREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[2\] " "Node \"ext_dma_DMACLSREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[3\] " "Node \"ext_dma_DMACLSREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[0\] " "Node \"ext_dma_DMACSREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[1\] " "Node \"ext_dma_DMACSREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[2\] " "Node \"ext_dma_DMACSREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[3\] " "Node \"ext_dma_DMACSREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[0\] " "Node \"ext_dma_DMACTC\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[1\] " "Node \"ext_dma_DMACTC\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[2\] " "Node \"ext_dma_DMACTC\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[3\] " "Node \"ext_dma_DMACTC\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[0\] " "Node \"ext_int\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[1\] " "Node \"ext_int\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[2\] " "Node \"ext_int\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[3\] " "Node \"ext_int\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[4\] " "Node \"ext_int\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[5\] " "Node \"ext_int\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[6\] " "Node \"ext_int\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[7\] " "Node \"ext_int\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_resetn " "Node \"ext_resetn\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_resetn" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[1\] " "Node \"gpio0_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[2\] " "Node \"gpio0_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[3\] " "Node \"gpio0_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[4\] " "Node \"gpio0_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[5\] " "Node \"gpio0_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[6\] " "Node \"gpio0_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[7\] " "Node \"gpio0_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[1\] " "Node \"gpio0_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[2\] " "Node \"gpio0_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[3\] " "Node \"gpio0_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[4\] " "Node \"gpio0_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[5\] " "Node \"gpio0_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[6\] " "Node \"gpio0_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[7\] " "Node \"gpio0_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[0\] " "Node \"gpio1_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[1\] " "Node \"gpio1_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[2\] " "Node \"gpio1_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[3\] " "Node \"gpio1_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[4\] " "Node \"gpio1_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[5\] " "Node \"gpio1_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[6\] " "Node \"gpio1_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[7\] " "Node \"gpio1_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[0\] " "Node \"gpio1_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[1\] " "Node \"gpio1_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[2\] " "Node \"gpio1_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[3\] " "Node \"gpio1_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[4\] " "Node \"gpio1_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[5\] " "Node \"gpio1_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[6\] " "Node \"gpio1_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[7\] " "Node \"gpio1_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[0\] " "Node \"gpio1_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[1\] " "Node \"gpio1_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[2\] " "Node \"gpio1_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[3\] " "Node \"gpio1_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[4\] " "Node \"gpio1_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[5\] " "Node \"gpio1_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[6\] " "Node \"gpio1_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[7\] " "Node \"gpio1_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[0\] " "Node \"gpio2_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[1\] " "Node \"gpio2_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[2\] " "Node \"gpio2_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[3\] " "Node \"gpio2_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[4\] " "Node \"gpio2_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[5\] " "Node \"gpio2_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[6\] " "Node \"gpio2_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[7\] " "Node \"gpio2_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[0\] " "Node \"gpio2_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[1\] " "Node \"gpio2_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[2\] " "Node \"gpio2_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[3\] " "Node \"gpio2_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[4\] " "Node \"gpio2_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[5\] " "Node \"gpio2_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[6\] " "Node \"gpio2_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[7\] " "Node \"gpio2_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[0\] " "Node \"gpio2_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[1\] " "Node \"gpio2_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[2\] " "Node \"gpio2_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[3\] " "Node \"gpio2_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[4\] " "Node \"gpio2_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[5\] " "Node \"gpio2_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[6\] " "Node \"gpio2_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[7\] " "Node \"gpio2_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[0\] " "Node \"gpio3_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[1\] " "Node \"gpio3_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[2\] " "Node \"gpio3_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[3\] " "Node \"gpio3_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[4\] " "Node \"gpio3_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[5\] " "Node \"gpio3_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[6\] " "Node \"gpio3_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[7\] " "Node \"gpio3_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[0\] " "Node \"gpio3_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[1\] " "Node \"gpio3_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[2\] " "Node \"gpio3_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[3\] " "Node \"gpio3_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[4\] " "Node \"gpio3_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[5\] " "Node \"gpio3_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[6\] " "Node \"gpio3_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[7\] " "Node \"gpio3_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[0\] " "Node \"gpio3_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[1\] " "Node \"gpio3_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[2\] " "Node \"gpio3_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[3\] " "Node \"gpio3_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[4\] " "Node \"gpio3_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[5\] " "Node \"gpio3_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[6\] " "Node \"gpio3_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[7\] " "Node \"gpio3_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[0\] " "Node \"gpio4_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[3\] " "Node \"gpio4_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[4\] " "Node \"gpio4_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[7\] " "Node \"gpio4_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[0\] " "Node \"gpio4_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[3\] " "Node \"gpio4_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[4\] " "Node \"gpio4_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[7\] " "Node \"gpio4_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[0\] " "Node \"gpio5_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[1\] " "Node \"gpio5_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[2\] " "Node \"gpio5_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[3\] " "Node \"gpio5_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[4\] " "Node \"gpio5_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[5\] " "Node \"gpio5_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[6\] " "Node \"gpio5_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[7\] " "Node \"gpio5_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[0\] " "Node \"gpio5_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[1\] " "Node \"gpio5_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[2\] " "Node \"gpio5_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[3\] " "Node \"gpio5_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[4\] " "Node \"gpio5_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[5\] " "Node \"gpio5_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[6\] " "Node \"gpio5_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[7\] " "Node \"gpio5_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[0\] " "Node \"gpio5_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[1\] " "Node \"gpio5_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[2\] " "Node \"gpio5_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[3\] " "Node \"gpio5_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[4\] " "Node \"gpio5_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[5\] " "Node \"gpio5_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[6\] " "Node \"gpio5_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[7\] " "Node \"gpio5_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[0\] " "Node \"gpio6_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[1\] " "Node \"gpio6_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[2\] " "Node \"gpio6_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[3\] " "Node \"gpio6_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[4\] " "Node \"gpio6_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[5\] " "Node \"gpio6_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[6\] " "Node \"gpio6_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[7\] " "Node \"gpio6_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[0\] " "Node \"gpio6_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[1\] " "Node \"gpio6_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[2\] " "Node \"gpio6_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[3\] " "Node \"gpio6_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[4\] " "Node \"gpio6_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[5\] " "Node \"gpio6_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[6\] " "Node \"gpio6_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[7\] " "Node \"gpio6_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[0\] " "Node \"gpio7_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[1\] " "Node \"gpio7_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[2\] " "Node \"gpio7_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[3\] " "Node \"gpio7_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[4\] " "Node \"gpio7_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[5\] " "Node \"gpio7_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[6\] " "Node \"gpio7_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[7\] " "Node \"gpio7_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[0\] " "Node \"gpio7_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[1\] " "Node \"gpio7_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[2\] " "Node \"gpio7_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[3\] " "Node \"gpio7_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[4\] " "Node \"gpio7_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[5\] " "Node \"gpio7_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[7\] " "Node \"gpio7_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[0\] " "Node \"gpio7_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[1\] " "Node \"gpio7_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[2\] " "Node \"gpio7_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[3\] " "Node \"gpio7_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[4\] " "Node \"gpio7_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[5\] " "Node \"gpio7_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[7\] " "Node \"gpio7_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[0\] " "Node \"gpio8_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[1\] " "Node \"gpio8_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[2\] " "Node \"gpio8_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[3\] " "Node \"gpio8_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[4\] " "Node \"gpio8_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[5\] " "Node \"gpio8_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[6\] " "Node \"gpio8_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[7\] " "Node \"gpio8_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[1\] " "Node \"gpio8_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[2\] " "Node \"gpio8_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[3\] " "Node \"gpio8_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[4\] " "Node \"gpio8_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[5\] " "Node \"gpio8_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[6\] " "Node \"gpio8_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[7\] " "Node \"gpio8_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[1\] " "Node \"gpio8_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[2\] " "Node \"gpio8_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[3\] " "Node \"gpio8_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[4\] " "Node \"gpio8_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[5\] " "Node \"gpio8_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[6\] " "Node \"gpio8_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[7\] " "Node \"gpio8_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[0\] " "Node \"gpio9_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[1\] " "Node \"gpio9_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[2\] " "Node \"gpio9_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[3\] " "Node \"gpio9_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[4\] " "Node \"gpio9_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[5\] " "Node \"gpio9_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[6\] " "Node \"gpio9_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[7\] " "Node \"gpio9_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[0\] " "Node \"gpio9_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[1\] " "Node \"gpio9_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[2\] " "Node \"gpio9_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[3\] " "Node \"gpio9_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[4\] " "Node \"gpio9_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[5\] " "Node \"gpio9_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[6\] " "Node \"gpio9_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[7\] " "Node \"gpio9_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[0\] " "Node \"gpio9_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[1\] " "Node \"gpio9_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[2\] " "Node \"gpio9_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[3\] " "Node \"gpio9_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[4\] " "Node \"gpio9_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[5\] " "Node \"gpio9_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[6\] " "Node \"gpio9_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[7\] " "Node \"gpio9_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[0\] " "Node \"local_int\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[1\] " "Node \"local_int\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[2\] " "Node \"local_int\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[3\] " "Node \"local_int\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[0\] " "Node \"mem_ahb_haddr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[10\] " "Node \"mem_ahb_haddr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[11\] " "Node \"mem_ahb_haddr\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[12\] " "Node \"mem_ahb_haddr\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[13\] " "Node \"mem_ahb_haddr\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[14\] " "Node \"mem_ahb_haddr\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[15\] " "Node \"mem_ahb_haddr\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[16\] " "Node \"mem_ahb_haddr\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[17\] " "Node \"mem_ahb_haddr\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[18\] " "Node \"mem_ahb_haddr\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[19\] " "Node \"mem_ahb_haddr\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[1\] " "Node \"mem_ahb_haddr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[20\] " "Node \"mem_ahb_haddr\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[21\] " "Node \"mem_ahb_haddr\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[22\] " "Node \"mem_ahb_haddr\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[23\] " "Node \"mem_ahb_haddr\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[24\] " "Node \"mem_ahb_haddr\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[25\] " "Node \"mem_ahb_haddr\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[26\] " "Node \"mem_ahb_haddr\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[27\] " "Node \"mem_ahb_haddr\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[28\] " "Node \"mem_ahb_haddr\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[29\] " "Node \"mem_ahb_haddr\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[2\] " "Node \"mem_ahb_haddr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[30\] " "Node \"mem_ahb_haddr\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[31\] " "Node \"mem_ahb_haddr\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[3\] " "Node \"mem_ahb_haddr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[4\] " "Node \"mem_ahb_haddr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[5\] " "Node \"mem_ahb_haddr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[6\] " "Node \"mem_ahb_haddr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[7\] " "Node \"mem_ahb_haddr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[8\] " "Node \"mem_ahb_haddr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[9\] " "Node \"mem_ahb_haddr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[0\] " "Node \"mem_ahb_hburst\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[1\] " "Node \"mem_ahb_hburst\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[2\] " "Node \"mem_ahb_hburst\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[0\] " "Node \"mem_ahb_hrdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[10\] " "Node \"mem_ahb_hrdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[11\] " "Node \"mem_ahb_hrdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[12\] " "Node \"mem_ahb_hrdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[13\] " "Node \"mem_ahb_hrdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[14\] " "Node \"mem_ahb_hrdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[15\] " "Node \"mem_ahb_hrdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[16\] " "Node \"mem_ahb_hrdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[17\] " "Node \"mem_ahb_hrdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[18\] " "Node \"mem_ahb_hrdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[19\] " "Node \"mem_ahb_hrdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[1\] " "Node \"mem_ahb_hrdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[20\] " "Node \"mem_ahb_hrdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[21\] " "Node \"mem_ahb_hrdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[22\] " "Node \"mem_ahb_hrdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[23\] " "Node \"mem_ahb_hrdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[24\] " "Node \"mem_ahb_hrdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[25\] " "Node \"mem_ahb_hrdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[26\] " "Node \"mem_ahb_hrdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[27\] " "Node \"mem_ahb_hrdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[28\] " "Node \"mem_ahb_hrdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[29\] " "Node \"mem_ahb_hrdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[2\] " "Node \"mem_ahb_hrdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[30\] " "Node \"mem_ahb_hrdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[31\] " "Node \"mem_ahb_hrdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[3\] " "Node \"mem_ahb_hrdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[4\] " "Node \"mem_ahb_hrdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[5\] " "Node \"mem_ahb_hrdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[6\] " "Node \"mem_ahb_hrdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[7\] " "Node \"mem_ahb_hrdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[8\] " "Node \"mem_ahb_hrdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[9\] " "Node \"mem_ahb_hrdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hready " "Node \"mem_ahb_hready\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hready" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hreadyout " "Node \"mem_ahb_hreadyout\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hreadyout" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hresp " "Node \"mem_ahb_hresp\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hresp" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[0\] " "Node \"mem_ahb_hsize\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[1\] " "Node \"mem_ahb_hsize\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[2\] " "Node \"mem_ahb_hsize\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_htrans\[0\] " "Node \"mem_ahb_htrans\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_htrans\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_htrans\[1\] " "Node \"mem_ahb_htrans\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_htrans\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[0\] " "Node \"mem_ahb_hwdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[10\] " "Node \"mem_ahb_hwdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[11\] " "Node \"mem_ahb_hwdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[12\] " "Node \"mem_ahb_hwdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[13\] " "Node \"mem_ahb_hwdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[14\] " "Node \"mem_ahb_hwdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[15\] " "Node \"mem_ahb_hwdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[16\] " "Node \"mem_ahb_hwdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[17\] " "Node \"mem_ahb_hwdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[18\] " "Node \"mem_ahb_hwdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[19\] " "Node \"mem_ahb_hwdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[1\] " "Node \"mem_ahb_hwdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[20\] " "Node \"mem_ahb_hwdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[21\] " "Node \"mem_ahb_hwdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[22\] " "Node \"mem_ahb_hwdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[23\] " "Node \"mem_ahb_hwdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[24\] " "Node \"mem_ahb_hwdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[25\] " "Node \"mem_ahb_hwdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[26\] " "Node \"mem_ahb_hwdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[27\] " "Node \"mem_ahb_hwdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[28\] " "Node \"mem_ahb_hwdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[29\] " "Node \"mem_ahb_hwdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[2\] " "Node \"mem_ahb_hwdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[30\] " "Node \"mem_ahb_hwdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[31\] " "Node \"mem_ahb_hwdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[3\] " "Node \"mem_ahb_hwdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[4\] " "Node \"mem_ahb_hwdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[5\] " "Node \"mem_ahb_hwdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[6\] " "Node \"mem_ahb_hwdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[7\] " "Node \"mem_ahb_hwdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[8\] " "Node \"mem_ahb_hwdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[9\] " "Node \"mem_ahb_hwdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwrite " "Node \"mem_ahb_hwrite\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwrite" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "resetn_out " "Node \"resetn_out\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "resetn_out" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[0\] " "Node \"slave_ahb_haddr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[10\] " "Node \"slave_ahb_haddr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[11\] " "Node \"slave_ahb_haddr\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[12\] " "Node \"slave_ahb_haddr\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[13\] " "Node \"slave_ahb_haddr\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[14\] " "Node \"slave_ahb_haddr\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[15\] " "Node \"slave_ahb_haddr\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[16\] " "Node \"slave_ahb_haddr\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[17\] " "Node \"slave_ahb_haddr\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[18\] " "Node \"slave_ahb_haddr\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[19\] " "Node \"slave_ahb_haddr\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[1\] " "Node \"slave_ahb_haddr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[20\] " "Node \"slave_ahb_haddr\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[21\] " "Node \"slave_ahb_haddr\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[22\] " "Node \"slave_ahb_haddr\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[23\] " "Node \"slave_ahb_haddr\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[24\] " "Node \"slave_ahb_haddr\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[25\] " "Node \"slave_ahb_haddr\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[26\] " "Node \"slave_ahb_haddr\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[27\] " "Node \"slave_ahb_haddr\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[28\] " "Node \"slave_ahb_haddr\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[29\] " "Node \"slave_ahb_haddr\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[2\] " "Node \"slave_ahb_haddr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[30\] " "Node \"slave_ahb_haddr\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[31\] " "Node \"slave_ahb_haddr\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[3\] " "Node \"slave_ahb_haddr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[4\] " "Node \"slave_ahb_haddr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[5\] " "Node \"slave_ahb_haddr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[6\] " "Node \"slave_ahb_haddr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[7\] " "Node \"slave_ahb_haddr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[8\] " "Node \"slave_ahb_haddr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[9\] " "Node \"slave_ahb_haddr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[0\] " "Node \"slave_ahb_hburst\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[1\] " "Node \"slave_ahb_hburst\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[2\] " "Node \"slave_ahb_hburst\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[0\] " "Node \"slave_ahb_hrdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[10\] " "Node \"slave_ahb_hrdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[11\] " "Node \"slave_ahb_hrdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[12\] " "Node \"slave_ahb_hrdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[13\] " "Node \"slave_ahb_hrdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[14\] " "Node \"slave_ahb_hrdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[15\] " "Node \"slave_ahb_hrdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[16\] " "Node \"slave_ahb_hrdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[17\] " "Node \"slave_ahb_hrdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[18\] " "Node \"slave_ahb_hrdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[19\] " "Node \"slave_ahb_hrdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[1\] " "Node \"slave_ahb_hrdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[20\] " "Node \"slave_ahb_hrdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[21\] " "Node \"slave_ahb_hrdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[22\] " "Node \"slave_ahb_hrdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[23\] " "Node \"slave_ahb_hrdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[24\] " "Node \"slave_ahb_hrdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[25\] " "Node \"slave_ahb_hrdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[26\] " "Node \"slave_ahb_hrdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[27\] " "Node \"slave_ahb_hrdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[28\] " "Node \"slave_ahb_hrdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[29\] " "Node \"slave_ahb_hrdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[2\] " "Node \"slave_ahb_hrdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[30\] " "Node \"slave_ahb_hrdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[31\] " "Node \"slave_ahb_hrdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[3\] " "Node \"slave_ahb_hrdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[4\] " "Node \"slave_ahb_hrdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[5\] " "Node \"slave_ahb_hrdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[6\] " "Node \"slave_ahb_hrdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[7\] " "Node \"slave_ahb_hrdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[8\] " "Node \"slave_ahb_hrdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[9\] " "Node \"slave_ahb_hrdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hready " "Node \"slave_ahb_hready\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hready" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hreadyout " "Node \"slave_ahb_hreadyout\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hreadyout" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hresp " "Node \"slave_ahb_hresp\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hresp" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsel " "Node \"slave_ahb_hsel\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsel" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[0\] " "Node \"slave_ahb_hsize\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[1\] " "Node \"slave_ahb_hsize\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[2\] " "Node \"slave_ahb_hsize\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_htrans\[0\] " "Node \"slave_ahb_htrans\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_htrans\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_htrans\[1\] " "Node \"slave_ahb_htrans\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_htrans\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[0\] " "Node \"slave_ahb_hwdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[10\] " "Node \"slave_ahb_hwdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[11\] " "Node \"slave_ahb_hwdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[12\] " "Node \"slave_ahb_hwdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[13\] " "Node \"slave_ahb_hwdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[14\] " "Node \"slave_ahb_hwdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[15\] " "Node \"slave_ahb_hwdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[16\] " "Node \"slave_ahb_hwdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[17\] " "Node \"slave_ahb_hwdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[18\] " "Node \"slave_ahb_hwdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[19\] " "Node \"slave_ahb_hwdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[1\] " "Node \"slave_ahb_hwdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[20\] " "Node \"slave_ahb_hwdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[21\] " "Node \"slave_ahb_hwdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[22\] " "Node \"slave_ahb_hwdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[23\] " "Node \"slave_ahb_hwdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[24\] " "Node \"slave_ahb_hwdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[25\] " "Node \"slave_ahb_hwdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[26\] " "Node \"slave_ahb_hwdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[27\] " "Node \"slave_ahb_hwdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[28\] " "Node \"slave_ahb_hwdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[29\] " "Node \"slave_ahb_hwdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[2\] " "Node \"slave_ahb_hwdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[30\] " "Node \"slave_ahb_hwdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[31\] " "Node \"slave_ahb_hwdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[3\] " "Node \"slave_ahb_hwdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[4\] " "Node \"slave_ahb_hwdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[5\] " "Node \"slave_ahb_hwdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[6\] " "Node \"slave_ahb_hwdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[7\] " "Node \"slave_ahb_hwdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[8\] " "Node \"slave_ahb_hwdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[9\] " "Node \"slave_ahb_hwdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwrite " "Node \"slave_ahb_hwrite\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwrite" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_hseBypass " "Node \"sys_ctrl_hseBypass\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_hseBypass" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_hseEnable " "Node \"sys_ctrl_hseEnable\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_hseEnable" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_pllEnable " "Node \"sys_ctrl_pllEnable\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_pllEnable" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_sleep " "Node \"sys_ctrl_sleep\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_sleep" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_standby " "Node \"sys_ctrl_standby\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_standby" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "usb0_id " "Node \"usb0_id\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "usb0_id" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306625324 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1778306625324 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:02 " "Fitter preparation operations ending: elapsed time is 00:00:02" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306625357 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1778306625699 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "15 Cyclone IV E " "15 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PIN_HSE 3.3-V LVTTL G5 " "Pin PIN_HSE uses I/O standard 3.3-V LVTTL at G5" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 25 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_CSN 3.3-V LVTTL G6 " "Pin SPI0_CSN uses I/O standard 3.3-V LVTTL at G6" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_CSN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 28 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_CSN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_SCK 3.3-V LVTTL F1 " "Pin SPI0_SCK uses I/O standard 3.3-V LVTTL at F1" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SCK } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 29 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART0_UARTTXD 3.3-V LVTTL M3 " "Pin UART0_UARTTXD uses I/O standard 3.3-V LVTTL at M3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTTXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 33 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTTXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BAUD_RATE 3.3-V LVTTL C2 " "Pin BAUD_RATE uses I/O standard 3.3-V LVTTL at C2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO4_1 3.3-V LVTTL H3 " "Pin GPIO4_1 uses I/O standard 3.3-V LVTTL at H3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 23 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO4_2 3.3-V LVTTL L3 " "Pin GPIO4_2 uses I/O standard 3.3-V LVTTL at L3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_2 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 24 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_SI_IO0 3.3-V LVTTL D2 " "Pin SPI0_SI_IO0 uses I/O standard 3.3-V LVTTL at D2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SI_IO0 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 30 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SI_IO0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TEST_SINGLE 3.3-V LVTTL E1 " "Pin TEST_SINGLE uses I/O standard 3.3-V LVTTL at E1" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART1_RX 3.3-V LVTTL M4 " "Pin UART1_RX uses I/O standard 3.3-V LVTTL at M4" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART1_TX 3.3-V LVTTL D1 " "Pin UART1_TX uses I/O standard 3.3-V LVTTL at D1" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_TX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 35 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_TX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "so_io1 3.3-V LVTTL F2 " "Pin so_io1 uses I/O standard 3.3-V LVTTL at F2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART0_UARTRXD 3.3-V LVTTL E3 " "Pin UART0_UARTRXD uses I/O standard 3.3-V LVTTL at E3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTRXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 32 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTRXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PIN_HSI 3.3-V LVTTL Y2 " "Pin PIN_HSI uses I/O standard 3.3-V LVTTL at Y2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSI } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PLL_CLKIN 3.3-V LVTTL J1 " "Pin PLL_CLKIN uses I/O standard 3.3-V LVTTL at J1" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PLL_CLKIN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 27 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_CLKIN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306625709 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1778306625709 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "4 " "Following 4 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "BAUD_RATE a permanently disabled " "Pin BAUD_RATE has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306625711 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "TEST_SINGLE a permanently disabled " "Pin TEST_SINGLE has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306625711 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "UART1_RX a permanently disabled " "Pin UART1_RX has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306625711 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "so_io1 a permanently disabled " "Pin so_io1 has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306625711 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1778306625711 ""}
{ "Info" "IQFIT_LEGACY_FLOW_QID_AND_CHECK_IO_COMPILE" "" "Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled" {  } {  } 0 11763 "Results from the I/O assignment analysis compilation cannot be preserved because I/O assignment analysis was run with Incremental Compilation enabled" 0 0 "Fitter" 0 -1 1778306625881 ""}
{ "Info" "IQEXE_ERROR_COUNT" "I/O Assignment Analysis 0 s 471 s Quartus II 64-Bit " "Quartus II 64-Bit I/O Assignment Analysis was successful. 0 errors, 471 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4899 " "Peak virtual memory: 4899 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306625905 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:03:45 2026 " "Processing ended: Sat May 09 14:03:45 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306625905 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306625905 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306625905 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1778306625905 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1778306626961 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II 64-Bit " "Running Quartus II 64-Bit Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306626961 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:03:46 2026 " "Processing started: Sat May 09 14:03:46 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306626961 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1778306626961 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off example_board -c example_board " "Command: quartus_fit --read_settings_files=off --write_settings_files=off example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1778306626961 ""}
{ "Info" "0" "" "qfit2_default_script.tcl version: #3" {  } {  } 0 0 "qfit2_default_script.tcl version: #3" 0 0 "Fitter" 0 0 1778306627058 ""}
{ "Info" "0" "" "Project  = example_board" {  } {  } 0 0 "Project  = example_board" 0 0 "Fitter" 0 0 1778306627058 ""}
{ "Info" "0" "" "Revision = example_board" {  } {  } 0 0 "Revision = example_board" 0 0 "Fitter" 0 0 1778306627058 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1778306627159 ""}
{ "Info" "IMPP_MPP_USER_DEVICE" "example_board EP4CE75F29C8 " "Selected device EP4CE75F29C8 for design \"example_board\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1778306627181 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778306627227 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1778306627227 ""}
{ "Info" "ICUT_CUT_PLL_COMPUTATION_SUCCESS" "altpll:pll_inst\|altpll_6o32:auto_generated\|pll1 Cyclone IV E PLL " "Implemented PLL \"altpll:pll_inst\|altpll_6o32:auto_generated\|pll1\" as Cyclone IV E PLL type" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] 13 1 0 0 " "Implementing clock multiplication of 13, clock division of 1, and phase shift of 0 degrees (0 ps) for altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] port" {  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 15099 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "Quartus II" 0 -1 1778306627299 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 30 2 0 } } { "" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 15535 "Implemented %3!s! \"%1!s!\" as %2!s! PLL type" 0 0 "Fitter" 0 -1 1778306627299 ""}
{ "Info" "IFITCC_FITCC_INFO_STANDARD_FIT_COMPILATION_ON" "" "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" {  } {  } 0 171004 "Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance" 0 0 "Fitter" 0 -1 1778306627337 ""}
{ "Warning" "WFITCC_FITCC_WARNING_DANGEROUS_HOLD_TIMING_SCENARIO" "" "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" {  } {  } 0 171002 "Current optimization assignments may cause the Fitter to introduce hold timing violations on connections clocked by global signals" 0 0 "Fitter" 0 -1 1778306627337 ""}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE40F29C8 " "Device EP4CE40F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306627717 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE30F29C8 " "Device EP4CE30F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306627717 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE55F29C8 " "Device EP4CE55F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306627717 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE115F29C8 " "Device EP4CE115F29C8 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1778306627717 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1778306627717 ""}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ F4 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location F4" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_ASDO_DATA1~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4579 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306627720 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ E2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location E2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_FLASH_nCE_nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4581 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306627720 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ P3 " "Pin ~ALTERA_DCLK~ is reserved at location P3" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DCLK~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4583 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306627720 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ N7 " "Pin ~ALTERA_DATA0~ is reserved at location N7" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4585 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306627720 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ P28 " "Pin ~ALTERA_nCEO~ is reserved at location P28" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ALTERA_nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4587 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1778306627720 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1778306627720 ""}
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" {  } {  } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1778306627721 ""}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1778306627728 ""}
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "15 15 " "No exact pin location assignment(s) for 15 pins of 15 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSE " "Pin PIN_HSE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 25 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_CSN " "Pin SPI0_CSN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_CSN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 28 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_CSN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SCK " "Pin SPI0_SCK not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SCK } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 29 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTTXD " "Pin UART0_UARTTXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTTXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 33 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTTXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "BAUD_RATE " "Pin BAUD_RATE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_1 " "Pin GPIO4_1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 23 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "GPIO4_2 " "Pin GPIO4_2 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_2 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 24 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SPI0_SI_IO0 " "Pin SPI0_SI_IO0 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SI_IO0 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 30 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SI_IO0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "TEST_SINGLE " "Pin TEST_SINGLE not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_RX " "Pin UART1_RX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART1_TX " "Pin UART1_TX not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_TX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 35 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_TX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "so_io1 " "Pin so_io1 not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "UART0_UARTRXD " "Pin UART0_UARTRXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTRXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 32 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTRXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PIN_HSI " "Pin PIN_HSI not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSI } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "PLL_CLKIN " "Pin PLL_CLKIN not assigned to an exact location on the device" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PLL_CLKIN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 27 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_CLKIN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1778306628706 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1778306628706 ""}
{ "Info" "ISTA_SDC_FOUND" "example_board.sdc " "Reading SDC File: 'example_board.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1778306629063 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN " "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629070 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629070 ""}  } {  } 0 332110 "%1!s!" 0 0 "Fitter" 0 -1 1778306629070 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "example_board.sdc 13 rv32\|resetn_out clock or keeper or register or port or pin or cell or partition " "Ignored filter at example_board.sdc(13): rv32\|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Fitter" 0 -1 1778306629071 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_false_path example_board.sdc 13 Argument <from> is not an object ID " "Ignored set_false_path at example_board.sdc(13): Argument <from> is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_false_path -from rv32\|resetn_out " "set_false_path -from rv32\|resetn_out" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629071 ""}  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Fitter" 0 -1 1778306629071 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "PIN_HSI (Rise) PIN_HSI (Rise) setup and hold " "From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) to pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306629083 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1778306629083 ""}
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1778306629083 ""}
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 4 clocks " "Found 4 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000      PIN_HSE " " 125.000      PIN_HSE" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000    PLL_CLKIN " " 125.000    PLL_CLKIN" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   9.615 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1778306629083 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1778306629083 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1) " "Promoted node altpll:pll_inst\|altpll_6o32:auto_generated\|clk\[0\] (placed in counter C0 of PLL_1)" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "alta_gclksw:gclksw_inst\|gclk_switch Global Clock CLKCTRL_G3 " "Automatically promoted alta_gclksw:gclksw_inst\|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { alta_gclksw:gclksw_inst|clkout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1175 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306629148 ""}  } { { "db/altpll_6o32.tdf" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/db/altpll_6o32.tdf" 36 2 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { altpll:pll_inst|altpll_6o32:auto_generated|clk[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1178 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306629148 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p)) " "Promoted node PIN_HSI~input (placed in PIN Y2 (CLK2, DIFFCLK_1p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "alta_gclksw:gclksw_inst\|gclk_switch Global Clock CLKCTRL_G3 " "Automatically promoted alta_gclksw:gclksw_inst\|gclk_switch to use location or clock signal Global Clock CLKCTRL_G3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3711 -1 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { alta_gclksw:gclksw_inst|clkout } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1175 9224 9983 0}  }  } }  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306629149 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI~input } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 4563 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306629149 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL" "sys_resetn  " "Promoted node sys_resetn " { { "Info" "IFSAC_FSAC_ASSIGN_USER_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176354 "Promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306629149 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 87 0 0 } } { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_resetn" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sys_resetn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 227 9224 9983 0}  }  } }  } 0 176352 "Promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306629149 ""}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "PLL_ENABLE  " "Automatically promoted node PLL_ENABLE " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1778306629149 ""}  } { { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 85 -1 0 } } { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PLL_ENABLE" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_ENABLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 1334 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1778306629149 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1778306629524 ""}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1778306629525 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1778306629525 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1778306629528 ""}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1778306629529 ""}
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1778306629530 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1778306629530 ""}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1778306629532 ""}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1778306629533 ""}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1778306629535 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1778306629535 ""}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "13 unused 3.3V 2 3 8 " "Number of I/O pins in group: 13 (unused VREF, 3.3V VCCIO, 2 input, 3 output, 8 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1778306629537 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1778306629537 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1778306629537 ""}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 40 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used --  40 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 48 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  48 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 59 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 58 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  58 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 52 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  52 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 47 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used --  47 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 59 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  59 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 57 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  57 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1778306629538 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1778306629538 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1778306629538 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1778306629570 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1778306630280 ""}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "dmactive " "Node \"dmactive\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "dmactive" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[0\] " "Node \"ext_dma_DMACBREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[1\] " "Node \"ext_dma_DMACBREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[2\] " "Node \"ext_dma_DMACBREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACBREQ\[3\] " "Node \"ext_dma_DMACBREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACBREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[0\] " "Node \"ext_dma_DMACCLR\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[1\] " "Node \"ext_dma_DMACCLR\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[2\] " "Node \"ext_dma_DMACCLR\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACCLR\[3\] " "Node \"ext_dma_DMACCLR\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACCLR\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[0\] " "Node \"ext_dma_DMACLBREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[1\] " "Node \"ext_dma_DMACLBREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[2\] " "Node \"ext_dma_DMACLBREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLBREQ\[3\] " "Node \"ext_dma_DMACLBREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLBREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[0\] " "Node \"ext_dma_DMACLSREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[1\] " "Node \"ext_dma_DMACLSREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[2\] " "Node \"ext_dma_DMACLSREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACLSREQ\[3\] " "Node \"ext_dma_DMACLSREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACLSREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[0\] " "Node \"ext_dma_DMACSREQ\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[1\] " "Node \"ext_dma_DMACSREQ\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[2\] " "Node \"ext_dma_DMACSREQ\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACSREQ\[3\] " "Node \"ext_dma_DMACSREQ\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACSREQ\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[0\] " "Node \"ext_dma_DMACTC\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[1\] " "Node \"ext_dma_DMACTC\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[2\] " "Node \"ext_dma_DMACTC\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_dma_DMACTC\[3\] " "Node \"ext_dma_DMACTC\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_dma_DMACTC\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[0\] " "Node \"ext_int\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[1\] " "Node \"ext_int\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[2\] " "Node \"ext_int\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[3\] " "Node \"ext_int\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[4\] " "Node \"ext_int\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[5\] " "Node \"ext_int\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[6\] " "Node \"ext_int\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_int\[7\] " "Node \"ext_int\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_int\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "ext_resetn " "Node \"ext_resetn\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "ext_resetn" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[1\] " "Node \"gpio0_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[2\] " "Node \"gpio0_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[3\] " "Node \"gpio0_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[4\] " "Node \"gpio0_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[5\] " "Node \"gpio0_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[6\] " "Node \"gpio0_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_data\[7\] " "Node \"gpio0_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[1\] " "Node \"gpio0_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[2\] " "Node \"gpio0_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[3\] " "Node \"gpio0_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[4\] " "Node \"gpio0_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[5\] " "Node \"gpio0_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[6\] " "Node \"gpio0_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio0_io_out_en\[7\] " "Node \"gpio0_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio0_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[0\] " "Node \"gpio1_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[1\] " "Node \"gpio1_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[2\] " "Node \"gpio1_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[3\] " "Node \"gpio1_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[4\] " "Node \"gpio1_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[5\] " "Node \"gpio1_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[6\] " "Node \"gpio1_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_in\[7\] " "Node \"gpio1_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[0\] " "Node \"gpio1_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[1\] " "Node \"gpio1_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[2\] " "Node \"gpio1_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[3\] " "Node \"gpio1_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[4\] " "Node \"gpio1_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[5\] " "Node \"gpio1_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[6\] " "Node \"gpio1_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_data\[7\] " "Node \"gpio1_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[0\] " "Node \"gpio1_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[1\] " "Node \"gpio1_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[2\] " "Node \"gpio1_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[3\] " "Node \"gpio1_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[4\] " "Node \"gpio1_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[5\] " "Node \"gpio1_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[6\] " "Node \"gpio1_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio1_io_out_en\[7\] " "Node \"gpio1_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio1_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[0\] " "Node \"gpio2_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[1\] " "Node \"gpio2_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[2\] " "Node \"gpio2_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[3\] " "Node \"gpio2_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[4\] " "Node \"gpio2_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[5\] " "Node \"gpio2_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[6\] " "Node \"gpio2_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_in\[7\] " "Node \"gpio2_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[0\] " "Node \"gpio2_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[1\] " "Node \"gpio2_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[2\] " "Node \"gpio2_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[3\] " "Node \"gpio2_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[4\] " "Node \"gpio2_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[5\] " "Node \"gpio2_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[6\] " "Node \"gpio2_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_data\[7\] " "Node \"gpio2_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[0\] " "Node \"gpio2_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[1\] " "Node \"gpio2_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[2\] " "Node \"gpio2_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[3\] " "Node \"gpio2_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[4\] " "Node \"gpio2_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[5\] " "Node \"gpio2_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[6\] " "Node \"gpio2_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio2_io_out_en\[7\] " "Node \"gpio2_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio2_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[0\] " "Node \"gpio3_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[1\] " "Node \"gpio3_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[2\] " "Node \"gpio3_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[3\] " "Node \"gpio3_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[4\] " "Node \"gpio3_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[5\] " "Node \"gpio3_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[6\] " "Node \"gpio3_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_in\[7\] " "Node \"gpio3_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[0\] " "Node \"gpio3_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[1\] " "Node \"gpio3_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[2\] " "Node \"gpio3_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[3\] " "Node \"gpio3_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[4\] " "Node \"gpio3_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[5\] " "Node \"gpio3_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[6\] " "Node \"gpio3_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_data\[7\] " "Node \"gpio3_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[0\] " "Node \"gpio3_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[1\] " "Node \"gpio3_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[2\] " "Node \"gpio3_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[3\] " "Node \"gpio3_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[4\] " "Node \"gpio3_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[5\] " "Node \"gpio3_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[6\] " "Node \"gpio3_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio3_io_out_en\[7\] " "Node \"gpio3_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio3_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[0\] " "Node \"gpio4_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[3\] " "Node \"gpio4_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[4\] " "Node \"gpio4_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_data\[7\] " "Node \"gpio4_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[0\] " "Node \"gpio4_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[3\] " "Node \"gpio4_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[4\] " "Node \"gpio4_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio4_io_out_en\[7\] " "Node \"gpio4_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio4_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[0\] " "Node \"gpio5_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[1\] " "Node \"gpio5_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[2\] " "Node \"gpio5_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[3\] " "Node \"gpio5_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[4\] " "Node \"gpio5_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[5\] " "Node \"gpio5_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[6\] " "Node \"gpio5_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_in\[7\] " "Node \"gpio5_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[0\] " "Node \"gpio5_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[1\] " "Node \"gpio5_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[2\] " "Node \"gpio5_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[3\] " "Node \"gpio5_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[4\] " "Node \"gpio5_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[5\] " "Node \"gpio5_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[6\] " "Node \"gpio5_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_data\[7\] " "Node \"gpio5_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[0\] " "Node \"gpio5_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[1\] " "Node \"gpio5_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[2\] " "Node \"gpio5_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[3\] " "Node \"gpio5_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[4\] " "Node \"gpio5_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[5\] " "Node \"gpio5_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[6\] " "Node \"gpio5_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio5_io_out_en\[7\] " "Node \"gpio5_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio5_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[0\] " "Node \"gpio6_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[1\] " "Node \"gpio6_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[2\] " "Node \"gpio6_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[3\] " "Node \"gpio6_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[4\] " "Node \"gpio6_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[5\] " "Node \"gpio6_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[6\] " "Node \"gpio6_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_data\[7\] " "Node \"gpio6_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[0\] " "Node \"gpio6_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[1\] " "Node \"gpio6_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[2\] " "Node \"gpio6_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[3\] " "Node \"gpio6_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[4\] " "Node \"gpio6_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[5\] " "Node \"gpio6_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[6\] " "Node \"gpio6_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio6_io_out_en\[7\] " "Node \"gpio6_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio6_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[0\] " "Node \"gpio7_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[1\] " "Node \"gpio7_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[2\] " "Node \"gpio7_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[3\] " "Node \"gpio7_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[4\] " "Node \"gpio7_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[5\] " "Node \"gpio7_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[6\] " "Node \"gpio7_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_in\[7\] " "Node \"gpio7_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[0\] " "Node \"gpio7_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[1\] " "Node \"gpio7_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[2\] " "Node \"gpio7_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[3\] " "Node \"gpio7_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[4\] " "Node \"gpio7_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[5\] " "Node \"gpio7_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_data\[7\] " "Node \"gpio7_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[0\] " "Node \"gpio7_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[1\] " "Node \"gpio7_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[2\] " "Node \"gpio7_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[3\] " "Node \"gpio7_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[4\] " "Node \"gpio7_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[5\] " "Node \"gpio7_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio7_io_out_en\[7\] " "Node \"gpio7_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio7_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[0\] " "Node \"gpio8_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[1\] " "Node \"gpio8_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[2\] " "Node \"gpio8_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[3\] " "Node \"gpio8_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[4\] " "Node \"gpio8_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[5\] " "Node \"gpio8_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[6\] " "Node \"gpio8_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_in\[7\] " "Node \"gpio8_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[1\] " "Node \"gpio8_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[2\] " "Node \"gpio8_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[3\] " "Node \"gpio8_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[4\] " "Node \"gpio8_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[5\] " "Node \"gpio8_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[6\] " "Node \"gpio8_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_data\[7\] " "Node \"gpio8_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[1\] " "Node \"gpio8_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[2\] " "Node \"gpio8_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[3\] " "Node \"gpio8_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[4\] " "Node \"gpio8_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[5\] " "Node \"gpio8_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[6\] " "Node \"gpio8_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio8_io_out_en\[7\] " "Node \"gpio8_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio8_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[0\] " "Node \"gpio9_io_in\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[1\] " "Node \"gpio9_io_in\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[2\] " "Node \"gpio9_io_in\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[3\] " "Node \"gpio9_io_in\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[4\] " "Node \"gpio9_io_in\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[5\] " "Node \"gpio9_io_in\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[6\] " "Node \"gpio9_io_in\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_in\[7\] " "Node \"gpio9_io_in\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_in\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[0\] " "Node \"gpio9_io_out_data\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[1\] " "Node \"gpio9_io_out_data\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[2\] " "Node \"gpio9_io_out_data\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[3\] " "Node \"gpio9_io_out_data\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[4\] " "Node \"gpio9_io_out_data\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[5\] " "Node \"gpio9_io_out_data\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[6\] " "Node \"gpio9_io_out_data\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_data\[7\] " "Node \"gpio9_io_out_data\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_data\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[0\] " "Node \"gpio9_io_out_en\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[1\] " "Node \"gpio9_io_out_en\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[2\] " "Node \"gpio9_io_out_en\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[3\] " "Node \"gpio9_io_out_en\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[4\] " "Node \"gpio9_io_out_en\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[5\] " "Node \"gpio9_io_out_en\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[6\] " "Node \"gpio9_io_out_en\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "gpio9_io_out_en\[7\] " "Node \"gpio9_io_out_en\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "gpio9_io_out_en\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[0\] " "Node \"local_int\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[1\] " "Node \"local_int\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[2\] " "Node \"local_int\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "local_int\[3\] " "Node \"local_int\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "local_int\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[0\] " "Node \"mem_ahb_haddr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[10\] " "Node \"mem_ahb_haddr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[11\] " "Node \"mem_ahb_haddr\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[12\] " "Node \"mem_ahb_haddr\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[13\] " "Node \"mem_ahb_haddr\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[14\] " "Node \"mem_ahb_haddr\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[15\] " "Node \"mem_ahb_haddr\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[16\] " "Node \"mem_ahb_haddr\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[17\] " "Node \"mem_ahb_haddr\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[18\] " "Node \"mem_ahb_haddr\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[19\] " "Node \"mem_ahb_haddr\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[1\] " "Node \"mem_ahb_haddr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[20\] " "Node \"mem_ahb_haddr\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[21\] " "Node \"mem_ahb_haddr\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[22\] " "Node \"mem_ahb_haddr\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[23\] " "Node \"mem_ahb_haddr\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[24\] " "Node \"mem_ahb_haddr\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[25\] " "Node \"mem_ahb_haddr\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[26\] " "Node \"mem_ahb_haddr\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[27\] " "Node \"mem_ahb_haddr\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[28\] " "Node \"mem_ahb_haddr\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[29\] " "Node \"mem_ahb_haddr\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[2\] " "Node \"mem_ahb_haddr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[30\] " "Node \"mem_ahb_haddr\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[31\] " "Node \"mem_ahb_haddr\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[3\] " "Node \"mem_ahb_haddr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[4\] " "Node \"mem_ahb_haddr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[5\] " "Node \"mem_ahb_haddr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[6\] " "Node \"mem_ahb_haddr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[7\] " "Node \"mem_ahb_haddr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[8\] " "Node \"mem_ahb_haddr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_haddr\[9\] " "Node \"mem_ahb_haddr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_haddr\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[0\] " "Node \"mem_ahb_hburst\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[1\] " "Node \"mem_ahb_hburst\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hburst\[2\] " "Node \"mem_ahb_hburst\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hburst\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[0\] " "Node \"mem_ahb_hrdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[10\] " "Node \"mem_ahb_hrdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[11\] " "Node \"mem_ahb_hrdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[12\] " "Node \"mem_ahb_hrdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[13\] " "Node \"mem_ahb_hrdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[14\] " "Node \"mem_ahb_hrdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[15\] " "Node \"mem_ahb_hrdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[16\] " "Node \"mem_ahb_hrdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[17\] " "Node \"mem_ahb_hrdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[18\] " "Node \"mem_ahb_hrdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[19\] " "Node \"mem_ahb_hrdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[1\] " "Node \"mem_ahb_hrdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[20\] " "Node \"mem_ahb_hrdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[21\] " "Node \"mem_ahb_hrdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[22\] " "Node \"mem_ahb_hrdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[23\] " "Node \"mem_ahb_hrdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[24\] " "Node \"mem_ahb_hrdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[25\] " "Node \"mem_ahb_hrdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[26\] " "Node \"mem_ahb_hrdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[27\] " "Node \"mem_ahb_hrdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[28\] " "Node \"mem_ahb_hrdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[29\] " "Node \"mem_ahb_hrdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[2\] " "Node \"mem_ahb_hrdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[30\] " "Node \"mem_ahb_hrdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[31\] " "Node \"mem_ahb_hrdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[3\] " "Node \"mem_ahb_hrdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[4\] " "Node \"mem_ahb_hrdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[5\] " "Node \"mem_ahb_hrdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[6\] " "Node \"mem_ahb_hrdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[7\] " "Node \"mem_ahb_hrdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[8\] " "Node \"mem_ahb_hrdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hrdata\[9\] " "Node \"mem_ahb_hrdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hrdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hready " "Node \"mem_ahb_hready\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hready" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hreadyout " "Node \"mem_ahb_hreadyout\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hreadyout" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hresp " "Node \"mem_ahb_hresp\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hresp" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[0\] " "Node \"mem_ahb_hsize\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[1\] " "Node \"mem_ahb_hsize\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hsize\[2\] " "Node \"mem_ahb_hsize\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hsize\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_htrans\[0\] " "Node \"mem_ahb_htrans\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_htrans\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_htrans\[1\] " "Node \"mem_ahb_htrans\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_htrans\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[0\] " "Node \"mem_ahb_hwdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[10\] " "Node \"mem_ahb_hwdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[11\] " "Node \"mem_ahb_hwdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[12\] " "Node \"mem_ahb_hwdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[13\] " "Node \"mem_ahb_hwdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[14\] " "Node \"mem_ahb_hwdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[15\] " "Node \"mem_ahb_hwdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[16\] " "Node \"mem_ahb_hwdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[17\] " "Node \"mem_ahb_hwdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[18\] " "Node \"mem_ahb_hwdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[19\] " "Node \"mem_ahb_hwdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[1\] " "Node \"mem_ahb_hwdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[20\] " "Node \"mem_ahb_hwdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[21\] " "Node \"mem_ahb_hwdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[22\] " "Node \"mem_ahb_hwdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[23\] " "Node \"mem_ahb_hwdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[24\] " "Node \"mem_ahb_hwdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[25\] " "Node \"mem_ahb_hwdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[26\] " "Node \"mem_ahb_hwdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[27\] " "Node \"mem_ahb_hwdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[28\] " "Node \"mem_ahb_hwdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[29\] " "Node \"mem_ahb_hwdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[2\] " "Node \"mem_ahb_hwdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[30\] " "Node \"mem_ahb_hwdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[31\] " "Node \"mem_ahb_hwdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[3\] " "Node \"mem_ahb_hwdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[4\] " "Node \"mem_ahb_hwdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[5\] " "Node \"mem_ahb_hwdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[6\] " "Node \"mem_ahb_hwdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[7\] " "Node \"mem_ahb_hwdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[8\] " "Node \"mem_ahb_hwdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwdata\[9\] " "Node \"mem_ahb_hwdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "mem_ahb_hwrite " "Node \"mem_ahb_hwrite\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "mem_ahb_hwrite" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "resetn_out " "Node \"resetn_out\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "resetn_out" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[0\] " "Node \"slave_ahb_haddr\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[10\] " "Node \"slave_ahb_haddr\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[11\] " "Node \"slave_ahb_haddr\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[12\] " "Node \"slave_ahb_haddr\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[13\] " "Node \"slave_ahb_haddr\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[14\] " "Node \"slave_ahb_haddr\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[15\] " "Node \"slave_ahb_haddr\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[16\] " "Node \"slave_ahb_haddr\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[17\] " "Node \"slave_ahb_haddr\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[18\] " "Node \"slave_ahb_haddr\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[19\] " "Node \"slave_ahb_haddr\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[1\] " "Node \"slave_ahb_haddr\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[20\] " "Node \"slave_ahb_haddr\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[21\] " "Node \"slave_ahb_haddr\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[22\] " "Node \"slave_ahb_haddr\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[23\] " "Node \"slave_ahb_haddr\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[24\] " "Node \"slave_ahb_haddr\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[25\] " "Node \"slave_ahb_haddr\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[26\] " "Node \"slave_ahb_haddr\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[27\] " "Node \"slave_ahb_haddr\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[28\] " "Node \"slave_ahb_haddr\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[29\] " "Node \"slave_ahb_haddr\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[2\] " "Node \"slave_ahb_haddr\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[30\] " "Node \"slave_ahb_haddr\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[31\] " "Node \"slave_ahb_haddr\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[3\] " "Node \"slave_ahb_haddr\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[4\] " "Node \"slave_ahb_haddr\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[5\] " "Node \"slave_ahb_haddr\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[6\] " "Node \"slave_ahb_haddr\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[7\] " "Node \"slave_ahb_haddr\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[8\] " "Node \"slave_ahb_haddr\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_haddr\[9\] " "Node \"slave_ahb_haddr\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_haddr\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[0\] " "Node \"slave_ahb_hburst\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[1\] " "Node \"slave_ahb_hburst\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hburst\[2\] " "Node \"slave_ahb_hburst\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hburst\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[0\] " "Node \"slave_ahb_hrdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[10\] " "Node \"slave_ahb_hrdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[11\] " "Node \"slave_ahb_hrdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[12\] " "Node \"slave_ahb_hrdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[13\] " "Node \"slave_ahb_hrdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[14\] " "Node \"slave_ahb_hrdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[15\] " "Node \"slave_ahb_hrdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[16\] " "Node \"slave_ahb_hrdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[17\] " "Node \"slave_ahb_hrdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[18\] " "Node \"slave_ahb_hrdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[19\] " "Node \"slave_ahb_hrdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[1\] " "Node \"slave_ahb_hrdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[20\] " "Node \"slave_ahb_hrdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[21\] " "Node \"slave_ahb_hrdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[22\] " "Node \"slave_ahb_hrdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[23\] " "Node \"slave_ahb_hrdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[24\] " "Node \"slave_ahb_hrdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[25\] " "Node \"slave_ahb_hrdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[26\] " "Node \"slave_ahb_hrdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[27\] " "Node \"slave_ahb_hrdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[28\] " "Node \"slave_ahb_hrdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[29\] " "Node \"slave_ahb_hrdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[2\] " "Node \"slave_ahb_hrdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[30\] " "Node \"slave_ahb_hrdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[31\] " "Node \"slave_ahb_hrdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[3\] " "Node \"slave_ahb_hrdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[4\] " "Node \"slave_ahb_hrdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[5\] " "Node \"slave_ahb_hrdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[6\] " "Node \"slave_ahb_hrdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[7\] " "Node \"slave_ahb_hrdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[8\] " "Node \"slave_ahb_hrdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hrdata\[9\] " "Node \"slave_ahb_hrdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hrdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hready " "Node \"slave_ahb_hready\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hready" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hreadyout " "Node \"slave_ahb_hreadyout\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hreadyout" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hresp " "Node \"slave_ahb_hresp\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hresp" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsel " "Node \"slave_ahb_hsel\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsel" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[0\] " "Node \"slave_ahb_hsize\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[1\] " "Node \"slave_ahb_hsize\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hsize\[2\] " "Node \"slave_ahb_hsize\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hsize\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_htrans\[0\] " "Node \"slave_ahb_htrans\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_htrans\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_htrans\[1\] " "Node \"slave_ahb_htrans\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_htrans\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[0\] " "Node \"slave_ahb_hwdata\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[10\] " "Node \"slave_ahb_hwdata\[10\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[10\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[11\] " "Node \"slave_ahb_hwdata\[11\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[11\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[12\] " "Node \"slave_ahb_hwdata\[12\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[12\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[13\] " "Node \"slave_ahb_hwdata\[13\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[13\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[14\] " "Node \"slave_ahb_hwdata\[14\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[14\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[15\] " "Node \"slave_ahb_hwdata\[15\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[15\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[16\] " "Node \"slave_ahb_hwdata\[16\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[16\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[17\] " "Node \"slave_ahb_hwdata\[17\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[17\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[18\] " "Node \"slave_ahb_hwdata\[18\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[18\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[19\] " "Node \"slave_ahb_hwdata\[19\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[19\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[1\] " "Node \"slave_ahb_hwdata\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[20\] " "Node \"slave_ahb_hwdata\[20\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[20\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[21\] " "Node \"slave_ahb_hwdata\[21\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[21\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[22\] " "Node \"slave_ahb_hwdata\[22\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[22\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[23\] " "Node \"slave_ahb_hwdata\[23\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[23\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[24\] " "Node \"slave_ahb_hwdata\[24\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[24\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[25\] " "Node \"slave_ahb_hwdata\[25\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[25\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[26\] " "Node \"slave_ahb_hwdata\[26\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[26\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[27\] " "Node \"slave_ahb_hwdata\[27\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[27\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[28\] " "Node \"slave_ahb_hwdata\[28\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[28\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[29\] " "Node \"slave_ahb_hwdata\[29\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[29\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[2\] " "Node \"slave_ahb_hwdata\[2\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[2\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[30\] " "Node \"slave_ahb_hwdata\[30\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[30\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[31\] " "Node \"slave_ahb_hwdata\[31\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[31\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[3\] " "Node \"slave_ahb_hwdata\[3\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[3\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[4\] " "Node \"slave_ahb_hwdata\[4\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[4\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[5\] " "Node \"slave_ahb_hwdata\[5\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[5\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[6\] " "Node \"slave_ahb_hwdata\[6\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[6\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[7\] " "Node \"slave_ahb_hwdata\[7\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[7\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[8\] " "Node \"slave_ahb_hwdata\[8\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[8\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwdata\[9\] " "Node \"slave_ahb_hwdata\[9\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwdata\[9\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "slave_ahb_hwrite " "Node \"slave_ahb_hwrite\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "slave_ahb_hwrite" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_hseBypass " "Node \"sys_ctrl_hseBypass\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_hseBypass" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_hseEnable " "Node \"sys_ctrl_hseEnable\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_hseEnable" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_pllEnable " "Node \"sys_ctrl_pllEnable\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_pllEnable" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_sleep " "Node \"sys_ctrl_sleep\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_sleep" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "sys_ctrl_standby " "Node \"sys_ctrl_standby\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "sys_ctrl_standby" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "usb0_id " "Node \"usb0_id\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "usb0_id" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1778306630308 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1778306630308 ""}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Fitter preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306630332 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1778306632105 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306632544 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1778306632560 ""}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1778306639292 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:07 " "Fitter placement operations ending: elapsed time is 00:00:07" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306639293 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Fitter" 0 -1 1778306639317 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1778306639579 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1778306639616 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic replication " "Starting physical synthesis algorithm logic replication" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Fitter" 0 -1 1778306639618 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "logic replication 0 " "Physical synthesis algorithm logic replication complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Fitter" 0 -1 1778306639675 ""}
{ "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:01 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:01" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Fitter" 0 -1 1778306639915 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1778306640629 ""}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "11 X47_Y0 X58_Y11 " "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X47_Y0 to location X58_Y11" {  } { { "loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 1 { 0 "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X47_Y0 to location X58_Y11"} { { 11 { 0 "Router estimated peak interconnect usage is 11% of the available device resources in the region that extends from location X47_Y0 to location X58_Y11"} 47 0 12 12 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1778306642887 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1778306642887 ""}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:07 " "Fitter routing operations ending: elapsed time is 00:00:07" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306648538 ""}
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "1.52 " "Total time spent on timing analysis during the Fitter is 1.52 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1778306648582 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1778306648631 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1778306648920 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1778306648965 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1778306649308 ""}
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:01 " "Fitter post-fit operations ending: elapsed time is 00:00:01" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1778306649768 ""}
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1778306650615 ""}
{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "15 Cyclone IV E " "15 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PIN_HSE 3.3-V LVTTL C23 " "Pin PIN_HSE uses I/O standard 3.3-V LVTTL at C23" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 25 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 219 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_CSN 3.3-V LVTTL AF13 " "Pin SPI0_CSN uses I/O standard 3.3-V LVTTL at AF13" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_CSN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 28 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_CSN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 213 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_SCK 3.3-V LVTTL AD12 " "Pin SPI0_SCK uses I/O standard 3.3-V LVTTL at AD12" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SCK } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 29 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 216 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART0_UARTTXD 3.3-V LVTTL AD15 " "Pin UART0_UARTTXD uses I/O standard 3.3-V LVTTL at AD15" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTTXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 33 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTTXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 215 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "BAUD_RATE 3.3-V LVTTL AB17 " "Pin BAUD_RATE uses I/O standard 3.3-V LVTTL at AB17" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO4_1 3.3-V LVTTL AE14 " "Pin GPIO4_1 uses I/O standard 3.3-V LVTTL at AE14" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 23 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 214 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "GPIO4_2 3.3-V LVTTL AB13 " "Pin GPIO4_2 uses I/O standard 3.3-V LVTTL at AB13" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { GPIO4_2 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 24 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO4_2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 217 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "SPI0_SI_IO0 3.3-V LVTTL AB16 " "Pin SPI0_SI_IO0 uses I/O standard 3.3-V LVTTL at AB16" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { SPI0_SI_IO0 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 30 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SPI0_SI_IO0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 212 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "TEST_SINGLE 3.3-V LVTTL AG25 " "Pin TEST_SINGLE uses I/O standard 3.3-V LVTTL at AG25" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART1_RX 3.3-V LVTTL AG12 " "Pin UART1_RX uses I/O standard 3.3-V LVTTL at AG12" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART1_TX 3.3-V LVTTL AC15 " "Pin UART1_TX uses I/O standard 3.3-V LVTTL at AC15" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_TX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 35 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_TX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 225 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "so_io1 3.3-V LVTTL V27 " "Pin so_io1 uses I/O standard 3.3-V LVTTL at V27" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "UART0_UARTRXD 3.3-V LVTTL AH12 " "Pin UART0_UARTRXD uses I/O standard 3.3-V LVTTL at AH12" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART0_UARTRXD } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 32 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART0_UARTRXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 223 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PIN_HSI 3.3-V LVTTL Y2 " "Pin PIN_HSI uses I/O standard 3.3-V LVTTL at Y2" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PIN_HSI } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 26 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PIN_HSI } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 220 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "PLL_CLKIN 3.3-V LVTTL J1 " "Pin PLL_CLKIN uses I/O standard 3.3-V LVTTL at J1" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { PLL_CLKIN } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 27 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PLL_CLKIN } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 221 9224 9983 0}  }  } }  } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Quartus II" 0 -1 1778306650621 ""}  } {  } 0 169177 "%1!d! pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1778306650621 ""}
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "4 " "Following 4 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "BAUD_RATE a permanently disabled " "Pin BAUD_RATE has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { BAUD_RATE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 22 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { BAUD_RATE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 218 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306650622 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "TEST_SINGLE a permanently disabled " "Pin TEST_SINGLE has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { TEST_SINGLE } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 31 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { TEST_SINGLE } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 222 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306650622 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "UART1_RX a permanently disabled " "Pin UART1_RX has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { UART1_RX } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 34 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { UART1_RX } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 224 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306650622 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "so_io1 a permanently disabled " "Pin so_io1 has a permanently disabled output enable" {  } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { so_io1 } } } { "example_board.v" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.v" 36 0 0 } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { so_io1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1778306650622 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1778306650622 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.fit.smsg " "Generated suppressed messages file D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/quartus_logs/example_board.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1778306650829 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 476 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 476 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5474 " "Peak virtual memory: 5474 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306651540 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:04:11 2026 " "Processing ended: Sat May 09 14:04:11 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306651540 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:25 " "Elapsed time: 00:00:25" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306651540 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:37 " "Total CPU time (on all processors): 00:00:37" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306651540 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1778306651540 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "Assembler FLOW_DISABLE_ASSEMBLER " "Skipped module Assembler due to the assignment FLOW_DISABLE_ASSEMBLER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Fitter" 0 -1 1778306652257 ""}
{ "Info" "IFLOW_DISABLED_MODULE" "PowerPlay Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" {  } {  } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Fitter" 0 -1 1778306652258 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1778306652875 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306652876 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:04:12 2026 " "Processing started: Sat May 09 14:04:12 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306652876 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778306652876 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta example_board -c example_board " "Command: quartus_sta example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778306652876 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" {  } {  } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1778306652995 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1778306653196 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1778306653243 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" {  } {  } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1778306653244 ""}
{ "Info" "ISTA_SDC_FOUND" "example_board.sdc " "Reading SDC File: 'example_board.sdc'" {  } {  } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Quartus II" 0 -1 1778306653528 ""}
{ "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "Deriving PLL clocks " "Deriving PLL clocks" { { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN " "create_clock -period 125.000 -waveform \{0.000 62.500\} -name PLL_CLKIN PLL_CLKIN" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""} { "Info" "ISTA_DERIVE_PLL_CLOCKS_INFO" "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} " "create_generated_clock -source \{pll_inst\|auto_generated\|pll1\|inclk\[0\]\} -multiply_by 13 -duty_cycle 50.00 -name \{pll_inst\|auto_generated\|pll1\|clk\[0\]\} \{pll_inst\|auto_generated\|pll1\|clk\[0\]\}" {  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""}  } {  } 0 332110 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""}
{ "Warning" "WSTA_FILTER_COULD_NOT_BE_MATCHED_WITH_LOCATION" "example_board.sdc 13 rv32\|resetn_out clock or keeper or register or port or pin or cell or partition " "Ignored filter at example_board.sdc(13): rv32\|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332174 "Ignored filter at %1!s!(%2!d!): %3!s! could not be matched with a %4!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""}
{ "Warning" "WSTA_IGNORED_ASSIGNMENT_WITH_REASON_AND_LOCATION" "set_false_path example_board.sdc 13 Argument <from> is not an object ID " "Ignored set_false_path at example_board.sdc(13): Argument <from> is not an object ID" { { "Info" "ISTA_SDC_COMMAND" "set_false_path -from rv32\|resetn_out " "set_false_path -from rv32\|resetn_out" {  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332050 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""}  } { { "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" "" { Text "D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/example_board.sdc" 13 -1 0 } }  } 0 332049 "Ignored %1!s! at %2!s!(%3!d!): %4!s!" 0 0 "Quartus II" 0 -1 1778306653535 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "PIN_HSI (Rise) PIN_HSI (Rise) setup and hold " "From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306653774 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) to pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306653774 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1778306653774 ""}
{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" {  } {  } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1778306653775 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Quartus II" 0 0 1778306653799 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.082 " "Worst-case setup slack is 2.082" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.082         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    2.082         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653832 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   92.467         0.000 PIN_HSI  " "   92.467         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653832 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306653832 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.264 " "Worst-case hold slack is 0.264" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.264         0.000 PIN_HSI  " "    0.264         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653843 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.264         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    0.264         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653843 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306653843 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306653846 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306653848 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.458 " "Worst-case minimum pulse width slack is 4.458" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.458         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    4.458         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.635         0.000 PIN_HSI  " "   49.635         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   62.371         0.000 PLL_CLKIN  " "   62.371         0.000 PLL_CLKIN " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  121.000         0.000 PIN_HSE  " "  121.000         0.000 PIN_HSE " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306653852 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" {  } {  } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Quartus II" 0 0 1778306653952 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 334003 "Started post-fitting delay annotation" 0 0 "Quartus II" 0 -1 1778306653982 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 334004 "Delay annotation completed successfully" 0 0 "Quartus II" 0 -1 1778306654454 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "PIN_HSI (Rise) PIN_HSI (Rise) setup and hold " "From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306654603 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) to pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306654603 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1778306654603 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 2.677 " "Worst-case setup slack is 2.677" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654621 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654621 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    2.677         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    2.677         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654621 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   93.062         0.000 PIN_HSI  " "   93.062         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654621 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654621 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.208 " "Worst-case hold slack is 0.208" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654627 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654627 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.208         0.000 PIN_HSI  " "    0.208         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654627 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.208         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    0.208         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654627 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654627 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306654632 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306654636 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.447 " "Worst-case minimum pulse width slack is 4.447" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.447         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    4.447         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.631         0.000 PIN_HSI  " "   49.631         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   62.365         0.000 PLL_CLKIN  " "   62.365         0.000 PLL_CLKIN " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  121.000         0.000 PIN_HSE  " "  121.000         0.000 PIN_HSE " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654639 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" {  } {  } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Quartus II" 0 0 1778306654733 ""}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "PIN_HSI (Rise) PIN_HSI (Rise) setup and hold " "From PIN_HSI (Rise) to PIN_HSI (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306654923 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) setup and hold " "From pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) to pll_inst\|auto_generated\|pll1\|clk\[0\] (Rise) (setup and hold)" {  } {  } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Quartus II" 0 -1 1778306654923 ""}  } {  } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Quartus II" 0 -1 1778306654923 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 6.421 " "Worst-case setup slack is 6.421" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    6.421         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    6.421         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654932 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   96.806         0.000 PIN_HSI  " "   96.806         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654932 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654932 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.084 " "Worst-case hold slack is 0.084" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654940 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654940 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.084         0.000 PIN_HSI  " "    0.084         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654940 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    0.084         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    0.084         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654940 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654940 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306654944 ""}
{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" {  } {  } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1778306654950 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 4.559 " "Worst-case minimum pulse width slack is 4.559" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    Slack End Point TNS Clock  " "    Slack End Point TNS Clock " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "    4.559         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\]  " "    4.559         0.000 pll_inst\|auto_generated\|pll1\|clk\[0\] " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   49.208         0.000 PIN_HSI  " "   49.208         0.000 PIN_HSI " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "   61.901         0.000 PLL_CLKIN  " "   61.901         0.000 PLL_CLKIN " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "  121.000         0.000 PIN_HSE  " "  121.000         0.000 PIN_HSE " {  } {  } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""}  } {  } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1778306654955 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1778306655308 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" {  } {  } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1778306655309 ""}
{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 11 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4712 " "Peak virtual memory: 4712 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306655413 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:04:15 2026 " "Processing ended: Sat May 09 14:04:15 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306655413 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306655413 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306655413 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778306655413 ""}
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778306656413 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778306656413 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:04:16 2026 " "Processing started: Sat May 09 14:04:16 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778306656413 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778306656413 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off example_board -c example_board " "Command: quartus_eda --read_settings_files=off --write_settings_files=off example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778306656413 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_85c_slow.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_85c_slow.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306657123 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_0c_slow.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_0c_slow.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306657324 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_min_1200mv_0c_fast.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_min_1200mv_0c_fast.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306657532 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306657729 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_85c_v_slow.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_85c_v_slow.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306657896 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_0c_v_slow.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_0c_v_slow.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306658054 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_min_1200mv_0c_v_fast.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_min_1200mv_0c_v_fast.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306658212 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_v.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_v.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778306658383 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4584 " "Peak virtual memory: 4584 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778306658453 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:04:18 2026 " "Processing ended: Sat May 09 14:04:18 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778306658453 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778306658453 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778306658453 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778306658453 ""}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 2265 s " "Quartus II Full Compilation was successful. 0 errors, 2265 warnings" {  } {  } 0 293000 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778306659093 ""}