--alt_mac_mult DATAA_CLEAR="NONE" DATAA_CLOCK="NONE" DATAA_WIDTH=10 DATAB_CLEAR="NONE" DATAB_CLOCK="NONE" DATAB_WIDTH=10 MULT_CLEAR="NONE" MULT_CLOCK="NONE" MULT_INPUT_A_IS_CONSTANT="NO" MULT_INPUT_B_IS_CONSTANT="NO" MULT_PIPELINE=0 MULT_REPRESENTATION_A="UNSIGNED" MULT_REPRESENTATION_B="UNSIGNED" OUTPUT_CLEAR="NONE" OUTPUT_CLOCK="NONE" OUTPUT_WIDTH=20 SIGNA_CLEAR="NONE" SIGNA_CLOCK="NONE" SIGNB_CLEAR="NONE" SIGNB_CLOCK="NONE" dataa datab dataout signa signb CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" --VERSION_BEGIN 13.0 cbx_alt_mac_mult 2013:04:24:18:08:47:SJ cbx_mgl 2013:04:24:18:11:10:SJ VERSION_END -- Copyright (C) 1991-2013 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License -- Subscription Agreement, Altera MegaCore Function License -- Agreement, or other applicable license agreement, including, -- without limitation, that your use is for the sole purpose of -- programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the -- applicable agreement for further details. FUNCTION mult_aql (dataa[9..0], datab[9..0]) RETURNS ( result[19..0]); --synthesis_resources = lut 165 SUBDESIGN mac_mult_iug1 ( dataa[9..0] : input; datab[9..0] : input; dataout[19..0] : output; signa : input; signb : input; ) VARIABLE mult1 : mult_aql; tmp_dataout[19..0] : WIRE; x_dataa[9..0] : WIRE; x_datab[9..0] : WIRE; x_output[19..0] : WIRE; BEGIN mult1.dataa[] = x_dataa[]; mult1.datab[] = x_datab[]; dataout[] = tmp_dataout[]; tmp_dataout[] = (x_output[] & (((signa # (! signa)) # signb) # (! signb))); x_dataa[] = ( dataa[]); x_datab[] = ( datab[]); x_output[19..0] = mult1.result[19..0]; END; --VALID FILE