{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1778307565068 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1778307565068 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 09 14:19:24 2026 " "Processing started: Sat May 09 14:19:24 2026" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1778307565068 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1778307565068 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off example_board -c example_board " "Command: quartus_eda --read_settings_files=off --write_settings_files=off example_board -c example_board" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1778307565068 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_85c_slow.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_85c_slow.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307565768 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_0c_slow.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_0c_slow.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307565985 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_min_1200mv_0c_fast.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_min_1200mv_0c_fast.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307566202 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board.vo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board.vo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307566411 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_85c_v_slow.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_85c_v_slow.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307566573 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_8_1200mv_0c_v_slow.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_8_1200mv_0c_v_slow.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307566737 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_min_1200mv_0c_v_fast.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_min_1200mv_0c_v_fast.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307566927 ""}
{ "Info" "IWSC_DONE_HDL_GENERATION" "example_board_v.sdo D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/ simulation " "Generated file example_board_v.sdo in folder \"D:/LYW/WBJW/CODE/NEW_TSB_3.0/AG32/example/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1778307567104 ""}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4584 " "Peak virtual memory: 4584 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1778307567173 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sat May 09 14:19:27 2026 " "Processing ended: Sat May 09 14:19:27 2026" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1778307567173 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1778307567173 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1778307567173 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1778307567173 ""}