=== User constraints === Fmax report User constraint: 8.000MHz, Fmax: 118.329MHz, Clock: PIN_HSE User constraint: 10.000MHz, Fmax: 118.329MHz, Clock: PIN_HSI User constraint: 104.000MHz, Fmax: 118.329MHz, Clock: pll_inst|auto_generated|pll1|clk[0] Clock transfer report: Worst setup: 116.549, with clock PIN_HSE Worst setup: 91.549, with clock PIN_HSI Worst setup: 1.164, with clock pll_inst|auto_generated|pll1|clk[0] === Auto constraints === Coverage report User constraints covered 3450 connections out of 6471 total, coverage: 53.3% Auto constraints covered 3450 connections out of 6471 total, coverage: 53.3% Setup from macro_inst|cfg_reg_inst|trig_threshold[0] to clken_ctrl_X58_Y6_N1, clock pll_inst|auto_generated|pll1|clk[0], constraint 9.615, skew -0.332, data 8.029 Slack: 1.164 Arrival Time: 8.966 0.000 0.000 R Launch Clock Edge Launch Clock Path: 0.000 0.000 RR example_board|PLL_CLKIN => PLL_CLKIN~input|padio 1.309 1.309 RR PLL_CLKIN~input|padio => PLL_CLKIN~input|combout 1.546 0.237 RR PLL_CLKIN~input|combout => pll_inst|auto_generated|pll1|clkin Compensation Path: -2.390 -3.936 RR pll_inst|auto_generated|pll1|clkfb => pll_inst|auto_generated|pll1|clkfbout -2.390 -0.000 RR pll_inst|auto_generated|pll1|clkfbout => pll_inst|auto_generated|pll1|clkfb Compensation Path End -1.410 0.980 RR pll_inst|auto_generated|pll1|clkin => pll_inst|auto_generated|pll1|clkout0 D -1.410 0.000 RR pll_inst|auto_generated|pll1|clkout0 => gclksw_inst|gclk_switch__alta_gclksw|clkin2 D -1.008 0.402 RR gclksw_inst|gclk_switch__alta_gclksw|clkin2 => gclksw_inst|gclk_switch__alta_gclksw|clkout -0.895 0.113 RR gclksw_inst|gclk_switch__alta_gclksw|clkout => gclksw_inst|gclk_switch|inclk -0.895 0.000 RR gclksw_inst|gclk_switch|inclk => gclksw_inst|gclk_switch|outclk 0.656 1.551 RR gclksw_inst|gclk_switch|outclk => clken_ctrl_X58_Y4_N0|ClkIn 0.804 0.148 RR clken_ctrl_X58_Y4_N0|ClkIn => clken_ctrl_X58_Y4_N0|ClkOut 0.937 0.133 RR clken_ctrl_X58_Y4_N0|ClkOut => macro_inst|cfg_reg_inst|trig_threshold[0]|Clk Data Path: 1.172 0.235 RF macro_inst|cfg_reg_inst|trig_threshold[0]|Clk => macro_inst|cfg_reg_inst|trig_threshold[0]|Q D 2.530 1.358 FF macro_inst|cfg_reg_inst|trig_threshold[0]|Q => macro_inst|trig_ctrl_inst|LessThan3~1|B 2.980 0.450 FF macro_inst|trig_ctrl_inst|LessThan3~1|B => macro_inst|trig_ctrl_inst|LessThan3~1|Cout 2.980 0.000 FF macro_inst|trig_ctrl_inst|LessThan3~1|Cout => macro_inst|trig_ctrl_inst|LessThan3~3|Cin 3.046 0.066 FR macro_inst|trig_ctrl_inst|LessThan3~3|Cin => macro_inst|trig_ctrl_inst|LessThan3~3|Cout 3.046 0.000 RR macro_inst|trig_ctrl_inst|LessThan3~3|Cout => macro_inst|trig_ctrl_inst|LessThan3~5|Cin 3.111 0.065 RF macro_inst|trig_ctrl_inst|LessThan3~5|Cin => macro_inst|trig_ctrl_inst|LessThan3~5|Cout 3.111 0.000 FF macro_inst|trig_ctrl_inst|LessThan3~5|Cout => macro_inst|cfg_reg_inst|trig_threshold[3]|Cin 3.177 0.066 FR macro_inst|cfg_reg_inst|trig_threshold[3]|Cin => macro_inst|cfg_reg_inst|trig_threshold[3]|Cout 3.177 0.000 RR macro_inst|cfg_reg_inst|trig_threshold[3]|Cout => macro_inst|apb_adc0_inst|apb_db[4]|Cin 3.242 0.065 RF macro_inst|apb_adc0_inst|apb_db[4]|Cin => macro_inst|apb_adc0_inst|apb_db[4]|Cout 3.242 0.000 FF macro_inst|apb_adc0_inst|apb_db[4]|Cout => macro_inst|cfg_reg_inst|trig_threshold[5]|Cin 3.308 0.066 FR macro_inst|cfg_reg_inst|trig_threshold[5]|Cin => macro_inst|cfg_reg_inst|trig_threshold[5]|Cout 3.308 0.000 RR macro_inst|cfg_reg_inst|trig_threshold[5]|Cout => macro_inst|apb_adc0_inst|apb_db[6]|Cin 3.373 0.065 RF macro_inst|apb_adc0_inst|apb_db[6]|Cin => macro_inst|apb_adc0_inst|apb_db[6]|Cout 3.373 0.000 FF macro_inst|apb_adc0_inst|apb_db[6]|Cout => macro_inst|cfg_reg_inst|trig_threshold[7]|Cin 3.439 0.066 FR macro_inst|cfg_reg_inst|trig_threshold[7]|Cin => macro_inst|cfg_reg_inst|trig_threshold[7]|Cout 3.439 0.000 RR macro_inst|cfg_reg_inst|trig_threshold[7]|Cout => macro_inst|apb_adc0_inst|apb_db[8]|Cin 3.504 0.065 RF macro_inst|apb_adc0_inst|apb_db[8]|Cin => macro_inst|apb_adc0_inst|apb_db[8]|Cout 3.504 0.000 FF macro_inst|apb_adc0_inst|apb_db[8]|Cout => macro_inst|cfg_reg_inst|trig_threshold[9]|Cin 3.570 0.066 FR macro_inst|cfg_reg_inst|trig_threshold[9]|Cin => macro_inst|cfg_reg_inst|trig_threshold[9]|Cout 3.570 0.000 RR macro_inst|cfg_reg_inst|trig_threshold[9]|Cout => macro_inst|apb_adc0_inst|apb_db[10]|Cin 3.635 0.065 RF macro_inst|apb_adc0_inst|apb_db[10]|Cin => macro_inst|apb_adc0_inst|apb_db[10]|Cout 3.635 0.000 FF macro_inst|apb_adc0_inst|apb_db[10]|Cout => macro_inst|apb_adc0_inst|apb_db[11]|Cin 4.059 0.424 FF macro_inst|apb_adc0_inst|apb_db[11]|Cin => macro_inst|apb_adc0_inst|apb_db[11]|LutOut 5.137 1.078 FF macro_inst|apb_adc0_inst|apb_db[11]|LutOut => macro_inst|trig_ctrl_inst|edge_trigger~0|B 5.671 0.534 FR macro_inst|trig_ctrl_inst|edge_trigger~0|B => macro_inst|trig_ctrl_inst|edge_trigger~0|LutOut 6.072 0.401 RR macro_inst|trig_ctrl_inst|edge_trigger~0|LutOut => macro_inst|trig_ctrl_inst|edge_trigger~2|C 6.355 0.283 RR macro_inst|trig_ctrl_inst|edge_trigger~2|C => macro_inst|trig_ctrl_inst|edge_trigger~2|LutOut 7.234 0.879 RR macro_inst|trig_ctrl_inst|edge_trigger~2|LutOut => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|D 7.335 0.101 RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|D => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|LutOut 8.209 0.874 RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~34|LutOut => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|D 8.310 0.101 RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|D => macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|LutOut 8.966 0.656 RR macro_inst|trig_ctrl_inst|auto_wait_cnt[7]~35|LutOut => clken_ctrl_X58_Y6_N1|ClkEn E Required Time: 10.130 9.615 9.615 R Latch Clock Edge Latch Clock Path: 9.615 0.000 RR example_board|PLL_CLKIN => PLL_CLKIN~input|padio 10.924 1.309 RR PLL_CLKIN~input|padio => PLL_CLKIN~input|combout 11.151 0.227 RR PLL_CLKIN~input|combout => pll_inst|auto_generated|pll1|clkin Compensation Path: 7.215 -3.936 RR pll_inst|auto_generated|pll1|clkfb => pll_inst|auto_generated|pll1|clkfbout 7.215 -0.000 RR pll_inst|auto_generated|pll1|clkfbout => pll_inst|auto_generated|pll1|clkfb Compensation Path End 8.195 0.980 RR pll_inst|auto_generated|pll1|clkin => pll_inst|auto_generated|pll1|clkout0 D 8.195 0.000 RR pll_inst|auto_generated|pll1|clkout0 => gclksw_inst|gclk_switch__alta_gclksw|clkin2 D 8.597 0.402 RR gclksw_inst|gclk_switch__alta_gclksw|clkin2 => gclksw_inst|gclk_switch__alta_gclksw|clkout 8.710 0.113 RR gclksw_inst|gclk_switch__alta_gclksw|clkout => gclksw_inst|gclk_switch|inclk 8.710 0.000 RR gclksw_inst|gclk_switch|inclk => gclksw_inst|gclk_switch|outclk 10.220 1.510 RR gclksw_inst|gclk_switch|outclk => clken_ctrl_X58_Y6_N1|ClkIn 10.120 -0.100 R Setup 10.130 0.010 Clock Variation