2006_BOOT/logic/simulation/modelsim/fpga_boot_v.sdo

// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE75F29C8 Package FBGA780
// 

//
// This file contains Slow Corner delays for the design using part EP4CE75F29C8,
// with speed grade 8, core voltage 1.2V, and temperature 85 Celsius
//

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "fpga_boot")
  (DATE "07/15/2025 15:09:48")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pll_inst\|auto_generated\|pll_lock_sync)
    (DELAY
      (ABSOLUTE
        (PORT clk (4300:4300:4300) (4890:4890:4890))
        (PORT d (99:99:99) (115:115:115))
        (PORT clrn (2236:2236:2236) (2224:2224:2224))
        (IOPATH (posedge clk) q (261:261:261) (261:261:261))
        (IOPATH (negedge clrn) q (247:247:247) (247:247:247))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (212:212:212))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pll_inst\|auto_generated\|locked)
    (DELAY
      (ABSOLUTE
        (PORT datac (3586:3586:3586) (4163:4163:4163))
        (PORT datad (295:295:295) (365:365:365))
        (IOPATH datac combout (324:324:324) (316:316:316))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (240:240:240) (258:258:258))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (1534:1534:1534) (1382:1382:1382))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO9_1\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (738:738:738) (847:847:847))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO3_0\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (738:738:738) (847:847:847))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSI\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (799:799:799) (908:908:908))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSE\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (809:809:809) (918:918:918))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE pll_inst\|auto_generated\|locked\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (917:917:917) (856:856:856))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (776:776:776) (715:715:715))
        (PORT oe (782:782:782) (713:713:713))
        (IOPATH i o (3052:3052:3052) (2932:2932:2932))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (751:751:751) (685:685:685))
        (PORT oe (774:774:774) (708:708:708))
        (IOPATH i o (3092:3092:3092) (2972:2972:2972))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (769:769:769) (701:701:701))
        (PORT oe (788:788:788) (717:717:717))
        (IOPATH i o (3032:3032:3032) (2912:2912:2912))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (769:769:769) (690:690:690))
        (PORT oe (764:764:764) (698:698:698))
        (IOPATH i o (3052:3052:3052) (2932:2932:2932))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_1\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (749:749:749) (672:672:672))
        (PORT oe (820:820:820) (749:749:749))
        (IOPATH i o (3052:3052:3052) (2932:2932:2932))
        (IOPATH oe o (3138:3138:3138) (2968:2968:2968))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (822:822:822) (766:766:766))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (858:858:858) (788:788:788))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (822:822:822) (765:765:765))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (857:857:857) (788:788:788))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datac (531:531:531) (505:505:505))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (763:763:763) (698:698:698))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (532:532:532) (506:506:506))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (762:762:762) (698:698:698))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (531:531:531) (506:506:506))
        (IOPATH datac combout (327:327:327) (316:316:316))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (763:763:763) (698:698:698))
        (IOPATH datad combout (177:177:177) (155:155:155))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio3_io_in\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (3299:3299:3299) (3533:3533:3533))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_in\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (3279:3279:3279) (3522:3522:3522))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rv32.sys_clk\~QIC_DANGLING_PORT)
    (DELAY
      (ABSOLUTE
        (PORT datad (2014:2014:2014) (1981:1981:1981))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE auto_generated_inst.gclksw_inst\|gclk_switch)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (207:207:207) (194:194:194))
        (PORT inclk[2] (2420:2420:2420) (2384:2384:2384))
        (PORT clkselect[0] (4526:4526:4526) (4244:4244:4244))
        (PORT clkselect[1] (5623:5623:5623) (5472:5472:5472))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE auto_generated_inst.pll_inst\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT areset (1886:1886:1886) (1886:1886:1886))
        (PORT inclk[0] (2422:2422:2422) (2422:2422:2422))
      )
    )
  )
)