2006_BOOT/logic/quartus_logs/fpga_boot.sta.rpt

TimeQuest Timing Analyzer report for fpga_boot
Tue Jul 15 15:09:47 2025
Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE'
 14. Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI'
 15. Clock to Output Times
 16. Minimum Clock to Output Times
 17. Slow 1200mV 85C Model Metastability Report
 18. Slow 1200mV 0C Model Fmax Summary
 19. Slow 1200mV 0C Model Setup Summary
 20. Slow 1200mV 0C Model Hold Summary
 21. Slow 1200mV 0C Model Recovery Summary
 22. Slow 1200mV 0C Model Removal Summary
 23. Slow 1200mV 0C Model Minimum Pulse Width Summary
 24. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
 25. Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
 26. Clock to Output Times
 27. Minimum Clock to Output Times
 28. Slow 1200mV 0C Model Metastability Report
 29. Fast 1200mV 0C Model Setup Summary
 30. Fast 1200mV 0C Model Hold Summary
 31. Fast 1200mV 0C Model Recovery Summary
 32. Fast 1200mV 0C Model Removal Summary
 33. Fast 1200mV 0C Model Minimum Pulse Width Summary
 34. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'
 35. Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'
 36. Clock to Output Times
 37. Minimum Clock to Output Times
 38. Fast 1200mV 0C Model Metastability Report
 39. Multicorner Timing Analysis Summary
 40. Clock to Output Times
 41. Minimum Clock to Output Times
 42. Board Trace Model Assignments
 43. Input Transition Times
 44. Signal Integrity Metrics (Slow 1200mv 0c Model)
 45. Signal Integrity Metrics (Slow 1200mv 85c Model)
 46. Signal Integrity Metrics (Fast 1200mv 0c Model)
 47. Clock Transfers
 48. Report TCCS
 49. Report RSKM
 50. Unconstrained Paths
 51. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                        ;
+--------------------+-----------------------------------------------------+
; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Full Version ;
; Revision Name      ; fpga_boot                                           ;
; Device Family      ; Cyclone IV E                                        ;
; Device Name        ; EP4CE75F29C8                                        ;
; Timing Models      ; Final                                               ;
; Delay Model        ; Combined                                            ;
; Rise/Fall Delays   ; Enabled                                             ;
+--------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processors 2-4         ; < 0.1%      ;
;     Processors 5-8         ;   0.0%      ;
+----------------------------+-------------+


+---------------------------------------------------+
; SDC File List                                     ;
+---------------+--------+--------------------------+
; SDC File Path ; Status ; Read at                  ;
+---------------+--------+--------------------------+
; fpga_boot.sdc ; OK     ; Tue Jul 15 15:09:46 2025 ;
+---------------+--------+--------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                          ;
+-------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+---------------------------------------+-----------------------------------------+
; Clock Name                          ; Type      ; Period  ; Frequency  ; Rise  ; Fall   ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master  ; Source                                ; Targets                                 ;
+-------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+---------------------------------------+-----------------------------------------+
; PIN_HSE                             ; Base      ; 125.000 ; 8.0 MHz    ; 0.000 ; 62.500 ;            ;           ;             ;       ;        ;           ;            ;          ;         ;                                       ; { PIN_HSE }                             ;
; PIN_HSI                             ; Base      ; 100.000 ; 10.0 MHz   ; 0.000 ; 50.000 ;            ;           ;             ;       ;        ;           ;            ;          ;         ;                                       ; { PIN_HSI }                             ;
; pll_inst|auto_generated|pll1|clk[0] ; Generated ; 4.166   ; 240.04 MHz ; 0.000 ; 2.083  ; 50.00      ; 1         ; 30          ;       ;        ;           ;            ; false    ; PIN_HSE ; pll_inst|auto_generated|pll1|inclk[0] ; { pll_inst|auto_generated|pll1|clk[0] } ;
+-------------------------------------+-----------+---------+------------+-------+--------+------------+-----------+-------------+-------+--------+-----------+------------+----------+---------+---------------------------------------+-----------------------------------------+


--------------------------------------
; Slow 1200mV 85C Model Fmax Summary ;
--------------------------------------
No paths to report.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


---------------------------------------
; Slow 1200mV 85C Model Setup Summary ;
---------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 85C Model Hold Summary ;
--------------------------------------
No paths to report.


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+---------+--------+--------------------------------+
; Clock   ; Slack  ; End Point TNS                  ;
+---------+--------+--------------------------------+
; PIN_HSE ; 62.371 ; 0.000                          ;
; PIN_HSI ; 96.000 ; 0.000                          ;
+---------+--------+--------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSE'                                                                              ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                        ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; 62.371  ; 62.371       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 62.371  ; 62.371       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 62.391  ; 62.391       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 62.419  ; 62.419       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 62.500  ; 62.500       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 62.500  ; 62.500       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 62.580  ; 62.580       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 62.609  ; 62.609       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 62.627  ; 62.627       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 62.627  ; 62.627       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 121.000 ; 125.000      ; 4.000          ; Port Rate        ; PIN_HSE ; Rise       ; PIN_HSE                                       ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+


+-------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'PIN_HSI'                                ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock   ; Clock Edge ; Target  ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; 96.000 ; 100.000      ; 4.000          ; Port Rate ; PIN_HSI ; Rise       ; PIN_HSI ;
+--------+--------------+----------------+-----------+---------+------------+---------+


+--------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                    ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 3.020 ; 3.083 ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 3.020 ; 3.083 ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; 0.209 ;       ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;       ; 0.140 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.932  ; 2.995  ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.932  ; 2.995  ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; -0.296 ;        ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;        ; -0.363 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


-------------------------------------
; Slow 1200mV 0C Model Fmax Summary ;
-------------------------------------
No paths to report.


--------------------------------------
; Slow 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Slow 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
+---------+--------+-------------------------------+
; Clock   ; Slack  ; End Point TNS                 ;
+---------+--------+-------------------------------+
; PIN_HSE ; 62.365 ; 0.000                         ;
; PIN_HSI ; 96.000 ; 0.000                         ;
+---------+--------+-------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'                                                                               ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                        ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; 62.365  ; 62.365       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 62.365  ; 62.365       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 62.404  ; 62.404       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 62.423  ; 62.423       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 62.500  ; 62.500       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 62.500  ; 62.500       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 62.576  ; 62.576       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 62.596  ; 62.596       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 62.635  ; 62.635       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 62.635  ; 62.635       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 121.000 ; 125.000      ; 4.000          ; Port Rate        ; PIN_HSE ; Rise       ; PIN_HSE                                       ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+


+-------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'                                 ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock   ; Clock Edge ; Target  ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; 96.000 ; 100.000      ; 4.000          ; Port Rate ; PIN_HSI ; Rise       ; PIN_HSI ;
+--------+--------------+----------------+-----------+---------+------------+---------+


+--------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                    ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.763 ; 2.798 ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.763 ; 2.798 ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; 0.329 ;       ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;       ; 0.239 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.684  ; 2.721  ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 2.684  ; 2.721  ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; -0.115 ;        ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;        ; -0.201 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


--------------------------------------
; Fast 1200mV 0C Model Setup Summary ;
--------------------------------------
No paths to report.


-------------------------------------
; Fast 1200mV 0C Model Hold Summary ;
-------------------------------------
No paths to report.


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+--------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
+---------+--------+-------------------------------+
; Clock   ; Slack  ; End Point TNS                 ;
+---------+--------+-------------------------------+
; PIN_HSE ; 61.901 ; 0.000                         ;
; PIN_HSI ; 96.000 ; 0.000                         ;
+---------+--------+-------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSE'                                                                               ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock   ; Clock Edge ; Target                                        ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+
; 61.901  ; 61.901       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 61.901  ; 61.901       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 61.948  ; 61.948       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 61.952  ; 61.952       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 62.500  ; 62.500       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 62.500  ; 62.500       ; 0.000          ; Low Pulse Width  ; PIN_HSE ; Rise       ; PIN_HSE~input|i                               ;
; 63.048  ; 63.048       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|inclk[0]         ;
; 63.052  ; 63.052       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; PIN_HSE~input|o                               ;
; 63.095  ; 63.095       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|clk[0]           ;
; 63.095  ; 63.095       ; 0.000          ; High Pulse Width ; PIN_HSE ; Rise       ; pll_inst|auto_generated|pll1|observablevcoout ;
; 121.000 ; 125.000      ; 4.000          ; Port Rate        ; PIN_HSE ; Rise       ; PIN_HSE                                       ;
+---------+--------------+----------------+------------------+---------+------------+-----------------------------------------------+


+-------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'PIN_HSI'                                 ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; Slack  ; Actual Width ; Required Width ; Type      ; Clock   ; Clock Edge ; Target  ;
+--------+--------------+----------------+-----------+---------+------------+---------+
; 96.000 ; 100.000      ; 4.000          ; Port Rate ; PIN_HSI ; Rise       ; PIN_HSI ;
+--------+--------------+----------------+-----------+---------+------------+---------+


+----------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                      ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.368  ; 1.932  ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.368  ; 1.932  ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; -0.062 ;        ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;        ; -0.040 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.325  ; 1.889  ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.325  ; 1.889  ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; -0.308 ;        ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;        ; -0.288 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                        ;
+------------------+-------+------+----------+---------+---------------------+
; Clock            ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
+------------------+-------+------+----------+---------+---------------------+
; Worst-case Slack ; N/A   ; N/A  ; N/A      ; N/A     ; 61.901              ;
;  PIN_HSE         ; N/A   ; N/A  ; N/A      ; N/A     ; 61.901              ;
;  PIN_HSI         ; N/A   ; N/A  ; N/A      ; N/A     ; 96.000              ;
; Design-wide TNS  ; 0.0   ; 0.0  ; 0.0      ; 0.0     ; 0.0                 ;
;  PIN_HSE         ; N/A   ; N/A  ; N/A      ; N/A     ; 0.000               ;
;  PIN_HSI         ; N/A   ; N/A  ; N/A      ; N/A     ; 0.000               ;
+------------------+-------+------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                    ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 3.020 ; 3.083 ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 3.020 ; 3.083 ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; 0.329 ;       ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;       ; 0.239 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+-------+-------+------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                              ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; Data Port                                ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                     ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.325  ; 1.889  ; Rise       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSI    ; 1.325  ; 1.889  ; Fall       ; PIN_HSI                             ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ; -0.308 ;        ; Rise       ; pll_inst|auto_generated|pll1|clk[0] ;
; alta_rv32:rv32|sys_clk~QIC_DANGLING_PORT ; PIN_HSE    ;        ; -0.363 ; Fall       ; pll_inst|auto_generated|pll1|clk[0] ;
+------------------------------------------+------------+--------+--------+------------+-------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                    ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin           ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; GPIO6_0       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO6_2       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO9_0       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO9_2       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; GPIO9_1       ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+----------------------------------------------------------------------------+
; Input Transition Times                                                     ;
+-------------------------+--------------+-----------------+-----------------+
; Pin                     ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+-------------------------+--------------+-----------------+-----------------+
; PIN_OSC                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO9_1                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; GPIO3_0                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; PIN_HSI                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; PIN_HSE                 ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_ASDO_DATA1~     ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_FLASH_nCE_nCSO~ ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_DATA0~          ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
+-------------------------+--------------+-----------------+-----------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; GPIO6_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; GPIO6_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; GPIO9_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; GPIO9_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; GPIO9_1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.89e-09 V                   ; 3.12 V              ; -0.11 V             ; 0.153 V                              ; 0.272 V                              ; 6.41e-10 s                  ; 4.57e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 8.89e-09 V                  ; 3.12 V             ; -0.11 V            ; 0.153 V                             ; 0.272 V                             ; 6.41e-10 s                 ; 4.57e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 3.51e-09 V                   ; 3.18 V              ; -0.157 V            ; 0.147 V                              ; 0.259 V                              ; 2.81e-10 s                  ; 2.53e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 3.51e-09 V                  ; 3.18 V             ; -0.157 V           ; 0.147 V                             ; 0.259 V                             ; 2.81e-10 s                 ; 2.53e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 6.38e-09 V                   ; 3.12 V              ; -0.0818 V           ; 0.205 V                              ; 0.244 V                              ; 8.86e-10 s                  ; 6.56e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 6.38e-09 V                  ; 3.12 V             ; -0.0818 V          ; 0.205 V                             ; 0.244 V                             ; 8.86e-10 s                 ; 6.56e-10 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; GPIO6_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; GPIO6_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; GPIO9_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; GPIO9_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; GPIO9_1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.5e-07 V                    ; 3.11 V              ; -0.0503 V           ; 0.122 V                              ; 0.172 V                              ; 7.08e-10 s                  ; 6.43e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.5e-07 V                   ; 3.11 V             ; -0.0503 V          ; 0.122 V                             ; 0.172 V                             ; 7.08e-10 s                 ; 6.43e-10 s                 ; Yes                       ; Yes                       ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.6e-07 V                    ; 3.13 V              ; -0.103 V            ; 0.164 V                              ; 0.134 V                              ; 3.14e-10 s                  ; 4.05e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.6e-07 V                   ; 3.13 V             ; -0.103 V           ; 0.164 V                             ; 0.134 V                             ; 3.14e-10 s                 ; 4.05e-10 s                 ; Yes                       ; No                        ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.04e-07 V                   ; 3.11 V              ; -0.0469 V           ; 0.191 V                              ; 0.215 V                              ; 1.08e-09 s                  ; 8.62e-10 s                  ; Yes                        ; No                         ; 3.08 V                      ; 5.04e-07 V                  ; 3.11 V             ; -0.0469 V          ; 0.191 V                             ; 0.215 V                             ; 1.08e-09 s                 ; 8.62e-10 s                 ; Yes                       ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin           ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; GPIO6_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO6_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO9_0       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO9_2       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; GPIO9_1       ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.85e-07 V                   ; 3.57 V              ; -0.141 V            ; 0.301 V                              ; 0.239 V                              ; 4.61e-10 s                  ; 4.2e-10 s                   ; No                         ; No                         ; 3.46 V                      ; 1.85e-07 V                  ; 3.57 V             ; -0.141 V           ; 0.301 V                             ; 0.239 V                             ; 4.61e-10 s                 ; 4.2e-10 s                  ; No                        ; No                        ;
; ~ALTERA_DCLK~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 6.54e-08 V                   ; 3.66 V              ; -0.26 V             ; 0.41 V                               ; 0.32 V                               ; 1.57e-10 s                  ; 2.15e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 6.54e-08 V                  ; 3.66 V             ; -0.26 V            ; 0.41 V                              ; 0.32 V                              ; 1.57e-10 s                 ; 2.15e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_nCEO~ ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.25e-07 V                   ; 3.57 V              ; -0.0855 V           ; 0.315 V                              ; 0.175 V                              ; 6.79e-10 s                  ; 6.15e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.25e-07 V                  ; 3.57 V             ; -0.0855 V          ; 0.315 V                             ; 0.175 V                             ; 6.79e-10 s                 ; 6.15e-10 s                 ; No                        ; No                        ;
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


-------------------
; Clock Transfers ;
-------------------
Nothing to report.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 1     ; 1    ;
; Unconstrained Input Port Paths  ; 1     ; 1    ;
; Unconstrained Output Ports      ; 1     ; 1    ;
; Unconstrained Output Port Paths ; 3     ; 3    ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
    Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    Info: Processing started: Tue Jul 15 15:09:45 2025
Info: Command: quartus_sta fpga_boot -c fpga_boot
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'fpga_boot.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {pll_inst|auto_generated|pll1|inclk[0]} -multiply_by 30 -duty_cycle 50.00 -name {pll_inst|auto_generated|pll1|clk[0]} {pll_inst|auto_generated|pll1|clk[0]}
Warning (332174): Ignored filter at fpga_boot.sdc(13): rv32|resetn_out could not be matched with a clock or keeper or register or port or pin or cell or partition
Warning (332049): Ignored set_false_path at fpga_boot.sdc(13): Argument <from> is not an object ID
    Info (332050): set_false_path -from rv32|resetn_out
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 62.371
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    62.371         0.000 PIN_HSE 
    Info (332119):    96.000         0.000 PIN_HSI 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 62.365
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    62.365         0.000 PIN_HSE 
    Info (332119):    96.000         0.000 PIN_HSI 
Info: Analyzing Fast 1200mV 0C Model
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 61.901
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):    61.901         0.000 PIN_HSE 
    Info (332119):    96.000         0.000 PIN_HSI 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 4666 megabytes
    Info: Processing ended: Tue Jul 15 15:09:47 2025
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02