af_ip.tcl 2.3 KB

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  1. set AGM_SUPRA true
  2. set DESIGN "fpga_boot"
  3. set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp }
  4. lappend IPLIST alta_rv32 alta_mipi_clk
  5. proc set_alta_partition {inst tag} {
  6. set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst]
  7. set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst]
  8. set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst]
  9. set section_id [string map { [ _ ] _ . _ | _} $inst_name]
  10. eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag"
  11. eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag"
  12. eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag"
  13. eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag"
  14. }
  15. load_package flow
  16. if { $DESIGN == "" } {
  17. set DESIGN $::quartus(args)
  18. }
  19. project_open $DESIGN
  20. set tag alta_auto
  21. if { [llength $IPLIST] > 0 } {
  22. # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them.
  23. set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag]
  24. foreach_in_collection part $asgn_col {
  25. set section_id [lindex $part 0]
  26. eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id"
  27. }
  28. eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag"
  29. eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag"
  30. eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag"
  31. catch { execute_module -tool map }
  32. foreach ip $IPLIST {
  33. foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] {
  34. set_alta_partition $inst $tag
  35. }
  36. foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] {
  37. set_alta_partition $inst $tag
  38. }
  39. }
  40. }
  41. eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation"
  42. project_close
  43. exit