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fpga_boot.root_partition.qmsg

fpga_boot.root_partition.qmsg 11 KB
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  1. { "Info" "IBAL_PROCESSED_MAX_DSP_BLOCKS_ASSIGNMENT" "0 partition Top " "Limiting DSP block usage to 0 DSP block(s) for the partition Top" {  } {  } 0 270000 "Limiting DSP block usage to %1!d! DSP block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1752563363378 ""}
    2. 

  2. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1752563363390 ""}
    3. 

  3. { "Info" "IBAL_PROCESSED_MAX_M4K_ASSIGNMENT" "4 Top " "Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top" {  } {  } 0 270017 "Limiting M4K/M9K RAM block usage to %1!d! M4K/M9K RAM block(s) for the %2!s!" 0 0 "Quartus II" 0 0 1752563363390 ""}
    4. 

  4. { "Info" "IQSYN_SYNTHESIZE_TOP_PARTITION" "" "Starting Logic Optimization and Technology Mapping for Top Partition" {  } {  } 0 281020 "Starting Logic Optimization and Technology Mapping for Top Partition" 0 0 "Quartus II" 0 0 1752563363449 ""}
    5. 

  5. { "Info" "ISCL_SCL_WYSIWYG_RESYNTHESIS" "0 balanced 0 " "Resynthesizing 0 WYSIWYG logic cells and I/Os using \"balanced\" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched" {  } {  } 0 17026 "Resynthesizing %1!d! WYSIWYG logic cells and I/Os using \"%2!s!\" technology mapper which leaves %3!d! WYSIWYG logic cells and I/Os untouched" 0 0 "Quartus II" 0 0 1752563363449 ""}
    6. 

  6. { "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" {  } {  } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363558 ""}
    7. 

  7. { "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "gpio3_io_in\[0\] " "Logic cell \"gpio3_io_in\[0\]\"" {  } { { "fpga_boot.v" "gpio3_io_in\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 313 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_in\[1\] " "Logic cell \"gpio9_io_in\[1\]\"" {  } { { "fpga_boot.v" "gpio9_io_in\[1\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 347 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_out_data\[0\] " "Logic cell \"gpio6_io_out_data\[0\]\"" {  } { { "fpga_boot.v" "gpio6_io_out_data\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 323 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_out_en\[0\] " "Logic cell \"gpio6_io_out_en\[0\]\"" {  } { { "fpga_boot.v" "gpio6_io_out_en\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 324 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_out_data\[2\] " "Logic cell \"gpio6_io_out_data\[2\]\"" {  } { { "fpga_boot.v" "gpio6_io_out_data\[2\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 323 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio6_io_out_en\[2\] " "Logic cell \"gpio6_io_out_en\[2\]\"" {  } { { "fpga_boot.v" "gpio6_io_out_en\[2\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 324 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_data\[0\] " "Logic cell \"gpio9_io_out_data\[0\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_data\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 339 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_en\[0\] " "Logic cell \"gpio9_io_out_en\[0\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_en\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 340 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_data\[2\] " "Logic cell \"gpio9_io_out_data\[2\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_data\[2\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 339 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_en\[2\] " "Logic cell \"gpio9_io_out_en\[2\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_en\[2\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 340 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[0\] " "Logic cell \"sys_ctrl_clkSource\[0\]\"" {  } { { "fpga_boot.v" "sys_ctrl_clkSource\[0\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 70 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "sys_ctrl_clkSource\[1\] " "Logic cell \"sys_ctrl_clkSource\[1\]\"" {  } { { "fpga_boot.v" "sys_ctrl_clkSource\[1\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 70 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_data\[1\] " "Logic cell \"gpio9_io_out_data\[1\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_data\[1\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 339 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""} { "Info" "ISCL_SCL_CELL_NAME" "gpio9_io_out_en\[1\] " "Logic cell \"gpio9_io_out_en\[1\]\"" {  } { { "fpga_boot.v" "gpio9_io_out_en\[1\]" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 340 -1 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Quartus II" 0 0 1752563363659 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Quartus II" 0 0 1752563363659 ""}
    8. 

  8. { "Warning" "WCUT_PLL_MULT_DIV_SPECIFIED_CLOCK_NOT_CONNECTED" "altpll:pll_inst\|altpll_9g32:auto_generated\|pll1 CLK\[1\] clk1_multiply_by clk1_divide_by " "PLL \"altpll:pll_inst\|altpll_9g32:auto_generated\|pll1\" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK\[1\] is not connected" {  } { { "db/altpll_9g32.tdf" "" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/db/altpll_9g32.tdf" 30 2 0 } } { "altpll.tdf" "" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/0202_boot_4/logic/fpga_boot.v" 151 0 0 } }  } 0 15899 "PLL \"%1!s!\" has parameters %3!s! and %4!s! specified but port %2!s! is not connected" 0 0 "Quartus II" 0 0 1752563363808 ""}
    9. 

  9. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_START" "speed " "Starting physical synthesis optimizations for speed" {  } {  } 0 128000 "Starting physical synthesis optimizations for %1!s!" 0 0 "Quartus II" 0 0 1752563363815 ""}
    10. 

  10. { "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Quartus II" 0 0 1752563364249 ""}
    11. 

  11. { "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 3 clocks " "Found 3 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 125.000      PIN_HSE " " 125.000      PIN_HSE" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000      PIN_HSI " " 100.000      PIN_HSI" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   4.166 pll_inst\|auto_generated\|pll1\|clk\[0\] " "   4.166 pll_inst\|auto_generated\|pll1\|clk\[0\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""}  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 0 1752563364249 ""}
    12. 

  12. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_START" "combinational resynthesis using boolean division " "Starting physical synthesis algorithm combinational resynthesis using boolean division" {  } {  } 0 128002 "Starting physical synthesis algorithm %1!s!" 0 0 "Quartus II" 0 0 1752563364257 ""}
    13. 

  13. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "combinational resynthesis using boolean division 0 " "Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps" {  } {  } 0 128003 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0 "Quartus II" 0 0 1752563364281 ""}
    14. 

  14. { "Info" "ICSYN_PHYSICAL_SYNTHESIS_END" "speed 00:00:00 " "Physical synthesis optimizations for speed complete: elapsed time is 00:00:00" {  } {  } 0 128001 "Physical synthesis optimizations for %1!s! complete: elapsed time is %2!s!" 0 0 "Quartus II" 0 0 1752563364282 ""}
    15. 

  15. { "Info" "ICUT_CUT_TM_SUMMARY" "44 " "Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "4 " "Implemented 4 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 0 1752563364321 ""} { "Info" "ICUT_CUT_TM_OPINS" "4 " "Implemented 4 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 0 1752563364321 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "1 " "Implemented 1 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Quartus II" 0 0 1752563364321 ""} { "Info" "ICUT_CUT_TM_LCELLS" "32 " "Implemented 32 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 0 1752563364321 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Quartus II" 0 0 1752563364321 ""} { "Info" "ICUT_CUT_TM_BLACKBOX" "1 " "Implemented 1 partitions" {  } {  } 0 21071 "Implemented %1!d! partitions" 0 0 "Quartus II" 0 0 1752563364321 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 0 1752563364321 ""}
    16. 

  16. { "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4675 " "Peak virtual memory: 4675 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 0 1752563364339 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 15 15:09:24 2025 " "Processing ended: Tue Jul 15 15:09:24 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 0 1752563364339 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 0 1752563364339 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 0 1752563364339 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 0 1752563364339 ""}
    17.