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fpga_boot.map.qmsg

fpga_boot.map.qmsg 80 KB
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  1. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1753773208215 ""}
    2. 

  2. { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1753773208215 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 29 15:13:28 2025 " "Processing started: Tue Jul 29 15:13:28 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1753773208215 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1753773208215 ""}
    3. 

  3. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off fpga_boot -c fpga_boot " "Command: quartus_map --read_settings_files=on --write_settings_files=off fpga_boot -c fpga_boot" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1753773208215 ""}
    4. 

  4. { "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "4 4 8 " "Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead." {  } {  } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1753773208638 ""}
    5. 

  5. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fpga_boot.v 1 1 " "Found 1 design units, including 1 entities, in source file fpga_boot.v" { { "Info" "ISGN_ENTITY_NAME" "1 fpga_boot " "Found entity 1: fpga_boot" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 5 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208718 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1753773208718 ""}
    6. 

  6. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "boot_ip.v 1 1 " "Found 1 design units, including 1 entities, in source file boot_ip.v" { { "Info" "ISGN_ENTITY_NAME" "1 boot_ip " "Found entity 1: boot_ip" {  } { { "boot_ip.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/boot_ip.v" 1 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208720 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1753773208720 ""}
    7. 

  7. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4171) " "Verilog HDL Declaration information at alta_sim.v(4171): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4171 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1753773208726 ""}
    8. 

  8. { "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "alta_sim.v(4325) " "Verilog HDL warning at alta_sim.v(4325): extended using \"x\" or \"z\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4325 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Quartus II" 0 -1 1753773208727 ""}
    9. 

  9. { "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "initVal initval alta_sim.v(4376) " "Verilog HDL Declaration information at alta_sim.v(4376): object \"initVal\" differs only in case from object \"initval\" in the same scope" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4376 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Quartus II" 0 -1 1753773208727 ""}
    10. 

  10. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v 57 57 " "Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" { { "Info" "ISGN_ENTITY_NAME" "1 alta_slice " "Found entity 1: alta_slice" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "2 alta_clkenctrl_rst " "Found entity 2: alta_clkenctrl_rst" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 85 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "3 alta_clkenctrl " "Found entity 3: alta_clkenctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 101 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "4 alta_asyncctrl " "Found entity 4: alta_asyncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 118 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "5 alta_syncctrl " "Found entity 5: alta_syncctrl" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 132 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "6 alta_io_gclk " "Found entity 6: alta_io_gclk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 146 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "7 alta_gclksel " "Found entity 7: alta_gclksel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 159 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "8 alta_gclkgen " "Found entity 8: alta_gclkgen" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 171 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "9 alta_gclkgen0 " "Found entity 9: alta_gclkgen0" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 184 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "10 alta_gclkgen2 " "Found entity 10: alta_gclkgen2" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 194 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "11 alta_io " "Found entity 11: alta_io" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 209 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "12 alta_rio " "Found entity 12: alta_rio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 275 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "13 alta_srff " "Found entity 13: alta_srff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 343 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "14 alta_dff " "Found entity 14: alta_dff" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 366 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "15 alta_ufm_gddd " "Found entity 15: alta_ufm_gddd" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 373 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "16 alta_dff_stall " "Found entity 16: alta_dff_stall" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 377 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "17 alta_srlat " "Found entity 17: alta_srlat" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "18 alta_dio " "Found entity 18: alta_dio" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 402 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "19 alta_indel " "Found entity 19: alta_indel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 498 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "20 alta_dpclkdel " "Found entity 20: alta_dpclkdel" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 509 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "21 alta_ufms " "Found entity 21: alta_ufms" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 520 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "22 alta_ufms_sim " "Found entity 22: alta_ufms_sim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 546 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "23 alta_pll " "Found entity 23: alta_pll" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 902 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "24 alta_pllx " "Found entity 24: alta_pllx" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 960 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "25 pll_clk_trim " "Found entity 25: pll_clk_trim" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "26 alta_pllv " "Found entity 26: alta_pllv" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 1999 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "27 alta_pllve " "Found entity 27: alta_pllve" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "28 alta_sram " "Found entity 28: alta_sram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2310 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "29 alta_dpram16x4 " "Found entity 29: alta_dpram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2349 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "30 alta_spram16x4 " "Found entity 30: alta_spram16x4" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2367 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "31 alta_wram " "Found entity 31: alta_wram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2384 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "32 alta_bram_pulse_generator " "Found entity 32: alta_bram_pulse_generator" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2423 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "33 alta_bram " "Found entity 33: alta_bram" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2440 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "34 alta_boot " "Found entity 34: alta_boot" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2611 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "35 alta_osc " "Found entity 35: alta_osc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2625 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "36 alta_ufml " "Found entity 36: alta_ufml" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2640 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "37 alta_jtag " "Found entity 37: alta_jtag" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2649 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "38 alta_mult " "Found entity 38: alta_mult" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2682 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "39 alta_dff_en " "Found entity 39: alta_dff_en" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2754 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "40 alta_multm_add " "Found entity 40: alta_multm_add" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2762 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "41 alta_multm " "Found entity 41: alta_multm" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2785 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "42 alta_i2c " "Found entity 42: alta_i2c" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3020 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "43 alta_spi " "Found entity 43: alta_spi" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3057 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "44 alta_irda " "Found entity 44: alta_irda" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3104 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "45 alta_bram9k " "Found entity 45: alta_bram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3124 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "46 alta_mcu " "Found entity 46: alta_mcu" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3365 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "47 alta_mcu_m3 " "Found entity 47: alta_mcu_m3" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3494 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "48 alta_remote " "Found entity 48: alta_remote" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3657 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "49 alta_saradc " "Found entity 49: alta_saradc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3668 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "50 alta_gclksw " "Found entity 50: alta_gclksw" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3683 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "51 alta_rv32 " "Found entity 51: alta_rv32" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3715 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "52 alta_mipi_clk " "Found entity 52: alta_mipi_clk" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3906 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "53 alta_adc " "Found entity 53: alta_adc" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3922 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "54 alta_dac " "Found entity 54: alta_dac" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3985 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "55 alta_cmp " "Found entity 55: alta_cmp" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4006 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "56 alta_ram4k " "Found entity 56: alta_ram4k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4062 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""} { "Info" "ISGN_ENTITY_NAME" "57 alta_ram9k " "Found entity 57: alta_ram9k" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 4241 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1753773208729 ""}
    11. 

  11. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_32_in fpga_boot.v(145) " "Verilog HDL Implicit Net warning at fpga_boot.v(145): created implicit net for \"PIN_32_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 145 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    12. 

  12. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_33_in fpga_boot.v(148) " "Verilog HDL Implicit Net warning at fpga_boot.v(148): created implicit net for \"PIN_33_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 148 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    13. 

  13. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_35_in fpga_boot.v(156) " "Verilog HDL Implicit Net warning at fpga_boot.v(156): created implicit net for \"PIN_35_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 156 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    14. 

  14. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_38_in fpga_boot.v(164) " "Verilog HDL Implicit Net warning at fpga_boot.v(164): created implicit net for \"PIN_38_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 164 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    15. 

  15. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_48_in fpga_boot.v(182) " "Verilog HDL Implicit Net warning at fpga_boot.v(182): created implicit net for \"PIN_48_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 182 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    16. 

  16. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_95_in fpga_boot.v(253) " "Verilog HDL Implicit Net warning at fpga_boot.v(253): created implicit net for \"PIN_95_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 253 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    17. 

  17. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_97_in fpga_boot.v(261) " "Verilog HDL Implicit Net warning at fpga_boot.v(261): created implicit net for \"PIN_97_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 261 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    18. 

  18. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_98_in fpga_boot.v(264) " "Verilog HDL Implicit Net warning at fpga_boot.v(264): created implicit net for \"PIN_98_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 264 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    19. 

  19. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSE_in fpga_boot.v(270) " "Verilog HDL Implicit Net warning at fpga_boot.v(270): created implicit net for \"PIN_HSE_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 270 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    20. 

  20. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_HSI_in fpga_boot.v(273) " "Verilog HDL Implicit Net warning at fpga_boot.v(273): created implicit net for \"PIN_HSI_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 273 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    21. 

  21. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "PIN_OSC_in fpga_boot.v(276) " "Verilog HDL Implicit Net warning at fpga_boot.v(276): created implicit net for \"PIN_OSC_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 276 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    22. 

  22. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "usb0_xcvr_clk fpga_boot.v(399) " "Verilog HDL Implicit Net warning at fpga_boot.v(399): created implicit net for \"usb0_xcvr_clk\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 399 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208734 ""}
    23. 

  23. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "bus_clk fpga_boot.v(418) " "Verilog HDL Implicit Net warning at fpga_boot.v(418): created implicit net for \"bus_clk\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 418 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208735 ""}
    24. 

  24. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "sys_clk fpga_boot.v(431) " "Verilog HDL Implicit Net warning at fpga_boot.v(431): created implicit net for \"sys_clk\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 431 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208735 ""}
    25. 

  25. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__5__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__5__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208735 ""}
    26. 

  26. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__4__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__4__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208735 ""}
    27. 

  27. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__3__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__3__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208735 ""}
    28. 

  28. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__2__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__2__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    29. 

  29. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__1__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__1__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    30. 

  30. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g0_in__0__ fpga_boot.v(489) " "Verilog HDL Implicit Net warning at fpga_boot.v(489): created implicit net for \"gpio_int_g0_in__0__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 489 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    31. 

  31. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__5__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__5__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    32. 

  32. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__4__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__4__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    33. 

  33. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__3__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__3__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    34. 

  34. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__2__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__2__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    35. 

  35. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__1__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__1__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    36. 

  36. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "gpio_int_g1_in__0__ fpga_boot.v(490) " "Verilog HDL Implicit Net warning at fpga_boot.v(490): created implicit net for \"gpio_int_g1_in__0__\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 490 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    37. 

  37. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd_12_ip_in fpga_boot.v(491) " "Verilog HDL Implicit Net warning at fpga_boot.v(491): created implicit net for \"rxd_12_ip_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 491 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    38. 

  38. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd_13_ip_in fpga_boot.v(492) " "Verilog HDL Implicit Net warning at fpga_boot.v(492): created implicit net for \"rxd_13_ip_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 492 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    39. 

  39. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd_14_ip_in fpga_boot.v(493) " "Verilog HDL Implicit Net warning at fpga_boot.v(493): created implicit net for \"rxd_14_ip_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 493 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    40. 

  40. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "rxd_15_ip_in fpga_boot.v(494) " "Verilog HDL Implicit Net warning at fpga_boot.v(494): created implicit net for \"rxd_15_ip_in\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 494 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    41. 

  41. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_12_ip_out_data fpga_boot.v(495) " "Verilog HDL Implicit Net warning at fpga_boot.v(495): created implicit net for \"txd_12_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 495 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    42. 

  42. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_12_ip_out_en fpga_boot.v(496) " "Verilog HDL Implicit Net warning at fpga_boot.v(496): created implicit net for \"txd_12_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 496 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    43. 

  43. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_13_ip_out_data fpga_boot.v(497) " "Verilog HDL Implicit Net warning at fpga_boot.v(497): created implicit net for \"txd_13_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 497 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    44. 

  44. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_13_ip_out_en fpga_boot.v(498) " "Verilog HDL Implicit Net warning at fpga_boot.v(498): created implicit net for \"txd_13_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 498 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208736 ""}
    45. 

  45. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_14_ip_out_data fpga_boot.v(499) " "Verilog HDL Implicit Net warning at fpga_boot.v(499): created implicit net for \"txd_14_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 499 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    46. 

  46. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_14_ip_out_en fpga_boot.v(500) " "Verilog HDL Implicit Net warning at fpga_boot.v(500): created implicit net for \"txd_14_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 500 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    47. 

  47. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_15_ip_out_data fpga_boot.v(501) " "Verilog HDL Implicit Net warning at fpga_boot.v(501): created implicit net for \"txd_15_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 501 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    48. 

  48. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txd_15_ip_out_en fpga_boot.v(502) " "Verilog HDL Implicit Net warning at fpga_boot.v(502): created implicit net for \"txd_15_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 502 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    49. 

  49. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_12_ip_out_data fpga_boot.v(503) " "Verilog HDL Implicit Net warning at fpga_boot.v(503): created implicit net for \"txen_12_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 503 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    50. 

  50. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_12_ip_out_en fpga_boot.v(504) " "Verilog HDL Implicit Net warning at fpga_boot.v(504): created implicit net for \"txen_12_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 504 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    51. 

  51. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_13_ip_out_data fpga_boot.v(505) " "Verilog HDL Implicit Net warning at fpga_boot.v(505): created implicit net for \"txen_13_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 505 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    52. 

  52. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_13_ip_out_en fpga_boot.v(506) " "Verilog HDL Implicit Net warning at fpga_boot.v(506): created implicit net for \"txen_13_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 506 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    53. 

  53. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_14_ip_out_data fpga_boot.v(507) " "Verilog HDL Implicit Net warning at fpga_boot.v(507): created implicit net for \"txen_14_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 507 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    54. 

  54. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_14_ip_out_en fpga_boot.v(508) " "Verilog HDL Implicit Net warning at fpga_boot.v(508): created implicit net for \"txen_14_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 508 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    55. 

  55. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_15_ip_out_data fpga_boot.v(509) " "Verilog HDL Implicit Net warning at fpga_boot.v(509): created implicit net for \"txen_15_ip_out_data\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 509 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    56. 

  56. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "txen_15_ip_out_en fpga_boot.v(510) " "Verilog HDL Implicit Net warning at fpga_boot.v(510): created implicit net for \"txen_15_ip_out_en\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 510 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    57. 

  57. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(180) " "Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 180 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    58. 

  58. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_int alta_sim.v(204) " "Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for \"ena_int\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 204 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    59. 

  59. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "ena_reg alta_sim.v(205) " "Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for \"ena_reg\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 205 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    60. 

  60. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_h alta_sim.v(476) " "Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for \"outreg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 476 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    61. 

  61. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "outreg_l alta_sim.v(477) " "Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for \"outreg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 477 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    62. 

  62. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_h alta_sim.v(485) " "Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for \"oe_reg_h\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 485 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    63. 

  63. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "oe_reg_l alta_sim.v(486) " "Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for \"oe_reg_l\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 486 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    64. 

  64. { "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "dffOut alta_sim.v(2758) " "Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for \"dffOut\"" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2758 0 0 } }  } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208737 ""}
    65. 

  65. { "Warning" "WVRFX_VERI_PARAM_DECL_BEHAVES_AS_LOCAL" "alta_bram_pulse_generator alta_sim.v(2428) " "Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module \"alta_bram_pulse_generator\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 2428 0 0 } }  } 0 10222 "Verilog HDL Parameter Declaration warning at %2!s!: Parameter Declaration in module \"%1!s!\" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List" 0 0 "Quartus II" 0 -1 1753773208743 ""}
    66. 

  66. { "Info" "ISGN_START_ELABORATION_TOP" "fpga_boot " "Elaborating entity \"fpga_boot\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1753773208800 ""}
    67. 

  67. { "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "PIN_OSC_in fpga_boot.v(276) " "Verilog HDL or VHDL warning at fpga_boot.v(276): object \"PIN_OSC_in\" assigned a value but never read" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 276 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Quartus II" 0 -1 1753773208808 "|fpga_boot"}
    68. 

  68. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll altpll:pll_inst " "Elaborating entity \"altpll\" for hierarchy \"altpll:pll_inst\"" {  } { { "fpga_boot.v" "pll_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 365 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208934 ""}
    69. 

  69. { "Info" "ISGN_ELABORATION_HEADER" "altpll:pll_inst " "Elaborated megafunction instantiation \"altpll:pll_inst\"" {  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 365 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Quartus II" 0 -1 1753773208938 ""}
    70. 

  70. { "Info" "ISGN_MEGAFN_PARAM_TOP" "altpll:pll_inst " "Instantiated megafunction \"altpll:pll_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 4 " "Parameter \"clk0_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 120 " "Parameter \"clk0_multiply_by\" = \"120\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 4 " "Parameter \"clk1_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 120 " "Parameter \"clk1_multiply_by\" = \"120\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 0 " "Parameter \"clk1_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 4 " "Parameter \"clk2_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 120 " "Parameter \"clk2_multiply_by\" = \"120\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_divide_by 8 " "Parameter \"clk3_divide_by\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_multiply_by 120 " "Parameter \"clk3_multiply_by\" = \"120\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_phase_shift 0 " "Parameter \"clk3_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_divide_by 4 " "Parameter \"clk4_divide_by\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_multiply_by 120 " "Parameter \"clk4_multiply_by\" = \"120\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_phase_shift 0 " "Parameter \"clk4_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK0 " "Parameter \"compensate_clock\" = \"CLK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 125000 " "Parameter \"inclk0_input_frequency\" = \"125000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone IV E " "Parameter \"intended_device_family\" = \"Cyclone IV E\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_UNUSED " "Parameter \"port_clk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_UNUSED " "Parameter \"port_clk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_USED " "Parameter \"port_clk3\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_UNUSED " "Parameter \"port_clk4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_phasecounterselect 3 " "Parameter \"width_phasecounterselect\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773208939 ""}  } { { "fpga_boot.v" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 365 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Quartus II" 0 -1 1753773208939 ""}
    71. 

  71. { "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_9g32.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_9g32.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_9g32 " "Found entity 1: altpll_9g32" {  } { { "db/altpll_9g32.tdf" "" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/db/altpll_9g32.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1753773209005 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1753773209005 ""}
    72. 

  72. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_9g32 altpll:pll_inst\|altpll_9g32:auto_generated " "Elaborating entity \"altpll_9g32\" for hierarchy \"altpll:pll_inst\|altpll_9g32:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209006 ""}
    73. 

  73. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_gclksw alta_gclksw:gclksw_inst " "Elaborating entity \"alta_gclksw\" for hierarchy \"alta_gclksw:gclksw_inst\"" {  } { { "fpga_boot.v" "gclksw_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 431 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209010 ""}
    74. 

  74. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "boot_ip boot_ip:macro_inst " "Elaborating entity \"boot_ip\" for hierarchy \"boot_ip:macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209016 ""}
    75. 

  75. { "Info" "ISGN_START_ELABORATION_HIERARCHY" "alta_rv32 alta_rv32:rv32 " "Elaborating entity \"alta_rv32\" for hierarchy \"alta_rv32:rv32\"" {  } { { "fpga_boot.v" "rv32" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 737 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209020 ""}
    76. 

  76. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_data alta_sim.v(3739) " "Output port \"gpio0_io_out_data\" at alta_sim.v(3739) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3739 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    77. 

  77. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio0_io_out_en alta_sim.v(3740) " "Output port \"gpio0_io_out_en\" at alta_sim.v(3740) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3740 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    78. 

  78. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_data alta_sim.v(3742) " "Output port \"gpio1_io_out_data\" at alta_sim.v(3742) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3742 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    79. 

  79. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio1_io_out_en alta_sim.v(3743) " "Output port \"gpio1_io_out_en\" at alta_sim.v(3743) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3743 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    80. 

  80. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_data alta_sim.v(3753) " "Output port \"gpio2_io_out_data\" at alta_sim.v(3753) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3753 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    81. 

  81. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio2_io_out_en alta_sim.v(3754) " "Output port \"gpio2_io_out_en\" at alta_sim.v(3754) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3754 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    82. 

  82. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_data alta_sim.v(3756) " "Output port \"gpio3_io_out_data\" at alta_sim.v(3756) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3756 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    83. 

  83. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio3_io_out_en alta_sim.v(3757) " "Output port \"gpio3_io_out_en\" at alta_sim.v(3757) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3757 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    84. 

  84. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_data alta_sim.v(3759) " "Output port \"gpio4_io_out_data\" at alta_sim.v(3759) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3759 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    85. 

  85. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio4_io_out_en alta_sim.v(3760) " "Output port \"gpio4_io_out_en\" at alta_sim.v(3760) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3760 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    86. 

  86. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_data alta_sim.v(3762) " "Output port \"gpio5_io_out_data\" at alta_sim.v(3762) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3762 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209022 "|fpga_boot|alta_rv32:rv32"}
    87. 

  87. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio5_io_out_en alta_sim.v(3763) " "Output port \"gpio5_io_out_en\" at alta_sim.v(3763) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3763 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    88. 

  88. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_data alta_sim.v(3765) " "Output port \"gpio6_io_out_data\" at alta_sim.v(3765) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3765 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    89. 

  89. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio6_io_out_en alta_sim.v(3766) " "Output port \"gpio6_io_out_en\" at alta_sim.v(3766) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3766 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    90. 

  90. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_data alta_sim.v(3768) " "Output port \"gpio7_io_out_data\" at alta_sim.v(3768) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3768 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    91. 

  91. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio7_io_out_en alta_sim.v(3769) " "Output port \"gpio7_io_out_en\" at alta_sim.v(3769) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3769 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    92. 

  92. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_data alta_sim.v(3771) " "Output port \"gpio8_io_out_data\" at alta_sim.v(3771) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3771 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    93. 

  93. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio8_io_out_en alta_sim.v(3772) " "Output port \"gpio8_io_out_en\" at alta_sim.v(3772) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3772 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    94. 

  94. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_data alta_sim.v(3774) " "Output port \"gpio9_io_out_data\" at alta_sim.v(3774) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3774 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    95. 

  95. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "gpio9_io_out_en alta_sim.v(3775) " "Output port \"gpio9_io_out_en\" at alta_sim.v(3775) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3775 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    96. 

  96. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGSTATE alta_sim.v(3780) " "Output port \"swj_JTAGSTATE\" at alta_sim.v(3780) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3780 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    97. 

  97. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGIR alta_sim.v(3781) " "Output port \"swj_JTAGIR\" at alta_sim.v(3781) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3781 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    98. 

  98. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "dmactive alta_sim.v(3778) " "Output port \"dmactive\" at alta_sim.v(3778) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3778 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    99. 

  99. { "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "swj_JTAGNSW alta_sim.v(3779) " "Output port \"swj_JTAGNSW\" at alta_sim.v(3779) has no driver" {  } { { "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" "" { Text "C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v" 3779 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Quartus II" 0 -1 1753773209023 "|fpga_boot|alta_rv32:rv32"}
    100. 

  100. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_CLK macro_inst " "Port \"SIM_CLK\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    101. 

  101. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_IO macro_inst " "Port \"SIM_IO\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    102. 

  102. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_IO_12 macro_inst " "Port \"SIM_IO_12\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    103. 

  103. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_IO_13 macro_inst " "Port \"SIM_IO_13\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    104. 

  104. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_IO_14 macro_inst " "Port \"SIM_IO_14\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    105. 

  105. { "Error" "ESGN_NON_EXISTENT_PORT" "SIM_IO_15 macro_inst " "Port \"SIM_IO_15\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209073 ""}
    106. 

  106. { "Error" "ESGN_NON_EXISTENT_PORT" "gpio_int_g0_in macro_inst " "Port \"gpio_int_g0_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    107. 

  107. { "Error" "ESGN_NON_EXISTENT_PORT" "gpio_int_g1_in macro_inst " "Port \"gpio_int_g1_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    108. 

  108. { "Error" "ESGN_NON_EXISTENT_PORT" "rxd_12_ip_in macro_inst " "Port \"rxd_12_ip_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    109. 

  109. { "Error" "ESGN_NON_EXISTENT_PORT" "rxd_13_ip_in macro_inst " "Port \"rxd_13_ip_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    110. 

  110. { "Error" "ESGN_NON_EXISTENT_PORT" "rxd_14_ip_in macro_inst " "Port \"rxd_14_ip_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    111. 

  111. { "Error" "ESGN_NON_EXISTENT_PORT" "rxd_15_ip_in macro_inst " "Port \"rxd_15_ip_in\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209075 ""}
    112. 

  112. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_12_ip_out_data macro_inst " "Port \"txd_12_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    113. 

  113. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_12_ip_out_en macro_inst " "Port \"txd_12_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    114. 

  114. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_13_ip_out_data macro_inst " "Port \"txd_13_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    115. 

  115. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_13_ip_out_en macro_inst " "Port \"txd_13_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    116. 

  116. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_14_ip_out_data macro_inst " "Port \"txd_14_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    117. 

  117. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_14_ip_out_en macro_inst " "Port \"txd_14_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    118. 

  118. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_15_ip_out_data macro_inst " "Port \"txd_15_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    119. 

  119. { "Error" "ESGN_NON_EXISTENT_PORT" "txd_15_ip_out_en macro_inst " "Port \"txd_15_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    120. 

  120. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_12_ip_out_data macro_inst " "Port \"txen_12_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    121. 

  121. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_12_ip_out_en macro_inst " "Port \"txen_12_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    122. 

  122. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_13_ip_out_data macro_inst " "Port \"txen_13_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    123. 

  123. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_13_ip_out_en macro_inst " "Port \"txen_13_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    124. 

  124. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_14_ip_out_data macro_inst " "Port \"txen_14_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    125. 

  125. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_14_ip_out_en macro_inst " "Port \"txen_14_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    126. 

  126. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_15_ip_out_data macro_inst " "Port \"txen_15_ip_out_data\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    127. 

  127. { "Error" "ESGN_NON_EXISTENT_PORT" "txen_15_ip_out_en macro_inst " "Port \"txen_15_ip_out_en\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    128. 

  128. { "Error" "ESGN_NON_EXISTENT_PORT" "uart14_rx macro_inst " "Port \"uart14_rx\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209076 ""}
    129. 

  129. { "Error" "ESGN_NON_EXISTENT_PORT" "uart14_tx macro_inst " "Port \"uart14_tx\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209077 ""}
    130. 

  130. { "Error" "ESGN_NON_EXISTENT_PORT" "uart15_rx macro_inst " "Port \"uart15_rx\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209077 ""}
    131. 

  131. { "Error" "ESGN_NON_EXISTENT_PORT" "uart15_tx macro_inst " "Port \"uart15_tx\" does not exist in macrofunction \"macro_inst\"" {  } { { "fpga_boot.v" "macro_inst" { Text "D:/LYW/NEW_DECODE/2006_boot/logic/fpga_boot.v" 543 0 0 } }  } 0 12002 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "Quartus II" 0 -1 1753773209077 ""}
    132. 

  132. { "Warning" "WSGN_CONNECTIVITY_WARNINGS" "2 " "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" {  } {  } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Quartus II" 0 -1 1753773209080 ""}
    133. 

  133. { "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/LYW/NEW_DECODE/2006_boot/logic/quartus_logs/fpga_boot.map.smsg " "Generated suppressed messages file D:/LYW/NEW_DECODE/2006_boot/logic/quartus_logs/fpga_boot.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Quartus II" 0 -1 1753773209133 ""}
    134. 

  134. { "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 32 s 81 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 32 errors, 81 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "4580 " "Peak virtual memory: 4580 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1753773209207 ""} { "Error" "EQEXE_END_BANNER_TIME" "Tue Jul 29 15:13:29 2025 " "Processing ended: Tue Jul 29 15:13:29 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1753773209207 ""} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1753773209207 ""} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1753773209207 ""}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1753773209207 ""}
    135.