2006_BOOT/logic/db/fpga_boot.hier_info

|fpga_boot
GPIO1_0 <= GPIO1_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_1 <= GPIO1_1.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_2 <= GPIO1_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_3 <= GPIO1_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_4 <= GPIO1_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_5 <= GPIO1_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_6 <= GPIO1_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_7 <= GPIO1_7.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_0 <= GPIO2_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_1 <= GPIO2_1.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_2 <= GPIO2_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_3 <= GPIO2_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_4 <= GPIO2_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_5 <= GPIO2_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_6 <= GPIO2_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_7 <= GPIO2_7.DB_MAX_OUTPUT_PORT_TYPE
GPIO3_0 => gpio3_io_in[0].DATAIN
GPIO3_1 => gpio3_io_in[1].DATAIN
GPIO3_2 => gpio3_io_in[2].DATAIN
GPIO3_3 => gpio3_io_in[3].DATAIN
GPIO3_4 => gpio3_io_in[4].DATAIN
GPIO6_0 <= GPIO6_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_2 <= GPIO6_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_4 <= GPIO6_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_6 <> GPIO6_6
GPIO9_0 <= GPIO9_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_1 <> GPIO9_1
GPIO9_2 <= GPIO9_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_3 <= GPIO9_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_4 <= GPIO9_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_5 <= GPIO9_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_6 <= GPIO9_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_7 <= GPIO9_7.DB_MAX_OUTPUT_PORT_TYPE
PIN_HSE => PIN_HSE_in.IN2
PIN_HSI => PIN_HSI_in.IN1
PIN_OSC => ~NO_FANOUT~
SIM_CLK <= boot_ip:macro_inst.SIM_CLK
SIM_IO[0] <> boot_ip:macro_inst.SIM_IO
SIM_IO[1] <> boot_ip:macro_inst.SIM_IO
SIM_IO[2] <> boot_ip:macro_inst.SIM_IO
SIM_IO[3] <> boot_ip:macro_inst.SIM_IO
SIM_IO[4] <> boot_ip:macro_inst.SIM_IO
SIM_IO[5] <> boot_ip:macro_inst.SIM_IO
SIM_IO[6] <> boot_ip:macro_inst.SIM_IO
SIM_IO[7] <> boot_ip:macro_inst.SIM_IO
SIM_IO[8] <> boot_ip:macro_inst.SIM_IO
SIM_IO[9] <> boot_ip:macro_inst.SIM_IO
SIM_IO[10] <> boot_ip:macro_inst.SIM_IO
SIM_IO[11] <> boot_ip:macro_inst.SIM_IO
SIM_IO_12 <> boot_ip:macro_inst.SIM_IO_12
SIM_IO_13 <> boot_ip:macro_inst.SIM_IO_13
SIM_IO_14 <> boot_ip:macro_inst.SIM_IO_14
SIM_IO_15 <> boot_ip:macro_inst.SIM_IO_15
UART4_UARTRXD => gpio7_io_in[1].DATAIN
UART4_UARTTXD <= UART4_UARTTXD.DB_MAX_OUTPUT_PORT_TYPE
uart14_rx => uart14_rx.IN1
uart14_tx <= boot_ip:macro_inst.uart14_tx
uart15_rx => uart15_rx.IN1
uart15_tx <= boot_ip:macro_inst.uart15_tx


|fpga_boot|altpll:pll_inst
inclk[0] => altpll_9g32:auto_generated.inclk[0]
inclk[1] => altpll_9g32:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => altpll_9g32:auto_generated.areset
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= altpll_9g32:auto_generated.locked
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>