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2006_BOOT
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logic
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db
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fpga_boot.eda.qmsg

fpga_boot.eda.qmsg 5.1 KB
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123456789101112 
  1. { "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1752563388198 ""}
    2. 

  2. { "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Full Version " "Version 13.0.0 Build 156 04/24/2013 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1752563388198 ""} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 15 15:09:48 2025 " "Processing started: Tue Jul 15 15:09:48 2025" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1752563388198 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1752563388198 ""}
    3. 

  3. { "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot " "Command: quartus_eda --read_settings_files=off --write_settings_files=off fpga_boot -c fpga_boot" {  } {  } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1752563388198 ""}
    4. 

  4. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_8_1200mv_85c_slow.vo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_8_1200mv_85c_slow.vo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388548 ""}
    5. 

  5. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_8_1200mv_0c_slow.vo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_8_1200mv_0c_slow.vo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388569 ""}
    6. 

  6. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_min_1200mv_0c_fast.vo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_min_1200mv_0c_fast.vo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388589 ""}
    7. 

  7. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot.vo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot.vo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388607 ""}
    8. 

  8. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_8_1200mv_85c_v_slow.sdo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_8_1200mv_85c_v_slow.sdo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388619 ""}
    9. 

  9. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_8_1200mv_0c_v_slow.sdo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_8_1200mv_0c_v_slow.sdo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388632 ""}
    10. 

  10. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_min_1200mv_0c_v_fast.sdo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_min_1200mv_0c_v_fast.sdo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388643 ""}
    11. 

  11. { "Info" "IWSC_DONE_HDL_GENERATION" "fpga_boot_v.sdo D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/ simulation " "Generated file fpga_boot_v.sdo in folder \"D:/LYW/NEW_DECODE/0202_boot_4/logic/simulation/modelsim/\" for EDA simulation tool" {  } {  } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1752563388655 ""}
    12. 

  12. { "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4545 " "Peak virtual memory: 4545 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1752563388694 ""} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 15 15:09:48 2025 " "Processing ended: Tue Jul 15 15:09:48 2025" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1752563388694 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1752563388694 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1752563388694 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1752563388694 ""}
    13.