// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE75F29C8 Package FBGA780
// 

//
// This file contains Fast Corner delays for the design using part EP4CE75F29C8,
// with speed grade M, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "fpga_boot")
  (DATE "07/15/2025 15:09:48")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pll_inst\|auto_generated\|pll_lock_sync)
    (DELAY
      (ABSOLUTE
        (PORT clk (2115:2115:2115) (1943:1943:1943))
        (PORT d (37:37:37) (50:50:50))
        (PORT clrn (1078:1078:1078) (1065:1065:1065))
        (IOPATH (posedge clk) q (105:105:105) (105:105:105))
        (IOPATH (negedge clrn) q (110:110:110) (110:110:110))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (84:84:84))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pll_inst\|auto_generated\|locked)
    (DELAY
      (ABSOLUTE
        (PORT datac (1794:1794:1794) (1631:1631:1631))
        (PORT datad (119:119:119) (157:157:157))
        (IOPATH datac combout (119:119:119) (124:124:124))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (91:91:91) (108:108:108))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (607:607:607) (688:688:688))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO9_1\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (223:223:223) (774:774:774))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO3_0\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (223:223:223) (774:774:774))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSI\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (283:283:283) (835:835:835))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSE\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (293:293:293) (845:845:845))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE pll_inst\|auto_generated\|locked\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (360:360:360) (375:375:375))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (304:304:304) (341:341:341))
        (PORT oe (304:304:304) (340:340:340))
        (IOPATH i o (1652:1652:1652) (1597:1597:1597))
        (IOPATH oe o (1696:1696:1696) (1622:1622:1622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (291:291:291) (325:325:325))
        (PORT oe (304:304:304) (339:339:339))
        (IOPATH i o (1692:1692:1692) (1637:1637:1637))
        (IOPATH oe o (1696:1696:1696) (1622:1622:1622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (295:295:295) (328:328:328))
        (PORT oe (306:306:306) (344:344:344))
        (IOPATH i o (1632:1632:1632) (1577:1577:1577))
        (IOPATH oe o (1696:1696:1696) (1622:1622:1622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (293:293:293) (327:327:327))
        (PORT oe (299:299:299) (334:334:334))
        (IOPATH i o (1652:1652:1652) (1597:1597:1597))
        (IOPATH oe o (1696:1696:1696) (1622:1622:1622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_1\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (285:285:285) (316:316:316))
        (PORT oe (319:319:319) (360:360:360))
        (IOPATH i o (1652:1652:1652) (1597:1597:1597))
        (IOPATH oe o (1696:1696:1696) (1622:1622:1622))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (317:317:317) (364:364:364))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (325:325:325) (376:376:376))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (317:317:317) (364:364:364))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (324:324:324) (376:376:376))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datac (196:196:196) (231:231:231))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (285:285:285) (323:323:323))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (197:197:197) (232:232:232))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (285:285:285) (323:323:323))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (197:197:197) (232:232:232))
        (IOPATH datac combout (119:119:119) (124:124:124))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (285:285:285) (323:323:323))
        (IOPATH datad combout (68:68:68) (63:63:63))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio3_io_in\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (1609:1609:1609) (1788:1788:1788))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_in\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (1599:1599:1599) (1781:1781:1781))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rv32.sys_clk\~QIC_DANGLING_PORT)
    (DELAY
      (ABSOLUTE
        (PORT datad (983:983:983) (1012:1012:1012))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE auto_generated_inst.gclksw_inst\|gclk_switch)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (102:102:102) (85:85:85))
        (PORT inclk[2] (1169:1169:1169) (1162:1162:1162))
        (PORT clkselect[0] (1895:1895:1895) (2143:2143:2143))
        (PORT clkselect[1] (2435:2435:2435) (2796:2796:2796))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE auto_generated_inst.pll_inst\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT areset (930:930:930) (930:930:930))
        (PORT inclk[0] (1158:1158:1158) (1158:1158:1158))
      )
    )
  )
)
