// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.


// 
// Device: Altera EP4CE75F29C8 Package FBGA780
// 

//
// This file contains Slow Corner delays for the design using part EP4CE75F29C8,
// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius
//

// 
// This SDF file should be used for ModelSim (Verilog) only
// 

(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "fpga_boot")
  (DATE "07/15/2025 15:09:48")
  (VENDOR "Altera")
  (PROGRAM "Quartus II 64-Bit")
  (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Full Version")
  (DIVIDER .)
  (TIMESCALE 1 ps)

  (CELL
    (CELLTYPE "dffeas")
    (INSTANCE pll_inst\|auto_generated\|pll_lock_sync)
    (DELAY
      (ABSOLUTE
        (PORT clk (3844:3844:3844) (4713:4713:4713))
        (PORT d (90:90:90) (101:101:101))
        (PORT clrn (2005:2005:2005) (1968:1968:1968))
        (IOPATH (posedge clk) q (240:240:240) (240:240:240))
        (IOPATH (negedge clrn) q (222:222:222) (222:222:222))
      )
    )
    (TIMINGCHECK
      (HOLD d (posedge clk) (195:195:195))
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE pll_inst\|auto_generated\|locked)
    (DELAY
      (ABSOLUTE
        (PORT datac (3191:3191:3191) (4036:4036:4036))
        (PORT datad (278:278:278) (333:333:333))
        (IOPATH datac combout (301:301:301) (285:285:285))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (229:229:229) (236:236:236))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE sys_ctrl_clkSource\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (1493:1493:1493) (1236:1236:1236))
        (IOPATH datac combout (305:305:305) (285:285:285))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO9_1\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (720:720:720) (816:816:816))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE GPIO3_0\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (720:720:720) (816:816:816))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSI\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (781:781:781) (877:877:877))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_ibuf")
    (INSTANCE PIN_HSE\~input)
    (DELAY
      (ABSOLUTE
        (IOPATH i o (791:791:791) (887:887:887))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE pll_inst\|auto_generated\|locked\~clkctrl)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (876:876:876) (775:775:775))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (750:750:750) (640:640:640))
        (PORT oe (760:760:760) (639:639:639))
        (IOPATH i o (2742:2742:2742) (2629:2629:2629))
        (IOPATH oe o (2803:2803:2803) (2637:2637:2637))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO6_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (728:728:728) (612:612:612))
        (PORT oe (750:750:750) (636:636:636))
        (IOPATH i o (2782:2782:2782) (2669:2669:2669))
        (IOPATH oe o (2803:2803:2803) (2637:2637:2637))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_0\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (749:749:749) (626:626:626))
        (PORT oe (767:767:767) (640:640:640))
        (IOPATH i o (2722:2722:2722) (2609:2609:2609))
        (IOPATH oe o (2803:2803:2803) (2637:2637:2637))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_2\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (748:748:748) (614:614:614))
        (PORT oe (741:741:741) (627:627:627))
        (IOPATH i o (2742:2742:2742) (2629:2629:2629))
        (IOPATH oe o (2803:2803:2803) (2637:2637:2637))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_io_obuf")
    (INSTANCE GPIO9_1\~output)
    (DELAY
      (ABSOLUTE
        (PORT i (728:728:728) (600:600:600))
        (PORT oe (799:799:799) (670:670:670))
        (IOPATH i o (2742:2742:2742) (2629:2629:2629))
        (IOPATH oe o (2803:2803:2803) (2637:2637:2637))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (807:807:807) (679:679:679))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (841:841:841) (701:701:701))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (807:807:807) (679:679:679))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio6_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (841:841:841) (700:700:700))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datac (518:518:518) (448:448:448))
        (IOPATH datac combout (305:305:305) (285:285:285))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (741:741:741) (624:624:624))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datac (519:519:519) (449:449:449))
        (IOPATH datac combout (305:305:305) (285:285:285))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[2\])
    (DELAY
      (ABSOLUTE
        (PORT datad (741:741:741) (623:623:623))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_data\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (518:518:518) (448:448:448))
        (IOPATH datac combout (305:305:305) (285:285:285))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_out_en\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datad (741:741:741) (624:624:624))
        (IOPATH datad combout (167:167:167) (143:143:143))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio3_io_in\[0\])
    (DELAY
      (ABSOLUTE
        (PORT datad (2886:2886:2886) (3032:3032:3032))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE gpio9_io_in\[1\])
    (DELAY
      (ABSOLUTE
        (PORT datac (2869:2869:2869) (3024:3024:3024))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_lcell_comb")
    (INSTANCE rv32.sys_clk\~QIC_DANGLING_PORT)
    (DELAY
      (ABSOLUTE
        (PORT datad (1801:1801:1801) (1744:1744:1744))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_clkctrl")
    (INSTANCE auto_generated_inst.gclksw_inst\|gclk_switch)
    (DELAY
      (ABSOLUTE
        (PORT inclk[0] (181:181:181) (177:177:177))
        (PORT inclk[2] (2107:2107:2107) (2074:2074:2074))
        (PORT clkselect[0] (4380:4380:4380) (3795:3795:3795))
        (PORT clkselect[1] (5422:5422:5422) (4895:4895:4895))
      )
    )
  )
  (CELL
    (CELLTYPE "cycloneive_pll")
    (INSTANCE auto_generated_inst.pll_inst\|auto_generated\|pll1)
    (DELAY
      (ABSOLUTE
        (PORT areset (1682:1682:1682) (1682:1682:1682))
        (PORT inclk[0] (2125:2125:2125) (2125:2125:2125))
      )
    )
  )
)
