set tool_name "ModelSim (Verilog)"
set corner_file_list {
	{{"Slow -8 1.2V 85 Model"} {fpga_boot_8_1200mv_85c_slow.vo fpga_boot_8_1200mv_85c_v_slow.sdo}}
	{{"Slow -8 1.2V 0 Model"} {fpga_boot_8_1200mv_0c_slow.vo fpga_boot_8_1200mv_0c_v_slow.sdo}}
	{{"Fast -M 1.2V 0 Model"} {fpga_boot_min_1200mv_0c_fast.vo fpga_boot_min_1200mv_0c_v_fast.sdo}}
}
