2006_APP/logic/multi_uart_ip/multi_uart.v

module multi_uart #(parameter CNT = 5, DATA_WIDTH = 8, FIFO_DEPTH = 1) (
  input            apb_clock,
  input            apb_resetn,
  input            apb_psel,
  input            apb_penable,
  input            apb_pwrite,
  input  [11:0]    apb_paddr,
  input  [31:0]    apb_pwdata,
  output [31:0]    apb_prdata,
  output           apb_pready,
  output [CNT-1:0] uart_txd,
  input  [CNT-1:0] uart_rxd,
  input  [CNT-1:0] tx_dma_clr,
  output [CNT-1:0] tx_dma_req,
  input  [CNT-1:0] rx_dma_clr,
  output [CNT-1:0] rx_dma_req,
  output [CNT-1:0] interrupts,
  
  output [CNT-1:0] uart_tx_busy
);

wire uart_en;
wire [15:0] ibrd;
wire [5:0] fbrd;

wire [CNT-1:0] clear_flags;
wire [CNT-1:0] tx_write;
wire [CNT-1:0] tx_full;
wire [CNT-1:0] tx_empty;
wire [CNT-1:0] tx_busy;
wire [CNT-1:0] tx_complete;
wire [CNT-1:0] tx_dma_en;

wire [CNT-1:0] rx_read;
wire [CNT-1:0] rx_full;
wire [CNT-1:0] rx_empty;
wire [CNT-1:0] rx_idle;
wire [CNT-1:0] framing_error;
wire [CNT-1:0] parity_error;
wire [CNT-1:0] break_error;
wire [CNT-1:0] overrun_error;
wire [CNT-1:0] rx_dma_en;
wire [DATA_WIDTH*CNT-1:0] rx_data;

baud_gen u_baud(
  .clk   (apb_clock ),
  .rstn  (apb_resetn),
  .ibrd  (ibrd      ),
  .fbrd  (fbrd      ),
  .stop  (!uart_en  ),
  .baud16(baud16    )
);

uart_regs #(CNT, DATA_WIDTH) u_regs(
  .apb_clock  (apb_clock  ),
  .apb_resetn (apb_resetn ),
  .apb_psel   (apb_psel   ),
  .apb_penable(apb_penable),
  .apb_pwrite (apb_pwrite ),
  .apb_paddr  (apb_paddr  ),
  .apb_pwdata (apb_pwdata ),
  .apb_prdata (apb_prdata ),
  .apb_pready (apb_pready ),

  .uart_en      (uart_en      ),
  .ibrd         (ibrd         ),
  .fbrd         (fbrd         ),
  .tx_write     (tx_write     ),
  .rx_read      (rx_read      ),
  .rx_data      (rx_data      ),
  .tx_full      (tx_full      ),
  .tx_empty     (tx_empty     ),
  .tx_busy      (tx_busy      ),
  .tx_complete  (tx_complete  ),
  .rx_full      (rx_full      ),
  .rx_empty     (rx_empty     ),
  .rx_idle      (rx_idle      ),
  .framing_error(framing_error),
  .parity_error (parity_error ),
  .break_error  (break_error  ),
  .overrun_error(overrun_error),
  .clear_flags  (clear_flags  ),
  .lcr_sps      (lcr_sps      ),
  .lcr_stp2     (lcr_stp2     ),
  .lcr_eps      (lcr_eps      ),
  .lcr_pen      (lcr_pen      ),
  .rx_dma_en    (rx_dma_en    ),
  .tx_dma_en    (tx_dma_en    ),
  .interrupts   (interrupts   ),
);

uart_tx #(DATA_WIDTH, FIFO_DEPTH) u_tx[CNT-1:0](
  .clk        (apb_clock                 ),
  .rstn       (apb_resetn                ),
  .baud16     (baud16                    ),
  .tx_write   (tx_write                  ),
  .tx_data    (apb_pwdata[DATA_WIDTH-1:0]),
  .lcr_sps    (lcr_sps                   ),
  .lcr_stp2   (lcr_stp2                  ),
  .lcr_eps    (lcr_eps                   ),
  .lcr_pen    (lcr_pen                   ),
  .tx_clear   (clear_flags               ),
  .tx_full    (tx_full                   ),
  .tx_empty   (tx_empty                  ),
  .tx_busy    (tx_busy                   ),
  .tx_complete(tx_complete               ),
  .tx_dma_en  (tx_dma_en                 ),
  .tx_dma_clr (tx_dma_clr                ),
  .tx_dma_req (tx_dma_req                ),
  .uart_txd   (uart_txd                  )
);

uart_rx #(DATA_WIDTH, FIFO_DEPTH) u_rx[CNT-1:0](
  .clk          (apb_clock    ),
  .rstn         (apb_resetn   ),
  .baud16       (baud16       ),
  .lcr_sps      (lcr_sps      ),
  .lcr_stp2     (lcr_stp2     ),
  .lcr_eps      (lcr_eps      ),
  .lcr_pen      (lcr_pen      ),
  .rx_read      (rx_read      ),
  .rx_clear     (clear_flags  ),
  .rx_full      (rx_full      ),
  .rx_empty     (rx_empty     ),
  .rx_data      (rx_data      ),
  .rx_idle      (rx_idle      ),
  .framing_error(framing_error),
  .parity_error (parity_error ),
  .break_error  (break_error  ),
  .overrun_error(overrun_error),
  .rx_dma_en    (rx_dma_en    ),
  .rx_dma_clr   (rx_dma_clr   ),
  .rx_dma_req   (rx_dma_req   ),
  .uart_rxd     (uart_rxd     )
);
assign uart_tx_busy = tx_busy;
endmodule