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test_uart.map.rpt

test_uart.map.rpt 298 KB
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
  1. Analysis & Synthesis report for test_uart
    2. 

  2. Tue Jul 15 16:26:14 2025
    3. 

  3. Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    4. 

  4. 

  5. 

  6. ---------------------
    7. 

  7. ; Table of Contents ;
    8. 

  8. ---------------------
    9. 

  9.   1. Legal Notice
    10. 

  10.   2. Analysis & Synthesis Summary
    11. 

  11.   3. Analysis & Synthesis Settings
    12. 

  12.   4. Parallel Compilation
    13. 

  13.   5. Analysis & Synthesis Source Files Read
    14. 

  14.   6. Partition Status Summary
    15. 

  15.   7. Partition for Top-Level Resource Utilization by Entity
    16. 

  16.   8. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state
    17. 

  17.   9. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state
    18. 

  18.  10. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state
    19. 

  19.  11. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state
    20. 

  20.  12. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state
    21. 

  21.  13. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state
    22. 

  22.  14. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state
    23. 

  23.  15. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state
    24. 

  24.  16. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state
    25. 

  25.  17. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state
    26. 

  26.  18. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state
    27. 

  27.  19. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state
    28. 

  28.  20. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state
    29. 

  29.  21. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state
    30. 

  30.  22. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state
    31. 

  31.  23. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state
    32. 

  32.  24. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state
    33. 

  33.  25. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state
    34. 

  34.  26. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state
    35. 

  35.  27. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state
    36. 

  36.  28. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state
    37. 

  37.  29. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state
    38. 

  38.  30. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state
    39. 

  39.  31. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state
    40. 

  40.  32. State Machine - |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|apbState
    41. 

  41.  33. Registers Removed During Synthesis
    42. 

  42.  34. Removed Registers Triggering Further Register Optimizations
    43. 

  43.  35. Multiplexer Restructuring Statistics (Restructuring Performed)
    44. 

  44.  36. Source assignments for Top-level Entity: |test_uart
    45. 

  45.  37. Parameter Settings for User Entity Instance: altpll:pll_inst
    46. 

  46.  38. Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst
    47. 

  47.  39. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst
    48. 

  48.  40. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb
    49. 

  49.  41. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|apb_mux:u_apb_mux
    50. 

  50.  42. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]
    51. 

  51.  43. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs
    52. 

  52.  44. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]
    53. 

  53.  45. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo
    54. 

  54.  46. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]
    55. 

  55.  47. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo
    56. 

  56.  48. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]
    57. 

  57.  49. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo
    58. 

  58.  50. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]
    59. 

  59.  51. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo
    60. 

  60.  52. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]
    61. 

  61.  53. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo
    62. 

  62.  54. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]
    63. 

  63.  55. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo
    64. 

  64.  56. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]
    65. 

  65.  57. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo
    66. 

  66.  58. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]
    67. 

  67.  59. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo
    68. 

  68.  60. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]
    69. 

  69.  61. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo
    70. 

  70.  62. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]
    71. 

  71.  63. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo
    72. 

  72.  64. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]
    73. 

  73.  65. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo
    74. 

  74.  66. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]
    75. 

  75.  67. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo
    76. 

  76.  68. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]
    77. 

  77.  69. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs
    78. 

  78.  70. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]
    79. 

  79.  71. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo
    80. 

  80.  72. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]
    81. 

  81.  73. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo
    82. 

  82.  74. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]
    83. 

  83.  75. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo
    84. 

  84.  76. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]
    85. 

  85.  77. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo
    86. 

  86.  78. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]
    87. 

  87.  79. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo
    88. 

  88.  80. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]
    89. 

  89.  81. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo
    90. 

  90.  82. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]
    91. 

  91.  83. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo
    92. 

  92.  84. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]
    93. 

  93.  85. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo
    94. 

  94.  86. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]
    95. 

  95.  87. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo
    96. 

  96.  88. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]
    97. 

  97.  89. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo
    98. 

  98.  90. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]
    99. 

  99.  91. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo
    100. 

  100.  92. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]
    101. 

  101.  93. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo
    102. 

  102.  94. Partition Dependent Files
    103. 

  103.  95. Partition "rv32" Resource Utilization by Entity
    104. 

  104.  96. Parameter Settings for User Entity Instance: alta_rv32:rv32
    105. 

  105.  97. Partition Dependent Files
    106. 

  106.  98. Port Connectivity Checks: "alta_rv32:rv32"
    107. 

  107.  99. Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[1]"
    108. 

  108. 100. Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[0]"
    109. 

  109. 101. Port Connectivity Checks: "multi_uart_ip:macro_inst|apb_mux:u_apb_mux"
    110. 

  110. 102. Port Connectivity Checks: "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb"
    111. 

  111. 103. Port Connectivity Checks: "multi_uart_ip:macro_inst"
    112. 

  112. 104. Port Connectivity Checks: "alta_gclksw:gclksw_inst"
    113. 

  113. 105. Elapsed Time Per Partition
    114. 

  114. 106. Analysis & Synthesis Messages
    115. 

  115. 107. Analysis & Synthesis Suppressed Messages
    116. 

  116. 

  117. 

  118. 

  119. ----------------
    120. 

  120. ; Legal Notice ;
    121. 

  121. ----------------
    122. 

  122. Copyright (C) 1991-2013 Altera Corporation
    123. 

  123. Your use of Altera Corporation's design tools, logic functions 
    124. 

  124. and other software and tools, and its AMPP partner logic 
    125. 

  125. functions, and any output files from any of the foregoing 
    126. 

  126. (including device programming or simulation files), and any 
    127. 

  127. associated documentation or information are expressly subject 
    128. 

  128. to the terms and conditions of the Altera Program License 
    129. 

  129. Subscription Agreement, Altera MegaCore Function License 
    130. 

  130. Agreement, or other applicable license agreement, including, 
    131. 

  131. without limitation, that your use is for the sole purpose of 
    132. 

  132. programming logic devices manufactured by Altera and sold by 
    133. 

  133. Altera or its authorized distributors.  Please refer to the 
    134. 

  134. applicable agreement for further details.
    135. 

  135. 

  136. 

  137. 

  138. +----------------------------------------------------------------------------------+
    139. 

  139. ; Analysis & Synthesis Summary                                                     ;
    140. 

  140. +------------------------------------+---------------------------------------------+
    141. 

  141. ; Analysis & Synthesis Status        ; Successful - Tue Jul 15 16:26:14 2025       ;
    142. 

  142. ; Quartus II 64-Bit Version          ; 13.0.0 Build 156 04/24/2013 SJ Full Version ;
    143. 

  143. ; Revision Name                      ; test_uart                                   ;
    144. 

  144. ; Top-level Entity Name              ; test_uart                                   ;
    145. 

  145. ; Family                             ; Cyclone IV E                                ;
    146. 

  146. ; Total logic elements               ; N/A until Partition Merge                   ;
    147. 

  147. ;     Total combinational functions  ; N/A until Partition Merge                   ;
    148. 

  148. ;     Dedicated logic registers      ; N/A until Partition Merge                   ;
    149. 

  149. ; Total registers                    ; N/A until Partition Merge                   ;
    150. 

  150. ; Total pins                         ; N/A until Partition Merge                   ;
    151. 

  151. ; Total virtual pins                 ; N/A until Partition Merge                   ;
    152. 

  152. ; Total memory bits                  ; N/A until Partition Merge                   ;
    153. 

  153. ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                   ;
    154. 

  154. ; Total PLLs                         ; N/A until Partition Merge                   ;
    155. 

  155. +------------------------------------+---------------------------------------------+
    156. 

  156. 

  157. 

  158. +----------------------------------------------------------------------------------------------------------------------+
    159. 

  159. ; Analysis & Synthesis Settings                                                                                        ;
    160. 

  160. +----------------------------------------------------------------------------+--------------------+--------------------+
    161. 

  161. ; Option                                                                     ; Setting            ; Default Value      ;
    162. 

  162. +----------------------------------------------------------------------------+--------------------+--------------------+
    163. 

  163. ; Device                                                                     ; EP4CE75F29C8       ;                    ;
    164. 

  164. ; Top-level entity name                                                      ; test_uart          ; test_uart          ;
    165. 

  165. ; Family name                                                                ; Cyclone IV E       ; Cyclone V          ;
    166. 

  166. ; Maximum processors allowed for parallel compilation                        ; All                ;                    ;
    167. 

  167. ; Maximum DSP Block Usage                                                    ; 0                  ; -1 (Unlimited)     ;
    168. 

  168. ; Auto Open-Drain Pins                                                       ; Off                ; On                 ;
    169. 

  169. ; Perform WYSIWYG Primitive Resynthesis                                      ; On                 ; Off                ;
    170. 

  170. ; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks                          ; 4                  ; -1 (Unlimited)     ;
    171. 

  171. ; Use smart compilation                                                      ; Off                ; Off                ;
    172. 

  172. ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
    173. 

  173. ; Enable compact report table                                                ; Off                ; Off                ;
    174. 

  174. ; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
    175. 

  175. ; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
    176. 

  176. ; Preserve fewer node names                                                  ; On                 ; On                 ;
    177. 

  177. ; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
    178. 

  178. ; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
    179. 

  179. ; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
    180. 

  180. ; State Machine Processing                                                   ; Auto               ; Auto               ;
    181. 

  181. ; Safe State Machine                                                         ; Off                ; Off                ;
    182. 

  182. ; Extract Verilog State Machines                                             ; On                 ; On                 ;
    183. 

  183. ; Extract VHDL State Machines                                                ; On                 ; On                 ;
    184. 

  184. ; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
    185. 

  185. ; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
    186. 

  186. ; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
    187. 

  187. ; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
    188. 

  188. ; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
    189. 

  189. ; Parallel Synthesis                                                         ; On                 ; On                 ;
    190. 

  190. ; DSP Block Balancing                                                        ; Auto               ; Auto               ;
    191. 

  191. ; NOT Gate Push-Back                                                         ; On                 ; On                 ;
    192. 

  192. ; Power-Up Don't Care                                                        ; On                 ; On                 ;
    193. 

  193. ; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
    194. 

  194. ; Remove Duplicate Registers                                                 ; On                 ; On                 ;
    195. 

  195. ; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
    196. 

  196. ; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
    197. 

  197. ; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
    198. 

  198. ; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
    199. 

  199. ; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
    200. 

  200. ; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
    201. 

  201. ; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
    202. 

  202. ; Optimization Technique                                                     ; Balanced           ; Balanced           ;
    203. 

  203. ; Carry Chain Length                                                         ; 70                 ; 70                 ;
    204. 

  204. ; Auto Carry Chains                                                          ; On                 ; On                 ;
    205. 

  205. ; Auto ROM Replacement                                                       ; On                 ; On                 ;
    206. 

  206. ; Auto RAM Replacement                                                       ; On                 ; On                 ;
    207. 

  207. ; Auto DSP Block Replacement                                                 ; On                 ; On                 ;
    208. 

  208. ; Auto Shift Register Replacement                                            ; Auto               ; Auto               ;
    209. 

  209. ; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
    210. 

  210. ; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
    211. 

  211. ; Strict RAM Replacement                                                     ; Off                ; Off                ;
    212. 

  212. ; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
    213. 

  213. ; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
    214. 

  214. ; Auto RAM Block Balancing                                                   ; On                 ; On                 ;
    215. 

  215. ; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
    216. 

  216. ; Auto Resource Sharing                                                      ; Off                ; Off                ;
    217. 

  217. ; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
    218. 

  218. ; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
    219. 

  219. ; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
    220. 

  220. ; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
    221. 

  221. ; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
    222. 

  222. ; Timing-Driven Synthesis                                                    ; On                 ; On                 ;
    223. 

  223. ; Report Parameter Settings                                                  ; On                 ; On                 ;
    224. 

  224. ; Report Source Assignments                                                  ; On                 ; On                 ;
    225. 

  225. ; Report Connectivity Checks                                                 ; On                 ; On                 ;
    226. 

  226. ; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
    227. 

  227. ; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
    228. 

  228. ; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
    229. 

  229. ; HDL message level                                                          ; Level2             ; Level2             ;
    230. 

  230. ; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
    231. 

  231. ; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
    232. 

  232. ; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
    233. 

  233. ; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
    234. 

  234. ; Clock MUX Protection                                                       ; On                 ; On                 ;
    235. 

  235. ; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
    236. 

  236. ; Block Design Naming                                                        ; Auto               ; Auto               ;
    237. 

  237. ; SDC constraint protection                                                  ; Off                ; Off                ;
    238. 

  238. ; Synthesis Effort                                                           ; Auto               ; Auto               ;
    239. 

  239. ; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
    240. 

  240. ; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
    241. 

  241. ; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
    242. 

  242. ; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
    243. 

  243. ; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
    244. 

  244. ; Synthesis Seed                                                             ; 1                  ; 1                  ;
    245. 

  245. +----------------------------------------------------------------------------+--------------------+--------------------+
    246. 

  246. 

  247. 

  248. +------------------------------------------+
    249. 

  249. ; Parallel Compilation                     ;
    250. 

  250. +----------------------------+-------------+
    251. 

  251. ; Processors                 ; Number      ;
    252. 

  252. +----------------------------+-------------+
    253. 

  253. ; Number detected on machine ; 8           ;
    254. 

  254. ; Maximum allowed            ; 4           ;
    255. 

  255. ;                            ;             ;
    256. 

  256. ; Average used               ; 1.89        ;
    257. 

  257. ; Maximum used               ; 2           ;
    258. 

  258. ;                            ;             ;
    259. 

  259. ; Usage by Processor         ; % Time Used ;
    260. 

  260. ;     Processor 1            ; 100.0%      ;
    261. 

  261. ;     Processor 2            ;  88.9%      ;
    262. 

  262. ;     Processors 3-8         ;   0.0%      ;
    263. 

  263. +----------------------------+-------------+
    264. 

  264. 

  265. 

  266. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    267. 

  267. ; Analysis & Synthesis Source Files Read                                                                                                                                                                                       ;
    268. 

  268. +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
    269. 

  269. ; File Name with User-Entered Path                                                ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                                    ; Library ;
    270. 

  270. +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
    271. 

  271. ; test_uart.v                                                                     ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/test_uart.v                                 ;         ;
    272. 

  272. ; multi_uart_ip.v                                                                 ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip.v                             ;         ;
    273. 

  273. ; multi_uart_ip/baud_gen.v                                                        ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/baud_gen.v                    ;         ;
    274. 

  274. ; multi_uart_ip/multi_uart.v                                                      ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/multi_uart.v                  ;         ;
    275. 

  275. ; multi_uart_ip/sync_fifo.v                                                       ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/sync_fifo.v                   ;         ;
    276. 

  276. ; multi_uart_ip/uart_regs.v                                                       ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_regs.v                   ;         ;
    277. 

  277. ; multi_uart_ip/uart_rx.v                                                         ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_rx.v                     ;         ;
    278. 

  278. ; multi_uart_ip/uart_tx.v                                                         ; yes             ; User Verilog HDL File        ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_tx.v                     ;         ;
    279. 

  279. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; yes             ; User Verilog HDL File        ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ;         ;
    280. 

  280. ; altpll.tdf                                                                      ; yes             ; Megafunction                 ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf                       ;         ;
    281. 

  281. ; aglobal130.inc                                                                  ; yes             ; Megafunction                 ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc                   ;         ;
    282. 

  282. ; stratix_pll.inc                                                                 ; yes             ; Megafunction                 ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc                  ;         ;
    283. 

  283. ; stratixii_pll.inc                                                               ; yes             ; Megafunction                 ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc                ;         ;
    284. 

  284. ; cycloneii_pll.inc                                                               ; yes             ; Megafunction                 ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc                ;         ;
    285. 

  285. ; db/altpll_9g32.tdf                                                              ; yes             ; Auto-Generated Megafunction  ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/db/altpll_9g32.tdf                          ;         ;
    286. 

  286. ; ahb2apb.v                                                                       ; yes             ; Auto-Found Verilog HDL File  ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/ahb2apb.v                                   ;         ;
    287. 

  287. ; apb_mux.v                                                                       ; yes             ; Auto-Found Verilog HDL File  ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/apb_mux.v                                   ;         ;
    288. 

  288. +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+
    289. 

  289. 

  290. 

  291. +-----------------------------------------------------------+
    292. 

  292. ; Partition Status Summary                                  ;
    293. 

  293. +----------------+-------------+----------------------------+
    294. 

  294. ; Partition Name ; Synthesized ; Reason                     ;
    295. 

  295. +----------------+-------------+----------------------------+
    296. 

  296. ; rv32           ; yes         ; netlist type = Source File ;
    297. 

  297. ; Top            ; yes         ; netlist type = Source File ;
    298. 

  298. +----------------+-------------+----------------------------+
    299. 

  299. 

  300. 

  301. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    302. 

  302. ; Partition for Top-Level Resource Utilization by Entity                                                                                                                                                                                                     ;
    303. 

  303. +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+
    304. 

  304. ; Compilation Hierarchy Node         ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                        ; Library Name ;
    305. 

  305. +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+
    306. 

  306. ; |test_uart                         ; 1889 (127)        ; 1303 (0)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart                                                                                 ; work         ;
    307. 

  307. ;    |alta_gclksw:gclksw_inst|       ; 0 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|alta_gclksw:gclksw_inst                                                         ; work         ;
    308. 

  308. ;    |altpll:pll_inst|               ; 0 (0)             ; 1 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|altpll:pll_inst                                                                 ; work         ;
    309. 

  309. ;       |altpll_9g32:auto_generated| ; 0 (0)             ; 1 (1)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|altpll:pll_inst|altpll_9g32:auto_generated                                      ; work         ;
    310. 

  310. ;    |multi_uart_ip:macro_inst|      ; 1762 (27)         ; 1302 (9)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst                                                        ; work         ;
    311. 

  311. ;       |ahb2apb:u_ahb2apb|          ; 13 (13)           ; 47 (47)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb                                      ; work         ;
    312. 

  312. ;       |apb_mux:u_apb_mux|          ; 19 (19)           ; 2 (2)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|apb_mux:u_apb_mux                                      ; work         ;
    313. 

  313. ;       |multi_uart:u_uart[0]|       ; 859 (0)           ; 624 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]                                   ; work         ;
    314. 

  314. ;          |baud_gen:u_baud|         ; 35 (35)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|baud_gen:u_baud                   ; work         ;
    315. 

  315. ;          |uart_regs:u_regs|        ; 247 (247)         ; 134 (134)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs                  ; work         ;
    316. 

  316. ;          |uart_rx:u_rx[0]|         ; 55 (53)           ; 44 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]                   ; work         ;
    317. 

  317. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; work         ;
    318. 

  318. ;          |uart_rx:u_rx[1]|         ; 55 (53)           ; 44 (35)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]                   ; work         ;
    319. 

  319. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; work         ;
    320. 

  320. ;          |uart_rx:u_rx[2]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]                   ; work         ;
    321. 

  321. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; work         ;
    322. 

  322. ;          |uart_rx:u_rx[3]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]                   ; work         ;
    323. 

  323. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; work         ;
    324. 

  324. ;          |uart_rx:u_rx[4]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]                   ; work         ;
    325. 

  325. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; work         ;
    326. 

  326. ;          |uart_rx:u_rx[5]|         ; 57 (55)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]                   ; work         ;
    327. 

  327. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; work         ;
    328. 

  328. ;          |uart_tx:u_tx[0]|         ; 42 (40)           ; 35 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]                   ; work         ;
    329. 

  329. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; work         ;
    330. 

  330. ;          |uart_tx:u_tx[1]|         ; 42 (40)           ; 35 (26)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]                   ; work         ;
    331. 

  331. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; work         ;
    332. 

  332. ;          |uart_tx:u_tx[2]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]                   ; work         ;
    333. 

  333. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; work         ;
    334. 

  334. ;          |uart_tx:u_tx[3]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]                   ; work         ;
    335. 

  335. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; work         ;
    336. 

  336. ;          |uart_tx:u_tx[4]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]                   ; work         ;
    337. 

  337. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; work         ;
    338. 

  338. ;          |uart_tx:u_tx[5]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]                   ; work         ;
    339. 

  339. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; work         ;
    340. 

  340. ;       |multi_uart:u_uart[1]|       ; 844 (0)           ; 620 (0)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]                                   ; work         ;
    341. 

  341. ;          |baud_gen:u_baud|         ; 35 (35)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|baud_gen:u_baud                   ; work         ;
    342. 

  342. ;          |uart_regs:u_regs|        ; 232 (232)         ; 134 (134)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs                  ; work         ;
    343. 

  343. ;          |uart_rx:u_rx[0]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]                   ; work         ;
    344. 

  344. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; work         ;
    345. 

  345. ;          |uart_rx:u_rx[1]|         ; 55 (53)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]                   ; work         ;
    346. 

  346. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; work         ;
    347. 

  347. ;          |uart_rx:u_rx[2]|         ; 56 (54)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]                   ; work         ;
    348. 

  348. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; work         ;
    349. 

  349. ;          |uart_rx:u_rx[3]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]                   ; work         ;
    350. 

  350. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; work         ;
    351. 

  351. ;          |uart_rx:u_rx[4]|         ; 54 (52)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]                   ; work         ;
    352. 

  352. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; work         ;
    353. 

  353. ;          |uart_rx:u_rx[5]|         ; 57 (55)           ; 43 (34)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]                   ; work         ;
    354. 

  354. ;             |sync_fifo:rx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; work         ;
    355. 

  355. ;          |uart_tx:u_tx[0]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]                   ; work         ;
    356. 

  356. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; work         ;
    357. 

  357. ;          |uart_tx:u_tx[1]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]                   ; work         ;
    358. 

  358. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; work         ;
    359. 

  359. ;          |uart_tx:u_tx[2]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]                   ; work         ;
    360. 

  360. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; work         ;
    361. 

  361. ;          |uart_tx:u_tx[3]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]                   ; work         ;
    362. 

  362. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; work         ;
    363. 

  363. ;          |uart_tx:u_tx[4]|         ; 42 (40)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]                   ; work         ;
    364. 

  364. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; work         ;
    365. 

  365. ;          |uart_tx:u_tx[5]|         ; 41 (39)           ; 34 (25)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]                   ; work         ;
    366. 

  366. ;             |sync_fifo:tx_fifo|    ; 2 (2)             ; 9 (9)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; work         ;
    367. 

  367. +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+
    368. 

  368. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    369. 

  369. 

  370. 

  371. Encoding Type:  One-Hot
    372. 

  372. +----------------------------------------------------------------------------------------------------------------------------------+
    373. 

  373. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state                                ;
    374. 

  374. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    375. 

  375. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    376. 

  376. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    377. 

  377. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    378. 

  378. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    379. 

  379. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    380. 

  380. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    381. 

  381. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    382. 

  382. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    383. 

  383. 

  384. 

  385. Encoding Type:  One-Hot
    386. 

  386. +----------------------------------------------------------------------------------------------------------------------------------+
    387. 

  387. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state                                ;
    388. 

  388. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    389. 

  389. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    390. 

  390. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    391. 

  391. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    392. 

  392. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    393. 

  393. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    394. 

  394. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    395. 

  395. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    396. 

  396. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    397. 

  397. 

  398. 

  399. Encoding Type:  One-Hot
    400. 

  400. +----------------------------------------------------------------------------------------------------------------------------------+
    401. 

  401. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state                                ;
    402. 

  402. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    403. 

  403. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    404. 

  404. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    405. 

  405. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    406. 

  406. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    407. 

  407. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    408. 

  408. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    409. 

  409. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    410. 

  410. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    411. 

  411. 

  412. 

  413. Encoding Type:  One-Hot
    414. 

  414. +----------------------------------------------------------------------------------------------------------------------------------+
    415. 

  415. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state                                ;
    416. 

  416. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    417. 

  417. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    418. 

  418. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    419. 

  419. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    420. 

  420. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    421. 

  421. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    422. 

  422. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    423. 

  423. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    424. 

  424. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    425. 

  425. 

  426. 

  427. Encoding Type:  One-Hot
    428. 

  428. +----------------------------------------------------------------------------------------------------------------------------------+
    429. 

  429. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state                                ;
    430. 

  430. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    431. 

  431. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    432. 

  432. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    433. 

  433. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    434. 

  434. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    435. 

  435. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    436. 

  436. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    437. 

  437. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    438. 

  438. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    439. 

  439. 

  440. 

  441. Encoding Type:  One-Hot
    442. 

  442. +----------------------------------------------------------------------------------------------------------------------------------+
    443. 

  443. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state                                ;
    444. 

  444. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    445. 

  445. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    446. 

  446. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    447. 

  447. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    448. 

  448. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    449. 

  449. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    450. 

  450. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    451. 

  451. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    452. 

  452. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    453. 

  453. 

  454. 

  455. Encoding Type:  One-Hot
    456. 

  456. +----------------------------------------------------------------------------------------------------------------------------------+
    457. 

  457. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state                                ;
    458. 

  458. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    459. 

  459. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    460. 

  460. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    461. 

  461. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    462. 

  462. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    463. 

  463. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    464. 

  464. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    465. 

  465. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    466. 

  466. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    467. 

  467. 

  468. 

  469. Encoding Type:  One-Hot
    470. 

  470. +----------------------------------------------------------------------------------------------------------------------------------+
    471. 

  471. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state                                ;
    472. 

  472. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    473. 

  473. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    474. 

  474. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    475. 

  475. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    476. 

  476. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    477. 

  477. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    478. 

  478. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    479. 

  479. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    480. 

  480. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    481. 

  481. 

  482. 

  483. Encoding Type:  One-Hot
    484. 

  484. +----------------------------------------------------------------------------------------------------------------------------------+
    485. 

  485. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state                                ;
    486. 

  486. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    487. 

  487. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    488. 

  488. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    489. 

  489. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    490. 

  490. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    491. 

  491. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    492. 

  492. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    493. 

  493. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    494. 

  494. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    495. 

  495. 

  496. 

  497. Encoding Type:  One-Hot
    498. 

  498. +----------------------------------------------------------------------------------------------------------------------------------+
    499. 

  499. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state                                ;
    500. 

  500. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    501. 

  501. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    502. 

  502. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    503. 

  503. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    504. 

  504. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    505. 

  505. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    506. 

  506. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    507. 

  507. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    508. 

  508. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    509. 

  509. 

  510. 

  511. Encoding Type:  One-Hot
    512. 

  512. +----------------------------------------------------------------------------------------------------------------------------------+
    513. 

  513. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state                                ;
    514. 

  514. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    515. 

  515. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    516. 

  516. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    517. 

  517. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    518. 

  518. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    519. 

  519. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    520. 

  520. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    521. 

  521. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    522. 

  522. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    523. 

  523. 

  524. 

  525. Encoding Type:  One-Hot
    526. 

  526. +----------------------------------------------------------------------------------------------------------------------------------+
    527. 

  527. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state                                ;
    528. 

  528. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    529. 

  529. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    530. 

  530. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    531. 

  531. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    532. 

  532. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    533. 

  533. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    534. 

  534. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    535. 

  535. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    536. 

  536. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    537. 

  537. 

  538. 

  539. Encoding Type:  One-Hot
    540. 

  540. +----------------------------------------------------------------------------------------------------------------------------------+
    541. 

  541. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state                                ;
    542. 

  542. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    543. 

  543. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    544. 

  544. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    545. 

  545. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    546. 

  546. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    547. 

  547. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    548. 

  548. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    549. 

  549. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    550. 

  550. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    551. 

  551. 

  552. 

  553. Encoding Type:  One-Hot
    554. 

  554. +----------------------------------------------------------------------------------------------------------------------------------+
    555. 

  555. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state                                ;
    556. 

  556. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    557. 

  557. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    558. 

  558. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    559. 

  559. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    560. 

  560. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    561. 

  561. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    562. 

  562. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    563. 

  563. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    564. 

  564. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    565. 

  565. 

  566. 

  567. Encoding Type:  One-Hot
    568. 

  568. +----------------------------------------------------------------------------------------------------------------------------------+
    569. 

  569. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state                                ;
    570. 

  570. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    571. 

  571. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    572. 

  572. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    573. 

  573. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    574. 

  574. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    575. 

  575. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    576. 

  576. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    577. 

  577. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    578. 

  578. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    579. 

  579. 

  580. 

  581. Encoding Type:  One-Hot
    582. 

  582. +----------------------------------------------------------------------------------------------------------------------------------+
    583. 

  583. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state                                ;
    584. 

  584. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    585. 

  585. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    586. 

  586. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    587. 

  587. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    588. 

  588. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    589. 

  589. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    590. 

  590. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    591. 

  591. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    592. 

  592. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    593. 

  593. 

  594. 

  595. Encoding Type:  One-Hot
    596. 

  596. +----------------------------------------------------------------------------------------------------------------------------------+
    597. 

  597. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state                                ;
    598. 

  598. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    599. 

  599. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    600. 

  600. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    601. 

  601. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    602. 

  602. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    603. 

  603. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    604. 

  604. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    605. 

  605. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    606. 

  606. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    607. 

  607. 

  608. 

  609. Encoding Type:  One-Hot
    610. 

  610. +----------------------------------------------------------------------------------------------------------------------------------+
    611. 

  611. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state                                ;
    612. 

  612. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    613. 

  613. ; Name                 ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ;
    614. 

  614. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    615. 

  615. ; rx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    616. 

  616. ; rx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    617. 

  617. ; rx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    618. 

  618. ; rx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    619. 

  619. ; rx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    620. 

  620. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    621. 

  621. 

  622. 

  623. Encoding Type:  One-Hot
    624. 

  624. +----------------------------------------------------------------------------------------------------------------------------------+
    625. 

  625. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state                                ;
    626. 

  626. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    627. 

  627. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    628. 

  628. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    629. 

  629. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    630. 

  630. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    631. 

  631. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    632. 

  632. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    633. 

  633. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    634. 

  634. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    635. 

  635. 

  636. 

  637. Encoding Type:  One-Hot
    638. 

  638. +----------------------------------------------------------------------------------------------------------------------------------+
    639. 

  639. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state                                ;
    640. 

  640. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    641. 

  641. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    642. 

  642. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    643. 

  643. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    644. 

  644. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    645. 

  645. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    646. 

  646. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    647. 

  647. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    648. 

  648. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    649. 

  649. 

  650. 

  651. Encoding Type:  One-Hot
    652. 

  652. +----------------------------------------------------------------------------------------------------------------------------------+
    653. 

  653. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state                                ;
    654. 

  654. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    655. 

  655. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    656. 

  656. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    657. 

  657. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    658. 

  658. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    659. 

  659. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    660. 

  660. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    661. 

  661. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    662. 

  662. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    663. 

  663. 

  664. 

  665. Encoding Type:  One-Hot
    666. 

  666. +----------------------------------------------------------------------------------------------------------------------------------+
    667. 

  667. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state                                ;
    668. 

  668. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    669. 

  669. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    670. 

  670. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    671. 

  671. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    672. 

  672. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    673. 

  673. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    674. 

  674. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    675. 

  675. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    676. 

  676. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    677. 

  677. 

  678. 

  679. Encoding Type:  One-Hot
    680. 

  680. +----------------------------------------------------------------------------------------------------------------------------------+
    681. 

  681. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state                                ;
    682. 

  682. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    683. 

  683. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    684. 

  684. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    685. 

  685. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    686. 

  686. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    687. 

  687. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    688. 

  688. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    689. 

  689. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    690. 

  690. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    691. 

  691. 

  692. 

  693. Encoding Type:  One-Hot
    694. 

  694. +----------------------------------------------------------------------------------------------------------------------------------+
    695. 

  695. ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state                                ;
    696. 

  696. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    697. 

  697. ; Name                 ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ;
    698. 

  698. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    699. 

  699. ; tx_state.UART_IDLE   ; 0                    ; 0                  ; 0                   ; 0                  ; 0                  ;
    700. 

  700. ; tx_state.UART_START  ; 0                    ; 0                  ; 1                   ; 1                  ; 0                  ;
    701. 

  701. ; tx_state.UART_DATA   ; 0                    ; 1                  ; 0                   ; 1                  ; 0                  ;
    702. 

  702. ; tx_state.UART_PARITY ; 1                    ; 0                  ; 0                   ; 1                  ; 0                  ;
    703. 

  703. ; tx_state.UART_STOP   ; 0                    ; 0                  ; 0                   ; 1                  ; 1                  ;
    704. 

  704. +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+
    705. 

  705. 

  706. 

  707. Encoding Type:  One-Hot
    708. 

  708. +--------------------------------------------------------------------------------+
    709. 

  709. ; State Machine - |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|apbState ;
    710. 

  710. +--------------------+------------------+--------------------+-------------------+
    711. 

  711. ; Name               ; apbState.apbIdle ; apbState.apbAccess ; apbState.apbSetup ;
    712. 

  712. +--------------------+------------------+--------------------+-------------------+
    713. 

  713. ; apbState.apbIdle   ; 0                ; 0                  ; 0                 ;
    714. 

  714. ; apbState.apbSetup  ; 1                ; 0                  ; 1                 ;
    715. 

  715. ; apbState.apbAccess ; 1                ; 1                  ; 0                 ;
    716. 

  716. +--------------------+------------------+--------------------+-------------------+
    717. 

  717. 

  718. 

  719. +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    720. 

  720. ; Registers Removed During Synthesis                                                                                                                                           ;
    721. 

  721. +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+
    722. 

  722. ; Register name                                                                     ; Reason for Removal                                                                       ;
    723. 

  723. +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+
    724. 

  724. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[16..31] ; Stuck at GND due to stuck port data_in                                                   ;
    725. 

  725. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[16..31] ; Stuck at GND due to stuck port data_in                                                   ;
    726. 

  726. ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[16..31]                         ; Stuck at GND due to stuck port data_in                                                   ;
    727. 

  727. ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|hresp                                  ; Stuck at GND due to stuck port data_in                                                   ;
    728. 

  728. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state~4          ; Lost fanout                                                                              ;
    729. 

  729. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state~5          ; Lost fanout                                                                              ;
    730. 

  730. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state~4          ; Lost fanout                                                                              ;
    731. 

  731. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state~5          ; Lost fanout                                                                              ;
    732. 

  732. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state~4          ; Lost fanout                                                                              ;
    733. 

  733. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state~5          ; Lost fanout                                                                              ;
    734. 

  734. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state~4          ; Lost fanout                                                                              ;
    735. 

  735. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state~5          ; Lost fanout                                                                              ;
    736. 

  736. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state~4          ; Lost fanout                                                                              ;
    737. 

  737. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state~5          ; Lost fanout                                                                              ;
    738. 

  738. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state~4          ; Lost fanout                                                                              ;
    739. 

  739. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state~5          ; Lost fanout                                                                              ;
    740. 

  740. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state~7          ; Lost fanout                                                                              ;
    741. 

  741. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state~8          ; Lost fanout                                                                              ;
    742. 

  742. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state~7          ; Lost fanout                                                                              ;
    743. 

  743. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state~8          ; Lost fanout                                                                              ;
    744. 

  744. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state~7          ; Lost fanout                                                                              ;
    745. 

  745. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state~8          ; Lost fanout                                                                              ;
    746. 

  746. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state~7          ; Lost fanout                                                                              ;
    747. 

  747. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state~8          ; Lost fanout                                                                              ;
    748. 

  748. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state~7          ; Lost fanout                                                                              ;
    749. 

  749. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state~8          ; Lost fanout                                                                              ;
    750. 

  750. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state~7          ; Lost fanout                                                                              ;
    751. 

  751. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state~8          ; Lost fanout                                                                              ;
    752. 

  752. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state~4          ; Lost fanout                                                                              ;
    753. 

  753. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state~5          ; Lost fanout                                                                              ;
    754. 

  754. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state~4          ; Lost fanout                                                                              ;
    755. 

  755. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state~5          ; Lost fanout                                                                              ;
    756. 

  756. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state~4          ; Lost fanout                                                                              ;
    757. 

  757. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state~5          ; Lost fanout                                                                              ;
    758. 

  758. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state~4          ; Lost fanout                                                                              ;
    759. 

  759. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state~5          ; Lost fanout                                                                              ;
    760. 

  760. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state~4          ; Lost fanout                                                                              ;
    761. 

  761. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state~5          ; Lost fanout                                                                              ;
    762. 

  762. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state~4          ; Lost fanout                                                                              ;
    763. 

  763. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state~5          ; Lost fanout                                                                              ;
    764. 

  764. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state~7          ; Lost fanout                                                                              ;
    765. 

  765. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state~8          ; Lost fanout                                                                              ;
    766. 

  766. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state~7          ; Lost fanout                                                                              ;
    767. 

  767. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state~8          ; Lost fanout                                                                              ;
    768. 

  768. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state~7          ; Lost fanout                                                                              ;
    769. 

  769. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state~8          ; Lost fanout                                                                              ;
    770. 

  770. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state~7          ; Lost fanout                                                                              ;
    771. 

  771. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state~8          ; Lost fanout                                                                              ;
    772. 

  772. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state~7          ; Lost fanout                                                                              ;
    773. 

  773. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state~8          ; Lost fanout                                                                              ;
    774. 

  774. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state~7          ; Lost fanout                                                                              ;
    775. 

  775. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state~8          ; Lost fanout                                                                              ;
    776. 

  776. ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|status_reg[3]      ; Merged with multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|status_reg[1] ;
    777. 

  777. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[3]      ; Merged with multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[1] ;
    778. 

  778. ; Total Number of Removed Registers = 99                                            ;                                                                                          ;
    779. 

  779. +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+
    780. 

  780. 

  781. 

  782. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    783. 

  783. ; Removed Registers Triggering Further Register Optimizations                                                                                                       ;
    784. 

  784. +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+
    785. 

  785. ; Register name                                                                 ; Reason for Removal        ; Registers Removed due to This Register                ;
    786. 

  786. +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+
    787. 

  787. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[31] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[31] ;
    788. 

  788. ;                                                                               ; due to stuck port data_in ;                                                       ;
    789. 

  789. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[30] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[30] ;
    790. 

  790. ;                                                                               ; due to stuck port data_in ;                                                       ;
    791. 

  791. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[29] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[29] ;
    792. 

  792. ;                                                                               ; due to stuck port data_in ;                                                       ;
    793. 

  793. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[28] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[28] ;
    794. 

  794. ;                                                                               ; due to stuck port data_in ;                                                       ;
    795. 

  795. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[27] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[27] ;
    796. 

  796. ;                                                                               ; due to stuck port data_in ;                                                       ;
    797. 

  797. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[26] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[26] ;
    798. 

  798. ;                                                                               ; due to stuck port data_in ;                                                       ;
    799. 

  799. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[25] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[25] ;
    800. 

  800. ;                                                                               ; due to stuck port data_in ;                                                       ;
    801. 

  801. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[24] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[24] ;
    802. 

  802. ;                                                                               ; due to stuck port data_in ;                                                       ;
    803. 

  803. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[23] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[23] ;
    804. 

  804. ;                                                                               ; due to stuck port data_in ;                                                       ;
    805. 

  805. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[22] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[22] ;
    806. 

  806. ;                                                                               ; due to stuck port data_in ;                                                       ;
    807. 

  807. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[21] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[21] ;
    808. 

  808. ;                                                                               ; due to stuck port data_in ;                                                       ;
    809. 

  809. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[20] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[20] ;
    810. 

  810. ;                                                                               ; due to stuck port data_in ;                                                       ;
    811. 

  811. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[19] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[19] ;
    812. 

  812. ;                                                                               ; due to stuck port data_in ;                                                       ;
    813. 

  813. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[18] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[18] ;
    814. 

  814. ;                                                                               ; due to stuck port data_in ;                                                       ;
    815. 

  815. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[17] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[17] ;
    816. 

  816. ;                                                                               ; due to stuck port data_in ;                                                       ;
    817. 

  817. ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[16] ; Stuck at GND              ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[16] ;
    818. 

  818. ;                                                                               ; due to stuck port data_in ;                                                       ;
    819. 

  819. +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+
    820. 

  820. 

  821. 

  822. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    823. 

  823. ; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                         ;
    824. 

  824. +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+
    825. 

  825. ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                               ;
    826. 

  826. +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+
    827. 

  827. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_data_cnt[2]  ;
    828. 

  828. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_shift_reg[3] ;
    829. 

  829. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_data_cnt[2]  ;
    830. 

  830. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_shift_reg[4] ;
    831. 

  831. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_data_cnt[2]  ;
    832. 

  832. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_shift_reg[2] ;
    833. 

  833. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_data_cnt[2]  ;
    834. 

  834. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_shift_reg[7] ;
    835. 

  835. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_data_cnt[0]  ;
    836. 

  836. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_shift_reg[7] ;
    837. 

  837. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_data_cnt[2]  ;
    838. 

  838. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_shift_reg[5] ;
    839. 

  839. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_data_cnt[0]  ;
    840. 

  840. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_shift_reg[5] ;
    841. 

  841. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_data_cnt[0]  ;
    842. 

  842. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_shift_reg[3] ;
    843. 

  843. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_data_cnt[0]  ;
    844. 

  844. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_shift_reg[3] ;
    845. 

  845. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_data_cnt[0]  ;
    846. 

  846. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_shift_reg[5] ;
    847. 

  847. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_data_cnt[1]  ;
    848. 

  848. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_shift_reg[7] ;
    849. 

  849. ; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_data_cnt[1]  ;
    850. 

  850. ; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_shift_reg[2] ;
    851. 

  851. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_data_cnt[0]  ;
    852. 

  852. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_data_cnt[0]  ;
    853. 

  853. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_data_cnt[0]  ;
    854. 

  854. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_data_cnt[2]  ;
    855. 

  855. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_data_cnt[0]  ;
    856. 

  856. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_data_cnt[1]  ;
    857. 

  857. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_data_cnt[0]  ;
    858. 

  858. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_data_cnt[0]  ;
    859. 

  859. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_data_cnt[0]  ;
    860. 

  860. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_data_cnt[2]  ;
    861. 

  861. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_data_cnt[1]  ;
    862. 

  862. ; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_data_cnt[1]  ;
    863. 

  863. ; 8:1                ; 16 bits   ; 80 LEs        ; 64 LEs               ; 16 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|rx_reg[5]      ;
    864. 

  864. ; 6:1                ; 10 bits   ; 40 LEs        ; 40 LEs               ; 0 LEs                  ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[1]  ;
    865. 

  865. ; 4:1                ; 11 bits   ; 22 LEs        ; 0 LEs                ; 22 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|pwrite                             ;
    866. 

  866. ; 64:1               ; 2 bits    ; 84 LEs        ; 10 LEs               ; 74 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[6]  ;
    867. 

  867. ; 69:1               ; 10 bits   ; 460 LEs       ; 50 LEs               ; 410 LEs                ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[11] ;
    868. 

  868. ; 69:1               ; 2 bits    ; 92 LEs        ; 14 LEs               ; 78 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[2]  ;
    869. 

  869. ; 69:1               ; 2 bits    ; 92 LEs        ; 18 LEs               ; 74 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[7]  ;
    870. 

  870. ; 69:1               ; 2 bits    ; 92 LEs        ; 18 LEs               ; 74 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[3]  ;
    871. 

  871. ; 74:1               ; 2 bits    ; 98 LEs        ; 24 LEs               ; 74 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[0]  ;
    872. 

  872. ; 74:1               ; 2 bits    ; 98 LEs        ; 24 LEs               ; 74 LEs                 ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[1]  ;
    873. 

  873. ; 74:1               ; 4 bits    ; 196 LEs       ; 44 LEs               ; 152 LEs                ; Yes        ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[4]  ;
    874. 

  874. ; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|ShiftLeft0     ;
    875. 

  875. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|Selector0       ;
    876. 

  876. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|Selector0       ;
    877. 

  877. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|Selector0       ;
    878. 

  878. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|Selector0       ;
    879. 

  879. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|Selector1       ;
    880. 

  880. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|Selector1       ;
    881. 

  881. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|Selector1       ;
    882. 

  882. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|Selector0       ;
    883. 

  883. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|Selector0       ;
    884. 

  884. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|Selector0       ;
    885. 

  885. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|Selector0       ;
    886. 

  886. ; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|Selector0       ;
    887. 

  887. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|Selector2       ;
    888. 

  888. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|Selector3       ;
    889. 

  889. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|Selector0       ;
    890. 

  890. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|Selector3       ;
    891. 

  891. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|Selector2       ;
    892. 

  892. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|Selector3       ;
    893. 

  893. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|Selector2       ;
    894. 

  894. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|Selector3       ;
    895. 

  895. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|Selector2       ;
    896. 

  896. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|Selector4       ;
    897. 

  897. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|Selector2       ;
    898. 

  898. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|Selector3       ;
    899. 

  899. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|Selector0       ;
    900. 

  900. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|Selector4       ;
    901. 

  901. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|Selector2       ;
    902. 

  902. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|Selector4       ;
    903. 

  903. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|Selector2       ;
    904. 

  904. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|Selector4       ;
    905. 

  905. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|Selector2       ;
    906. 

  906. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|Selector4       ;
    907. 

  907. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|Selector0       ;
    908. 

  908. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|Selector3       ;
    909. 

  909. ; 10:1               ; 3 bits    ; 18 LEs        ; 9 LEs                ; 9 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|Selector1       ;
    910. 

  910. ; 10:1               ; 2 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; No         ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|Selector3       ;
    911. 

  911. +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+
    912. 

  912. 

  913. 

  914. +---------------------------------------------------------------------+
    915. 

  915. ; Source assignments for Top-level Entity: |test_uart                 ;
    916. 

  916. +------------------------------+-------+------+-----------------------+
    917. 

  917. ; Assignment                   ; Value ; From ; To                    ;
    918. 

  918. +------------------------------+-------+------+-----------------------+
    919. 

  919. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[7]        ;
    920. 

  920. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[7]        ;
    921. 

  921. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[6]        ;
    922. 

  922. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[6]        ;
    923. 

  923. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[5]        ;
    924. 

  924. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[5]        ;
    925. 

  925. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[4]        ;
    926. 

  926. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[4]        ;
    927. 

  927. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[3]        ;
    928. 

  928. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[3]        ;
    929. 

  929. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[2]        ;
    930. 

  930. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[2]        ;
    931. 

  931. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[1]        ;
    932. 

  932. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[1]        ;
    933. 

  933. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio3_io_in[0]        ;
    934. 

  934. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio3_io_in[0]        ;
    935. 

  935. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[7]        ;
    936. 

  936. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[7]        ;
    937. 

  937. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[6]        ;
    938. 

  938. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[6]        ;
    939. 

  939. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[5]        ;
    940. 

  940. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[5]        ;
    941. 

  941. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[4]        ;
    942. 

  942. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[4]        ;
    943. 

  943. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[3]        ;
    944. 

  944. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[3]        ;
    945. 

  945. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[2]        ;
    946. 

  946. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[2]        ;
    947. 

  947. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[1]        ;
    948. 

  948. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[1]        ;
    949. 

  949. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio4_io_in[0]        ;
    950. 

  950. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio4_io_in[0]        ;
    951. 

  951. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[7]        ;
    952. 

  952. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[7]        ;
    953. 

  953. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[6]        ;
    954. 

  954. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[6]        ;
    955. 

  955. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[5]        ;
    956. 

  956. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[5]        ;
    957. 

  957. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[4]        ;
    958. 

  958. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[4]        ;
    959. 

  959. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[3]        ;
    960. 

  960. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[3]        ;
    961. 

  961. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[2]        ;
    962. 

  962. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[2]        ;
    963. 

  963. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[1]        ;
    964. 

  964. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[1]        ;
    965. 

  965. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio5_io_in[0]        ;
    966. 

  966. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio5_io_in[0]        ;
    967. 

  967. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[7]        ;
    968. 

  968. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[7]        ;
    969. 

  969. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[6]        ;
    970. 

  970. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[6]        ;
    971. 

  971. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[5]        ;
    972. 

  972. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[5]        ;
    973. 

  973. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[4]        ;
    974. 

  974. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[4]        ;
    975. 

  975. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[3]        ;
    976. 

  976. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[3]        ;
    977. 

  977. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[2]        ;
    978. 

  978. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[2]        ;
    979. 

  979. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[1]        ;
    980. 

  980. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[1]        ;
    981. 

  981. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_in[0]        ;
    982. 

  982. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_in[0]        ;
    983. 

  983. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[7]        ;
    984. 

  984. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[7]        ;
    985. 

  985. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[6]        ;
    986. 

  986. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[6]        ;
    987. 

  987. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[5]        ;
    988. 

  988. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[5]        ;
    989. 

  989. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[4]        ;
    990. 

  990. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[4]        ;
    991. 

  991. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[3]        ;
    992. 

  992. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[3]        ;
    993. 

  993. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[2]        ;
    994. 

  994. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[2]        ;
    995. 

  995. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[1]        ;
    996. 

  996. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[1]        ;
    997. 

  997. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_in[0]        ;
    998. 

  998. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_in[0]        ;
    999. 

  999. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[7]        ;
    1000. 

  1000. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[7]        ;
    1001. 

  1001. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[6]        ;
    1002. 

  1002. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[6]        ;
    1003. 

  1003. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[5]        ;
    1004. 

  1004. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[5]        ;
    1005. 

  1005. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[4]        ;
    1006. 

  1006. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[4]        ;
    1007. 

  1007. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[3]        ;
    1008. 

  1008. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[3]        ;
    1009. 

  1009. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[2]        ;
    1010. 

  1010. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[2]        ;
    1011. 

  1011. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[1]        ;
    1012. 

  1012. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[1]        ;
    1013. 

  1013. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_in[0]        ;
    1014. 

  1014. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_in[0]        ;
    1015. 

  1015. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; PLL_ENABLE            ;
    1016. 

  1016. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; PLL_ENABLE            ;
    1017. 

  1017. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; PLL_LOCK              ;
    1018. 

  1018. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; PLL_LOCK              ;
    1019. 

  1019. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_resetn            ;
    1020. 

  1020. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_resetn            ;
    1021. 

  1021. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_stop         ;
    1022. 

  1022. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_stop         ;
    1023. 

  1023. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_clkSource[1] ;
    1024. 

  1024. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_clkSource[1] ;
    1025. 

  1025. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; sys_ctrl_clkSource[0] ;
    1026. 

  1026. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; sys_ctrl_clkSource[0] ;
    1027. 

  1027. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[7]  ;
    1028. 

  1028. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[7]  ;
    1029. 

  1029. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[6]  ;
    1030. 

  1030. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[6]  ;
    1031. 

  1031. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[5]  ;
    1032. 

  1032. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[5]  ;
    1033. 

  1033. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[4]  ;
    1034. 

  1034. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[4]  ;
    1035. 

  1035. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[3]  ;
    1036. 

  1036. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[3]  ;
    1037. 

  1037. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[2]  ;
    1038. 

  1038. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[2]  ;
    1039. 

  1039. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[1]  ;
    1040. 

  1040. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[1]  ;
    1041. 

  1041. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_data[0]  ;
    1042. 

  1042. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_data[0]  ;
    1043. 

  1043. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[7]    ;
    1044. 

  1044. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[7]    ;
    1045. 

  1045. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[6]    ;
    1046. 

  1046. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[6]    ;
    1047. 

  1047. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[5]    ;
    1048. 

  1048. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[5]    ;
    1049. 

  1049. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[4]    ;
    1050. 

  1050. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[4]    ;
    1051. 

  1051. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[3]    ;
    1052. 

  1052. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[3]    ;
    1053. 

  1053. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[2]    ;
    1054. 

  1054. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[2]    ;
    1055. 

  1055. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[1]    ;
    1056. 

  1056. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[1]    ;
    1057. 

  1057. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio1_io_out_en[0]    ;
    1058. 

  1058. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio1_io_out_en[0]    ;
    1059. 

  1059. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[7]  ;
    1060. 

  1060. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[7]  ;
    1061. 

  1061. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[6]  ;
    1062. 

  1062. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[6]  ;
    1063. 

  1063. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[5]  ;
    1064. 

  1064. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[5]  ;
    1065. 

  1065. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[4]  ;
    1066. 

  1066. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[4]  ;
    1067. 

  1067. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[3]  ;
    1068. 

  1068. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[3]  ;
    1069. 

  1069. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[2]  ;
    1070. 

  1070. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[2]  ;
    1071. 

  1071. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[1]  ;
    1072. 

  1072. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[1]  ;
    1073. 

  1073. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_data[0]  ;
    1074. 

  1074. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_data[0]  ;
    1075. 

  1075. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[7]    ;
    1076. 

  1076. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[7]    ;
    1077. 

  1077. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[6]    ;
    1078. 

  1078. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[6]    ;
    1079. 

  1079. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[5]    ;
    1080. 

  1080. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[5]    ;
    1081. 

  1081. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[4]    ;
    1082. 

  1082. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[4]    ;
    1083. 

  1083. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[3]    ;
    1084. 

  1084. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[3]    ;
    1085. 

  1085. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[2]    ;
    1086. 

  1086. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[2]    ;
    1087. 

  1087. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[1]    ;
    1088. 

  1088. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[1]    ;
    1089. 

  1089. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio2_io_out_en[0]    ;
    1090. 

  1090. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio2_io_out_en[0]    ;
    1091. 

  1091. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_data[6]  ;
    1092. 

  1092. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_data[6]  ;
    1093. 

  1093. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_data[4]  ;
    1094. 

  1094. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_data[4]  ;
    1095. 

  1095. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_data[2]  ;
    1096. 

  1096. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_data[2]  ;
    1097. 

  1097. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_data[0]  ;
    1098. 

  1098. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_data[0]  ;
    1099. 

  1099. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_en[6]    ;
    1100. 

  1100. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_en[6]    ;
    1101. 

  1101. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_en[4]    ;
    1102. 

  1102. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_en[4]    ;
    1103. 

  1103. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_en[2]    ;
    1104. 

  1104. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_en[2]    ;
    1105. 

  1105. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio6_io_out_en[0]    ;
    1106. 

  1106. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio6_io_out_en[0]    ;
    1107. 

  1107. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_out_data[6]  ;
    1108. 

  1108. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_out_data[6]  ;
    1109. 

  1109. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio7_io_out_en[6]    ;
    1110. 

  1110. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio7_io_out_en[6]    ;
    1111. 

  1111. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[7]  ;
    1112. 

  1112. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[7]  ;
    1113. 

  1113. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[6]  ;
    1114. 

  1114. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[6]  ;
    1115. 

  1115. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[4]  ;
    1116. 

  1116. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[4]  ;
    1117. 

  1117. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[3]  ;
    1118. 

  1118. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[3]  ;
    1119. 

  1119. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[2]  ;
    1120. 

  1120. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[2]  ;
    1121. 

  1121. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[1]  ;
    1122. 

  1122. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[1]  ;
    1123. 

  1123. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_data[0]  ;
    1124. 

  1124. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_data[0]  ;
    1125. 

  1125. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[7]    ;
    1126. 

  1126. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[7]    ;
    1127. 

  1127. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[6]    ;
    1128. 

  1128. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[6]    ;
    1129. 

  1129. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[4]    ;
    1130. 

  1130. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[4]    ;
    1131. 

  1131. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[3]    ;
    1132. 

  1132. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[3]    ;
    1133. 

  1133. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[2]    ;
    1134. 

  1134. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[2]    ;
    1135. 

  1135. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[1]    ;
    1136. 

  1136. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[1]    ;
    1137. 

  1137. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio8_io_out_en[0]    ;
    1138. 

  1138. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio8_io_out_en[0]    ;
    1139. 

  1139. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[7]  ;
    1140. 

  1140. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[7]  ;
    1141. 

  1141. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[6]  ;
    1142. 

  1142. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[6]  ;
    1143. 

  1143. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[5]  ;
    1144. 

  1144. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[5]  ;
    1145. 

  1145. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[4]  ;
    1146. 

  1146. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[4]  ;
    1147. 

  1147. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[3]  ;
    1148. 

  1148. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[3]  ;
    1149. 

  1149. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[2]  ;
    1150. 

  1150. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[2]  ;
    1151. 

  1151. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[1]  ;
    1152. 

  1152. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[1]  ;
    1153. 

  1153. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_data[0]  ;
    1154. 

  1154. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_data[0]  ;
    1155. 

  1155. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[7]    ;
    1156. 

  1156. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[7]    ;
    1157. 

  1157. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[6]    ;
    1158. 

  1158. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[6]    ;
    1159. 

  1159. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[5]    ;
    1160. 

  1160. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[5]    ;
    1161. 

  1161. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[4]    ;
    1162. 

  1162. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[4]    ;
    1163. 

  1163. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[3]    ;
    1164. 

  1164. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[3]    ;
    1165. 

  1165. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[2]    ;
    1166. 

  1166. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[2]    ;
    1167. 

  1167. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[1]    ;
    1168. 

  1168. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[1]    ;
    1169. 

  1169. ; IGNORE_LCELL_BUFFERS         ; off   ; -    ; gpio9_io_out_en[0]    ;
    1170. 

  1170. ; REMOVE_REDUNDANT_LOGIC_CELLS ; off   ; -    ; gpio9_io_out_en[0]    ;
    1171. 

  1171. +------------------------------+-------+------+-----------------------+
    1172. 

  1172. 

  1173. 

  1174. +--------------------------------------------------------------------+
    1175. 

  1175. ; Parameter Settings for User Entity Instance: altpll:pll_inst       ;
    1176. 

  1176. +-------------------------------+-------------------+----------------+
    1177. 

  1177. ; Parameter Name                ; Value             ; Type           ;
    1178. 

  1178. +-------------------------------+-------------------+----------------+
    1179. 

  1179. ; OPERATION_MODE                ; NORMAL            ; Untyped        ;
    1180. 

  1180. ; PLL_TYPE                      ; AUTO              ; Untyped        ;
    1181. 

  1181. ; LPM_HINT                      ; UNUSED            ; Untyped        ;
    1182. 

  1182. ; QUALIFY_CONF_DONE             ; OFF               ; Untyped        ;
    1183. 

  1183. ; COMPENSATE_CLOCK              ; CLK0              ; Untyped        ;
    1184. 

  1184. ; SCAN_CHAIN                    ; LONG              ; Untyped        ;
    1185. 

  1185. ; PRIMARY_CLOCK                 ; INCLK0            ; Untyped        ;
    1186. 

  1186. ; INCLK0_INPUT_FREQUENCY        ; 125000            ; Signed Integer ;
    1187. 

  1187. ; INCLK1_INPUT_FREQUENCY        ; 0                 ; Untyped        ;
    1188. 

  1188. ; GATE_LOCK_SIGNAL              ; NO                ; Untyped        ;
    1189. 

  1189. ; GATE_LOCK_COUNTER             ; 0                 ; Untyped        ;
    1190. 

  1190. ; LOCK_HIGH                     ; 1                 ; Untyped        ;
    1191. 

  1191. ; LOCK_LOW                      ; 1                 ; Untyped        ;
    1192. 

  1192. ; VALID_LOCK_MULTIPLIER         ; 1                 ; Untyped        ;
    1193. 

  1193. ; INVALID_LOCK_MULTIPLIER       ; 5                 ; Untyped        ;
    1194. 

  1194. ; SWITCH_OVER_ON_LOSSCLK        ; OFF               ; Untyped        ;
    1195. 

  1195. ; SWITCH_OVER_ON_GATED_LOCK     ; OFF               ; Untyped        ;
    1196. 

  1196. ; ENABLE_SWITCH_OVER_COUNTER    ; OFF               ; Untyped        ;
    1197. 

  1197. ; SKIP_VCO                      ; OFF               ; Untyped        ;
    1198. 

  1198. ; SWITCH_OVER_COUNTER           ; 0                 ; Untyped        ;
    1199. 

  1199. ; SWITCH_OVER_TYPE              ; AUTO              ; Untyped        ;
    1200. 

  1200. ; FEEDBACK_SOURCE               ; EXTCLK0           ; Untyped        ;
    1201. 

  1201. ; BANDWIDTH                     ; 0                 ; Untyped        ;
    1202. 

  1202. ; BANDWIDTH_TYPE                ; AUTO              ; Untyped        ;
    1203. 

  1203. ; SPREAD_FREQUENCY              ; 0                 ; Untyped        ;
    1204. 

  1204. ; DOWN_SPREAD                   ; 0                 ; Untyped        ;
    1205. 

  1205. ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF               ; Untyped        ;
    1206. 

  1206. ; SELF_RESET_ON_LOSS_LOCK       ; OFF               ; Untyped        ;
    1207. 

  1207. ; CLK9_MULTIPLY_BY              ; 0                 ; Untyped        ;
    1208. 

  1208. ; CLK8_MULTIPLY_BY              ; 0                 ; Untyped        ;
    1209. 

  1209. ; CLK7_MULTIPLY_BY              ; 0                 ; Untyped        ;
    1210. 

  1210. ; CLK6_MULTIPLY_BY              ; 0                 ; Untyped        ;
    1211. 

  1211. ; CLK5_MULTIPLY_BY              ; 1                 ; Untyped        ;
    1212. 

  1212. ; CLK4_MULTIPLY_BY              ; 120               ; Signed Integer ;
    1213. 

  1213. ; CLK3_MULTIPLY_BY              ; 120               ; Signed Integer ;
    1214. 

  1214. ; CLK2_MULTIPLY_BY              ; 120               ; Signed Integer ;
    1215. 

  1215. ; CLK1_MULTIPLY_BY              ; 120               ; Signed Integer ;
    1216. 

  1216. ; CLK0_MULTIPLY_BY              ; 120               ; Signed Integer ;
    1217. 

  1217. ; CLK9_DIVIDE_BY                ; 0                 ; Untyped        ;
    1218. 

  1218. ; CLK8_DIVIDE_BY                ; 0                 ; Untyped        ;
    1219. 

  1219. ; CLK7_DIVIDE_BY                ; 0                 ; Untyped        ;
    1220. 

  1220. ; CLK6_DIVIDE_BY                ; 0                 ; Untyped        ;
    1221. 

  1221. ; CLK5_DIVIDE_BY                ; 1                 ; Untyped        ;
    1222. 

  1222. ; CLK4_DIVIDE_BY                ; 4                 ; Signed Integer ;
    1223. 

  1223. ; CLK3_DIVIDE_BY                ; 8                 ; Signed Integer ;
    1224. 

  1224. ; CLK2_DIVIDE_BY                ; 4                 ; Signed Integer ;
    1225. 

  1225. ; CLK1_DIVIDE_BY                ; 4                 ; Signed Integer ;
    1226. 

  1226. ; CLK0_DIVIDE_BY                ; 4                 ; Signed Integer ;
    1227. 

  1227. ; CLK9_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1228. 

  1228. ; CLK8_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1229. 

  1229. ; CLK7_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1230. 

  1230. ; CLK6_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1231. 

  1231. ; CLK5_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1232. 

  1232. ; CLK4_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1233. 

  1233. ; CLK3_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1234. 

  1234. ; CLK2_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1235. 

  1235. ; CLK1_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1236. 

  1236. ; CLK0_PHASE_SHIFT              ; 0                 ; Untyped        ;
    1237. 

  1237. ; CLK5_TIME_DELAY               ; 0                 ; Untyped        ;
    1238. 

  1238. ; CLK4_TIME_DELAY               ; 0                 ; Untyped        ;
    1239. 

  1239. ; CLK3_TIME_DELAY               ; 0                 ; Untyped        ;
    1240. 

  1240. ; CLK2_TIME_DELAY               ; 0                 ; Untyped        ;
    1241. 

  1241. ; CLK1_TIME_DELAY               ; 0                 ; Untyped        ;
    1242. 

  1242. ; CLK0_TIME_DELAY               ; 0                 ; Untyped        ;
    1243. 

  1243. ; CLK9_DUTY_CYCLE               ; 50                ; Untyped        ;
    1244. 

  1244. ; CLK8_DUTY_CYCLE               ; 50                ; Untyped        ;
    1245. 

  1245. ; CLK7_DUTY_CYCLE               ; 50                ; Untyped        ;
    1246. 

  1246. ; CLK6_DUTY_CYCLE               ; 50                ; Untyped        ;
    1247. 

  1247. ; CLK5_DUTY_CYCLE               ; 50                ; Untyped        ;
    1248. 

  1248. ; CLK4_DUTY_CYCLE               ; 50                ; Untyped        ;
    1249. 

  1249. ; CLK3_DUTY_CYCLE               ; 50                ; Untyped        ;
    1250. 

  1250. ; CLK2_DUTY_CYCLE               ; 50                ; Untyped        ;
    1251. 

  1251. ; CLK1_DUTY_CYCLE               ; 50                ; Untyped        ;
    1252. 

  1252. ; CLK0_DUTY_CYCLE               ; 50                ; Untyped        ;
    1253. 

  1253. ; CLK9_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1254. 

  1254. ; CLK8_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1255. 

  1255. ; CLK7_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1256. 

  1256. ; CLK6_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1257. 

  1257. ; CLK5_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1258. 

  1258. ; CLK4_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1259. 

  1259. ; CLK3_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1260. 

  1260. ; CLK2_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1261. 

  1261. ; CLK1_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1262. 

  1262. ; CLK0_USE_EVEN_COUNTER_MODE    ; OFF               ; Untyped        ;
    1263. 

  1263. ; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1264. 

  1264. ; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1265. 

  1265. ; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1266. 

  1266. ; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1267. 

  1267. ; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1268. 

  1268. ; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1269. 

  1269. ; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1270. 

  1270. ; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1271. 

  1271. ; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1272. 

  1272. ; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF               ; Untyped        ;
    1273. 

  1273. ; LOCK_WINDOW_UI                ;  0.05             ; Untyped        ;
    1274. 

  1274. ; LOCK_WINDOW_UI_BITS           ; UNUSED            ; Untyped        ;
    1275. 

  1275. ; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED            ; Untyped        ;
    1276. 

  1276. ; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED            ; Untyped        ;
    1277. 

  1277. ; DPA_MULTIPLY_BY               ; 0                 ; Untyped        ;
    1278. 

  1278. ; DPA_DIVIDE_BY                 ; 1                 ; Untyped        ;
    1279. 

  1279. ; DPA_DIVIDER                   ; 0                 ; Untyped        ;
    1280. 

  1280. ; EXTCLK3_MULTIPLY_BY           ; 1                 ; Untyped        ;
    1281. 

  1281. ; EXTCLK2_MULTIPLY_BY           ; 1                 ; Untyped        ;
    1282. 

  1282. ; EXTCLK1_MULTIPLY_BY           ; 1                 ; Untyped        ;
    1283. 

  1283. ; EXTCLK0_MULTIPLY_BY           ; 1                 ; Untyped        ;
    1284. 

  1284. ; EXTCLK3_DIVIDE_BY             ; 1                 ; Untyped        ;
    1285. 

  1285. ; EXTCLK2_DIVIDE_BY             ; 1                 ; Untyped        ;
    1286. 

  1286. ; EXTCLK1_DIVIDE_BY             ; 1                 ; Untyped        ;
    1287. 

  1287. ; EXTCLK0_DIVIDE_BY             ; 1                 ; Untyped        ;
    1288. 

  1288. ; EXTCLK3_PHASE_SHIFT           ; 0                 ; Untyped        ;
    1289. 

  1289. ; EXTCLK2_PHASE_SHIFT           ; 0                 ; Untyped        ;
    1290. 

  1290. ; EXTCLK1_PHASE_SHIFT           ; 0                 ; Untyped        ;
    1291. 

  1291. ; EXTCLK0_PHASE_SHIFT           ; 0                 ; Untyped        ;
    1292. 

  1292. ; EXTCLK3_TIME_DELAY            ; 0                 ; Untyped        ;
    1293. 

  1293. ; EXTCLK2_TIME_DELAY            ; 0                 ; Untyped        ;
    1294. 

  1294. ; EXTCLK1_TIME_DELAY            ; 0                 ; Untyped        ;
    1295. 

  1295. ; EXTCLK0_TIME_DELAY            ; 0                 ; Untyped        ;
    1296. 

  1296. ; EXTCLK3_DUTY_CYCLE            ; 50                ; Untyped        ;
    1297. 

  1297. ; EXTCLK2_DUTY_CYCLE            ; 50                ; Untyped        ;
    1298. 

  1298. ; EXTCLK1_DUTY_CYCLE            ; 50                ; Untyped        ;
    1299. 

  1299. ; EXTCLK0_DUTY_CYCLE            ; 50                ; Untyped        ;
    1300. 

  1300. ; VCO_MULTIPLY_BY               ; 0                 ; Untyped        ;
    1301. 

  1301. ; VCO_DIVIDE_BY                 ; 0                 ; Untyped        ;
    1302. 

  1302. ; SCLKOUT0_PHASE_SHIFT          ; 0                 ; Untyped        ;
    1303. 

  1303. ; SCLKOUT1_PHASE_SHIFT          ; 0                 ; Untyped        ;
    1304. 

  1304. ; VCO_MIN                       ; 0                 ; Untyped        ;
    1305. 

  1305. ; VCO_MAX                       ; 0                 ; Untyped        ;
    1306. 

  1306. ; VCO_CENTER                    ; 0                 ; Untyped        ;
    1307. 

  1307. ; PFD_MIN                       ; 0                 ; Untyped        ;
    1308. 

  1308. ; PFD_MAX                       ; 0                 ; Untyped        ;
    1309. 

  1309. ; M_INITIAL                     ; 0                 ; Untyped        ;
    1310. 

  1310. ; M                             ; 0                 ; Untyped        ;
    1311. 

  1311. ; N                             ; 1                 ; Untyped        ;
    1312. 

  1312. ; M2                            ; 1                 ; Untyped        ;
    1313. 

  1313. ; N2                            ; 1                 ; Untyped        ;
    1314. 

  1314. ; SS                            ; 1                 ; Untyped        ;
    1315. 

  1315. ; C0_HIGH                       ; 0                 ; Untyped        ;
    1316. 

  1316. ; C1_HIGH                       ; 0                 ; Untyped        ;
    1317. 

  1317. ; C2_HIGH                       ; 0                 ; Untyped        ;
    1318. 

  1318. ; C3_HIGH                       ; 0                 ; Untyped        ;
    1319. 

  1319. ; C4_HIGH                       ; 0                 ; Untyped        ;
    1320. 

  1320. ; C5_HIGH                       ; 0                 ; Untyped        ;
    1321. 

  1321. ; C6_HIGH                       ; 0                 ; Untyped        ;
    1322. 

  1322. ; C7_HIGH                       ; 0                 ; Untyped        ;
    1323. 

  1323. ; C8_HIGH                       ; 0                 ; Untyped        ;
    1324. 

  1324. ; C9_HIGH                       ; 0                 ; Untyped        ;
    1325. 

  1325. ; C0_LOW                        ; 0                 ; Untyped        ;
    1326. 

  1326. ; C1_LOW                        ; 0                 ; Untyped        ;
    1327. 

  1327. ; C2_LOW                        ; 0                 ; Untyped        ;
    1328. 

  1328. ; C3_LOW                        ; 0                 ; Untyped        ;
    1329. 

  1329. ; C4_LOW                        ; 0                 ; Untyped        ;
    1330. 

  1330. ; C5_LOW                        ; 0                 ; Untyped        ;
    1331. 

  1331. ; C6_LOW                        ; 0                 ; Untyped        ;
    1332. 

  1332. ; C7_LOW                        ; 0                 ; Untyped        ;
    1333. 

  1333. ; C8_LOW                        ; 0                 ; Untyped        ;
    1334. 

  1334. ; C9_LOW                        ; 0                 ; Untyped        ;
    1335. 

  1335. ; C0_INITIAL                    ; 0                 ; Untyped        ;
    1336. 

  1336. ; C1_INITIAL                    ; 0                 ; Untyped        ;
    1337. 

  1337. ; C2_INITIAL                    ; 0                 ; Untyped        ;
    1338. 

  1338. ; C3_INITIAL                    ; 0                 ; Untyped        ;
    1339. 

  1339. ; C4_INITIAL                    ; 0                 ; Untyped        ;
    1340. 

  1340. ; C5_INITIAL                    ; 0                 ; Untyped        ;
    1341. 

  1341. ; C6_INITIAL                    ; 0                 ; Untyped        ;
    1342. 

  1342. ; C7_INITIAL                    ; 0                 ; Untyped        ;
    1343. 

  1343. ; C8_INITIAL                    ; 0                 ; Untyped        ;
    1344. 

  1344. ; C9_INITIAL                    ; 0                 ; Untyped        ;
    1345. 

  1345. ; C0_MODE                       ; BYPASS            ; Untyped        ;
    1346. 

  1346. ; C1_MODE                       ; BYPASS            ; Untyped        ;
    1347. 

  1347. ; C2_MODE                       ; BYPASS            ; Untyped        ;
    1348. 

  1348. ; C3_MODE                       ; BYPASS            ; Untyped        ;
    1349. 

  1349. ; C4_MODE                       ; BYPASS            ; Untyped        ;
    1350. 

  1350. ; C5_MODE                       ; BYPASS            ; Untyped        ;
    1351. 

  1351. ; C6_MODE                       ; BYPASS            ; Untyped        ;
    1352. 

  1352. ; C7_MODE                       ; BYPASS            ; Untyped        ;
    1353. 

  1353. ; C8_MODE                       ; BYPASS            ; Untyped        ;
    1354. 

  1354. ; C9_MODE                       ; BYPASS            ; Untyped        ;
    1355. 

  1355. ; C0_PH                         ; 0                 ; Untyped        ;
    1356. 

  1356. ; C1_PH                         ; 0                 ; Untyped        ;
    1357. 

  1357. ; C2_PH                         ; 0                 ; Untyped        ;
    1358. 

  1358. ; C3_PH                         ; 0                 ; Untyped        ;
    1359. 

  1359. ; C4_PH                         ; 0                 ; Untyped        ;
    1360. 

  1360. ; C5_PH                         ; 0                 ; Untyped        ;
    1361. 

  1361. ; C6_PH                         ; 0                 ; Untyped        ;
    1362. 

  1362. ; C7_PH                         ; 0                 ; Untyped        ;
    1363. 

  1363. ; C8_PH                         ; 0                 ; Untyped        ;
    1364. 

  1364. ; C9_PH                         ; 0                 ; Untyped        ;
    1365. 

  1365. ; L0_HIGH                       ; 1                 ; Untyped        ;
    1366. 

  1366. ; L1_HIGH                       ; 1                 ; Untyped        ;
    1367. 

  1367. ; G0_HIGH                       ; 1                 ; Untyped        ;
    1368. 

  1368. ; G1_HIGH                       ; 1                 ; Untyped        ;
    1369. 

  1369. ; G2_HIGH                       ; 1                 ; Untyped        ;
    1370. 

  1370. ; G3_HIGH                       ; 1                 ; Untyped        ;
    1371. 

  1371. ; E0_HIGH                       ; 1                 ; Untyped        ;
    1372. 

  1372. ; E1_HIGH                       ; 1                 ; Untyped        ;
    1373. 

  1373. ; E2_HIGH                       ; 1                 ; Untyped        ;
    1374. 

  1374. ; E3_HIGH                       ; 1                 ; Untyped        ;
    1375. 

  1375. ; L0_LOW                        ; 1                 ; Untyped        ;
    1376. 

  1376. ; L1_LOW                        ; 1                 ; Untyped        ;
    1377. 

  1377. ; G0_LOW                        ; 1                 ; Untyped        ;
    1378. 

  1378. ; G1_LOW                        ; 1                 ; Untyped        ;
    1379. 

  1379. ; G2_LOW                        ; 1                 ; Untyped        ;
    1380. 

  1380. ; G3_LOW                        ; 1                 ; Untyped        ;
    1381. 

  1381. ; E0_LOW                        ; 1                 ; Untyped        ;
    1382. 

  1382. ; E1_LOW                        ; 1                 ; Untyped        ;
    1383. 

  1383. ; E2_LOW                        ; 1                 ; Untyped        ;
    1384. 

  1384. ; E3_LOW                        ; 1                 ; Untyped        ;
    1385. 

  1385. ; L0_INITIAL                    ; 1                 ; Untyped        ;
    1386. 

  1386. ; L1_INITIAL                    ; 1                 ; Untyped        ;
    1387. 

  1387. ; G0_INITIAL                    ; 1                 ; Untyped        ;
    1388. 

  1388. ; G1_INITIAL                    ; 1                 ; Untyped        ;
    1389. 

  1389. ; G2_INITIAL                    ; 1                 ; Untyped        ;
    1390. 

  1390. ; G3_INITIAL                    ; 1                 ; Untyped        ;
    1391. 

  1391. ; E0_INITIAL                    ; 1                 ; Untyped        ;
    1392. 

  1392. ; E1_INITIAL                    ; 1                 ; Untyped        ;
    1393. 

  1393. ; E2_INITIAL                    ; 1                 ; Untyped        ;
    1394. 

  1394. ; E3_INITIAL                    ; 1                 ; Untyped        ;
    1395. 

  1395. ; L0_MODE                       ; BYPASS            ; Untyped        ;
    1396. 

  1396. ; L1_MODE                       ; BYPASS            ; Untyped        ;
    1397. 

  1397. ; G0_MODE                       ; BYPASS            ; Untyped        ;
    1398. 

  1398. ; G1_MODE                       ; BYPASS            ; Untyped        ;
    1399. 

  1399. ; G2_MODE                       ; BYPASS            ; Untyped        ;
    1400. 

  1400. ; G3_MODE                       ; BYPASS            ; Untyped        ;
    1401. 

  1401. ; E0_MODE                       ; BYPASS            ; Untyped        ;
    1402. 

  1402. ; E1_MODE                       ; BYPASS            ; Untyped        ;
    1403. 

  1403. ; E2_MODE                       ; BYPASS            ; Untyped        ;
    1404. 

  1404. ; E3_MODE                       ; BYPASS            ; Untyped        ;
    1405. 

  1405. ; L0_PH                         ; 0                 ; Untyped        ;
    1406. 

  1406. ; L1_PH                         ; 0                 ; Untyped        ;
    1407. 

  1407. ; G0_PH                         ; 0                 ; Untyped        ;
    1408. 

  1408. ; G1_PH                         ; 0                 ; Untyped        ;
    1409. 

  1409. ; G2_PH                         ; 0                 ; Untyped        ;
    1410. 

  1410. ; G3_PH                         ; 0                 ; Untyped        ;
    1411. 

  1411. ; E0_PH                         ; 0                 ; Untyped        ;
    1412. 

  1412. ; E1_PH                         ; 0                 ; Untyped        ;
    1413. 

  1413. ; E2_PH                         ; 0                 ; Untyped        ;
    1414. 

  1414. ; E3_PH                         ; 0                 ; Untyped        ;
    1415. 

  1415. ; M_PH                          ; 0                 ; Untyped        ;
    1416. 

  1416. ; C1_USE_CASC_IN                ; OFF               ; Untyped        ;
    1417. 

  1417. ; C2_USE_CASC_IN                ; OFF               ; Untyped        ;
    1418. 

  1418. ; C3_USE_CASC_IN                ; OFF               ; Untyped        ;
    1419. 

  1419. ; C4_USE_CASC_IN                ; OFF               ; Untyped        ;
    1420. 

  1420. ; C5_USE_CASC_IN                ; OFF               ; Untyped        ;
    1421. 

  1421. ; C6_USE_CASC_IN                ; OFF               ; Untyped        ;
    1422. 

  1422. ; C7_USE_CASC_IN                ; OFF               ; Untyped        ;
    1423. 

  1423. ; C8_USE_CASC_IN                ; OFF               ; Untyped        ;
    1424. 

  1424. ; C9_USE_CASC_IN                ; OFF               ; Untyped        ;
    1425. 

  1425. ; CLK0_COUNTER                  ; G0                ; Untyped        ;
    1426. 

  1426. ; CLK1_COUNTER                  ; G0                ; Untyped        ;
    1427. 

  1427. ; CLK2_COUNTER                  ; G0                ; Untyped        ;
    1428. 

  1428. ; CLK3_COUNTER                  ; G0                ; Untyped        ;
    1429. 

  1429. ; CLK4_COUNTER                  ; G0                ; Untyped        ;
    1430. 

  1430. ; CLK5_COUNTER                  ; G0                ; Untyped        ;
    1431. 

  1431. ; CLK6_COUNTER                  ; E0                ; Untyped        ;
    1432. 

  1432. ; CLK7_COUNTER                  ; E1                ; Untyped        ;
    1433. 

  1433. ; CLK8_COUNTER                  ; E2                ; Untyped        ;
    1434. 

  1434. ; CLK9_COUNTER                  ; E3                ; Untyped        ;
    1435. 

  1435. ; L0_TIME_DELAY                 ; 0                 ; Untyped        ;
    1436. 

  1436. ; L1_TIME_DELAY                 ; 0                 ; Untyped        ;
    1437. 

  1437. ; G0_TIME_DELAY                 ; 0                 ; Untyped        ;
    1438. 

  1438. ; G1_TIME_DELAY                 ; 0                 ; Untyped        ;
    1439. 

  1439. ; G2_TIME_DELAY                 ; 0                 ; Untyped        ;
    1440. 

  1440. ; G3_TIME_DELAY                 ; 0                 ; Untyped        ;
    1441. 

  1441. ; E0_TIME_DELAY                 ; 0                 ; Untyped        ;
    1442. 

  1442. ; E1_TIME_DELAY                 ; 0                 ; Untyped        ;
    1443. 

  1443. ; E2_TIME_DELAY                 ; 0                 ; Untyped        ;
    1444. 

  1444. ; E3_TIME_DELAY                 ; 0                 ; Untyped        ;
    1445. 

  1445. ; M_TIME_DELAY                  ; 0                 ; Untyped        ;
    1446. 

  1446. ; N_TIME_DELAY                  ; 0                 ; Untyped        ;
    1447. 

  1447. ; EXTCLK3_COUNTER               ; E3                ; Untyped        ;
    1448. 

  1448. ; EXTCLK2_COUNTER               ; E2                ; Untyped        ;
    1449. 

  1449. ; EXTCLK1_COUNTER               ; E1                ; Untyped        ;
    1450. 

  1450. ; EXTCLK0_COUNTER               ; E0                ; Untyped        ;
    1451. 

  1451. ; ENABLE0_COUNTER               ; L0                ; Untyped        ;
    1452. 

  1452. ; ENABLE1_COUNTER               ; L0                ; Untyped        ;
    1453. 

  1453. ; CHARGE_PUMP_CURRENT           ; 2                 ; Untyped        ;
    1454. 

  1454. ; LOOP_FILTER_R                 ;  1.000000         ; Untyped        ;
    1455. 

  1455. ; LOOP_FILTER_C                 ; 5                 ; Untyped        ;
    1456. 

  1456. ; CHARGE_PUMP_CURRENT_BITS      ; 9999              ; Untyped        ;
    1457. 

  1457. ; LOOP_FILTER_R_BITS            ; 9999              ; Untyped        ;
    1458. 

  1458. ; LOOP_FILTER_C_BITS            ; 9999              ; Untyped        ;
    1459. 

  1459. ; VCO_POST_SCALE                ; 0                 ; Untyped        ;
    1460. 

  1460. ; CLK2_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    1461. 

  1461. ; CLK1_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    1462. 

  1462. ; CLK0_OUTPUT_FREQUENCY         ; 0                 ; Untyped        ;
    1463. 

  1463. ; INTENDED_DEVICE_FAMILY        ; Cyclone IV E      ; Untyped        ;
    1464. 

  1464. ; PORT_CLKENA0                  ; PORT_CONNECTIVITY ; Untyped        ;
    1465. 

  1465. ; PORT_CLKENA1                  ; PORT_CONNECTIVITY ; Untyped        ;
    1466. 

  1466. ; PORT_CLKENA2                  ; PORT_CONNECTIVITY ; Untyped        ;
    1467. 

  1467. ; PORT_CLKENA3                  ; PORT_CONNECTIVITY ; Untyped        ;
    1468. 

  1468. ; PORT_CLKENA4                  ; PORT_CONNECTIVITY ; Untyped        ;
    1469. 

  1469. ; PORT_CLKENA5                  ; PORT_CONNECTIVITY ; Untyped        ;
    1470. 

  1470. ; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY ; Untyped        ;
    1471. 

  1471. ; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY ; Untyped        ;
    1472. 

  1472. ; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY ; Untyped        ;
    1473. 

  1473. ; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY ; Untyped        ;
    1474. 

  1474. ; PORT_EXTCLK0                  ; PORT_CONNECTIVITY ; Untyped        ;
    1475. 

  1475. ; PORT_EXTCLK1                  ; PORT_CONNECTIVITY ; Untyped        ;
    1476. 

  1476. ; PORT_EXTCLK2                  ; PORT_CONNECTIVITY ; Untyped        ;
    1477. 

  1477. ; PORT_EXTCLK3                  ; PORT_CONNECTIVITY ; Untyped        ;
    1478. 

  1478. ; PORT_CLKBAD0                  ; PORT_CONNECTIVITY ; Untyped        ;
    1479. 

  1479. ; PORT_CLKBAD1                  ; PORT_CONNECTIVITY ; Untyped        ;
    1480. 

  1480. ; PORT_CLK0                     ; PORT_USED         ; Untyped        ;
    1481. 

  1481. ; PORT_CLK1                     ; PORT_UNUSED       ; Untyped        ;
    1482. 

  1482. ; PORT_CLK2                     ; PORT_UNUSED       ; Untyped        ;
    1483. 

  1483. ; PORT_CLK3                     ; PORT_USED         ; Untyped        ;
    1484. 

  1484. ; PORT_CLK4                     ; PORT_UNUSED       ; Untyped        ;
    1485. 

  1485. ; PORT_CLK5                     ; PORT_CONNECTIVITY ; Untyped        ;
    1486. 

  1486. ; PORT_CLK6                     ; PORT_UNUSED       ; Untyped        ;
    1487. 

  1487. ; PORT_CLK7                     ; PORT_UNUSED       ; Untyped        ;
    1488. 

  1488. ; PORT_CLK8                     ; PORT_UNUSED       ; Untyped        ;
    1489. 

  1489. ; PORT_CLK9                     ; PORT_UNUSED       ; Untyped        ;
    1490. 

  1490. ; PORT_SCANDATA                 ; PORT_CONNECTIVITY ; Untyped        ;
    1491. 

  1491. ; PORT_SCANDATAOUT              ; PORT_CONNECTIVITY ; Untyped        ;
    1492. 

  1492. ; PORT_SCANDONE                 ; PORT_CONNECTIVITY ; Untyped        ;
    1493. 

  1493. ; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY ; Untyped        ;
    1494. 

  1494. ; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY ; Untyped        ;
    1495. 

  1495. ; PORT_ACTIVECLOCK              ; PORT_CONNECTIVITY ; Untyped        ;
    1496. 

  1496. ; PORT_CLKLOSS                  ; PORT_CONNECTIVITY ; Untyped        ;
    1497. 

  1497. ; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped        ;
    1498. 

  1498. ; PORT_INCLK0                   ; PORT_USED         ; Untyped        ;
    1499. 

  1499. ; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped        ;
    1500. 

  1500. ; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped        ;
    1501. 

  1501. ; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped        ;
    1502. 

  1502. ; PORT_ARESET                   ; PORT_USED         ; Untyped        ;
    1503. 

  1503. ; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped        ;
    1504. 

  1504. ; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped        ;
    1505. 

  1505. ; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped        ;
    1506. 

  1506. ; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped        ;
    1507. 

  1507. ; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped        ;
    1508. 

  1508. ; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped        ;
    1509. 

  1509. ; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped        ;
    1510. 

  1510. ; PORT_LOCKED                   ; PORT_USED         ; Untyped        ;
    1511. 

  1511. ; PORT_CONFIGUPDATE             ; PORT_CONNECTIVITY ; Untyped        ;
    1512. 

  1512. ; PORT_FBOUT                    ; PORT_CONNECTIVITY ; Untyped        ;
    1513. 

  1513. ; PORT_PHASEDONE                ; PORT_CONNECTIVITY ; Untyped        ;
    1514. 

  1514. ; PORT_PHASESTEP                ; PORT_CONNECTIVITY ; Untyped        ;
    1515. 

  1515. ; PORT_PHASEUPDOWN              ; PORT_CONNECTIVITY ; Untyped        ;
    1516. 

  1516. ; PORT_SCANCLKENA               ; PORT_CONNECTIVITY ; Untyped        ;
    1517. 

  1517. ; PORT_PHASECOUNTERSELECT       ; PORT_CONNECTIVITY ; Untyped        ;
    1518. 

  1518. ; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY ; Untyped        ;
    1519. 

  1519. ; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY ; Untyped        ;
    1520. 

  1520. ; M_TEST_SOURCE                 ; 5                 ; Untyped        ;
    1521. 

  1521. ; C0_TEST_SOURCE                ; 5                 ; Untyped        ;
    1522. 

  1522. ; C1_TEST_SOURCE                ; 5                 ; Untyped        ;
    1523. 

  1523. ; C2_TEST_SOURCE                ; 5                 ; Untyped        ;
    1524. 

  1524. ; C3_TEST_SOURCE                ; 5                 ; Untyped        ;
    1525. 

  1525. ; C4_TEST_SOURCE                ; 5                 ; Untyped        ;
    1526. 

  1526. ; C5_TEST_SOURCE                ; 5                 ; Untyped        ;
    1527. 

  1527. ; C6_TEST_SOURCE                ; 5                 ; Untyped        ;
    1528. 

  1528. ; C7_TEST_SOURCE                ; 5                 ; Untyped        ;
    1529. 

  1529. ; C8_TEST_SOURCE                ; 5                 ; Untyped        ;
    1530. 

  1530. ; C9_TEST_SOURCE                ; 5                 ; Untyped        ;
    1531. 

  1531. ; CBXI_PARAMETER                ; altpll_9g32       ; Untyped        ;
    1532. 

  1532. ; VCO_FREQUENCY_CONTROL         ; AUTO              ; Untyped        ;
    1533. 

  1533. ; VCO_PHASE_SHIFT_STEP          ; 0                 ; Untyped        ;
    1534. 

  1534. ; WIDTH_CLOCK                   ; 5                 ; Signed Integer ;
    1535. 

  1535. ; WIDTH_PHASECOUNTERSELECT      ; 3                 ; Signed Integer ;
    1536. 

  1536. ; USING_FBMIMICBIDIR_PORT       ; OFF               ; Untyped        ;
    1537. 

  1537. ; DEVICE_FAMILY                 ; Cyclone IV E      ; Untyped        ;
    1538. 

  1538. ; SCAN_CHAIN_MIF_FILE           ; UNUSED            ; Untyped        ;
    1539. 

  1539. ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF               ; Untyped        ;
    1540. 

  1540. ; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY     ;
    1541. 

  1541. ; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY   ;
    1542. 

  1542. ; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE   ;
    1543. 

  1543. ; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE ;
    1544. 

  1544. +-------------------------------+-------------------+----------------+
    1545. 

  1545. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1546. 

  1546. 

  1547. 

  1548. +----------------------------------------------------------------------+
    1549. 

  1549. ; Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst ;
    1550. 

  1550. +----------------+-------+---------------------------------------------+
    1551. 

  1551. ; Parameter Name ; Value ; Type                                        ;
    1552. 

  1552. +----------------+-------+---------------------------------------------+
    1553. 

  1553. ; coord_x        ; 0     ; Signed Integer                              ;
    1554. 

  1554. ; coord_y        ; 0     ; Signed Integer                              ;
    1555. 

  1555. ; coord_z        ; 0     ; Signed Integer                              ;
    1556. 

  1556. ; ENA_REG_MODE   ; 0     ; Unsigned Binary                             ;
    1557. 

  1557. +----------------+-------+---------------------------------------------+
    1558. 

  1558. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1559. 

  1559. 

  1560. 

  1561. +-----------------------------------------------------------------------+
    1562. 

  1562. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst ;
    1563. 

  1563. +----------------+-------+----------------------------------------------+
    1564. 

  1564. ; Parameter Name ; Value ; Type                                         ;
    1565. 

  1565. +----------------+-------+----------------------------------------------+
    1566. 

  1566. ; UART_GROUP     ; 2     ; Signed Integer                               ;
    1567. 

  1567. ; UART_COUNT     ; 6     ; Signed Integer                               ;
    1568. 

  1568. ; UART_TOTAL     ; 12    ; Signed Integer                               ;
    1569. 

  1569. +----------------+-------+----------------------------------------------+
    1570. 

  1570. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1571. 

  1571. 

  1572. 

  1573. +-----------------------------------------------------------------------------------------+
    1574. 

  1574. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb ;
    1575. 

  1575. +----------------+-------+----------------------------------------------------------------+
    1576. 

  1576. ; Parameter Name ; Value ; Type                                                           ;
    1577. 

  1577. +----------------+-------+----------------------------------------------------------------+
    1578. 

  1578. ; ADDR_BITS      ; 13    ; Signed Integer                                                 ;
    1579. 

  1579. ; DATA_BITS      ; 32    ; Signed Integer                                                 ;
    1580. 

  1580. +----------------+-------+----------------------------------------------------------------+
    1581. 

  1581. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1582. 

  1582. 

  1583. 

  1584. +-----------------------------------------------------------------------------------------+
    1585. 

  1585. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|apb_mux:u_apb_mux ;
    1586. 

  1586. +----------------+-------+----------------------------------------------------------------+
    1587. 

  1587. ; Parameter Name ; Value ; Type                                                           ;
    1588. 

  1588. +----------------+-------+----------------------------------------------------------------+
    1589. 

  1589. ; APB_CNT        ; 2     ; Signed Integer                                                 ;
    1590. 

  1590. ; ADDR_BITS      ; 12    ; Signed Integer                                                 ;
    1591. 

  1591. ; DATA_BITS      ; 32    ; Signed Integer                                                 ;
    1592. 

  1592. +----------------+-------+----------------------------------------------------------------+
    1593. 

  1593. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1594. 

  1594. 

  1595. 

  1596. +--------------------------------------------------------------------------------------------+
    1597. 

  1597. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0] ;
    1598. 

  1598. +----------------+-------+-------------------------------------------------------------------+
    1599. 

  1599. ; Parameter Name ; Value ; Type                                                              ;
    1600. 

  1600. +----------------+-------+-------------------------------------------------------------------+
    1601. 

  1601. ; CNT            ; 6     ; Signed Integer                                                    ;
    1602. 

  1602. ; DATA_WIDTH     ; 8     ; Signed Integer                                                    ;
    1603. 

  1603. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                    ;
    1604. 

  1604. +----------------+-------+-------------------------------------------------------------------+
    1605. 

  1605. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1606. 

  1606. 

  1607. 

  1608. +-------------------------------------------------------------------------------------------------------------+
    1609. 

  1609. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs ;
    1610. 

  1610. +----------------+-------+------------------------------------------------------------------------------------+
    1611. 

  1611. ; Parameter Name ; Value ; Type                                                                               ;
    1612. 

  1612. +----------------+-------+------------------------------------------------------------------------------------+
    1613. 

  1613. ; CNT            ; 6     ; Signed Integer                                                                     ;
    1614. 

  1614. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                     ;
    1615. 

  1615. +----------------+-------+------------------------------------------------------------------------------------+
    1616. 

  1616. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1617. 

  1617. 

  1618. 

  1619. +------------------------------------------------------------------------------------------------------------+
    1620. 

  1620. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0] ;
    1621. 

  1621. +----------------+-------+-----------------------------------------------------------------------------------+
    1622. 

  1622. ; Parameter Name ; Value ; Type                                                                              ;
    1623. 

  1623. +----------------+-------+-----------------------------------------------------------------------------------+
    1624. 

  1624. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1625. 

  1625. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1626. 

  1626. +----------------+-------+-----------------------------------------------------------------------------------+
    1627. 

  1627. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1628. 

  1628. 

  1629. 

  1630. +------------------------------------------------------------------------------------------------------------------------------+
    1631. 

  1631. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ;
    1632. 

  1632. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1633. 

  1633. ; Parameter Name ; Value ; Type                                                                                                ;
    1634. 

  1634. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1635. 

  1635. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1636. 

  1636. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1637. 

  1637. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1638. 

  1638. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1639. 

  1639. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1640. 

  1640. 

  1641. 

  1642. +------------------------------------------------------------------------------------------------------------+
    1643. 

  1643. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1] ;
    1644. 

  1644. +----------------+-------+-----------------------------------------------------------------------------------+
    1645. 

  1645. ; Parameter Name ; Value ; Type                                                                              ;
    1646. 

  1646. +----------------+-------+-----------------------------------------------------------------------------------+
    1647. 

  1647. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1648. 

  1648. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1649. 

  1649. +----------------+-------+-----------------------------------------------------------------------------------+
    1650. 

  1650. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1651. 

  1651. 

  1652. 

  1653. +------------------------------------------------------------------------------------------------------------------------------+
    1654. 

  1654. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ;
    1655. 

  1655. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1656. 

  1656. ; Parameter Name ; Value ; Type                                                                                                ;
    1657. 

  1657. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1658. 

  1658. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1659. 

  1659. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1660. 

  1660. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1661. 

  1661. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1662. 

  1662. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1663. 

  1663. 

  1664. 

  1665. +------------------------------------------------------------------------------------------------------------+
    1666. 

  1666. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2] ;
    1667. 

  1667. +----------------+-------+-----------------------------------------------------------------------------------+
    1668. 

  1668. ; Parameter Name ; Value ; Type                                                                              ;
    1669. 

  1669. +----------------+-------+-----------------------------------------------------------------------------------+
    1670. 

  1670. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1671. 

  1671. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1672. 

  1672. +----------------+-------+-----------------------------------------------------------------------------------+
    1673. 

  1673. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1674. 

  1674. 

  1675. 

  1676. +------------------------------------------------------------------------------------------------------------------------------+
    1677. 

  1677. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ;
    1678. 

  1678. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1679. 

  1679. ; Parameter Name ; Value ; Type                                                                                                ;
    1680. 

  1680. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1681. 

  1681. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1682. 

  1682. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1683. 

  1683. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1684. 

  1684. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1685. 

  1685. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1686. 

  1686. 

  1687. 

  1688. +------------------------------------------------------------------------------------------------------------+
    1689. 

  1689. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3] ;
    1690. 

  1690. +----------------+-------+-----------------------------------------------------------------------------------+
    1691. 

  1691. ; Parameter Name ; Value ; Type                                                                              ;
    1692. 

  1692. +----------------+-------+-----------------------------------------------------------------------------------+
    1693. 

  1693. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1694. 

  1694. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1695. 

  1695. +----------------+-------+-----------------------------------------------------------------------------------+
    1696. 

  1696. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1697. 

  1697. 

  1698. 

  1699. +------------------------------------------------------------------------------------------------------------------------------+
    1700. 

  1700. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ;
    1701. 

  1701. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1702. 

  1702. ; Parameter Name ; Value ; Type                                                                                                ;
    1703. 

  1703. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1704. 

  1704. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1705. 

  1705. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1706. 

  1706. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1707. 

  1707. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1708. 

  1708. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1709. 

  1709. 

  1710. 

  1711. +------------------------------------------------------------------------------------------------------------+
    1712. 

  1712. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4] ;
    1713. 

  1713. +----------------+-------+-----------------------------------------------------------------------------------+
    1714. 

  1714. ; Parameter Name ; Value ; Type                                                                              ;
    1715. 

  1715. +----------------+-------+-----------------------------------------------------------------------------------+
    1716. 

  1716. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1717. 

  1717. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1718. 

  1718. +----------------+-------+-----------------------------------------------------------------------------------+
    1719. 

  1719. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1720. 

  1720. 

  1721. 

  1722. +------------------------------------------------------------------------------------------------------------------------------+
    1723. 

  1723. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ;
    1724. 

  1724. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1725. 

  1725. ; Parameter Name ; Value ; Type                                                                                                ;
    1726. 

  1726. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1727. 

  1727. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1728. 

  1728. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1729. 

  1729. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1730. 

  1730. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1731. 

  1731. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1732. 

  1732. 

  1733. 

  1734. +------------------------------------------------------------------------------------------------------------+
    1735. 

  1735. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5] ;
    1736. 

  1736. +----------------+-------+-----------------------------------------------------------------------------------+
    1737. 

  1737. ; Parameter Name ; Value ; Type                                                                              ;
    1738. 

  1738. +----------------+-------+-----------------------------------------------------------------------------------+
    1739. 

  1739. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1740. 

  1740. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1741. 

  1741. +----------------+-------+-----------------------------------------------------------------------------------+
    1742. 

  1742. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1743. 

  1743. 

  1744. 

  1745. +------------------------------------------------------------------------------------------------------------------------------+
    1746. 

  1746. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ;
    1747. 

  1747. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1748. 

  1748. ; Parameter Name ; Value ; Type                                                                                                ;
    1749. 

  1749. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1750. 

  1750. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1751. 

  1751. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1752. 

  1752. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1753. 

  1753. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1754. 

  1754. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1755. 

  1755. 

  1756. 

  1757. +------------------------------------------------------------------------------------------------------------+
    1758. 

  1758. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0] ;
    1759. 

  1759. +----------------+-------+-----------------------------------------------------------------------------------+
    1760. 

  1760. ; Parameter Name ; Value ; Type                                                                              ;
    1761. 

  1761. +----------------+-------+-----------------------------------------------------------------------------------+
    1762. 

  1762. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1763. 

  1763. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1764. 

  1764. +----------------+-------+-----------------------------------------------------------------------------------+
    1765. 

  1765. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1766. 

  1766. 

  1767. 

  1768. +------------------------------------------------------------------------------------------------------------------------------+
    1769. 

  1769. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ;
    1770. 

  1770. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1771. 

  1771. ; Parameter Name ; Value ; Type                                                                                                ;
    1772. 

  1772. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1773. 

  1773. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1774. 

  1774. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1775. 

  1775. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1776. 

  1776. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1777. 

  1777. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1778. 

  1778. 

  1779. 

  1780. +------------------------------------------------------------------------------------------------------------+
    1781. 

  1781. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1] ;
    1782. 

  1782. +----------------+-------+-----------------------------------------------------------------------------------+
    1783. 

  1783. ; Parameter Name ; Value ; Type                                                                              ;
    1784. 

  1784. +----------------+-------+-----------------------------------------------------------------------------------+
    1785. 

  1785. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1786. 

  1786. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1787. 

  1787. +----------------+-------+-----------------------------------------------------------------------------------+
    1788. 

  1788. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1789. 

  1789. 

  1790. 

  1791. +------------------------------------------------------------------------------------------------------------------------------+
    1792. 

  1792. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ;
    1793. 

  1793. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1794. 

  1794. ; Parameter Name ; Value ; Type                                                                                                ;
    1795. 

  1795. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1796. 

  1796. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1797. 

  1797. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1798. 

  1798. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1799. 

  1799. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1800. 

  1800. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1801. 

  1801. 

  1802. 

  1803. +------------------------------------------------------------------------------------------------------------+
    1804. 

  1804. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2] ;
    1805. 

  1805. +----------------+-------+-----------------------------------------------------------------------------------+
    1806. 

  1806. ; Parameter Name ; Value ; Type                                                                              ;
    1807. 

  1807. +----------------+-------+-----------------------------------------------------------------------------------+
    1808. 

  1808. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1809. 

  1809. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1810. 

  1810. +----------------+-------+-----------------------------------------------------------------------------------+
    1811. 

  1811. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1812. 

  1812. 

  1813. 

  1814. +------------------------------------------------------------------------------------------------------------------------------+
    1815. 

  1815. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ;
    1816. 

  1816. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1817. 

  1817. ; Parameter Name ; Value ; Type                                                                                                ;
    1818. 

  1818. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1819. 

  1819. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1820. 

  1820. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1821. 

  1821. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1822. 

  1822. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1823. 

  1823. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1824. 

  1824. 

  1825. 

  1826. +------------------------------------------------------------------------------------------------------------+
    1827. 

  1827. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3] ;
    1828. 

  1828. +----------------+-------+-----------------------------------------------------------------------------------+
    1829. 

  1829. ; Parameter Name ; Value ; Type                                                                              ;
    1830. 

  1830. +----------------+-------+-----------------------------------------------------------------------------------+
    1831. 

  1831. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1832. 

  1832. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1833. 

  1833. +----------------+-------+-----------------------------------------------------------------------------------+
    1834. 

  1834. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1835. 

  1835. 

  1836. 

  1837. +------------------------------------------------------------------------------------------------------------------------------+
    1838. 

  1838. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ;
    1839. 

  1839. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1840. 

  1840. ; Parameter Name ; Value ; Type                                                                                                ;
    1841. 

  1841. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1842. 

  1842. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1843. 

  1843. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1844. 

  1844. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1845. 

  1845. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1846. 

  1846. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1847. 

  1847. 

  1848. 

  1849. +------------------------------------------------------------------------------------------------------------+
    1850. 

  1850. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4] ;
    1851. 

  1851. +----------------+-------+-----------------------------------------------------------------------------------+
    1852. 

  1852. ; Parameter Name ; Value ; Type                                                                              ;
    1853. 

  1853. +----------------+-------+-----------------------------------------------------------------------------------+
    1854. 

  1854. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1855. 

  1855. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1856. 

  1856. +----------------+-------+-----------------------------------------------------------------------------------+
    1857. 

  1857. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1858. 

  1858. 

  1859. 

  1860. +------------------------------------------------------------------------------------------------------------------------------+
    1861. 

  1861. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ;
    1862. 

  1862. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1863. 

  1863. ; Parameter Name ; Value ; Type                                                                                                ;
    1864. 

  1864. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1865. 

  1865. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1866. 

  1866. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1867. 

  1867. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1868. 

  1868. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1869. 

  1869. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1870. 

  1870. 

  1871. 

  1872. +------------------------------------------------------------------------------------------------------------+
    1873. 

  1873. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5] ;
    1874. 

  1874. +----------------+-------+-----------------------------------------------------------------------------------+
    1875. 

  1875. ; Parameter Name ; Value ; Type                                                                              ;
    1876. 

  1876. +----------------+-------+-----------------------------------------------------------------------------------+
    1877. 

  1877. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1878. 

  1878. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1879. 

  1879. +----------------+-------+-----------------------------------------------------------------------------------+
    1880. 

  1880. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1881. 

  1881. 

  1882. 

  1883. +------------------------------------------------------------------------------------------------------------------------------+
    1884. 

  1884. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ;
    1885. 

  1885. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1886. 

  1886. ; Parameter Name ; Value ; Type                                                                                                ;
    1887. 

  1887. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1888. 

  1888. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1889. 

  1889. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1890. 

  1890. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1891. 

  1891. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1892. 

  1892. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1893. 

  1893. 

  1894. 

  1895. +--------------------------------------------------------------------------------------------+
    1896. 

  1896. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1] ;
    1897. 

  1897. +----------------+-------+-------------------------------------------------------------------+
    1898. 

  1898. ; Parameter Name ; Value ; Type                                                              ;
    1899. 

  1899. +----------------+-------+-------------------------------------------------------------------+
    1900. 

  1900. ; CNT            ; 6     ; Signed Integer                                                    ;
    1901. 

  1901. ; DATA_WIDTH     ; 8     ; Signed Integer                                                    ;
    1902. 

  1902. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                    ;
    1903. 

  1903. +----------------+-------+-------------------------------------------------------------------+
    1904. 

  1904. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1905. 

  1905. 

  1906. 

  1907. +-------------------------------------------------------------------------------------------------------------+
    1908. 

  1908. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs ;
    1909. 

  1909. +----------------+-------+------------------------------------------------------------------------------------+
    1910. 

  1910. ; Parameter Name ; Value ; Type                                                                               ;
    1911. 

  1911. +----------------+-------+------------------------------------------------------------------------------------+
    1912. 

  1912. ; CNT            ; 6     ; Signed Integer                                                                     ;
    1913. 

  1913. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                     ;
    1914. 

  1914. +----------------+-------+------------------------------------------------------------------------------------+
    1915. 

  1915. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1916. 

  1916. 

  1917. 

  1918. +------------------------------------------------------------------------------------------------------------+
    1919. 

  1919. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0] ;
    1920. 

  1920. +----------------+-------+-----------------------------------------------------------------------------------+
    1921. 

  1921. ; Parameter Name ; Value ; Type                                                                              ;
    1922. 

  1922. +----------------+-------+-----------------------------------------------------------------------------------+
    1923. 

  1923. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1924. 

  1924. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1925. 

  1925. +----------------+-------+-----------------------------------------------------------------------------------+
    1926. 

  1926. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1927. 

  1927. 

  1928. 

  1929. +------------------------------------------------------------------------------------------------------------------------------+
    1930. 

  1930. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ;
    1931. 

  1931. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1932. 

  1932. ; Parameter Name ; Value ; Type                                                                                                ;
    1933. 

  1933. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1934. 

  1934. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1935. 

  1935. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1936. 

  1936. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1937. 

  1937. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1938. 

  1938. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1939. 

  1939. 

  1940. 

  1941. +------------------------------------------------------------------------------------------------------------+
    1942. 

  1942. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1] ;
    1943. 

  1943. +----------------+-------+-----------------------------------------------------------------------------------+
    1944. 

  1944. ; Parameter Name ; Value ; Type                                                                              ;
    1945. 

  1945. +----------------+-------+-----------------------------------------------------------------------------------+
    1946. 

  1946. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1947. 

  1947. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1948. 

  1948. +----------------+-------+-----------------------------------------------------------------------------------+
    1949. 

  1949. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1950. 

  1950. 

  1951. 

  1952. +------------------------------------------------------------------------------------------------------------------------------+
    1953. 

  1953. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ;
    1954. 

  1954. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1955. 

  1955. ; Parameter Name ; Value ; Type                                                                                                ;
    1956. 

  1956. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1957. 

  1957. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1958. 

  1958. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1959. 

  1959. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1960. 

  1960. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1961. 

  1961. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1962. 

  1962. 

  1963. 

  1964. +------------------------------------------------------------------------------------------------------------+
    1965. 

  1965. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2] ;
    1966. 

  1966. +----------------+-------+-----------------------------------------------------------------------------------+
    1967. 

  1967. ; Parameter Name ; Value ; Type                                                                              ;
    1968. 

  1968. +----------------+-------+-----------------------------------------------------------------------------------+
    1969. 

  1969. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1970. 

  1970. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1971. 

  1971. +----------------+-------+-----------------------------------------------------------------------------------+
    1972. 

  1972. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1973. 

  1973. 

  1974. 

  1975. +------------------------------------------------------------------------------------------------------------------------------+
    1976. 

  1976. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ;
    1977. 

  1977. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1978. 

  1978. ; Parameter Name ; Value ; Type                                                                                                ;
    1979. 

  1979. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1980. 

  1980. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    1981. 

  1981. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    1982. 

  1982. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    1983. 

  1983. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    1984. 

  1984. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1985. 

  1985. 

  1986. 

  1987. +------------------------------------------------------------------------------------------------------------+
    1988. 

  1988. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3] ;
    1989. 

  1989. +----------------+-------+-----------------------------------------------------------------------------------+
    1990. 

  1990. ; Parameter Name ; Value ; Type                                                                              ;
    1991. 

  1991. +----------------+-------+-----------------------------------------------------------------------------------+
    1992. 

  1992. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    1993. 

  1993. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    1994. 

  1994. +----------------+-------+-----------------------------------------------------------------------------------+
    1995. 

  1995. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    1996. 

  1996. 

  1997. 

  1998. +------------------------------------------------------------------------------------------------------------------------------+
    1999. 

  1999. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ;
    2000. 

  2000. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2001. 

  2001. ; Parameter Name ; Value ; Type                                                                                                ;
    2002. 

  2002. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2003. 

  2003. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2004. 

  2004. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2005. 

  2005. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2006. 

  2006. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2007. 

  2007. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2008. 

  2008. 

  2009. 

  2010. +------------------------------------------------------------------------------------------------------------+
    2011. 

  2011. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4] ;
    2012. 

  2012. +----------------+-------+-----------------------------------------------------------------------------------+
    2013. 

  2013. ; Parameter Name ; Value ; Type                                                                              ;
    2014. 

  2014. +----------------+-------+-----------------------------------------------------------------------------------+
    2015. 

  2015. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2016. 

  2016. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2017. 

  2017. +----------------+-------+-----------------------------------------------------------------------------------+
    2018. 

  2018. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2019. 

  2019. 

  2020. 

  2021. +------------------------------------------------------------------------------------------------------------------------------+
    2022. 

  2022. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ;
    2023. 

  2023. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2024. 

  2024. ; Parameter Name ; Value ; Type                                                                                                ;
    2025. 

  2025. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2026. 

  2026. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2027. 

  2027. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2028. 

  2028. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2029. 

  2029. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2030. 

  2030. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2031. 

  2031. 

  2032. 

  2033. +------------------------------------------------------------------------------------------------------------+
    2034. 

  2034. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5] ;
    2035. 

  2035. +----------------+-------+-----------------------------------------------------------------------------------+
    2036. 

  2036. ; Parameter Name ; Value ; Type                                                                              ;
    2037. 

  2037. +----------------+-------+-----------------------------------------------------------------------------------+
    2038. 

  2038. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2039. 

  2039. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2040. 

  2040. +----------------+-------+-----------------------------------------------------------------------------------+
    2041. 

  2041. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2042. 

  2042. 

  2043. 

  2044. +------------------------------------------------------------------------------------------------------------------------------+
    2045. 

  2045. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ;
    2046. 

  2046. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2047. 

  2047. ; Parameter Name ; Value ; Type                                                                                                ;
    2048. 

  2048. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2049. 

  2049. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2050. 

  2050. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2051. 

  2051. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2052. 

  2052. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2053. 

  2053. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2054. 

  2054. 

  2055. 

  2056. +------------------------------------------------------------------------------------------------------------+
    2057. 

  2057. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0] ;
    2058. 

  2058. +----------------+-------+-----------------------------------------------------------------------------------+
    2059. 

  2059. ; Parameter Name ; Value ; Type                                                                              ;
    2060. 

  2060. +----------------+-------+-----------------------------------------------------------------------------------+
    2061. 

  2061. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2062. 

  2062. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2063. 

  2063. +----------------+-------+-----------------------------------------------------------------------------------+
    2064. 

  2064. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2065. 

  2065. 

  2066. 

  2067. +------------------------------------------------------------------------------------------------------------------------------+
    2068. 

  2068. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ;
    2069. 

  2069. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2070. 

  2070. ; Parameter Name ; Value ; Type                                                                                                ;
    2071. 

  2071. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2072. 

  2072. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2073. 

  2073. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2074. 

  2074. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2075. 

  2075. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2076. 

  2076. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2077. 

  2077. 

  2078. 

  2079. +------------------------------------------------------------------------------------------------------------+
    2080. 

  2080. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1] ;
    2081. 

  2081. +----------------+-------+-----------------------------------------------------------------------------------+
    2082. 

  2082. ; Parameter Name ; Value ; Type                                                                              ;
    2083. 

  2083. +----------------+-------+-----------------------------------------------------------------------------------+
    2084. 

  2084. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2085. 

  2085. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2086. 

  2086. +----------------+-------+-----------------------------------------------------------------------------------+
    2087. 

  2087. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2088. 

  2088. 

  2089. 

  2090. +------------------------------------------------------------------------------------------------------------------------------+
    2091. 

  2091. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ;
    2092. 

  2092. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2093. 

  2093. ; Parameter Name ; Value ; Type                                                                                                ;
    2094. 

  2094. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2095. 

  2095. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2096. 

  2096. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2097. 

  2097. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2098. 

  2098. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2099. 

  2099. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2100. 

  2100. 

  2101. 

  2102. +------------------------------------------------------------------------------------------------------------+
    2103. 

  2103. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2] ;
    2104. 

  2104. +----------------+-------+-----------------------------------------------------------------------------------+
    2105. 

  2105. ; Parameter Name ; Value ; Type                                                                              ;
    2106. 

  2106. +----------------+-------+-----------------------------------------------------------------------------------+
    2107. 

  2107. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2108. 

  2108. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2109. 

  2109. +----------------+-------+-----------------------------------------------------------------------------------+
    2110. 

  2110. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2111. 

  2111. 

  2112. 

  2113. +------------------------------------------------------------------------------------------------------------------------------+
    2114. 

  2114. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ;
    2115. 

  2115. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2116. 

  2116. ; Parameter Name ; Value ; Type                                                                                                ;
    2117. 

  2117. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2118. 

  2118. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2119. 

  2119. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2120. 

  2120. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2121. 

  2121. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2122. 

  2122. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2123. 

  2123. 

  2124. 

  2125. +------------------------------------------------------------------------------------------------------------+
    2126. 

  2126. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3] ;
    2127. 

  2127. +----------------+-------+-----------------------------------------------------------------------------------+
    2128. 

  2128. ; Parameter Name ; Value ; Type                                                                              ;
    2129. 

  2129. +----------------+-------+-----------------------------------------------------------------------------------+
    2130. 

  2130. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2131. 

  2131. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2132. 

  2132. +----------------+-------+-----------------------------------------------------------------------------------+
    2133. 

  2133. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2134. 

  2134. 

  2135. 

  2136. +------------------------------------------------------------------------------------------------------------------------------+
    2137. 

  2137. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ;
    2138. 

  2138. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2139. 

  2139. ; Parameter Name ; Value ; Type                                                                                                ;
    2140. 

  2140. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2141. 

  2141. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2142. 

  2142. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2143. 

  2143. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2144. 

  2144. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2145. 

  2145. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2146. 

  2146. 

  2147. 

  2148. +------------------------------------------------------------------------------------------------------------+
    2149. 

  2149. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4] ;
    2150. 

  2150. +----------------+-------+-----------------------------------------------------------------------------------+
    2151. 

  2151. ; Parameter Name ; Value ; Type                                                                              ;
    2152. 

  2152. +----------------+-------+-----------------------------------------------------------------------------------+
    2153. 

  2153. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2154. 

  2154. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2155. 

  2155. +----------------+-------+-----------------------------------------------------------------------------------+
    2156. 

  2156. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2157. 

  2157. 

  2158. 

  2159. +------------------------------------------------------------------------------------------------------------------------------+
    2160. 

  2160. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ;
    2161. 

  2161. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2162. 

  2162. ; Parameter Name ; Value ; Type                                                                                                ;
    2163. 

  2163. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2164. 

  2164. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2165. 

  2165. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2166. 

  2166. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2167. 

  2167. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2168. 

  2168. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2169. 

  2169. 

  2170. 

  2171. +------------------------------------------------------------------------------------------------------------+
    2172. 

  2172. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5] ;
    2173. 

  2173. +----------------+-------+-----------------------------------------------------------------------------------+
    2174. 

  2174. ; Parameter Name ; Value ; Type                                                                              ;
    2175. 

  2175. +----------------+-------+-----------------------------------------------------------------------------------+
    2176. 

  2176. ; DATA_WIDTH     ; 8     ; Signed Integer                                                                    ;
    2177. 

  2177. ; FIFO_DEPTH     ; 1     ; Signed Integer                                                                    ;
    2178. 

  2178. +----------------+-------+-----------------------------------------------------------------------------------+
    2179. 

  2179. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2180. 

  2180. 

  2181. 

  2182. +------------------------------------------------------------------------------------------------------------------------------+
    2183. 

  2183. ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ;
    2184. 

  2184. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2185. 

  2185. ; Parameter Name ; Value ; Type                                                                                                ;
    2186. 

  2186. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2187. 

  2187. ; WIDTH          ; 8     ; Signed Integer                                                                                      ;
    2188. 

  2188. ; DEPTH          ; 1     ; Signed Integer                                                                                      ;
    2189. 

  2189. ; SHOWAEAD       ; 1     ; Signed Integer                                                                                      ;
    2190. 

  2190. +----------------+-------+-----------------------------------------------------------------------------------------------------+
    2191. 

  2191. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2192. 

  2192. 

  2193. 

  2194. +---------------------------------------------------------------------------------------------------------------------------------------------------+
    2195. 

  2195. ; Partition Dependent Files                                                                                                                         ;
    2196. 

  2196. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    2197. 

  2197. ; File                                                                            ; Location           ; Library ; Checksum                         ;
    2198. 

  2198. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    2199. 

  2199. ; libraries/megafunctions/aglobal130.inc                                          ; Quartus II Install ; work    ; 6fc5170a475a9c6f00c3fd7627b30d31 ;
    2200. 

  2200. ; libraries/megafunctions/altpll.tdf                                              ; Quartus II Install ; work    ; 2fbd40fef3231c521503c3b7162ebe3e ;
    2201. 

  2201. ; libraries/megafunctions/cycloneii_pll.inc                                       ; Quartus II Install ; work    ; c2ee779f089b03bc181df753ea85b3ef ;
    2202. 

  2202. ; libraries/megafunctions/stratix_pll.inc                                         ; Quartus II Install ; work    ; a9a94c5b0e18105f7ae8c218a67ec9f7 ;
    2203. 

  2203. ; libraries/megafunctions/stratixii_pll.inc                                       ; Quartus II Install ; work    ; 6797ab505ed700f1a221e4a213e106a6 ;
    2204. 

  2204. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute           ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    2205. 

  2205. ; ahb2apb.v                                                                       ; Project Directory  ; work    ; c0ffc445ab6981ccc770b94b804da175 ;
    2206. 

  2206. ; apb_mux.v                                                                       ; Project Directory  ; work    ; 116a3aadafa91dc333e285e787adcfbd ;
    2207. 

  2207. ; db/altpll_9g32.tdf                                                              ; Project Directory  ; work    ; 6571784d6e255593b8053aed7770dc66 ;
    2208. 

  2208. ; multi_uart_ip.v                                                                 ; Project Directory  ; work    ; f903c122b611903a57ce62ebf868c67c ;
    2209. 

  2209. ; multi_uart_ip/baud_gen.v                                                        ; Project Directory  ; work    ; 9cc17364fcb27f4ebdc9b9f7e74df21b ;
    2210. 

  2210. ; multi_uart_ip/multi_uart.v                                                      ; Project Directory  ; work    ; 0e8563a5553efcaa477674a21da00cb7 ;
    2211. 

  2211. ; multi_uart_ip/sync_fifo.v                                                       ; Project Directory  ; work    ; 2c5edbc41601ae09647b7a780aa8bdf1 ;
    2212. 

  2212. ; multi_uart_ip/uart_regs.v                                                       ; Project Directory  ; work    ; d2486baae9a756bd165a62753eff3d6a ;
    2213. 

  2213. ; multi_uart_ip/uart_rx.v                                                         ; Project Directory  ; work    ; a94e4e50768cb2f98b014a60af8722f4 ;
    2214. 

  2214. ; multi_uart_ip/uart_tx.v                                                         ; Project Directory  ; work    ; 26da0d543584fcfa1fbc29e7c62d286c ;
    2215. 

  2215. ; test_uart.v                                                                     ; Project Directory  ; work    ; 6e45d9343f699dc713c0cc45ba601a9c ;
    2216. 

  2216. +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+
    2217. 

  2217. 

  2218. 

  2219. +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    2220. 

  2220. ; Partition "rv32" Resource Utilization by Entity                                                                                                                                   ;
    2221. 

  2221. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
    2222. 

  2222. ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name       ; Library Name ;
    2223. 

  2223. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
    2224. 

  2224. ; |test_uart                 ; 1 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart                ; work         ;
    2225. 

  2225. ;    |alta_rv32:rv32|        ; 1 (1)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |test_uart|alta_rv32:rv32 ; work         ;
    2226. 

  2226. +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+
    2227. 

  2227. Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
    2228. 

  2228. 

  2229. 

  2230. +-------------------------------------------------------------+
    2231. 

  2231. ; Parameter Settings for User Entity Instance: alta_rv32:rv32 ;
    2232. 

  2232. +----------------+-------+------------------------------------+
    2233. 

  2233. ; Parameter Name ; Value ; Type                               ;
    2234. 

  2234. +----------------+-------+------------------------------------+
    2235. 

  2235. ; coord_x        ; 0     ; Signed Integer                     ;
    2236. 

  2236. ; coord_y        ; 0     ; Signed Integer                     ;
    2237. 

  2237. ; coord_z        ; 0     ; Signed Integer                     ;
    2238. 

  2238. +----------------+-------+------------------------------------+
    2239. 

  2239. Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
    2240. 

  2240. 

  2241. 

  2242. +-----------------------------------------------------------------------------------------------------------------------------------------+
    2243. 

  2243. ; Partition Dependent Files                                                                                                               ;
    2244. 

  2244. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    2245. 

  2245. ; File                                                                            ; Location ; Library ; Checksum                         ;
    2246. 

  2246. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    2247. 

  2247. ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work    ; 08f2cc6cdebd91dbc2e05d999cace46c ;
    2248. 

  2248. +---------------------------------------------------------------------------------+----------+---------+----------------------------------+
    2249. 

  2249. 

  2250. 

  2251. +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    2252. 

  2252. ; Port Connectivity Checks: "alta_rv32:rv32"                                                                                                                               ;
    2253. 

  2253. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    2254. 

  2254. ; Port                    ; Type             ; Severity ; Details                                                                                                          ;
    2255. 

  2255. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    2256. 

  2256. ; ext_resetn              ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    2257. 

  2257. ; test_mode               ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2258. 

  2258. ; usb0_xcvr_clk           ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    2259. 

  2259. ; usb0_id                 ; Partition Input  ; Warning  ; Stuck at VCC. Constants will not propagate across partition boundaries                                           ;
    2260. 

  2260. ; sys_ctrl_hseEnable      ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2261. 

  2261. ; sys_ctrl_hseBypass      ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2262. 

  2262. ; sys_ctrl_sleep          ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2263. 

  2263. ; sys_ctrl_standby        ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2264. 

  2264. ; dmactive                ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2265. 

  2265. ; swj_JTAGNSW             ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2266. 

  2266. ; swj_JTAGSTATE           ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2267. 

  2267. ; swj_JTAGIR              ; Partition Output ; Info     ; Explicitly unconnected                                                                                           ;
    2268. 

  2268. ; ext_int                 ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2269. 

  2269. ; gpio0_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2270. 

  2270. ; gpio0_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2271. 

  2271. ; gpio0_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2272. 

  2272. ; gpio1_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2273. 

  2273. ; gpio2_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2274. 

  2274. ; gpio3_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2275. 

  2275. ; gpio3_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2276. 

  2276. ; gpio4_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2277. 

  2277. ; gpio4_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2278. 

  2278. ; gpio5_io_out_data       ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2279. 

  2279. ; gpio5_io_out_en         ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2280. 

  2280. ; gpio6_io_out_data[7]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2281. 

  2281. ; gpio6_io_out_data[5]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2282. 

  2282. ; gpio6_io_out_data[3]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2283. 

  2283. ; gpio6_io_out_data[1]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2284. 

  2284. ; gpio6_io_out_en[7]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2285. 

  2285. ; gpio6_io_out_en[5]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2286. 

  2286. ; gpio6_io_out_en[3]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2287. 

  2287. ; gpio6_io_out_en[1]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2288. 

  2288. ; gpio7_io_out_data[5..0] ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2289. 

  2289. ; gpio7_io_out_data[7]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2290. 

  2290. ; gpio7_io_out_en[5..0]   ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2291. 

  2291. ; gpio7_io_out_en[7]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2292. 

  2292. ; gpio8_io_in             ; Partition Input  ; Warning  ; Stuck at GND. Constants will not propagate across partition boundaries                                           ;
    2293. 

  2293. ; gpio8_io_out_data[5]    ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2294. 

  2294. ; gpio8_io_out_en[5]      ; Partition Output ; Warning  ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ;
    2295. 

  2295. +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+
    2296. 

  2296. 

  2297. 

  2298. +----------------------------------------------------------------------------------------------------------------------+
    2299. 

  2299. ; Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[1]"                                            ;
    2300. 

  2300. +------------+--------+----------+-------------------------------------------------------------------------------------+
    2301. 

  2301. ; Port       ; Type   ; Severity ; Details                                                                             ;
    2302. 

  2302. +------------+--------+----------+-------------------------------------------------------------------------------------+
    2303. 

  2303. ; tx_dma_clr ; Input  ; Info     ; Stuck at GND                                                                        ;
    2304. 

  2304. ; tx_dma_req ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2305. 

  2305. ; rx_dma_clr ; Input  ; Info     ; Stuck at GND                                                                        ;
    2306. 

  2306. ; rx_dma_req ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2307. 

  2307. +------------+--------+----------+-------------------------------------------------------------------------------------+
    2308. 

  2308. 

  2309. 

  2310. +----------------------------------------------------------------------------------------------------------------------------+
    2311. 

  2311. ; Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[0]"                                                  ;
    2312. 

  2312. +------------------+--------+----------+-------------------------------------------------------------------------------------+
    2313. 

  2313. ; Port             ; Type   ; Severity ; Details                                                                             ;
    2314. 

  2314. +------------------+--------+----------+-------------------------------------------------------------------------------------+
    2315. 

  2315. ; tx_dma_clr[5..2] ; Input  ; Info     ; Stuck at GND                                                                        ;
    2316. 

  2316. ; tx_dma_req[5..2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2317. 

  2317. ; rx_dma_clr[5..2] ; Input  ; Info     ; Stuck at GND                                                                        ;
    2318. 

  2318. ; rx_dma_req[5..2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2319. 

  2319. +------------------+--------+----------+-------------------------------------------------------------------------------------+
    2320. 

  2320. 

  2321. 

  2322. +------------------------------------------------------------------------+
    2323. 

  2323. ; Port Connectivity Checks: "multi_uart_ip:macro_inst|apb_mux:u_apb_mux" ;
    2324. 

  2324. +-----------------+-------+----------+-----------------------------------+
    2325. 

  2325. ; Port            ; Type  ; Severity ; Details                           ;
    2326. 

  2326. +-----------------+-------+----------+-----------------------------------+
    2327. 

  2327. ; apb_out_pslverr ; Input ; Info     ; Stuck at GND                      ;
    2328. 

  2328. +-----------------+-------+----------+-----------------------------------+
    2329. 

  2329. 

  2330. 

  2331. +---------------------------------------------------------------------------------------------------------------------------+
    2332. 

  2332. ; Port Connectivity Checks: "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb"                                                    ;
    2333. 

  2333. +-----------------+--------+----------+-------------------------------------------------------------------------------------+
    2334. 

  2334. ; Port            ; Type   ; Severity ; Details                                                                             ;
    2335. 

  2335. +-----------------+--------+----------+-------------------------------------------------------------------------------------+
    2336. 

  2336. ; ahb_hmastlock   ; Input  ; Info     ; Stuck at GND                                                                        ;
    2337. 

  2337. ; ahb_hsel        ; Input  ; Info     ; Stuck at VCC                                                                        ;
    2338. 

  2338. ; ahb_hprot[1..0] ; Input  ; Info     ; Stuck at VCC                                                                        ;
    2339. 

  2339. ; ahb_hprot[3..2] ; Input  ; Info     ; Stuck at GND                                                                        ;
    2340. 

  2340. ; apb_pstrb       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2341. 

  2341. ; apb_pprot       ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
    2342. 

  2342. +-----------------+--------+----------+-------------------------------------------------------------------------------------+
    2343. 

  2343. 

  2344. 

  2345. +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
    2346. 

  2346. ; Port Connectivity Checks: "multi_uart_ip:macro_inst"                                                                                                                                   ;
    2347. 

  2347. +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
    2348. 

  2348. ; Port                ; Type   ; Severity ; Details                                                                                                                                      ;
    2349. 

  2349. +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
    2350. 

  2350. ; ext_int_in          ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
    2351. 

  2351. ; rxd_14_ip_in        ; Output ; Warning  ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed.                                     ;
    2352. 

  2352. ; txd_14_ip_out_data  ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
    2353. 

  2353. ; txd_14_ip_out_en    ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
    2354. 

  2354. ; txen_14_ip_out_data ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
    2355. 

  2355. ; txen_14_ip_out_en   ; Input  ; Warning  ; Declared by entity but not connected by instance. If a default value exists, it will be used.  Otherwise, the port will be connected to GND. ;
    2356. 

  2356. +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+
    2357. 

  2357. 

  2358. 

  2359. +-----------------------------------------------------+
    2360. 

  2360. ; Port Connectivity Checks: "alta_gclksw:gclksw_inst" ;
    2361. 

  2361. +--------+-------+----------+-------------------------+
    2362. 

  2362. ; Port   ; Type  ; Severity ; Details                 ;
    2363. 

  2363. +--------+-------+----------+-------------------------+
    2364. 

  2364. ; ena    ; Input ; Info     ; Stuck at VCC            ;
    2365. 

  2365. ; clkin3 ; Input ; Info     ; Explicitly unconnected  ;
    2366. 

  2366. +--------+-------+----------+-------------------------+
    2367. 

  2367. 

  2368. 

  2369. +-------------------------------+
    2370. 

  2370. ; Elapsed Time Per Partition    ;
    2371. 

  2371. +----------------+--------------+
    2372. 

  2372. ; Partition Name ; Elapsed Time ;
    2373. 

  2373. +----------------+--------------+
    2374. 

  2374. ; Top            ; 00:00:07     ;
    2375. 

  2375. ; rv32           ; 00:00:07     ;
    2376. 

  2376. +----------------+--------------+
    2377. 

  2377. 

  2378. 

  2379. +-------------------------------+
    2380. 

  2380. ; Analysis & Synthesis Messages ;
    2381. 

  2381. +-------------------------------+
    2382. 

  2382. Info: *******************************************************************
    2383. 

  2383. Info: Running Quartus II 64-Bit Analysis & Synthesis
    2384. 

  2384.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    2385. 

  2385.     Info: Processing started: Tue Jul 15 16:26:04 2025
    2386. 

  2386. Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test_uart -c test_uart
    2387. 

  2387. Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead.
    2388. 

  2388. Info (12021): Found 1 design units, including 1 entities, in source file test_uart.v
    2389. 

  2389.     Info (12023): Found entity 1: test_uart
    2390. 

  2390. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip.v
    2391. 

  2391.     Info (12023): Found entity 1: multi_uart_ip
    2392. 

  2392. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/baud_gen.v
    2393. 

  2393.     Info (12023): Found entity 1: baud_gen
    2394. 

  2394. Warning (10275): Verilog HDL Module Instantiation warning at multi_uart.v(90): ignored dangling comma in List of Port Connections
    2395. 

  2395. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/multi_uart.v
    2396. 

  2396.     Info (12023): Found entity 1: multi_uart
    2397. 

  2397. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/sync_fifo.v
    2398. 

  2398.     Info (12023): Found entity 1: sync_fifo
    2399. 

  2399. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_regs.v
    2400. 

  2400.     Info (12023): Found entity 1: uart_regs
    2401. 

  2401. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_rx.v
    2402. 

  2402.     Info (12023): Found entity 1: uart_rx
    2403. 

  2403. Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_tx.v
    2404. 

  2404.     Info (12023): Found entity 1: uart_tx
    2405. 

  2405. Info (12021): Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v
    2406. 

  2406.     Info (12023): Found entity 1: alta_slice
    2407. 

  2407.     Info (12023): Found entity 2: alta_clkenctrl_rst
    2408. 

  2408.     Info (12023): Found entity 3: alta_clkenctrl
    2409. 

  2409.     Info (12023): Found entity 4: alta_asyncctrl
    2410. 

  2410.     Info (12023): Found entity 5: alta_syncctrl
    2411. 

  2411.     Info (12023): Found entity 6: alta_io_gclk
    2412. 

  2412.     Info (12023): Found entity 7: alta_gclksel
    2413. 

  2413.     Info (12023): Found entity 8: alta_gclkgen
    2414. 

  2414.     Info (12023): Found entity 9: alta_gclkgen0
    2415. 

  2415.     Info (12023): Found entity 10: alta_gclkgen2
    2416. 

  2416.     Info (12023): Found entity 11: alta_io
    2417. 

  2417.     Info (12023): Found entity 12: alta_rio
    2418. 

  2418.     Info (12023): Found entity 13: alta_srff
    2419. 

  2419.     Info (12023): Found entity 14: alta_dff
    2420. 

  2420.     Info (12023): Found entity 15: alta_ufm_gddd
    2421. 

  2421.     Info (12023): Found entity 16: alta_dff_stall
    2422. 

  2422.     Info (12023): Found entity 17: alta_srlat
    2423. 

  2423.     Info (12023): Found entity 18: alta_dio
    2424. 

  2424.     Info (12023): Found entity 19: alta_indel
    2425. 

  2425.     Info (12023): Found entity 20: alta_dpclkdel
    2426. 

  2426.     Info (12023): Found entity 21: alta_ufms
    2427. 

  2427.     Info (12023): Found entity 22: alta_ufms_sim
    2428. 

  2428.     Info (12023): Found entity 23: alta_pll
    2429. 

  2429.     Info (12023): Found entity 24: alta_pllx
    2430. 

  2430.     Info (12023): Found entity 25: pll_clk_trim
    2431. 

  2431.     Info (12023): Found entity 26: alta_pllv
    2432. 

  2432.     Info (12023): Found entity 27: alta_pllve
    2433. 

  2433.     Info (12023): Found entity 28: alta_sram
    2434. 

  2434.     Info (12023): Found entity 29: alta_dpram16x4
    2435. 

  2435.     Info (12023): Found entity 30: alta_spram16x4
    2436. 

  2436.     Info (12023): Found entity 31: alta_wram
    2437. 

  2437.     Info (12023): Found entity 32: alta_bram_pulse_generator
    2438. 

  2438.     Info (12023): Found entity 33: alta_bram
    2439. 

  2439.     Info (12023): Found entity 34: alta_boot
    2440. 

  2440.     Info (12023): Found entity 35: alta_osc
    2441. 

  2441.     Info (12023): Found entity 36: alta_ufml
    2442. 

  2442.     Info (12023): Found entity 37: alta_jtag
    2443. 

  2443.     Info (12023): Found entity 38: alta_mult
    2444. 

  2444.     Info (12023): Found entity 39: alta_dff_en
    2445. 

  2445.     Info (12023): Found entity 40: alta_multm_add
    2446. 

  2446.     Info (12023): Found entity 41: alta_multm
    2447. 

  2447.     Info (12023): Found entity 42: alta_i2c
    2448. 

  2448.     Info (12023): Found entity 43: alta_spi
    2449. 

  2449.     Info (12023): Found entity 44: alta_irda
    2450. 

  2450.     Info (12023): Found entity 45: alta_bram9k
    2451. 

  2451.     Info (12023): Found entity 46: alta_mcu
    2452. 

  2452.     Info (12023): Found entity 47: alta_mcu_m3
    2453. 

  2453.     Info (12023): Found entity 48: alta_remote
    2454. 

  2454.     Info (12023): Found entity 49: alta_saradc
    2455. 

  2455.     Info (12023): Found entity 50: alta_gclksw
    2456. 

  2456.     Info (12023): Found entity 51: alta_rv32
    2457. 

  2457.     Info (12023): Found entity 52: alta_mipi_clk
    2458. 

  2458.     Info (12023): Found entity 53: alta_adc
    2459. 

  2459.     Info (12023): Found entity 54: alta_dac
    2460. 

  2460.     Info (12023): Found entity 55: alta_cmp
    2461. 

  2461.     Info (12023): Found entity 56: alta_ram4k
    2462. 

  2462.     Info (12023): Found entity 57: alta_ram9k
    2463. 

  2463. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(143): created implicit net for "PIN_32_in"
    2464. 

  2464. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(146): created implicit net for "PIN_33_in"
    2465. 

  2465. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(154): created implicit net for "PIN_35_in"
    2466. 

  2466. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(162): created implicit net for "PIN_38_in"
    2467. 

  2467. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(180): created implicit net for "PIN_48_in"
    2468. 

  2468. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(201): created implicit net for "PIN_66_in"
    2469. 

  2469. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(259): created implicit net for "PIN_95_in"
    2470. 

  2470. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(267): created implicit net for "PIN_97_in"
    2471. 

  2471. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(270): created implicit net for "PIN_98_in"
    2472. 

  2472. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(276): created implicit net for "PIN_HSE_in"
    2473. 

  2473. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(279): created implicit net for "PIN_HSI_in"
    2474. 

  2474. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(282): created implicit net for "PIN_OSC_in"
    2475. 

  2475. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(405): created implicit net for "usb0_xcvr_clk"
    2476. 

  2476. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(424): created implicit net for "bus_clk"
    2477. 

  2477. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(437): created implicit net for "sys_clk"
    2478. 

  2478. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__5__"
    2479. 

  2479. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__4__"
    2480. 

  2480. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__3__"
    2481. 

  2481. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__2__"
    2482. 

  2482. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__1__"
    2483. 

  2483. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__0__"
    2484. 

  2484. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__5__"
    2485. 

  2485. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__4__"
    2486. 

  2486. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__3__"
    2487. 

  2487. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__2__"
    2488. 

  2488. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__1__"
    2489. 

  2489. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__0__"
    2490. 

  2490. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(494): created implicit net for "rxd_12_ip_in"
    2491. 

  2491. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(495): created implicit net for "rxd_13_ip_in"
    2492. 

  2492. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(496): created implicit net for "rxd_15_ip_in"
    2493. 

  2493. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(497): created implicit net for "txd_12_ip_out_data"
    2494. 

  2494. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(498): created implicit net for "txd_12_ip_out_en"
    2495. 

  2495. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(499): created implicit net for "txd_13_ip_out_data"
    2496. 

  2496. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(500): created implicit net for "txd_13_ip_out_en"
    2497. 

  2497. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(501): created implicit net for "txd_15_ip_out_data"
    2498. 

  2498. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(502): created implicit net for "txd_15_ip_out_en"
    2499. 

  2499. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(503): created implicit net for "txen_12_ip_out_data"
    2500. 

  2500. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(504): created implicit net for "txen_12_ip_out_en"
    2501. 

  2501. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(505): created implicit net for "txen_13_ip_out_data"
    2502. 

  2502. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(506): created implicit net for "txen_13_ip_out_en"
    2503. 

  2503. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(507): created implicit net for "txen_15_ip_out_data"
    2504. 

  2504. Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(508): created implicit net for "txen_15_ip_out_en"
    2505. 

  2505. Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(51): created implicit net for "baud16"
    2506. 

  2506. Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(83): created implicit net for "lcr_sps"
    2507. 

  2507. Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(84): created implicit net for "lcr_stp2"
    2508. 

  2508. Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(85): created implicit net for "lcr_eps"
    2509. 

  2509. Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(86): created implicit net for "lcr_pen"
    2510. 

  2510. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for "ena_reg"
    2511. 

  2511. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for "ena_int"
    2512. 

  2512. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for "ena_reg"
    2513. 

  2513. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for "outreg_h"
    2514. 

  2514. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for "outreg_l"
    2515. 

  2515. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for "oe_reg_h"
    2516. 

  2516. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for "oe_reg_l"
    2517. 

  2517. Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for "dffOut"
    2518. 

  2518. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(105): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2519. 

  2519. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(106): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2520. 

  2520. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(126): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2521. 

  2521. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(127): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2522. 

  2522. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(128): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2523. 

  2523. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(38): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2524. 

  2524. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(39): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2525. 

  2525. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(40): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2526. 

  2526. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(41): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2527. 

  2527. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(42): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2528. 

  2528. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(43): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2529. 

  2529. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(44): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2530. 

  2530. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(45): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2531. 

  2531. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(46): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2532. 

  2532. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(47): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2533. 

  2533. Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(49): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2534. 

  2534. Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(21): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2535. 

  2535. Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(22): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2536. 

  2536. Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(23): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2537. 

  2537. Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(24): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2538. 

  2538. Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(25): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2539. 

  2539. Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(12): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2540. 

  2540. Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(13): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2541. 

  2541. Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(18): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2542. 

  2542. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(24): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2543. 

  2543. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(25): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2544. 

  2544. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(26): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2545. 

  2545. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(27): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2546. 

  2546. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(28): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2547. 

  2547. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(30): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2548. 

  2548. Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(31): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2549. 

  2549. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(228): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2550. 

  2550. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(229): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2551. 

  2551. Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(230): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2552. 

  2552. Warning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List
    2553. 

  2553. Info (12127): Elaborating entity "test_uart" for the top level hierarchy
    2554. 

  2554. Warning (10036): Verilog HDL or VHDL warning at test_uart.v(282): object "PIN_OSC_in" assigned a value but never read
    2555. 

  2555. Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll_inst"
    2556. 

  2556. Info (12130): Elaborated megafunction instantiation "altpll:pll_inst"
    2557. 

  2557. Info (12133): Instantiated megafunction "altpll:pll_inst" with the following parameter:
    2558. 

  2558.     Info (12134): Parameter "bandwidth_type" = "AUTO"
    2559. 

  2559.     Info (12134): Parameter "clk0_divide_by" = "4"
    2560. 

  2560.     Info (12134): Parameter "clk0_multiply_by" = "120"
    2561. 

  2561.     Info (12134): Parameter "clk0_phase_shift" = "0"
    2562. 

  2562.     Info (12134): Parameter "clk1_divide_by" = "4"
    2563. 

  2563.     Info (12134): Parameter "clk1_multiply_by" = "120"
    2564. 

  2564.     Info (12134): Parameter "clk1_phase_shift" = "0"
    2565. 

  2565.     Info (12134): Parameter "clk2_divide_by" = "4"
    2566. 

  2566.     Info (12134): Parameter "clk2_multiply_by" = "120"
    2567. 

  2567.     Info (12134): Parameter "clk2_phase_shift" = "0"
    2568. 

  2568.     Info (12134): Parameter "clk3_divide_by" = "8"
    2569. 

  2569.     Info (12134): Parameter "clk3_multiply_by" = "120"
    2570. 

  2570.     Info (12134): Parameter "clk3_phase_shift" = "0"
    2571. 

  2571.     Info (12134): Parameter "clk4_divide_by" = "4"
    2572. 

  2572.     Info (12134): Parameter "clk4_multiply_by" = "120"
    2573. 

  2573.     Info (12134): Parameter "clk4_phase_shift" = "0"
    2574. 

  2574.     Info (12134): Parameter "compensate_clock" = "CLK0"
    2575. 

  2575.     Info (12134): Parameter "inclk0_input_frequency" = "125000"
    2576. 

  2576.     Info (12134): Parameter "lpm_type" = "altpll"
    2577. 

  2577.     Info (12134): Parameter "operation_mode" = "NORMAL"
    2578. 

  2578.     Info (12134): Parameter "pll_type" = "AUTO"
    2579. 

  2579.     Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
    2580. 

  2580.     Info (12134): Parameter "port_areset" = "PORT_USED"
    2581. 

  2581.     Info (12134): Parameter "port_inclk0" = "PORT_USED"
    2582. 

  2582.     Info (12134): Parameter "port_locked" = "PORT_USED"
    2583. 

  2583.     Info (12134): Parameter "port_clk0" = "PORT_USED"
    2584. 

  2584.     Info (12134): Parameter "port_clk1" = "PORT_UNUSED"
    2585. 

  2585.     Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
    2586. 

  2586.     Info (12134): Parameter "port_clk3" = "PORT_USED"
    2587. 

  2587.     Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    2588. 

  2588.     Info (12134): Parameter "width_clock" = "5"
    2589. 

  2589.     Info (12134): Parameter "width_phasecounterselect" = "3"
    2590. 

  2590. Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9g32.tdf
    2591. 

  2591.     Info (12023): Found entity 1: altpll_9g32
    2592. 

  2592. Info (12128): Elaborating entity "altpll_9g32" for hierarchy "altpll:pll_inst|altpll_9g32:auto_generated"
    2593. 

  2593. Info (12128): Elaborating entity "alta_gclksw" for hierarchy "alta_gclksw:gclksw_inst"
    2594. 

  2594. Info (12128): Elaborating entity "multi_uart_ip" for hierarchy "multi_uart_ip:macro_inst"
    2595. 

  2595. Warning (10230): Verilog HDL assignment warning at multi_uart_ip.v(238): truncated value with size 8 to match size of target (1)
    2596. 

  2596. Warning (10030): Net "tx_dma_clr[11..2]" at multi_uart_ip.v(108) has no driver or initial value, using a default initial value '0'
    2597. 

  2597. Warning (10030): Net "rx_dma_clr[11..2]" at multi_uart_ip.v(110) has no driver or initial value, using a default initial value '0'
    2598. 

  2598. Warning (12125): Using design file ahb2apb.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    2599. 

  2599.     Info (12023): Found entity 1: ahb2apb
    2600. 

  2600. Info (12128): Elaborating entity "ahb2apb" for hierarchy "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb"
    2601. 

  2601. Warning (10764): Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned
    2602. 

  2602. Warning (10230): Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4)
    2603. 

  2603. Warning (12125): Using design file apb_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    2604. 

  2604.     Info (12023): Found entity 1: apb_mux
    2605. 

  2605. Info (12128): Elaborating entity "apb_mux" for hierarchy "multi_uart_ip:macro_inst|apb_mux:u_apb_mux"
    2606. 

  2606. Info (12128): Elaborating entity "multi_uart" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]"
    2607. 

  2607. Info (12128): Elaborating entity "baud_gen" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|baud_gen:u_baud"
    2608. 

  2608. Warning (10230): Verilog HDL assignment warning at baud_gen.v(21): truncated value with size 32 to match size of target (16)
    2609. 

  2609. Warning (10230): Verilog HDL assignment warning at baud_gen.v(31): truncated value with size 32 to match size of target (6)
    2610. 

  2610. Info (12128): Elaborating entity "uart_regs" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs"
    2611. 

  2611. Warning (10230): Verilog HDL assignment warning at uart_regs.v(87): truncated value with size 16 to match size of target (6)
    2612. 

  2612. Warning (10230): Verilog HDL assignment warning at uart_regs.v(208): truncated value with size 32 to match size of target (6)
    2613. 

  2613. Info (12128): Elaborating entity "uart_tx" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]"
    2614. 

  2614. Warning (10230): Verilog HDL assignment warning at uart_tx.v(90): truncated value with size 32 to match size of target (3)
    2615. 

  2615. Warning (10230): Verilog HDL assignment warning at uart_tx.v(92): truncated value with size 32 to match size of target (3)
    2616. 

  2616. Warning (10230): Verilog HDL assignment warning at uart_tx.v(100): truncated value with size 32 to match size of target (1)
    2617. 

  2617. Warning (10230): Verilog HDL assignment warning at uart_tx.v(110): truncated value with size 32 to match size of target (4)
    2618. 

  2618. Info (12128): Elaborating entity "sync_fifo" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo"
    2619. 

  2619. Warning (10230): Verilog HDL assignment warning at sync_fifo.v(36): truncated value with size 32 to match size of target (1)
    2620. 

  2620. Warning (10230): Verilog HDL assignment warning at sync_fifo.v(38): truncated value with size 32 to match size of target (1)
    2621. 

  2621. Info (12128): Elaborating entity "uart_rx" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]"
    2622. 

  2622. Warning (10230): Verilog HDL assignment warning at uart_rx.v(88): truncated value with size 32 to match size of target (4)
    2623. 

  2623. Warning (10230): Verilog HDL assignment warning at uart_rx.v(91): truncated value with size 32 to match size of target (4)
    2624. 

  2624. Warning (10230): Verilog HDL assignment warning at uart_rx.v(93): truncated value with size 32 to match size of target (4)
    2625. 

  2625. Warning (10230): Verilog HDL assignment warning at uart_rx.v(118): truncated value with size 32 to match size of target (4)
    2626. 

  2626. Warning (10230): Verilog HDL assignment warning at uart_rx.v(120): truncated value with size 32 to match size of target (4)
    2627. 

  2627. Info (12128): Elaborating entity "alta_rv32" for hierarchy "alta_rv32:rv32"
    2628. 

  2628. Warning (10034): Output port "gpio0_io_out_data" at alta_sim.v(3739) has no driver
    2629. 

  2629. Warning (10034): Output port "gpio0_io_out_en" at alta_sim.v(3740) has no driver
    2630. 

  2630. Warning (10034): Output port "gpio1_io_out_data" at alta_sim.v(3742) has no driver
    2631. 

  2631. Warning (10034): Output port "gpio1_io_out_en" at alta_sim.v(3743) has no driver
    2632. 

  2632. Warning (10034): Output port "gpio2_io_out_data" at alta_sim.v(3753) has no driver
    2633. 

  2633. Warning (10034): Output port "gpio2_io_out_en" at alta_sim.v(3754) has no driver
    2634. 

  2634. Warning (10034): Output port "gpio3_io_out_data" at alta_sim.v(3756) has no driver
    2635. 

  2635. Warning (10034): Output port "gpio3_io_out_en" at alta_sim.v(3757) has no driver
    2636. 

  2636. Warning (10034): Output port "gpio4_io_out_data" at alta_sim.v(3759) has no driver
    2637. 

  2637. Warning (10034): Output port "gpio4_io_out_en" at alta_sim.v(3760) has no driver
    2638. 

  2638. Warning (10034): Output port "gpio5_io_out_data" at alta_sim.v(3762) has no driver
    2639. 

  2639. Warning (10034): Output port "gpio5_io_out_en" at alta_sim.v(3763) has no driver
    2640. 

  2640. Warning (10034): Output port "gpio6_io_out_data" at alta_sim.v(3765) has no driver
    2641. 

  2641. Warning (10034): Output port "gpio6_io_out_en" at alta_sim.v(3766) has no driver
    2642. 

  2642. Warning (10034): Output port "gpio7_io_out_data" at alta_sim.v(3768) has no driver
    2643. 

  2643. Warning (10034): Output port "gpio7_io_out_en" at alta_sim.v(3769) has no driver
    2644. 

  2644. Warning (10034): Output port "gpio8_io_out_data" at alta_sim.v(3771) has no driver
    2645. 

  2645. Warning (10034): Output port "gpio8_io_out_en" at alta_sim.v(3772) has no driver
    2646. 

  2646. Warning (10034): Output port "gpio9_io_out_data" at alta_sim.v(3774) has no driver
    2647. 

  2647. Warning (10034): Output port "gpio9_io_out_en" at alta_sim.v(3775) has no driver
    2648. 

  2648. Warning (10034): Output port "swj_JTAGSTATE" at alta_sim.v(3780) has no driver
    2649. 

  2649. Warning (10034): Output port "swj_JTAGIR" at alta_sim.v(3781) has no driver
    2650. 

  2650. Warning (10034): Output port "dmactive" at alta_sim.v(3778) has no driver
    2651. 

  2651. Warning (10034): Output port "swj_JTAGNSW" at alta_sim.v(3779) has no driver
    2652. 

  2652. Info (12206): 2 design partitions require synthesis
    2653. 

  2653.     Info (12210): Partition "rv32" requires synthesis because its netlist type is Source File
    2654. 

  2654.     Info (12210): Partition "Top" requires synthesis because its netlist type is Source File
    2655. 

  2655. Info (12209): No design partitions will skip synthesis in the current incremental compilation
    2656. 

  2656. Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder
    2657. 

  2657. Info (281037): Using 4 processors to synthesize 2 partitions in parallel
    2658. 

  2658. Info: *******************************************************************
    2659. 

  2659. Info: Running Quartus II 64-Bit Analysis & Synthesis
    2660. 

  2660.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    2661. 

  2661.     Info: Processing started: Tue Jul 15 16:26:06 2025
    2662. 

  2662. Info: Command: quartus_map --parallel=1 --helper=0 --partition=Top test_uart -c test_uart
    2663. 

  2663. Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
    2664. 

  2664.     Warning (13049): Converted tri-state buffer "multi_uart_ip:macro_inst|rxd_15_ip_in" feeding internal logic into a wire
    2665. 

  2665. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top
    2666. 

  2666. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
    2667. 

  2667. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top
    2668. 

  2668. Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition
    2669. 

  2669. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    2670. 

  2670. Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
    2671. 

  2671.     Warning (13047): Converted the fan-out from the tri-state buffer "multi_uart_ip:macro_inst|rxd_12_ip_in" to the node "gpio6_io_in[3]" into an OR gate
    2672. 

  2672.     Warning (13047): Converted the fan-out from the tri-state buffer "multi_uart_ip:macro_inst|rxd_13_ip_in" to the node "gpio6_io_in[5]" into an OR gate
    2673. 

  2673. Info (13000): Registers with preset signals will power-up high
    2674. 

  2674. Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
    2675. 

  2675. Info (286031): Timing-Driven Synthesis is running on partition "Top"
    2676. 

  2676. Info (17049): 48 registers lost all their fanouts during netlist optimizations.
    2677. 

  2677. Info (17016): Found the following redundant logic cells in design
    2678. 

  2678.     Info (17048): Logic cell "gpio3_io_in[0]"
    2679. 

  2679.     Info (17048): Logic cell "gpio3_io_in[1]"
    2680. 

  2680.     Info (17048): Logic cell "gpio3_io_in[2]"
    2681. 

  2681.     Info (17048): Logic cell "gpio3_io_in[3]"
    2682. 

  2682.     Info (17048): Logic cell "gpio3_io_in[4]"
    2683. 

  2683.     Info (17048): Logic cell "gpio4_io_in[0]"
    2684. 

  2684.     Info (17048): Logic cell "gpio4_io_in[1]"
    2685. 

  2685.     Info (17048): Logic cell "gpio4_io_in[2]"
    2686. 

  2686.     Info (17048): Logic cell "gpio4_io_in[3]"
    2687. 

  2687.     Info (17048): Logic cell "gpio4_io_in[4]"
    2688. 

  2688.     Info (17048): Logic cell "gpio4_io_in[5]"
    2689. 

  2689.     Info (17048): Logic cell "gpio5_io_in[0]"
    2690. 

  2690.     Info (17048): Logic cell "gpio5_io_in[1]"
    2691. 

  2691.     Info (17048): Logic cell "gpio5_io_in[2]"
    2692. 

  2692.     Info (17048): Logic cell "gpio5_io_in[3]"
    2693. 

  2693.     Info (17048): Logic cell "gpio5_io_in[4]"
    2694. 

  2694.     Info (17048): Logic cell "gpio5_io_in[5]"
    2695. 

  2695.     Info (17048): Logic cell "gpio6_io_in[6]"
    2696. 

  2696.     Info (17048): Logic cell "gpio6_io_in[7]"
    2697. 

  2697.     Info (17048): Logic cell "gpio7_io_in[1]"
    2698. 

  2698.     Info (17048): Logic cell "gpio9_io_in[1]"
    2699. 

  2699.     Info (17048): Logic cell "gpio1_io_out_data[0]"
    2700. 

  2700.     Info (17048): Logic cell "gpio1_io_out_en[0]"
    2701. 

  2701.     Info (17048): Logic cell "gpio1_io_out_data[1]"
    2702. 

  2702.     Info (17048): Logic cell "gpio1_io_out_en[1]"
    2703. 

  2703.     Info (17048): Logic cell "gpio1_io_out_data[2]"
    2704. 

  2704.     Info (17048): Logic cell "gpio1_io_out_en[2]"
    2705. 

  2705.     Info (17048): Logic cell "gpio1_io_out_data[3]"
    2706. 

  2706.     Info (17048): Logic cell "gpio1_io_out_en[3]"
    2707. 

  2707.     Info (17048): Logic cell "gpio1_io_out_data[4]"
    2708. 

  2708.     Info (17048): Logic cell "gpio1_io_out_en[4]"
    2709. 

  2709.     Info (17048): Logic cell "gpio1_io_out_data[5]"
    2710. 

  2710.     Info (17048): Logic cell "gpio1_io_out_en[5]"
    2711. 

  2711.     Info (17048): Logic cell "gpio1_io_out_data[6]"
    2712. 

  2712.     Info (17048): Logic cell "gpio1_io_out_en[6]"
    2713. 

  2713.     Info (17048): Logic cell "gpio1_io_out_data[7]"
    2714. 

  2714.     Info (17048): Logic cell "gpio1_io_out_en[7]"
    2715. 

  2715.     Info (17048): Logic cell "gpio2_io_out_data[0]"
    2716. 

  2716.     Info (17048): Logic cell "gpio2_io_out_en[0]"
    2717. 

  2717.     Info (17048): Logic cell "gpio2_io_out_data[1]"
    2718. 

  2718.     Info (17048): Logic cell "gpio2_io_out_en[1]"
    2719. 

  2719.     Info (17048): Logic cell "gpio2_io_out_data[2]"
    2720. 

  2720.     Info (17048): Logic cell "gpio2_io_out_en[2]"
    2721. 

  2721.     Info (17048): Logic cell "gpio2_io_out_data[3]"
    2722. 

  2722.     Info (17048): Logic cell "gpio2_io_out_en[3]"
    2723. 

  2723.     Info (17048): Logic cell "gpio2_io_out_data[4]"
    2724. 

  2724.     Info (17048): Logic cell "gpio2_io_out_en[4]"
    2725. 

  2725.     Info (17048): Logic cell "gpio2_io_out_data[5]"
    2726. 

  2726.     Info (17048): Logic cell "gpio2_io_out_en[5]"
    2727. 

  2727.     Info (17048): Logic cell "gpio2_io_out_data[6]"
    2728. 

  2728.     Info (17048): Logic cell "gpio2_io_out_en[6]"
    2729. 

  2729.     Info (17048): Logic cell "gpio2_io_out_data[7]"
    2730. 

  2730.     Info (17048): Logic cell "gpio2_io_out_en[7]"
    2731. 

  2731.     Info (17048): Logic cell "gpio6_io_out_data[0]"
    2732. 

  2732.     Info (17048): Logic cell "gpio6_io_out_en[0]"
    2733. 

  2733.     Info (17048): Logic cell "gpio6_io_out_data[2]"
    2734. 

  2734.     Info (17048): Logic cell "gpio6_io_out_en[2]"
    2735. 

  2735.     Info (17048): Logic cell "gpio6_io_out_data[4]"
    2736. 

  2736.     Info (17048): Logic cell "gpio6_io_out_en[4]"
    2737. 

  2737.     Info (17048): Logic cell "gpio9_io_out_data[0]"
    2738. 

  2738.     Info (17048): Logic cell "gpio9_io_out_en[0]"
    2739. 

  2739.     Info (17048): Logic cell "gpio9_io_out_data[2]"
    2740. 

  2740.     Info (17048): Logic cell "gpio9_io_out_en[2]"
    2741. 

  2741.     Info (17048): Logic cell "gpio9_io_out_data[3]"
    2742. 

  2742.     Info (17048): Logic cell "gpio9_io_out_en[3]"
    2743. 

  2743.     Info (17048): Logic cell "gpio9_io_out_data[4]"
    2744. 

  2744.     Info (17048): Logic cell "gpio9_io_out_en[4]"
    2745. 

  2745.     Info (17048): Logic cell "gpio9_io_out_data[5]"
    2746. 

  2746.     Info (17048): Logic cell "gpio9_io_out_en[5]"
    2747. 

  2747.     Info (17048): Logic cell "gpio9_io_out_data[6]"
    2748. 

  2748.     Info (17048): Logic cell "gpio9_io_out_en[6]"
    2749. 

  2749.     Info (17048): Logic cell "gpio9_io_out_data[7]"
    2750. 

  2750.     Info (17048): Logic cell "gpio9_io_out_en[7]"
    2751. 

  2751.     Info (17048): Logic cell "sys_resetn"
    2752. 

  2752.     Info (17048): Logic cell "gpio8_io_out_data[4]"
    2753. 

  2753.     Info (17048): Logic cell "gpio8_io_out_en[4]"
    2754. 

  2754.     Info (17048): Logic cell "gpio8_io_out_data[6]"
    2755. 

  2755.     Info (17048): Logic cell "gpio8_io_out_en[6]"
    2756. 

  2756.     Info (17048): Logic cell "gpio7_io_out_data[6]"
    2757. 

  2757.     Info (17048): Logic cell "gpio8_io_out_en[7]"
    2758. 

  2758.     Info (17048): Logic cell "gpio8_io_out_data[1]"
    2759. 

  2759.     Info (17048): Logic cell "gpio8_io_out_en[1]"
    2760. 

  2760.     Info (17048): Logic cell "gpio8_io_out_data[3]"
    2761. 

  2761.     Info (17048): Logic cell "gpio8_io_out_en[3]"
    2762. 

  2762.     Info (17048): Logic cell "sys_ctrl_clkSource[0]"
    2763. 

  2763.     Info (17048): Logic cell "sys_ctrl_clkSource[1]"
    2764. 

  2764.     Info (17048): Logic cell "gpio6_io_out_data[6]"
    2765. 

  2765.     Info (17048): Logic cell "gpio6_io_out_en[6]"
    2766. 

  2766.     Info (17048): Logic cell "gpio9_io_out_data[1]"
    2767. 

  2767.     Info (17048): Logic cell "gpio9_io_out_en[1]"
    2768. 

  2768.     Info (17048): Logic cell "gpio8_io_out_data[0]"
    2769. 

  2769.     Info (17048): Logic cell "gpio8_io_out_en[0]"
    2770. 

  2770.     Info (17048): Logic cell "gpio8_io_out_data[2]"
    2771. 

  2771.     Info (17048): Logic cell "gpio8_io_out_en[2]"
    2772. 

  2772.     Info (17048): Logic cell "gpio7_io_out_en[6]"
    2773. 

  2773.     Info (17048): Logic cell "gpio8_io_out_data[7]"
    2774. 

  2774.     Info (17048): Logic cell "PLL_ENABLE"
    2775. 

  2775. Warning (15899): PLL "altpll:pll_inst|altpll_9g32:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected
    2776. 

  2776. Info (128000): Starting physical synthesis optimizations for speed
    2777. 

  2777. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    2778. 

  2778. Info (332111): Found 4 clocks
    2779. 

  2779.     Info (332111):   Period   Clock Name
    2780. 

  2780.     Info (332111): ======== ============
    2781. 

  2781.     Info (332111):  125.000      PIN_HSE
    2782. 

  2782.     Info (332111):  100.000      PIN_HSI
    2783. 

  2783.     Info (332111):    4.166 pll_inst|auto_generated|pll1|clk[0]
    2784. 

  2784.     Info (332111):    8.333 pll_inst|auto_generated|pll1|clk[3]
    2785. 

  2785. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    2786. 

  2786. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    2787. 

  2787. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    2788. 

  2788. Info (21057): Implemented 2476 device resources after synthesis - the final resource count might be different
    2789. 

  2789.     Info (21058): Implemented 11 input pins
    2790. 

  2790.     Info (21059): Implemented 30 output pins
    2791. 

  2791.     Info (21060): Implemented 17 bidirectional pins
    2792. 

  2792.     Info (21061): Implemented 2414 logic cells
    2793. 

  2793.     Info (21065): Implemented 1 PLLs
    2794. 

  2794.     Info (21071): Implemented 1 partitions
    2795. 

  2795. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings
    2796. 

  2796.     Info: Peak virtual memory: 4692 megabytes
    2797. 

  2797.     Info: Processing ended: Tue Jul 15 16:26:13 2025
    2798. 

  2798.     Info: Elapsed time: 00:00:07
    2799. 

  2799.     Info: Total CPU time (on all processors): 00:00:09
    2800. 

  2800. Info: *******************************************************************
    2801. 

  2801. Info: Running Quartus II 64-Bit Analysis & Synthesis
    2802. 

  2802.     Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
    2803. 

  2803.     Info: Processing started: Tue Jul 15 16:26:06 2025
    2804. 

  2804. Info: Command: quartus_map --parallel=1 --helper=1 --partition=rv32 test_uart -c test_uart
    2805. 

  2805. Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32
    2806. 

  2806. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
    2807. 

  2807. Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32
    2808. 

  2808. Info (281019): Starting Logic Optimization and Technology Mapping for Partition rv32
    2809. 

  2809. Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched
    2810. 

  2810. Warning (13024): Output pins are stuck at VCC or GND
    2811. 

  2811.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[0]" is stuck at GND
    2812. 

  2812.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[1]" is stuck at GND
    2813. 

  2813.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[2]" is stuck at GND
    2814. 

  2814.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[3]" is stuck at GND
    2815. 

  2815.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[4]" is stuck at GND
    2816. 

  2816.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[5]" is stuck at GND
    2817. 

  2817.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[6]" is stuck at GND
    2818. 

  2818.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[7]" is stuck at GND
    2819. 

  2819.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[0]" is stuck at GND
    2820. 

  2820.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[1]" is stuck at GND
    2821. 

  2821.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[2]" is stuck at GND
    2822. 

  2822.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[3]" is stuck at GND
    2823. 

  2823.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[4]" is stuck at GND
    2824. 

  2824.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[5]" is stuck at GND
    2825. 

  2825.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[6]" is stuck at GND
    2826. 

  2826.     Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[7]" is stuck at GND
    2827. 

  2827.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[0]" is stuck at GND
    2828. 

  2828.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[1]" is stuck at GND
    2829. 

  2829.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[2]" is stuck at GND
    2830. 

  2830.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[3]" is stuck at GND
    2831. 

  2831.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[4]" is stuck at GND
    2832. 

  2832.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[5]" is stuck at GND
    2833. 

  2833.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[6]" is stuck at GND
    2834. 

  2834.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[7]" is stuck at GND
    2835. 

  2835.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[0]" is stuck at GND
    2836. 

  2836.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[1]" is stuck at GND
    2837. 

  2837.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[2]" is stuck at GND
    2838. 

  2838.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[3]" is stuck at GND
    2839. 

  2839.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[4]" is stuck at GND
    2840. 

  2840.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[5]" is stuck at GND
    2841. 

  2841.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[6]" is stuck at GND
    2842. 

  2842.     Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[7]" is stuck at GND
    2843. 

  2843.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[0]" is stuck at GND
    2844. 

  2844.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[1]" is stuck at GND
    2845. 

  2845.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[2]" is stuck at GND
    2846. 

  2846.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[3]" is stuck at GND
    2847. 

  2847.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[4]" is stuck at GND
    2848. 

  2848.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[5]" is stuck at GND
    2849. 

  2849.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[6]" is stuck at GND
    2850. 

  2850.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[7]" is stuck at GND
    2851. 

  2851.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[0]" is stuck at GND
    2852. 

  2852.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[1]" is stuck at GND
    2853. 

  2853.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[2]" is stuck at GND
    2854. 

  2854.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[3]" is stuck at GND
    2855. 

  2855.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[4]" is stuck at GND
    2856. 

  2856.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[5]" is stuck at GND
    2857. 

  2857.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[6]" is stuck at GND
    2858. 

  2858.     Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[7]" is stuck at GND
    2859. 

  2859.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[0]" is stuck at GND
    2860. 

  2860.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[1]" is stuck at GND
    2861. 

  2861.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[2]" is stuck at GND
    2862. 

  2862.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[3]" is stuck at GND
    2863. 

  2863.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[4]" is stuck at GND
    2864. 

  2864.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[5]" is stuck at GND
    2865. 

  2865.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[6]" is stuck at GND
    2866. 

  2866.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[7]" is stuck at GND
    2867. 

  2867.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[0]" is stuck at GND
    2868. 

  2868.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[1]" is stuck at GND
    2869. 

  2869.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[2]" is stuck at GND
    2870. 

  2870.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[3]" is stuck at GND
    2871. 

  2871.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[4]" is stuck at GND
    2872. 

  2872.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[5]" is stuck at GND
    2873. 

  2873.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[6]" is stuck at GND
    2874. 

  2874.     Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[7]" is stuck at GND
    2875. 

  2875.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[0]" is stuck at GND
    2876. 

  2876.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[1]" is stuck at GND
    2877. 

  2877.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[2]" is stuck at GND
    2878. 

  2878.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[3]" is stuck at GND
    2879. 

  2879.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[4]" is stuck at GND
    2880. 

  2880.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[5]" is stuck at GND
    2881. 

  2881.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[6]" is stuck at GND
    2882. 

  2882.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[7]" is stuck at GND
    2883. 

  2883.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[0]" is stuck at GND
    2884. 

  2884.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[1]" is stuck at GND
    2885. 

  2885.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[2]" is stuck at GND
    2886. 

  2886.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[3]" is stuck at GND
    2887. 

  2887.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[4]" is stuck at GND
    2888. 

  2888.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[5]" is stuck at GND
    2889. 

  2889.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[6]" is stuck at GND
    2890. 

  2890.     Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[7]" is stuck at GND
    2891. 

  2891.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[0]" is stuck at GND
    2892. 

  2892.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[1]" is stuck at GND
    2893. 

  2893.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[2]" is stuck at GND
    2894. 

  2894.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[3]" is stuck at GND
    2895. 

  2895.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[4]" is stuck at GND
    2896. 

  2896.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[5]" is stuck at GND
    2897. 

  2897.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[6]" is stuck at GND
    2898. 

  2898.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[7]" is stuck at GND
    2899. 

  2899.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[0]" is stuck at GND
    2900. 

  2900.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[1]" is stuck at GND
    2901. 

  2901.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[2]" is stuck at GND
    2902. 

  2902.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[3]" is stuck at GND
    2903. 

  2903.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[4]" is stuck at GND
    2904. 

  2904.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[5]" is stuck at GND
    2905. 

  2905.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[6]" is stuck at GND
    2906. 

  2906.     Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[7]" is stuck at GND
    2907. 

  2907.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[0]" is stuck at GND
    2908. 

  2908.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[1]" is stuck at GND
    2909. 

  2909.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[2]" is stuck at GND
    2910. 

  2910.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[3]" is stuck at GND
    2911. 

  2911.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[4]" is stuck at GND
    2912. 

  2912.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[5]" is stuck at GND
    2913. 

  2913.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[6]" is stuck at GND
    2914. 

  2914.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[7]" is stuck at GND
    2915. 

  2915.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[0]" is stuck at GND
    2916. 

  2916.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[1]" is stuck at GND
    2917. 

  2917.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[2]" is stuck at GND
    2918. 

  2918.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[3]" is stuck at GND
    2919. 

  2919.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[4]" is stuck at GND
    2920. 

  2920.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[5]" is stuck at GND
    2921. 

  2921.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[6]" is stuck at GND
    2922. 

  2922.     Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[7]" is stuck at GND
    2923. 

  2923.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[0]" is stuck at GND
    2924. 

  2924.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[1]" is stuck at GND
    2925. 

  2925.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[2]" is stuck at GND
    2926. 

  2926.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[3]" is stuck at GND
    2927. 

  2927.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[4]" is stuck at GND
    2928. 

  2928.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[5]" is stuck at GND
    2929. 

  2929.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[6]" is stuck at GND
    2930. 

  2930.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[7]" is stuck at GND
    2931. 

  2931.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[0]" is stuck at GND
    2932. 

  2932.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[1]" is stuck at GND
    2933. 

  2933.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[2]" is stuck at GND
    2934. 

  2934.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[3]" is stuck at GND
    2935. 

  2935.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[4]" is stuck at GND
    2936. 

  2936.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[5]" is stuck at GND
    2937. 

  2937.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[6]" is stuck at GND
    2938. 

  2938.     Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[7]" is stuck at GND
    2939. 

  2939.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[0]" is stuck at GND
    2940. 

  2940.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[1]" is stuck at GND
    2941. 

  2941.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[2]" is stuck at GND
    2942. 

  2942.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[3]" is stuck at GND
    2943. 

  2943.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[4]" is stuck at GND
    2944. 

  2944.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[5]" is stuck at GND
    2945. 

  2945.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[6]" is stuck at GND
    2946. 

  2946.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[7]" is stuck at GND
    2947. 

  2947.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[0]" is stuck at GND
    2948. 

  2948.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[1]" is stuck at GND
    2949. 

  2949.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[2]" is stuck at GND
    2950. 

  2950.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[3]" is stuck at GND
    2951. 

  2951.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[4]" is stuck at GND
    2952. 

  2952.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[5]" is stuck at GND
    2953. 

  2953.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[6]" is stuck at GND
    2954. 

  2954.     Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[7]" is stuck at GND
    2955. 

  2955.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[0]" is stuck at GND
    2956. 

  2956.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[1]" is stuck at GND
    2957. 

  2957.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[2]" is stuck at GND
    2958. 

  2958.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[3]" is stuck at GND
    2959. 

  2959.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[4]" is stuck at GND
    2960. 

  2960.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[5]" is stuck at GND
    2961. 

  2961.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[6]" is stuck at GND
    2962. 

  2962.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[7]" is stuck at GND
    2963. 

  2963.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[0]" is stuck at GND
    2964. 

  2964.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[1]" is stuck at GND
    2965. 

  2965.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[2]" is stuck at GND
    2966. 

  2966.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[3]" is stuck at GND
    2967. 

  2967.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[4]" is stuck at GND
    2968. 

  2968.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[5]" is stuck at GND
    2969. 

  2969.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[6]" is stuck at GND
    2970. 

  2970.     Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[7]" is stuck at GND
    2971. 

  2971.     Warning (13410): Pin "alta_rv32:rv32|dmactive" is stuck at GND
    2972. 

  2972.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGNSW" is stuck at GND
    2973. 

  2973.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[0]" is stuck at GND
    2974. 

  2974.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[1]" is stuck at GND
    2975. 

  2975.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[2]" is stuck at GND
    2976. 

  2976.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[3]" is stuck at GND
    2977. 

  2977.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[0]" is stuck at GND
    2978. 

  2978.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[1]" is stuck at GND
    2979. 

  2979.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[2]" is stuck at GND
    2980. 

  2980.     Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[3]" is stuck at GND
    2981. 

  2981. Info (128000): Starting physical synthesis optimizations for speed
    2982. 

  2982. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
    2983. 

  2983. Info (332111): Found 4 clocks
    2984. 

  2984.     Info (332111):   Period   Clock Name
    2985. 

  2985.     Info (332111): ======== ============
    2986. 

  2986.     Info (332111):  125.000      PIN_HSE
    2987. 

  2987.     Info (332111):  100.000      PIN_HSI
    2988. 

  2988.     Info (332111):    4.166 pll_inst|auto_generated|pll1|clk[0]
    2989. 

  2989.     Info (332111):    8.333 pll_inst|auto_generated|pll1|clk[3]
    2990. 

  2990. Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division
    2991. 

  2991. Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps
    2992. 

  2992. Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01
    2993. 

  2993. Info (21057): Implemented 520 device resources after synthesis - the final resource count might be different
    2994. 

  2994.     Info (21058): Implemented 224 input pins
    2995. 

  2995.     Info (21059): Implemented 295 output pins
    2996. 

  2996.     Info (21061): Implemented 1 logic cells
    2997. 

  2997. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings
    2998. 

  2998.     Info: Peak virtual memory: 4676 megabytes
    2999. 

  2999.     Info: Processing ended: Tue Jul 15 16:26:08 2025
    3000. 

  3000.     Info: Elapsed time: 00:00:02
    3001. 

  3001.     Info: Total CPU time (on all processors): 00:00:03
    3002. 

  3002. Info (281038): Finished parallel synthesis of all partitions
    3003. 

  3003. Info (144001): Generated suppressed messages file D:/LYW/NEW_DECODE/2006_APP_s2/logic/quartus_logs/test_uart.map.smsg
    3004. 

  3004. Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 316 warnings
    3005. 

  3005.     Info: Peak virtual memory: 4628 megabytes
    3006. 

  3006.     Info: Processing ended: Tue Jul 15 16:26:14 2025
    3007. 

  3007.     Info: Elapsed time: 00:00:10
    3008. 

  3008.     Info: Total CPU time (on all processors): 00:00:11
    3009. 

  3009. 

  3010. 

  3011. +------------------------------------------+
    3012. 

  3012. ; Analysis & Synthesis Suppressed Messages ;
    3013. 

  3013. +------------------------------------------+
    3014. 

  3014. The suppressed messages can be found in D:/LYW/NEW_DECODE/2006_APP_s2/logic/quartus_logs/test_uart.map.smsg.
    3015. 

  3015. 

  3016.