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- EDA Netlist Writer report for test_uart
- Tue Jul 15 16:27:16 2025
- Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2013 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +-------------------------------------------------------------------+
- ; EDA Netlist Writer Summary ;
- +---------------------------+---------------------------------------+
- ; EDA Netlist Writer Status ; Successful - Tue Jul 15 16:27:16 2025 ;
- ; Revision Name ; test_uart ;
- ; Top-level Entity Name ; test_uart ;
- ; Family ; Cyclone IV E ;
- ; Simulation Files Creation ; Successful ;
- +---------------------------+---------------------------------------+
- +------------------------------------------------------------------------------------------------------------------------+
- ; Simulation Settings ;
- +---------------------------------------------------------------------------------------------------+--------------------+
- ; Option ; Setting ;
- +---------------------------------------------------------------------------------------------------+--------------------+
- ; Tool Name ; ModelSim (Verilog) ;
- ; Generate netlist for functional simulation only ; Off ;
- ; Time scale ; 1 ps ;
- ; Truncate long hierarchy paths ; Off ;
- ; Map illegal HDL characters ; Off ;
- ; Flatten buses into individual nodes ; Off ;
- ; Maintain hierarchy ; Partition Only ;
- ; Bring out device-wide set/reset signals as ports ; Off ;
- ; Enable glitch filtering ; Off ;
- ; Do not write top level VHDL entity ; Off ;
- ; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
- ; Architecture name in VHDL output netlist ; structure ;
- ; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
- ; Generate third-party EDA tool command script for gate-level simulation ; Off ;
- +---------------------------------------------------------------------------------------------------+--------------------+
- +--------------------------------------------------------------------------------------------+
- ; Simulation Generated Files ;
- +--------------------------------------------------------------------------------------------+
- ; Generated Files ;
- +--------------------------------------------------------------------------------------------+
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_8_1200mv_85c_slow.vo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_8_1200mv_0c_slow.vo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_min_1200mv_0c_fast.vo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart.vo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_8_1200mv_85c_v_slow.sdo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_8_1200mv_0c_v_slow.sdo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_min_1200mv_0c_v_fast.sdo ;
- ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/test_uart_v.sdo ;
- +--------------------------------------------------------------------------------------------+
- +-----------------------------+
- ; EDA Netlist Writer Messages ;
- +-----------------------------+
- Info: *******************************************************************
- Info: Running Quartus II 64-Bit EDA Netlist Writer
- Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version
- Info: Processing started: Tue Jul 15 16:27:13 2025
- Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off test_uart -c test_uart
- Info (204019): Generated file test_uart_8_1200mv_85c_slow.vo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_8_1200mv_0c_slow.vo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_min_1200mv_0c_fast.vo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart.vo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_8_1200mv_85c_v_slow.sdo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_8_1200mv_0c_v_slow.sdo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_min_1200mv_0c_v_fast.sdo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info (204019): Generated file test_uart_v.sdo in folder "D:/LYW/NEW_DECODE/2006_APP_s2/logic/simulation/modelsim/" for EDA simulation tool
- Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings
- Info: Peak virtual memory: 4572 megabytes
- Info: Processing ended: Tue Jul 15 16:27:16 2025
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
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