2006_APP/logic/multi_uart_ip/baud_gen.v

module baud_gen (
  input clk,
  input rstn,
  input [15:0] ibrd,
  input [5:0] fbrd,
  input stop,
  output reg baud16
);

reg [15:0] i_cnt;
reg [5:0]  f_cnt;
reg f_del;
wire [5:0] f_rev = { f_cnt[0], f_cnt[1], f_cnt[2], f_cnt[3], f_cnt[4], f_cnt[5] };

always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
    i_cnt <= 16'h1;
  end else if (stop || !f_del && i_cnt == 1 || i_cnt == 0) begin
    i_cnt <= ibrd;
  end else begin
    i_cnt <= i_cnt - 1;
  end
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
    f_cnt <= 6'h0;
  end else if (stop) begin
    f_cnt <= 6'h0;
  end else if (baud16) begin
    f_cnt <= f_cnt + 1;
  end
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
    baud16 <= 1'b0;
  end else if (!stop && (!f_del && i_cnt == 1 || i_cnt == 0)) begin
    baud16 <= 1'b1;
  end else begin
    baud16 <= 1'b0;
  end
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
    f_del <= 1'b0;
  end else if (f_rev < fbrd) begin
    f_del <= 1'b1;
  end else begin
    f_del <= 1'b0;
  end
end

always @(posedge clk or negedge rstn) begin
  if (!rstn) begin
  end
end

endmodule